Repository: GorgonMeducer/Generic_MCU_Software_Infrastructure Branch: master Commit: 1f07332ffb04 Files: 217 Total size: 2.5 MB Directory structure: gitextract_iu0vyl3p/ ├── .gitattributes ├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── example/ │ ├── RTE/ │ │ ├── Device/ │ │ │ └── CMSDK_CM7_SP/ │ │ │ ├── RTE_Device.h │ │ │ ├── startup_CMSDK_CM7.s │ │ │ └── system_CMSDK_CM7.c │ │ └── _V2M-MPS2/ │ │ └── RTE_Components.h │ ├── app_cfg.h │ ├── app_platform/ │ │ ├── app_cfg.h │ │ ├── app_platform.c │ │ ├── app_platform.h │ │ ├── stdout_USART.c │ │ └── stdout_USART.h │ ├── build/ │ │ └── mdk/ │ │ ├── Abstract.txt │ │ ├── Blinky.sct │ │ ├── Blinky.uvguix │ │ ├── Blinky.uvguix.gabriel │ │ ├── Blinky.uvoptx │ │ ├── Blinky.uvprojx │ │ ├── Dbg_MPS2.ini │ │ ├── Dbg_Sim.ini │ │ ├── EventRecorderStub.scvd │ │ ├── FVP_cfg.txt │ │ ├── MPS2_CS_ETB.ini │ │ ├── MPS2_CS_TPIU.ini │ │ └── RTE/ │ │ ├── Board_Support/ │ │ │ ├── MK64FN1M0xxx12/ │ │ │ │ ├── board.c │ │ │ │ ├── board.h │ │ │ │ ├── clock_config.c │ │ │ │ ├── clock_config.h │ │ │ │ ├── peripherals.c │ │ │ │ ├── peripherals.h │ │ │ │ ├── pin_mux.c │ │ │ │ └── pin_mux.h │ │ │ ├── board.c │ │ │ ├── board.h │ │ │ ├── clock_config.c │ │ │ ├── clock_config.h │ │ │ ├── peripherals.c │ │ │ ├── peripherals.h │ │ │ ├── pin_mux.c │ │ │ └── pin_mux.h │ │ ├── Device/ │ │ │ ├── ARMCM4_FP/ │ │ │ │ ├── startup_ARMCM4.s │ │ │ │ └── system_ARMCM4.c │ │ │ ├── CMSDK_CM4_FP/ │ │ │ │ ├── RTE_Device.h │ │ │ │ ├── startup_CMSDK_CM4.s │ │ │ │ └── system_CMSDK_CM4.c │ │ │ ├── CMSDK_CM7_DP/ │ │ │ │ ├── RTE_Device.h │ │ │ │ ├── startup_CMSDK_CM7.s │ │ │ │ └── system_CMSDK_CM7.c │ │ │ ├── CMSDK_CM7_SP/ │ │ │ │ ├── RTE_Device.h │ │ │ │ ├── startup_CMSDK_CM7.s │ │ │ │ └── system_CMSDK_CM7.c │ │ │ └── MK64FN1M0xxx12/ │ │ │ ├── MK64F12.h │ │ │ ├── MK64F12_features.h │ │ │ ├── MK64FN1M0xxx12_flash.scf │ │ │ ├── MK64FN1M0xxx12_ram.scf │ │ │ ├── RTE_Device.h │ │ │ ├── fsl_device_registers.h │ │ │ ├── startup_MK64F12.s │ │ │ ├── startup_MK64F12.s.0000 │ │ │ ├── system_MK64F12.c │ │ │ ├── system_MK64F12.c.0000 │ │ │ └── system_MK64F12.h │ │ ├── _FRDM-K64/ │ │ │ └── RTE_Components.h │ │ ├── _FastModel/ │ │ │ └── RTE_Components.h │ │ └── _V2M-MPS2/ │ │ └── RTE_Components.h │ ├── menu_example.c │ ├── scheduler_example.c │ └── system.c └── sources/ ├── app_cfg.h └── gmsi/ ├── app_cfg.h ├── arch/ │ ├── app_cfg.h │ ├── arch.h │ └── arm/ │ ├── app_cfg.h │ └── cortex-m/ │ ├── app_cfg.h │ ├── arch_cortex-m.c │ └── arch_cortex-m.h ├── default.c ├── gmsi.c ├── gmsi.h ├── hal/ │ ├── app_cfg.h │ ├── bsp/ │ │ ├── app_cfg.h │ │ ├── bsp.c │ │ └── bsp.h │ ├── component/ │ │ ├── app_cfg.h │ │ ├── bootloader/ │ │ │ ├── app_cfg.h │ │ │ ├── bootloader.c │ │ │ └── bootloader.h │ │ ├── component.c │ │ ├── component.h │ │ ├── key/ │ │ │ ├── app_cfg.h │ │ │ ├── key.c │ │ │ ├── key.h │ │ │ ├── key_interface.h │ │ │ └── key_queue/ │ │ │ ├── app_cfg.h │ │ │ ├── key_queue.c │ │ │ └── key_queue.h │ │ ├── memory/ │ │ │ ├── app_cfg.h │ │ │ ├── interface.h │ │ │ ├── mal/ │ │ │ │ ├── app_cfg.h │ │ │ │ ├── interface.h │ │ │ │ ├── mal.c │ │ │ │ ├── mal.h │ │ │ │ ├── sdf_w25qxxx/ │ │ │ │ │ ├── app_cfg.h │ │ │ │ │ ├── interface.h │ │ │ │ │ ├── sdf_w25qxxx.c │ │ │ │ │ └── sdf_w25qxxx.h │ │ │ │ └── sram/ │ │ │ │ ├── app_cfg.h │ │ │ │ ├── interface.h │ │ │ │ ├── sram.c │ │ │ │ └── sram.h │ │ │ ├── memory.h │ │ │ └── page/ │ │ │ ├── app_cfg.h │ │ │ ├── interface.h │ │ │ ├── page.c │ │ │ └── page.h │ │ └── sw_sdio/ │ │ ├── app_cfg.h │ │ ├── sw_sdio.c │ │ └── sw_sdio.h │ ├── hal.c │ └── hal.h ├── service/ │ ├── app_cfg.h │ ├── communication/ │ │ ├── app_cfg.h │ │ ├── communication.h │ │ ├── crc/ │ │ │ ├── app_cfg.h │ │ │ ├── crc.c │ │ │ ├── crc.h │ │ │ ├── crc16.c │ │ │ ├── crc32.c │ │ │ ├── crc7.c │ │ │ └── crc8.c │ │ ├── frame/ │ │ │ ├── app_cfg.h │ │ │ ├── es_simple_frame/ │ │ │ │ ├── app_cfg.h │ │ │ │ ├── es_simple_frame.c │ │ │ │ └── es_simple_frame.h │ │ │ ├── frame.h │ │ │ └── iframe.h │ │ ├── telegraph_engine/ │ │ │ ├── app_cfg.h │ │ │ ├── telegraph_engine.c │ │ │ └── telegraph_engine.h │ │ └── xmodem/ │ │ ├── app_cfg.h │ │ ├── xmodem.c │ │ └── xmodem.h │ ├── encryption/ │ │ ├── app_cfg.h │ │ ├── encryption.h │ │ └── random/ │ │ ├── app_cfg.h │ │ ├── random.c │ │ └── random.h │ ├── gui/ │ │ ├── app_cfg.h │ │ ├── gui.h │ │ └── tgui/ │ │ ├── app_cfg.h │ │ ├── grid/ │ │ │ ├── app_cfg.h │ │ │ ├── grid.c │ │ │ ├── grid.h │ │ │ └── interface.h │ │ ├── interface.h │ │ ├── tgui.c │ │ └── tgui.h │ ├── memory/ │ │ ├── app_cfg.h │ │ ├── block/ │ │ │ ├── __class_block.h │ │ │ ├── app_cfg.h │ │ │ ├── block.c │ │ │ └── block.h │ │ ├── block_queue/ │ │ │ ├── app_cfg.h │ │ │ ├── block_queue.c │ │ │ └── block_queue.h │ │ ├── epool/ │ │ │ ├── app_cfg.h │ │ │ ├── epool.c │ │ │ └── epool.h │ │ ├── memory.c │ │ ├── memory.h │ │ └── stream2block/ │ │ ├── app_cfg.h │ │ ├── stream2block.c │ │ └── stream2block.h │ ├── scheduler/ │ │ ├── app_cfg.h │ │ ├── scheduler.c │ │ ├── scheduler.h │ │ ├── scheduler_internal.h │ │ ├── shell.c │ │ ├── task.c │ │ └── task.h │ ├── service.c │ ├── service.h │ └── time/ │ ├── app_cfg.h │ ├── multiple_delay/ │ │ ├── app_cfg.h │ │ ├── multiple_delay.c │ │ └── multiple_delay.h │ ├── time.c │ └── time.h └── utilities/ ├── app_type.h ├── arm/ │ ├── arm_compiler.h │ ├── signal.c │ └── signal.h ├── avr/ │ ├── app_type.h │ ├── avr_compiler.h │ └── signal.h ├── communicate.h ├── compiler.h ├── delegate.c ├── delegate.h ├── error.h ├── ooc.h ├── preprocessor/ │ ├── connect.h │ ├── language_extension.h │ ├── macro_repeat.h │ ├── mf_u8_dec2str.h │ └── preprocessor.h ├── simple_fsm.h ├── template/ │ ├── t_list.c │ ├── t_list.h │ ├── t_pool.h │ ├── t_queue.h │ └── template.h ├── tiny_fsm.h └── usebits.h ================================================ FILE CONTENTS ================================================ ================================================ FILE: .gitattributes ================================================ # Auto detect text files and perform LF normalization * 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See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: README.md ================================================ # Generic_MCU_Software_Infrastructure Provides necessary software infrastructures, services, macros to support some high level abstruct concepts and/or paradigm, such as OOPC, FSM, delegate (event-driven) and etc Currently GMSI provides following services: - epool a common pool infrastructure, which could be considered as an abstract class for pool (heap). The letter "e" here represents "embedded". - block a building block class which provides the basis of block based buffer services. block_t will be used by other services, such as block_queue, stream2block, es_simple_frame and etc. Both dynamic(heap) and static memory allocation are supported. - block_queue A queue of block_t which implemented as a block list. - stream2block a dedicated stream-based service which provides stream interface for block devices, i.e. IO devices which support burst transfer mode (such as SPI, USART using DMA). A serial port tempalte is provided to use USART with the minimal requirments of Data-Receiving-Complete interrupt and Data-Transfering-Complete interrupt. Example project demostrates how to use stream2block with usart. WHY using stream2block service rather than simple QUEUE + ISR ? Simple QUEUE + ISR does works for normal applications, but you have to provide atomicity protection for queues. This will hurt real-time response of interrupt significantly if the stream is accessed frequently in super-loop, i.e. enqueue or dequeue. On the other hand, some device might encourage users to use DMA or other methods which can generate burst transations, in other words, a stream has to be converted into blocks. When stream2block is designed, it works like a double-bufferred system, so when one block is used for queue access, another block is used for a burst transaction. The burst IO transactiond and the queue are connected via a list, which works like a queue of blocks. You only need to provide atomicity protection on the list but not the queue. So, frequenly accessing queue in the super-loop will not hurt any real-time response, as list accesses are relatively less freqently comparing those accesses in normal QUEUE + ISR scheme. - es_simple_frame A communication service with provides encoding and decoding functions based on a simple frame structure, which only contains a 8bit header, a 16bit length, an optional data field and a 16bits CRC checksum. This service can be configured working with exchangable buffer ( block_t ) or static memory buffer. - multiple_delay A dedicated temporal module which can provide delay monitoring service for finite state machine or tasks in RTOS. A 1ms timer event handler is required to drive a 32bit counter. - scheduler A dedicated non-preeptive finite state machine scheduler. - crc Various CRC functions. - xmodem A dedicated module which implements Xmodem communication protocal. - bootloader A bootloader logic template. You just need to 1) implement the memories access driver, 2)describe the supported memories in the target device, and 3) provide a stream interface (i_byte_pipe_t) for communication. - key A dedicated module which provides general key-board services, such as signal filtering, key event detection and key buffer. - sw_sdio A dedicated module which provides software-implemented sdio driver. - mal Memory Abstruct Layer, provides unified, random access API for all kinds of page-based and/or non-page-based memories. - page A dedicated service which provide random accesses for page-based memories. ... ================================================ FILE: example/RTE/Device/CMSDK_CM7_SP/RTE_Device.h ================================================ /* ----------------------------------------------------------------------------- * Copyright (c) 2016 ARM Ltd. * * This software is provided 'as-is', without any express or implied warranty. * In no event will the authors be held liable for any damages arising from * the use of this software. Permission is granted to anyone to use this * software for any purpose, including commercial applications, and to alter * it and redistribute it freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software in * a product, an acknowledgment in the product documentation would be * appreciated but is not required. * * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * * 3. This notice may not be removed or altered from any source distribution. * * $Date: 25. April 2016 * $Revision: V1.0.0 * * Project: RTE Device Configuration for ARM CMSDK_CM device * -------------------------------------------------------------------------- */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_USART0 1 // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART #define RTE_USART1 0 // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART #define RTE_UART2 0 // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART #define RTE_UART3 0 #endif /* __RTE_DEVICE_H */ ================================================ FILE: example/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s ================================================ ;/**************************************************************************//** ; * @file startup_CMSDK_CM7.s ; * @brief CMSIS Core Device Startup File for ; * CMSDK_CM7 Device ; * @version V3.05 ; * @date 09. November 2016 ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2016 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD UART0RX_Handler ; 0 UART 0 receive interrupt DCD UART0TX_Handler ; 1 UART 0 transmit interrupt DCD UART1RX_Handler ; 2 UART 1 receive interrupt DCD UART1TX_Handler ; 3 UART 1 transmit interrupt DCD UART2RX_Handler ; 4 UART 2 receive interrupt DCD UART2TX_Handler ; 5 UART 2 transmit interrupt DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt DCD TIMER0_Handler ; 8 Timer 0 interrupt DCD TIMER1_Handler ; 9 Timer 1 interrupt DCD DUALTIMER_Handler ; 10 Dual Timer interrupt DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt DCD ETHERNET_Handler ; 13 Ethernet interrupt DCD I2S_Handler ; 14 Audio I2S interrupt DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt DCD UART3RX_Handler ; 18 UART 3 receive interrupt DCD UART3TX_Handler ; 19 UART 3 transmit interrupt DCD UART4RX_Handler ; 20 UART 4 receive interrupt DCD UART4TX_Handler ; 21 UART 4 transmit interrupt DCD SPI_2_Handler ; 22 SPI #2 interrupt DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0) DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1) DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2) DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3) DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4) DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5) DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6) DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7) __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT UART0RX_Handler [WEAK] EXPORT UART0TX_Handler [WEAK] EXPORT UART1RX_Handler [WEAK] EXPORT UART1TX_Handler [WEAK] EXPORT UART2RX_Handler [WEAK] EXPORT UART2TX_Handler [WEAK] EXPORT GPIO0ALL_Handler [WEAK] EXPORT GPIO1ALL_Handler [WEAK] EXPORT TIMER0_Handler [WEAK] EXPORT TIMER1_Handler [WEAK] EXPORT DUALTIMER_Handler [WEAK] EXPORT SPI_0_1_Handler [WEAK] EXPORT UART_0_1_2_OVF_Handler [WEAK] EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TOUCHSCREEN_Handler [WEAK] EXPORT GPIO2_Handler [WEAK] EXPORT GPIO3_Handler [WEAK] EXPORT UART3RX_Handler [WEAK] EXPORT UART3TX_Handler [WEAK] EXPORT UART4RX_Handler [WEAK] EXPORT UART4TX_Handler [WEAK] EXPORT SPI_2_Handler [WEAK] EXPORT SPI_3_4_Handler [WEAK] EXPORT GPIO0_0_Handler [WEAK] EXPORT GPIO0_1_Handler [WEAK] EXPORT GPIO0_2_Handler [WEAK] EXPORT GPIO0_3_Handler [WEAK] EXPORT GPIO0_4_Handler [WEAK] EXPORT GPIO0_5_Handler [WEAK] EXPORT GPIO0_6_Handler [WEAK] EXPORT GPIO0_7_Handler [WEAK] UART0RX_Handler UART0TX_Handler UART1RX_Handler UART1TX_Handler UART2RX_Handler UART2TX_Handler GPIO0ALL_Handler GPIO1ALL_Handler TIMER0_Handler TIMER1_Handler DUALTIMER_Handler SPI_0_1_Handler UART_0_1_2_OVF_Handler ETHERNET_Handler I2S_Handler TOUCHSCREEN_Handler GPIO2_Handler GPIO3_Handler UART3RX_Handler UART3TX_Handler UART4RX_Handler UART4TX_Handler SPI_2_Handler SPI_3_4_Handler GPIO0_0_Handler GPIO0_1_Handler GPIO0_2_Handler GPIO0_3_Handler GPIO0_4_Handler GPIO0_5_Handler GPIO0_6_Handler GPIO0_7_Handler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END ================================================ FILE: example/RTE/Device/CMSDK_CM7_SP/system_CMSDK_CM7.c ================================================ /**************************************************************************//** * @file system_CMSDK_CM7.c * @brief CMSIS Device System Source File for * CMSDK_CM7 Device * @version V4.00 * @date 02. November 2015 ******************************************************************************/ /* Copyright (c) 2011 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined (CMSDK_CM7) #include "CMSDK_CM7.h" #elif defined (CMSDK_CM7_SP) #include "CMSDK_CM7_SP.h" #elif defined (CMSDK_CM7_DP) #include "CMSDK_CM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } void SystemInit (void) { #if (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: example/RTE/_V2M-MPS2/RTE_Components.h ================================================ /* * Auto generated Run-Time-Environment Component Configuration File * *** Do not modify ! *** * * Project: 'Blinky' * Target: 'V2M-MPS2' */ #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H /* * Define the Device Header File: */ #define CMSIS_device_header "CMSDK_CM7_SP.h" #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ #define RTE_Drivers_USART #endif /* RTE_COMPONENTS_H */ ================================================ FILE: example/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #ifndef __SYSTEM_APP_CFG_H__ #define __SYSTEM_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- /*----------------------------------------------------------------------------* * Application Platform Configuration * *----------------------------------------------------------------------------*/ // STDOUT (via UART) configuration // SerialPort Baudrate // Configure the baudrate of the UART which is used as stdout (printf) #define USART_BAUDRATE (115200) // Block Input Timeout in ms <0-65535> // When timeout, all received bytes will be imported to input stream (STREAM_IN), 0 means disabling the timeout feature. #define STREAM_IN_RCV_TIMEOUT (5) // Output Stream (STREAM_OUT) // The size of output buffer block <8-4096> // Output stream will be transfered in blocks, the size of an output block is defined here. #define OUTPUT_STREAM_BLOCK_SIZE (32) // The number of output blocks in a dedicated heap <2-65535> // All output blocks are allocated from a dedicated heap, the size of the heap is defined here. #define OUTPUT_STREAM_BLOCK_COUNT (4) // // Input Stream (STREAM_IN) // The size of input buffer block <8-4096> // Input stream will be received in blocks, the size of an input block is defined here. #define INPUT_STREAM_BLOCK_SIZE (16) // The number of input blocks in a dedicated heap <2-65535> // All input blocks are allocated from a dedicated heap, the size of the heap is defined here. #define INPUT_STREAM_BLOCK_COUNT (8) // // // Simple Frame Encoding / Decodign configuration // Frame Buffer Size in byte <1-65536> // The frame buffer is only used to store the data decoded from a valid frame. Reply data can also be stored in this buffer. #define FRAME_BUFFER_SIZE (1024) // // Multiple Delay Service Configuration // Maximum number of delay objects supported <1-65536> // A dedicated pool is provided to hold all the delay objects. The pool size determined the maximum allowed delay tasks supported at the same time. #define DELAY_OBJ_POOL_SIZE 8 // #define USE_SERVICE_ES_SIMPLE_FRAME ENABLED #define USE_SERVICE_MULTIPLE_DELAY ENABLED #define USE_SERVICE_TELEGRAPH_ENGINE ENABLED #define USE_SERVICE_BLOCK ENABLED #define USE_SERVICE_BLOCK_QUEUE ENABLED #define USE_SERVICE_STREAM_TO_BLOCK ENABLED #define DEMO_MULTIPLE_DELAY DISABLED #define DEMO_FRAME_USE_BLOCK_MODE ENABLED /*----------------------------------------------------------------------------* * Scheduler Configuration * *----------------------------------------------------------------------------*/ //! \name configure safe task service:1.2K for current configuration //! @{ #define TASK_SCHEDULER DISABLED #define SAFE_TASK_THREAD_SYNC ENABLED //!< disable semaphore support #define SAFE_TASK_CRITICAL_SECTION ENABLED //!< enable critical support #define SAFE_TASK_CALL_STACK ENABLED #define SAFE_TASK_USE_RESERVED_SYSTEM_RAM DISABLED #define SAFE_TASK_QUEUE_POOL_SIZE (1ul) //!< task queue pool size #define SAFE_TASK_POOL_SIZE (8ul) //!< task pool size //! @} /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: example/app_platform/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __APP_PLATFORM_APP_CFG_H__ #define __APP_PLATFORM_APP_CFG_H__ /*============================ INCLUDES ======================================*/ #include "..\..\sources\gmsi\gmsi.h" // Import GMSI Support /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: example/app_platform/app_platform.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include #include "app_platform.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ static void counter_overflow(void); extern void SystemCoreClockUpdate (void); /*============================ IMPLEMENTATION ================================*/ #if __IS_COMPILER_ARM_COMPILER_6__ __asm(".global __use_no_semihosting\n\t"); __asm(".global __ARM_use_no_argv\n\t"); void _sys_exit(int ch) { while(1); } void _ttywrch(int ch) { } #include FILEHANDLE $Sub$$_sys_open(const char *name, int openmode) { return 0; } #endif /* \note please put it into a 1ms timer handler */ void app_platform_1ms_event_handler(void) { STREAM_IN_1ms_event_handler(); } __attribute__((constructor(101))) /*! \note initialize board specific package * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ void app_platform_init( void ) { do { SystemCoreClockUpdate(); gmsi_platform_init(); if (!stdout_init()) { break; } return ; } while(false); NVIC_SystemReset(); } /* EOF */ ================================================ FILE: example/app_platform/app_platform.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_APP_PLATFORM_H__ #define __USE_APP_PLATFORM_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include #include #include ".\stdout_USART.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /* \note please put it into a 1ms timer handler */ extern void app_platform_1ms_event_handler(void); /*! \brief start performance counter (cycle accurate) */ extern void start_counter(void); /*! \brief stop performance counter (cycle accurate) *! \retval cycle elapsed. */ extern int32_t stop_counter(void); #endif ================================================ FILE: example/app_platform/stdout_USART.c ================================================ /*----------------------------------------------------------------------------- * Name: stdout_USART.c * Purpose: STDOUT USART Template * Rev.: 1.0.0 *-----------------------------------------------------------------------------*/ /* Copyright (c) 2013 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include #include enum { /* ---------------------- CMSDK_CM4 Specific Interrupt Numbers ------------------ */ UART0RX_IRQn = 0, /* UART 0 receive interrupt */ UART0TX_IRQn = 1, /* UART 0 transmit interrupt */ UART1RX_IRQn = 2, /* UART 1 receive interrupt */ UART1TX_IRQn = 3, /* UART 1 transmit interrupt */ UART2RX_IRQn = 4, /* UART 2 receive interrupt */ UART2TX_IRQn = 5, /* UART 2 transmit interrupt */ GPIO0ALL_IRQn = 6, /* GPIO 0 combined interrupt */ GPIO1ALL_IRQn = 7, /* GPIO 1 combined interrupt */ TIMER0_IRQn = 8, /* Timer 0 interrupt */ TIMER1_IRQn = 9, /* Timer 1 interrupt */ DUALTIMER_IRQn = 10, /* Dual Timer interrupt */ SPI_0_1_IRQn = 11, /* SPI #0, #1 interrupt */ UART_0_1_2_OVF_IRQn = 12, /* UART overflow (0, 1 & 2) interrupt */ ETHERNET_IRQn = 13, /* Ethernet interrupt */ I2S_IRQn = 14, /* Audio I2S interrupt */ TOUCHSCREEN_IRQn = 15, /* Touch Screen interrupt */ GPIO2_IRQn = 16, /* GPIO 2 combined interrupt */ GPIO3_IRQn = 17, /* GPIO 3 combined interrupt */ UART3RX_IRQn = 18, /* UART 3 receive interrupt */ UART3TX_IRQn = 19, /* UART 3 transmit interrupt */ UART4RX_IRQn = 20, /* UART 4 receive interrupt */ UART4TX_IRQn = 21, /* UART 4 transmit interrupt */ SPI_2_IRQn = 22, /* SPI #2 interrupt */ SPI_3_4_IRQn = 23, /* SPI #3, SPI #4 interrupt */ GPIO0_0_IRQn = 24, /* GPIO 0 individual interrupt ( 0) */ GPIO0_1_IRQn = 25, /* GPIO 0 individual interrupt ( 1) */ GPIO0_2_IRQn = 26, /* GPIO 0 individual interrupt ( 2) */ GPIO0_3_IRQn = 27, /* GPIO 0 individual interrupt ( 3) */ GPIO0_4_IRQn = 28, /* GPIO 0 individual interrupt ( 4) */ GPIO0_5_IRQn = 29, /* GPIO 0 individual interrupt ( 5) */ GPIO0_6_IRQn = 30, /* GPIO 0 individual interrupt ( 6) */ GPIO0_7_IRQn = 31 /* GPIO 0 individual interrupt ( 7) */ }; /*============================ MACROS ========================================*/ /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ typedef struct { __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ union { __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ }; __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; /* CMSDK_UART DATA Register Definitions */ #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ #define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */ /* CMSDK_UART STATE Register Definitions */ #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ #define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ #define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ #define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ #define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */ /* CMSDK_UART CTRL Register Definitions */ #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ #define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ #define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ #define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */ #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */ /* CMSDK_UART BAUDDIV Register Definitions */ #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ /* ================================================================================ */ /* ================ Peripheral declaration ================ */ /* ================================================================================ */ //#define CMSDK_UART0_BASE_ADDRESS (0x41303000ul) #define CMSDK_UART0_BASE_ADDRESS (0x40004000ul) #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE_ADDRESS) //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // STDOUT USART Interface // Connect to hardware via Driver_USART# <0-255> // Select driver control block for USART interface #define USART_DRV_NUM 0 // #ifndef USART_BAUDRATE # define USART_BAUDRATE 115200 #endif #ifndef STREAM_IN_RCV_TIMEOUT # warning No defined macro STREAM_IN_RCV_TIMEOUT, default value 10 is used. # define STREAM_IN_RCV_TIMEOUT (10) #endif #ifndef OUTPUT_STREAM_BLOCK_SIZE # warning No defined macro OUTPUT_STREAM_BLOCK_SIZE, default value 32 is used. # define OUTPUT_STREAM_BLOCK_SIZE (32) #endif #ifndef OUTPUT_STREAM_BLOCK_COUNT # warning No defined macro OUTPUT_STREAM_BLOCK_COUNT, default value 4 is used. # define OUTPUT_STREAM_BLOCK_COUNT (4) #endif #ifndef INPUT_STREAM_BLOCK_SIZE # warning No defined macro INPUT_STREAM_BLOCK_SIZE, default value 32 is used. # define INPUT_STREAM_BLOCK_SIZE (32) #endif #ifndef INPUT_STREAM_BLOCK_COUNT # warning No defined macro INPUT_STREAM_BLOCK_COUNT, default value 8 is used. # define INPUT_STREAM_BLOCK_COUNT (8) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define __USE_SERIAL_PORT_INPUT_ADAPTER(__NUM) \ \ void STREAM_IN_serial_port_enable_rx_cpl_interrupt(void) \ { \ CMSDK_UART##__NUM->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; \ } \ \ void STREAM_IN_serial_port_disable_rx_cpl_interrupt(void) \ { \ CMSDK_UART##__NUM->CTRL &= ~CMSDK_UART_CTRL_RXIRQEN_Msk; \ } \ \ uint8_t STREAM_IN_serial_port_get_byte(void) \ { \ return CMSDK_UART##__NUM->DATA; \ } \ /* this function is called instead of the original UART0RX_Handler() */ \ void USART##__NUM##_RX_CPL_Handler(void) \ { \ /*! clear interrupt flag */ \ CMSDK_UART##__NUM->INTCLEAR = CMSDK_UART##__NUM->INTSTATUS; \ STREAM_IN_insert_serial_port_rx_cpl_event_handler(); \ } #define __USE_SERIAL_PORT_OUTPUT_ADAPTER(__NUM) \ \ void STREAM_OUT_serial_port_enable_tx_cpl_interrupt(void) \ { \ CMSDK_UART##__NUM->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; \ } \ \ void STREAM_OUT_serial_port_disbale_tx_cpl_interrupt(void) \ { \ CMSDK_UART##__NUM->CTRL &= ~CMSDK_UART_CTRL_TXIRQEN_Msk; \ } \ \ void STREAM_OUT_serial_port_fill_byte(uint8_t chByte) \ { \ CMSDK_UART##__NUM->DATA = chByte; \ } \ \ /* this function is called instead of the original UART0TX_Handler() */ \ void USART##__NUM##_TX_CPL_Handler(void) \ { \ /*! clear interrupt flag */ \ CMSDK_UART##__NUM->INTCLEAR = CMSDK_UART##__NUM->INTSTATUS; \ /*! implement our own version of uart tx interrupt */ \ \ STREAM_OUT_insert_serial_port_tx_cpl_event_handler(); \ } #define USE_SERIAL_PORT_INPUT_ADAPTER(__NUM) \ __USE_SERIAL_PORT_INPUT_ADAPTER(__NUM) #define USE_SERIAL_PORT_OUTPUT_ADAPTER(__NUM) \ __USE_SERIAL_PORT_OUTPUT_ADAPTER(__NUM) /*============================ TYPES =========================================*/ //! \note define a buffer for output stream //! @{ DEF_OUTPUT_STREAM_BUFFER( STREAM_OUT, OUTPUT_STREAM_BLOCK_SIZE) END_DEF_OUTPUT_STREAM_BUFFER( STREAM_OUT) //! \note add an adapter for serial port STREAM_OUT_SERIAL_PORT_ADAPTER( STREAM_OUT, OUTPUT_STREAM_BLOCK_COUNT) //! @} //! \note define a buffer for input stream //! @{ DEF_INPUT_STREAM_BUFFER(STREAM_IN, INPUT_STREAM_BLOCK_SIZE) END_DEF_INPUT_STREAM_BUFFER(STREAM_IN) //! \note add an adapter for serial port STREAM_IN_SERIAL_PORT_ADAPTER(STREAM_IN, INPUT_STREAM_BLOCK_COUNT) //! @} /*------------------------------------------------------------------------------* * Implement Serial Port input interfaces required by STREAM_OUT adapter * *------------------------------------------------------------------------------*/ USE_SERIAL_PORT_INPUT_ADAPTER(USART_DRV_NUM) /*------------------------------------------------------------------------------* * Implement Serial Port output interfaces required by STREAM_OUT adapter * *------------------------------------------------------------------------------*/ USE_SERIAL_PORT_OUTPUT_ADAPTER(USART_DRV_NUM) /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize usart for stdout * \param none * \retval true initialization succeeded. * \retval false initialization failed */ bool stdout_init (void) { STREAM_OUT_output_stream_adapter_init(); STREAM_IN_input_stream_adapter_init(); CMSDK_UART0->CTRL = 0; /* Disable UART when changing configuration */ CMSDK_UART0->BAUDDIV = 651; /* 25MHz / 38400 = 651 */ CMSDK_UART0->CTRL = CMSDK_UART_CTRL_TXEN_Msk | CMSDK_UART_CTRL_RXEN_Msk | CMSDK_UART_CTRL_RXIRQEN_Msk; NVIC_ClearPendingIRQ(UART0RX_IRQn); NVIC_EnableIRQ(UART0RX_IRQn); NVIC_ClearPendingIRQ(UART0TX_IRQn); NVIC_EnableIRQ(UART0TX_IRQn); return true; } /** Put a character to the stdout \param[in] ch Character to output \return The character written, or -1 on write error. */ int stdout_putchar (int ch) { while(!STREAM_OUT.Stream.WriteByte(ch)) ; return ch; } int stdin_getchar (void) { uint8_t chByte; while(!STREAM_IN.Stream.ReadByte(&chByte)); return chByte; } ================================================ FILE: example/app_platform/stdout_USART.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_STDOUT_USART_H__ #define __USE_STDOUT_USART_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #ifndef OUTPUT_STREAM_BLOCK_SIZE # define OUTPUT_STREAM_BLOCK_SIZE (32) #endif #ifndef INPUT_STREAM_BLOCK_SIZE # define INPUT_STREAM_BLOCK_SIZE (32) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \note define a buffer for output stream //! @{ EXTERN_OUTPUT_STREAM_BUFFER( STREAM_OUT, OUTPUT_STREAM_BLOCK_SIZE) END_EXTERN_OUTPUT_STREAM_BUFFER( STREAM_OUT) //! \note add an adapter for serial port EXTERN_STREAM_OUT_SERIAL_PORT_ADAPTER( STREAM_OUT) //! @} //! \note define a buffer for input stream //! @{ EXTERN_INPUT_STREAM_BUFFER( STREAM_IN, INPUT_STREAM_BLOCK_SIZE) END_EXTERN_INPUT_STREAM_BUFFER( STREAM_OUT) //! \note add an adapter for serial port EXTERN_STREAM_IN_SERIAL_PORT_ADAPTER( STREAM_IN) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize usart for stdout * \param none * \retval true initialization succeeded. * \retval false initialization failed */ extern bool stdout_init (void); #endif ================================================ FILE: example/build/mdk/Abstract.txt ================================================ The 'Blinky' project is a simple demo program for ARM 'Cortex-M7' microcontroller using ARM 'V2M-MPS2' Evaluation Board. Compliant to Cortex Microcontroller Software Interface Standard (CMSIS). Example functionality: - Clock Settings: - XTAL = 50 MHz - CCLK = 25 MHz - Timer0 is used in interrupt mode - LEDs are blinking with speed depending on Timer0 interrupt period - colour GLCD display shows - init message - Button status - LED status - Touch status - 'Hello World' is output onto serial port USART0 - USART0 settings: 115200 baud, 8 data bits, no parity, 1 stop bit The Blinky program is available in different targets: Simulator: configured for software Simulator FastModels: configured for FastModels MPS2 Simulator V2M-MPS2: configured for MPS2 (uses ULINK2 as debugger) V2M-MPS2 Trace (ETB): configured for MPS2 (uses ULINKpro as debugger) shows use of Embedded Trace Buffer V2M-MPS2 Trace (TPIU): configured for MPS2 (uses ULINKpro as debugger) shows use of 4bit Trace (use CoreSight 20 connector) ================================================ FILE: example/build/mdk/Blinky.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc ; command above MUST be in first line (no comment above!) #define __STACK_SIZE 0x1000 #define __HEAP_SIZE 0x0400 ; ************************************************************* ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* LR_IROM1 0x00000000 0x00400000 { ; load region size_region ER_IROM1 0x00000000 0x00400000 { ; load address = execution address *.o (RESET, +First) * (InRoot$$Sections) * (+RO) } ; Reserve empty region for stack ARM_LIB_STACK 0x20000000 ALIGN 8 EMPTY __STACK_SIZE { } RW_IRAM1 +0 0x00400000 { ; RW data * (+RW +ZI) } RW_IRAM_NO_INIT +0 UNINIT { * (.bss.noinit) } ; Reserve empty region for heap ARM_LIB_HEAP +0 ALIGN 8 EMPTY __HEAP_SIZE { } } ================================================ FILE: example/build/mdk/Blinky.uvguix ================================================ -6.1
### uVision Project, (C) Keil Software
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0 1600 1200 1 0 100 0 .\Abstract.txt 0 1 1 1 0 ================================================ FILE: example/build/mdk/Blinky.uvguix.gabriel ================================================ -6.1
### uVision Project, (C) Keil Software
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0 1440 900 1 0 100 1 RTE\Device\ARMCM4_FP\startup_ARMCM4.s 0 89 108 1 0 ..\..\system.c 4 216 232 1 0 ================================================ FILE: example/build/mdk/Blinky.uvoptx ================================================ 1.0
### uVision Project, (C) Keil Software
*.c *.s*; *.src; *.a* *.obj; *.o *.lib *.txt; *.h; *.inc; *.md *.plm *.cpp 0 0 0 FastModel 0x4 ARM-ADS 12000000 1 1 0 1 0 1 65535 0 0 0 79 66 8 .\Out\ 1 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 1 7 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 5 BIN\DbgFM.DLL 0 DbgFM -I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -PF -MA 0 UL2CM3 UL2CM3(-S0 -C0 -P0 -FC1000 -FD20000000 0 ARMRTXEVENTFLAGS -L70 -Z18 -C0 -M0 -T1 0 DLGTARM (1010=2469,166,2919,723,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=2040,160,2298,748,0)(1012=-1,-1,-1,-1,0) 0 ARMDBGFLAGS 0 DLGUARM (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) 0 1 s_tSTREAM_INStreamInService 1 0 0x200010D8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Source Files 1 0 0 0 1 1 1 0 0 0 ..\..\system.c system.c 0 0 1 2 5 0 0 0 ..\..\app_cfg.h app_cfg.h 0 0 1 3 1 0 0 0 ..\..\menu_example.c menu_example.c 0 0 1 4 1 0 0 0 ..\..\scheduler_example.c scheduler_example.c 0 0 Documentation 1 0 0 0 2 5 5 0 0 0 .\Abstract.txt Abstract.txt 0 0 gmsi 1 0 0 0 3 6 1 0 0 0 ..\..\..\sources\gmsi\utilities\arm\signal.c signal.c 0 0 3 7 1 1 0 0 ..\..\..\sources\gmsi\gmsi.c gmsi.c 0 0 3 8 1 0 0 0 ..\..\..\sources\gmsi\hal\bsp\bsp.c bsp.c 0 0 3 9 1 0 0 0 ..\..\..\sources\gmsi\hal\hal.c hal.c 0 0 3 10 1 0 0 0 ..\..\..\sources\gmsi\hal\component\component.c component.c 0 0 3 11 1 0 0 0 ..\..\..\sources\gmsi\hal\component\bootloader\bootloader.c bootloader.c 0 0 3 12 1 0 0 0 ..\..\..\sources\gmsi\hal\component\key\key.c key.c 0 0 3 13 1 0 0 0 ..\..\..\sources\gmsi\hal\component\key\key_queue\key_queue.c key_queue.c 0 0 3 14 1 0 0 0 ..\..\..\sources\gmsi\hal\component\memory\mal\mal.c mal.c 0 0 3 15 1 0 0 0 ..\..\..\sources\gmsi\hal\component\memory\mal\sdf_w25qxxx\sdf_w25qxxx.c sdf_w25qxxx.c 0 0 3 16 1 0 0 0 ..\..\..\sources\gmsi\hal\component\memory\mal\sram\sram.c sram.c 0 0 3 17 1 0 0 0 ..\..\..\sources\gmsi\hal\component\memory\page\page.c page.c 0 0 3 18 1 0 0 0 ..\..\..\sources\gmsi\hal\component\sw_sdio\sw_sdio.c sw_sdio.c 0 0 3 19 1 0 0 0 ..\..\..\sources\gmsi\service\communication\crc\crc.c crc.c 0 0 3 20 1 0 0 0 ..\..\..\sources\gmsi\service\communication\crc\crc7.c crc7.c 0 0 3 21 1 0 0 0 ..\..\..\sources\gmsi\service\communication\crc\crc8.c crc8.c 0 0 3 22 1 0 0 0 ..\..\..\sources\gmsi\service\communication\crc\crc16.c crc16.c 0 0 3 23 1 0 0 0 ..\..\..\sources\gmsi\service\communication\crc\crc32.c crc32.c 0 0 3 24 1 0 0 0 ..\..\..\sources\gmsi\service\communication\frame\es_simple_frame\es_simple_frame.c es_simple_frame.c 0 0 3 25 1 0 0 0 ..\..\..\sources\gmsi\service\communication\xmodem\xmodem.c xmodem.c 0 0 3 26 1 0 0 0 ..\..\..\sources\gmsi\service\encryption\random\random.c random.c 0 0 3 27 1 0 0 0 ..\..\..\sources\gmsi\service\memory\memory.c memory.c 0 0 3 28 1 0 0 0 ..\..\..\sources\gmsi\service\memory\epool\epool.c epool.c 0 0 3 29 1 0 0 0 ..\..\..\sources\gmsi\service\scheduler\scheduler.c scheduler.c 0 0 3 30 1 0 0 0 ..\..\..\sources\gmsi\service\scheduler\shell.c shell.c 0 0 3 31 1 0 0 0 ..\..\..\sources\gmsi\service\scheduler\task.c task.c 0 0 3 32 1 0 0 0 ..\..\..\sources\gmsi\service\service.c service.c 0 0 3 33 1 0 0 0 ..\..\..\sources\gmsi\service\memory\stream2block\stream2block.c stream2block.c 0 0 3 34 5 0 0 0 ..\..\..\sources\gmsi\service\memory\stream2block\stream2block.h stream2block.h 0 0 3 35 5 0 0 0 ..\..\..\sources\app_cfg.h app_cfg.h 0 0 3 36 1 0 0 0 ..\..\..\sources\gmsi\utilities\template\t_list.c t_list.c 0 0 3 37 5 0 0 0 ..\..\..\sources\gmsi\utilities\template\t_list.h t_list.h 0 0 3 38 5 0 0 0 ..\..\..\sources\gmsi\utilities\template\t_pool.h t_pool.h 0 0 3 39 5 0 0 0 ..\..\..\sources\gmsi\utilities\template\t_queue.h t_queue.h 0 0 3 40 5 0 0 0 ..\..\..\sources\gmsi\utilities\template\template.h template.h 0 0 3 41 1 0 0 0 ..\..\..\sources\gmsi\service\communication\telegraph_engine\telegraph_engine.c telegraph_engine.c 0 0 3 42 5 0 0 0 ..\..\..\sources\gmsi\service\communication\telegraph_engine\telegraph_engine.h telegraph_engine.h 0 0 3 43 1 0 0 0 ..\..\..\sources\gmsi\service\time\time.c time.c 0 0 3 44 5 0 0 0 ..\..\..\sources\gmsi\service\time\time.h time.h 0 0 3 45 1 0 0 0 ..\..\..\sources\gmsi\service\time\multiple_delay\multiple_delay.c multiple_delay.c 0 0 3 46 5 0 0 0 ..\..\..\sources\gmsi\service\time\multiple_delay\multiple_delay.h multiple_delay.h 0 0 3 47 1 0 0 0 ..\..\..\sources\gmsi\service\memory\block_queue\block_queue.c block_queue.c 0 0 3 48 5 0 0 0 ..\..\..\sources\gmsi\service\memory\block_queue\block_queue.h block_queue.h 0 0 3 49 1 0 0 0 ..\..\..\sources\gmsi\service\memory\block\block.c block.c 0 0 3 50 5 0 0 0 ..\..\..\sources\gmsi\service\memory\block\block.h block.h 0 0 3 51 5 0 0 0 ..\..\..\README.md README.md 0 0 3 52 1 0 0 0 ..\..\..\sources\gmsi\utilities\delegate.c delegate.c 0 0 3 53 1 0 0 0 ..\..\..\sources\gmsi\arch\arm\cortex-m\arch_cortex-m.c arch_cortex-m.c 0 0 3 54 4 0 0 0 ..\..\..\sources\gmsi\arch\arm\cortex-m\perf_counter\lib\perf_counter.lib perf_counter.lib 0 0 app_platform 1 0 0 0 4 55 5 0 0 0 ..\..\app_platform\app_platform.h app_platform.h 0 0 4 56 1 0 0 0 ..\..\app_platform\app_platform.c app_platform.c 0 0 4 57 1 0 0 0 ..\..\app_platform\stdout_USART.c stdout_USART.c 0 0 4 58 5 0 0 0 ..\..\app_platform\stdout_USART.h stdout_USART.h 0 0 PLOOC 1 0 0 0 5 59 5 0 0 0 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc.h plooc.h 0 0 5 60 5 0 0 0 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class.h plooc_class.h 0 0 5 61 5 0 0 0 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_black_box.h plooc_class_black_box.h 0 0 5 62 5 0 0 0 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_simple.h plooc_class_simple.h 0 0 5 63 5 0 0 0 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_strict.h plooc_class_strict.h 0 0 ::CMSIS 0 0 0 1 ::Compiler 1 0 0 1 ::Device 1 0 0 1 ================================================ FILE: example/build/mdk/Blinky.uvprojx ================================================ 2.1
### uVision Project, (C) Keil Software
FastModel 0x4 ARM-ADS 6160000::V6.16::ARMCLANG 1 ARMCM4_FP ARM ARM.CMSIS.5.7.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) 0 $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h 0 0 0 0 0 0 1 .\Out\ Blinky 1 0 1 1 1 .\Out\ 1 0 0 0 0 armcc -E ..\..\Blinky.c --c99 -o output.log 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 3 1 SARMCM3.DLL -MPU DCM.DLL -pCM4 SARMCM3.DLL -MPU TCM.DLL -pCM4 1 0 0 0 16 0 1 0 1 0 4096 1 BIN\UL2CM3.DLL 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 "Cortex-M4" 0 0 0 1 1 0 0 2 0 0 0 0 8 1 1 0 0 3 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x20000000 0x20000 1 0x0 0x40000 0 0x0 0x0 1 0x0 0x0 1 0x0 0x0 1 0x0 0x0 1 0x0 0x40000 1 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x20000000 0x20000 0 0x0 0x0 1 6 0 0 1 0 0 0 0 0 3 0 0 1 0 0 6 3 1 1 0 0 0 -fms-extensions __USER_APP_CFG_H__=\"../example/app_cfg.h\" ..\..\..\sources\gmsi 1 0 0 0 0 0 0 0 0 4 0 0 0 0 1 0 0x00000000 0x20000000 .\Blinky.sct --entry=Reset_Handler Source Files system.c 1 ..\..\system.c app_cfg.h 5 ..\..\app_cfg.h menu_example.c 1 ..\..\menu_example.c scheduler_example.c 1 ..\..\scheduler_example.c 2 0 0 0 0 0 2 2 2 2 11 1 2 0 2 2 2 2 2 2 2 2 0 2 2 2 2 2 0 0 2 2 2 2 2 Documentation Abstract.txt 5 .\Abstract.txt gmsi signal.c 1 ..\..\..\sources\gmsi\utilities\arm\signal.c gmsi.c 1 ..\..\..\sources\gmsi\gmsi.c bsp.c 1 ..\..\..\sources\gmsi\hal\bsp\bsp.c hal.c 1 ..\..\..\sources\gmsi\hal\hal.c component.c 1 ..\..\..\sources\gmsi\hal\component\component.c bootloader.c 1 ..\..\..\sources\gmsi\hal\component\bootloader\bootloader.c key.c 1 ..\..\..\sources\gmsi\hal\component\key\key.c key_queue.c 1 ..\..\..\sources\gmsi\hal\component\key\key_queue\key_queue.c mal.c 1 ..\..\..\sources\gmsi\hal\component\memory\mal\mal.c sdf_w25qxxx.c 1 ..\..\..\sources\gmsi\hal\component\memory\mal\sdf_w25qxxx\sdf_w25qxxx.c sram.c 1 ..\..\..\sources\gmsi\hal\component\memory\mal\sram\sram.c page.c 1 ..\..\..\sources\gmsi\hal\component\memory\page\page.c sw_sdio.c 1 ..\..\..\sources\gmsi\hal\component\sw_sdio\sw_sdio.c crc.c 1 ..\..\..\sources\gmsi\service\communication\crc\crc.c crc7.c 1 ..\..\..\sources\gmsi\service\communication\crc\crc7.c crc8.c 1 ..\..\..\sources\gmsi\service\communication\crc\crc8.c crc16.c 1 ..\..\..\sources\gmsi\service\communication\crc\crc16.c crc32.c 1 ..\..\..\sources\gmsi\service\communication\crc\crc32.c es_simple_frame.c 1 ..\..\..\sources\gmsi\service\communication\frame\es_simple_frame\es_simple_frame.c xmodem.c 1 ..\..\..\sources\gmsi\service\communication\xmodem\xmodem.c random.c 1 ..\..\..\sources\gmsi\service\encryption\random\random.c memory.c 1 ..\..\..\sources\gmsi\service\memory\memory.c epool.c 1 ..\..\..\sources\gmsi\service\memory\epool\epool.c scheduler.c 1 ..\..\..\sources\gmsi\service\scheduler\scheduler.c shell.c 1 ..\..\..\sources\gmsi\service\scheduler\shell.c task.c 1 ..\..\..\sources\gmsi\service\scheduler\task.c service.c 1 ..\..\..\sources\gmsi\service\service.c stream2block.c 1 ..\..\..\sources\gmsi\service\memory\stream2block\stream2block.c stream2block.h 5 ..\..\..\sources\gmsi\service\memory\stream2block\stream2block.h app_cfg.h 5 ..\..\..\sources\app_cfg.h t_list.c 1 ..\..\..\sources\gmsi\utilities\template\t_list.c t_list.h 5 ..\..\..\sources\gmsi\utilities\template\t_list.h t_pool.h 5 ..\..\..\sources\gmsi\utilities\template\t_pool.h t_queue.h 5 ..\..\..\sources\gmsi\utilities\template\t_queue.h template.h 5 ..\..\..\sources\gmsi\utilities\template\template.h telegraph_engine.c 1 ..\..\..\sources\gmsi\service\communication\telegraph_engine\telegraph_engine.c telegraph_engine.h 5 ..\..\..\sources\gmsi\service\communication\telegraph_engine\telegraph_engine.h time.c 1 ..\..\..\sources\gmsi\service\time\time.c time.h 5 ..\..\..\sources\gmsi\service\time\time.h multiple_delay.c 1 ..\..\..\sources\gmsi\service\time\multiple_delay\multiple_delay.c multiple_delay.h 5 ..\..\..\sources\gmsi\service\time\multiple_delay\multiple_delay.h block_queue.c 1 ..\..\..\sources\gmsi\service\memory\block_queue\block_queue.c block_queue.h 5 ..\..\..\sources\gmsi\service\memory\block_queue\block_queue.h block.c 1 ..\..\..\sources\gmsi\service\memory\block\block.c block.h 5 ..\..\..\sources\gmsi\service\memory\block\block.h README.md 5 ..\..\..\README.md delegate.c 1 ..\..\..\sources\gmsi\utilities\delegate.c arch_cortex-m.c 1 ..\..\..\sources\gmsi\arch\arm\cortex-m\arch_cortex-m.c perf_counter.lib 4 ..\..\..\sources\gmsi\arch\arm\cortex-m\perf_counter\lib\perf_counter.lib app_platform app_platform.h 5 ..\..\app_platform\app_platform.h app_platform.c 1 ..\..\app_platform\app_platform.c stdout_USART.c 1 ..\..\app_platform\stdout_USART.c stdout_USART.h 5 ..\..\app_platform\stdout_USART.h PLOOC plooc.h 5 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc.h plooc_class.h 5 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class.h plooc_class_black_box.h 5 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_black_box.h plooc_class_simple.h 5 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_simple.h plooc_class_strict.h 5 ..\..\..\sources\gmsi\utilities\3rd-party\PLOOC\plooc_class_strict.h ::CMSIS ::Compiler ::Device RTE\Board_Support\MK64FN1M0xxx12\board.c RTE\Board_Support\MK64FN1M0xxx12\board.h RTE\Board_Support\MK64FN1M0xxx12\clock_config.c RTE\Board_Support\MK64FN1M0xxx12\clock_config.h RTE\Board_Support\MK64FN1M0xxx12\peripherals.c RTE\Board_Support\MK64FN1M0xxx12\peripherals.h RTE\Board_Support\MK64FN1M0xxx12\pin_mux.c RTE\Board_Support\MK64FN1M0xxx12\pin_mux.h RTE\Board_Support\board.c RTE\Board_Support\board.h RTE\Board_Support\clock_config.c RTE\Board_Support\clock_config.h RTE\Board_Support\peripherals.c RTE\Board_Support\peripherals.h RTE\Board_Support\pin_mux.c RTE\Board_Support\pin_mux.h RTE\Device\ARMCM4_FP\startup_ARMCM4.s RTE\Device\ARMCM4_FP\system_ARMCM4.c RTE\Device\CMSDK_CM3\startup_CMSDK_CM3.s RTE\Device\CMSDK_CM3\system_CMSDK_CM3.c RTE\Device\CMSDK_CM4\startup_CMSDK_CM4.s RTE\Device\CMSDK_CM4\system_CMSDK_CM4.c RTE\Device\CMSDK_CM4_FP\RTE_Device.h RTE\Device\CMSDK_CM4_FP\startup_CMSDK_CM4.s RTE\Device\CMSDK_CM4_FP\system_CMSDK_CM4.c RTE\Device\CMSDK_CM7_DP\RTE_Device.h RTE\Device\CMSDK_CM7_DP\startup_CMSDK_CM7.s RTE\Device\CMSDK_CM7_DP\system_CMSDK_CM7.c RTE\Device\CMSDK_CM7_SP\RTE_Device.h RTE\Device\CMSDK_CM7_SP\startup_CMSDK_CM7.s RTE\Device\CMSDK_CM7_SP\system_CMSDK_CM7.c RTE\Device\CMSDK_Pelican\startup_CMSDK_Pelican.s RTE\Device\CMSDK_Pelican\system_CMSDK_Pelican.c RTE\Device\MK64FN1M0xxx12\MK64F12.h RTE\Device\MK64FN1M0xxx12\MK64F12_features.h RTE\Device\MK64FN1M0xxx12\MK64FN1M0xxx12_flash.scf RTE\Device\MK64FN1M0xxx12\MK64FN1M0xxx12_ram.scf RTE\Device\MK64FN1M0xxx12\RTE_Device.h RTE\Device\MK64FN1M0xxx12\fsl_device_registers.h RTE\Device\MK64FN1M0xxx12\startup_MK64F12.s RTE\Device\MK64FN1M0xxx12\system_MK64F12.c RTE\Device\MK64FN1M0xxx12\system_MK64F12.h Blinky 1 ================================================ FILE: example/build/mdk/Dbg_MPS2.ini ================================================ /*---------------------------------------------------------------------------- * Name: Dbg_MPS2.ini * Purpose: MPS2 Debug Initialization File * Note(s): *---------------------------------------------------------------------------- * This file is part of the uVision/ARM development tools. * This software may only be used under the terms of a valid, current, * end user licence from KEIL for a compatible version of KEIL software * development tools. Nothing else gives you the right to use this software. * * This software is supplied "AS IS" without warranties of any kind. * * Copyright (c) 2013 Keil - An ARM Company. All rights reserved. *----------------------------------------------------------------------------*/ _WDWORD(0x4001F000, 0x00000001); // Remap on ================================================ FILE: example/build/mdk/Dbg_Sim.ini ================================================ /*---------------------------------------------------------------------------- * Name: Dbg_Sim.ini * Purpose: Simulation Debug Initialization File * Note(s): *---------------------------------------------------------------------------- * This file is part of the uVision/ARM development tools. * This software may only be used under the terms of a valid, current, * end user licence from KEIL for a compatible version of KEIL software * development tools. Nothing else gives you the right to use this software. * * This software is supplied "AS IS" without warranties of any kind. * * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. *----------------------------------------------------------------------------*/ MAP 0x40028000, 0x40028FFF READ WRITE // FPGA address space MAP 0x4002F000, 0x4002FFFF READ WRITE // SCC address space MAP 0x40021000, 0x40021FFF READ WRITE // SSP0 address space ================================================ FILE: example/build/mdk/EventRecorderStub.scvd ================================================ ================================================ FILE: example/build/mdk/FVP_cfg.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.telnetterminal0.mode="raw" # (string, init-time) default = 'telnet' : Terminal initialisation mode fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) fvp_mps2.telnetterminal1.mode="raw" # (string, init-time) default = 'telnet' : Terminal initialisation mode fvp_mps2.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected fvp_mps2.telnetterminal1.start_port=0x1389 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) fvp_mps2.telnetterminal2.mode="raw" # (string, init-time) default = 'telnet' : Terminal initialisation mode fvp_mps2.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected fvp_mps2.telnetterminal2.start_port=0x138A # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted #---------------------------------------------------------------------------------------------- ================================================ FILE: example/build/mdk/MPS2_CS_ETB.ini ================================================ FUNC void SetupETB() { unsigned int value; // Disable ITM/DWT flush when using TMC/ETB //value = _RDWORD(0xE000E008); //value |= (1UL << 12); //_WDWORD(0xE000E008, value); // Disable TPIU Funnel value = _RDWORD(0xE00F1000); value &= 0x0000F00; _WDWORD(0xE00F1000, value); // Set TMC Funnel priorities _WDWORD(0xE00F3004, 0x00000D1); // Port 0 (ETM-I) - prio 0, Port 1 (ETM-D) - prio 1, Port 2 (ITM) - prio 2 value = _RDWORD(0xE00F3000); // Read Hold Time value &= 0xFFFFFF00; value |= 0x00000007; // Enable ATB Slave Ports: Port 0 (ETM-I), Port 1: ETM-D, Port 2: ITM _WDWORD(0xE00F3000, value); } FUNC void SetupMPS2() { // SP = _RDWORD(0x20000000); // Setup Stack Pointer // PC = _RDWORD(0x20000004); // Setup Program Counter // _WDWORD(0xE000ED08, 0x20000000); // Setup Vector Table Offset Register } FUNC void OnResetExec() { // _WDWORD(0x4001F000, 0x00000000); // Remap off _WDWORD(0x4001F000, 0x00000001); // Remap on SetupMPS2(); SetupETB(); } //LOAD %L INCREMENTAL OnResetExec(); ================================================ FILE: example/build/mdk/MPS2_CS_TPIU.ini ================================================ FUNC void SetupTPIU() { unsigned int value; // TPIU Funnel Setup _WDWORD(0xE00F1004, 0x00000D1); // Port 0 (ETM-I) - prio 0, Port 1 (ETM-D) - prio 1, Port 2 (ITM) - prio 2 value = _RDWORD(0xE00F1000); // Read Hold Time value &= 0xFFFFFF00; value |= 0x00000007; // Enable ATB Slave Ports: Port 0 (ETM-I), Port 1: ETM-D, Port 2: ITM _WDWORD(0xE00F1000, value); // Disable TMC Funnel value = _RDWORD(0xE00F3000); value &= 0x0000F00; _WDWORD(0xE00F3000, value); } FUNC void SetupMPS2() { // SP = _RDWORD(0x20000000); // Setup Stack Pointer // PC = _RDWORD(0x20000004); // Setup Program Counter // _WDWORD(0xE000ED08, 0x20000000); // Setup Vector Table Offset Register } FUNC void OnResetExec() { // _WDWORD(0x4001F000, 0x00000000); // Remap off _WDWORD(0x4001F000, 0x00000001); // Remap on SetupMPS2(); SetupTPIU(); } //LOAD %L INCREMENTAL OnResetExec(); //g, main ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/board.c ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "fsl_common.h" //#include "fsl_debug_console.h" #include "board.h" #if false /* Initialize debug console. */ void BOARD_InitDebugConsole(void) { uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); } #endif ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/board.h ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _BOARD_H_ #define _BOARD_H_ #include "clock_config.h" #include "fsl_gpio.h" /******************************************************************************* * Definitions ******************************************************************************/ /* The board name */ #define BOARD_NAME "FRDM-K64F" /* The UART to use for debug messages. */ #define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART #define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0 #define BOARD_DEBUG_UART_INSTANCE 0U #define BOARD_DEBUG_UART_CLKSRC SYS_CLK #define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetCoreSysClkFreq() #define BOARD_UART_IRQ UART0_RX_TX_IRQn #define BOARD_UART_IRQ_HANDLER UART0_RX_TX_IRQHandler #ifndef BOARD_DEBUG_UART_BAUDRATE #define BOARD_DEBUG_UART_BAUDRATE 115200 #endif /* BOARD_DEBUG_UART_BAUDRATE */ /* Board led color mapping */ #define LOGIC_LED_ON 0U #define LOGIC_LED_OFF 1U #ifndef BOARD_LED_RED_GPIO #define BOARD_LED_RED_GPIO GPIOB #endif #define BOARD_LED_RED_GPIO_PORT PORTB #ifndef BOARD_LED_RED_GPIO_PIN #define BOARD_LED_RED_GPIO_PIN 22U #endif #ifndef BOARD_LED_GREEN_GPIO #define BOARD_LED_GREEN_GPIO GPIOE #endif #define BOARD_LED_GREEN_GPIO_PORT PORTE #ifndef BOARD_LED_GREEN_GPIO_PIN #define BOARD_LED_GREEN_GPIO_PIN 26U #endif #ifndef BOARD_LED_BLUE_GPIO #define BOARD_LED_BLUE_GPIO GPIOB #endif #define BOARD_LED_BLUE_GPIO_PORT PORTB #ifndef BOARD_LED_BLUE_GPIO_PIN #define BOARD_LED_BLUE_GPIO_PIN 21U #endif #define LED_RED_INIT(output) \ GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ #define LED_RED_ON() \ GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ #define LED_RED_OFF() \ GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ #define LED_RED_TOGGLE() \ GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ #define LED_GREEN_INIT(output) \ GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ #define LED_GREEN_ON() \ GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ #define LED_GREEN_OFF() \ GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ #define LED_GREEN_TOGGLE() \ GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ #define LED_BLUE_INIT(output) \ GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ #define LED_BLUE_ON() \ GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ #define LED_BLUE_OFF() \ GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ #define LED_BLUE_TOGGLE() \ GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ /* The SDHC instance/channel used for board */ #define BOARD_SDHC_CD_GPIO_IRQ_HANDLER PORTB_IRQHandler /* SDHC base address, clock and card detection pin */ #define BOARD_SDHC_BASEADDR SDHC #define BOARD_SDHC_CLKSRC kCLOCK_CoreSysClk #define BOARD_SDHC_CLK_FREQ CLOCK_GetFreq(kCLOCK_CoreSysClk) #define BOARD_SDHC_IRQ SDHC_IRQn #define BOARD_SDHC_CD_GPIO_BASE GPIOE #ifndef BOARD_SDHC_CD_GPIO_PIN #define BOARD_SDHC_CD_GPIO_PIN 6U #endif #define BOARD_SDHC_CD_PORT_BASE PORTE #define BOARD_SDHC_CD_PORT_IRQ PORTE_IRQn #define BOARD_SDHC_CD_PORT_IRQ_HANDLER PORTE_IRQHandler #define BOARD_SDHC_CD_LOGIC_RISING #define BOARD_ACCEL_I2C_BASEADDR I2C0 /* ERPC DSPI configuration */ #define ERPC_BOARD_DSPI_BASEADDR SPI0 #define ERPC_BOARD_DSPI_BAUDRATE 500000U #define ERPC_BOARD_DSPI_CLKSRC DSPI0_CLK_SRC #define ERPC_BOARD_DSPI_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC) #define ERPC_BOARD_DSPI_INT_GPIO GPIOB #define ERPC_BOARD_DSPI_INT_PORT PORTB #define ERPC_BOARD_DSPI_INT_PIN 2U #define ERPC_BOARD_DSPI_INT_PIN_IRQ PORTB_IRQn #define ERPC_BOARD_DSPI_INT_PIN_IRQ_HANDLER PORTB_IRQHandler /* DAC base address */ #define BOARD_DAC_BASEADDR DAC0 /* Board accelerometer driver */ #define BOARD_ACCEL_FXOS #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ /******************************************************************************* * API ******************************************************************************/ void BOARD_InitDebugConsole(void); #if defined(__cplusplus) } #endif /* __cplusplus */ #endif /* _BOARD_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/clock_config.c ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * How to setup clock using clock driver functions: * * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock * and flash clock are in allowed range during clock mode switch. * * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. * * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and * internal reference clock(MCGIRCLK). Follow the steps to setup: * * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. * * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig * explicitly to setup MCGIRCLK. * * 3). Don't need to configure FLL explicitly, because if target mode is FLL * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, * if the target mode is not FLL mode, the FLL is disabled. * * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. * * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. */ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!ClocksProfile product: Clocks v1.0 processor: MK64FN1M0xxx12 package_id: MK64FN1M0VLL12 mcu_data: ksdk2_0 processor_version: 1.0.1 board: FRDM-K64F * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ #include "fsl_smc.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */ #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ /******************************************************************************* * Variables ******************************************************************************/ /* System clock frequency. */ extern uint32_t SystemCoreClock; /******************************************************************************* * Code ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockRUN(); } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetFllExtRefDiv * Description : Configure FLL external reference divider (FRDIV). * Param frdiv : The value to set FRDIV. * *END**************************************************************************/ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) { MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); } /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!Configuration name: BOARD_BootClockRUN outputs: - {id: Bus_clock.outFreq, value: 60 MHz} - {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'} - {id: Flash_clock.outFreq, value: 24 MHz} - {id: FlexBus_clock.outFreq, value: 40 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGFFCLK.outFreq, value: 1.5625 MHz} - {id: MCGIRCLK.outFreq, value: 32.768 kHz} - {id: OSCERCLK.outFreq, value: 50 MHz} - {id: PLLFLLCLK.outFreq, value: 120 MHz} - {id: System_clock.outFreq, value: 120 MHz} settings: - {id: MCGMode, value: PEE} - {id: MCG.FCRDIV.scale, value: '1', locked: true} - {id: MCG.FRDIV.scale, value: '32'} - {id: MCG.IREFS.sel, value: MCG.FRDIV} - {id: MCG.PLLS.sel, value: MCG.PLL} - {id: MCG.PRDIV.scale, value: '20', locked: true} - {id: MCG.VDIV.scale, value: '48', locked: true} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: OSC_CR_ERCLKEN_CFG, value: Enabled} - {id: RTCCLKOUTConfig, value: 'yes'} - {id: RTC_CR_OSCE_CFG, value: Enabled} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF} - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.OUTDIV2.scale, value: '2'} - {id: SIM.OUTDIV3.scale, value: '3'} - {id: SIM.OUTDIV4.scale, value: '5'} - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK} - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK} - {id: SIM.USBDIV.scale, value: '5'} - {id: SIM.USBFRAC.scale, value: '2'} - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV} sources: - {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockRUN = { .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .prdiv = 0x13U, /* PLL Reference divider: divided by 20 */ .vdiv = 0x18U, /* VCO divider: multiplied by 48 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { .freq = 50000000U, /* Oscillator frequency: 50000000Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ } }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Initializes OSC0 according to board configuration. */ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); /* Configure the Internal Reference clock (MCGIRCLK). */ CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs, mcgConfig_BOARD_BootClockRUN.fcrdiv); /* Configure FLL external reference divider (FRDIV). */ CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); /* Set MCG to PEE mode. */ CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockRUN.pll0Config); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } /******************************************************************************* ********************* Configuration BOARD_BootClockVLPR *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!Configuration name: BOARD_BootClockVLPR outputs: - {id: Bus_clock.outFreq, value: 4 MHz} - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'} - {id: Flash_clock.outFreq, value: 800 kHz} - {id: FlexBus_clock.outFreq, value: 4 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGIRCLK.outFreq, value: 4 MHz} - {id: System_clock.outFreq, value: 4 MHz} settings: - {id: MCGMode, value: BLPI} - {id: powerMode, value: VLPR} - {id: MCG.CLKS.sel, value: MCG.IRCS} - {id: MCG.FCRDIV.scale, value: '1'} - {id: MCG.FRDIV.scale, value: '32'} - {id: MCG.IRCS.sel, value: MCG.FCRDIV} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: RTC_CR_OSCE_CFG, value: Enabled} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF} - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.OUTDIV3.scale, value: '1'} - {id: SIM.OUTDIV4.scale, value: '5'} - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK} - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} sources: - {id: OSC.OSC.outFreq, value: 50 MHz} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ /******************************************************************************* * Variables for BOARD_BootClockVLPR configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockVLPR = { .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */ .vdiv = 0x0U, /* VCO divider: multiplied by 24 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockVLPR = { .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */ }; const osc_config_t oscConfig_BOARD_BootClockVLPR = { .freq = 0U, /* Oscillator frequency: 0Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ } }; /******************************************************************************* * Code for BOARD_BootClockVLPR configuration ******************************************************************************/ void BOARD_BootClockVLPR(void) { /* Set the system clock dividers in SIM to safe value. */ CLOCK_SetSimSafeDivs(); /* Set MCG to BLPI mode. */ CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs, mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); /* Set VLPR power mode. */ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) SMC_SetPowerModeVlpr(SMC, false); #else SMC_SetPowerModeVlpr(SMC); #endif while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) { } /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/clock_config.h ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _CLOCK_CONFIG_H_ #define _CLOCK_CONFIG_H_ #include "fsl_common.h" /******************************************************************************* * Definitions ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes default configuration of clocks. * */ void BOARD_InitBootClocks(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ #define BOARD_XTAL0_CLK_HZ 50000000U /*!< Board xtal0 frequency in Hz */ /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /******************************************************************************* * Definitions for BOARD_BootClockRUN configuration ******************************************************************************/ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ /*! @brief MCG set for BOARD_BootClockRUN configuration. */ extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; /*! @brief SIM module set for BOARD_BootClockRUN configuration. */ extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; /*! @brief OSC set for BOARD_BootClockRUN configuration. */ extern const osc_config_t oscConfig_BOARD_BootClockRUN; /******************************************************************************* * API for BOARD_BootClockRUN configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes configuration of clocks. * */ void BOARD_BootClockRUN(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ /******************************************************************************* ********************* Configuration BOARD_BootClockVLPR *********************** ******************************************************************************/ /******************************************************************************* * Definitions for BOARD_BootClockVLPR configuration ******************************************************************************/ #define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */ /*! @brief MCG set for BOARD_BootClockVLPR configuration. */ extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR; /*! @brief SIM module set for BOARD_BootClockVLPR configuration. */ extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR; /*! @brief OSC set for BOARD_BootClockVLPR configuration. */ extern const osc_config_t oscConfig_BOARD_BootClockVLPR; /******************************************************************************* * API for BOARD_BootClockVLPR configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes configuration of clocks. * */ void BOARD_BootClockVLPR(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ #endif /* _CLOCK_CONFIG_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/peripherals.c ================================================ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Peripherals v1.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Included files ******************************************************************************/ #include "peripherals.h" /******************************************************************************* * BOARD_InitBootPeripherals function ******************************************************************************/ void BOARD_InitBootPeripherals(void) { } ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/peripherals.h ================================================ #ifndef _PERIPHERALS_H_ #define _PERIPHERALS_H_ #if defined(__cplusplus) extern "C" { #endif /*_cplusplus. */ /******************************************************************************* * BOARD_InitBootPeripherals function ******************************************************************************/ void BOARD_InitBootPeripherals(void); #if defined(__cplusplus) } #endif /*_cplusplus. */ #endif /* _PERIPHERALS_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/pin_mux.c ================================================ /* * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Pins v3.0 processor: MK64FN1M0xxx12 package_id: MK64FN1M0VLL12 mcu_data: ksdk2_0 processor_version: 2.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ #include "fsl_common.h" #include "fsl_port.h" #include "pin_mux.h" /*FUNCTION********************************************************************** * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. * *END**************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); } #define PIN16_IDX 16u /*!< Pin number for pin 16 in a port */ #define PIN17_IDX 17u /*!< Pin number for pin 17 in a port */ #define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART 0 transmit data source select: UART0_TX pin */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN} - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /*FUNCTION********************************************************************** * * Function Name : BOARD_InitPins * Description : Configures pin routing and optionally pin electrical features. * *END**************************************************************************/ void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_PortB); /* Port B Clock Gate Control: Clock enabled */ PORT_SetPinMux(PORTB, PIN16_IDX, kPORT_MuxAlt3); /* PORTB16 (pin 62) is configured as UART0_RX */ PORT_SetPinMux(PORTB, PIN17_IDX, kPORT_MuxAlt3); /* PORTB17 (pin 63) is configured as UART0_TX */ SIM->SOPT5 = ((SIM->SOPT5 & (~(SIM_SOPT5_UART0TXSRC_MASK))) /* Mask bits to zero which are setting */ | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) /* UART 0 transmit data source select: UART0_TX pin */ ); } /******************************************************************************* * EOF ******************************************************************************/ ================================================ FILE: example/build/mdk/RTE/Board_Support/MK64FN1M0xxx12/pin_mux.h ================================================ /* * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ /******************************************************************************* * Definitions ******************************************************************************/ /*! @brief Direction type */ typedef enum _pin_mux_direction { kPIN_MUX_DirectionInput = 0U, /* Input direction */ kPIN_MUX_DirectionOutput = 1U, /* Output direction */ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ } pin_mux_direction_t; /*! * @addtogroup pin_mux * @{ */ /******************************************************************************* * API ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /*! * @brief Calls initialization functions. * */ void BOARD_InitBootPins(void); /*! * @brief Configures pin routing and optionally pin electrical features. * */ void BOARD_InitPins(void); #if defined(__cplusplus) } #endif /*! * @} */ #endif /* _PIN_MUX_H_ */ /******************************************************************************* * EOF ******************************************************************************/ ================================================ FILE: example/build/mdk/RTE/Board_Support/board.c ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "fsl_common.h" #include "fsl_debug_console.h" #include "board.h" /* Initialize debug console. */ void BOARD_InitDebugConsole(void) { // s } ================================================ FILE: example/build/mdk/RTE/Board_Support/board.h ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _BOARD_H_ #define _BOARD_H_ #include "clock_config.h" #include "fsl_gpio.h" /******************************************************************************* * Definitions ******************************************************************************/ /* The board name */ /* The UART to use for debug messages. */ #define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART #define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0 #define BOARD_DEBUG_UART_INSTANCE 0U #define BOARD_DEBUG_UART_CLKSRC SYS_CLK #define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetCoreSysClkFreq() #define BOARD_UART_IRQ UART0_RX_TX_IRQn #define BOARD_UART_IRQ_HANDLER UART0_RX_TX_IRQHandler #ifndef BOARD_DEBUG_UART_BAUDRATE #define BOARD_DEBUG_UART_BAUDRATE 115200 #endif /* BOARD_DEBUG_UART_BAUDRATE */ /* Board led color mapping */ #define LOGIC_LED_ON 0U #define LOGIC_LED_OFF 1U #ifndef BOARD_LED_RED_GPIO #define BOARD_LED_RED_GPIO GPIOB #endif #define BOARD_LED_RED_GPIO_PORT PORTB #ifndef BOARD_LED_RED_GPIO_PIN #define BOARD_LED_RED_GPIO_PIN 22U #endif #ifndef BOARD_LED_GREEN_GPIO #define BOARD_LED_GREEN_GPIO GPIOE #endif #define BOARD_LED_GREEN_GPIO_PORT PORTE #ifndef BOARD_LED_GREEN_GPIO_PIN #define BOARD_LED_GREEN_GPIO_PIN 26U #endif #ifndef BOARD_LED_BLUE_GPIO #define BOARD_LED_BLUE_GPIO GPIOB #endif #define BOARD_LED_BLUE_GPIO_PORT PORTB #ifndef BOARD_LED_BLUE_GPIO_PIN #define BOARD_LED_BLUE_GPIO_PIN 21U #endif #define LED_RED_INIT(output) \ GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ #define LED_RED_ON() \ GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ #define LED_RED_OFF() \ GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ #define LED_RED_TOGGLE() \ GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ #define LED_GREEN_INIT(output) \ GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ #define LED_GREEN_ON() \ GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ #define LED_GREEN_OFF() \ GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ #define LED_GREEN_TOGGLE() \ GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ #define LED_BLUE_INIT(output) \ GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ #define LED_BLUE_ON() \ GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ #define LED_BLUE_OFF() \ GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ #define LED_BLUE_TOGGLE() \ GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ /* The SDHC instance/channel used for board */ #define BOARD_SDHC_CD_GPIO_IRQ_HANDLER PORTB_IRQHandler /* SDHC base address, clock and card detection pin */ #define BOARD_SDHC_BASEADDR SDHC #define BOARD_SDHC_CLKSRC kCLOCK_CoreSysClk #define BOARD_SDHC_CLK_FREQ CLOCK_GetFreq(kCLOCK_CoreSysClk) #define BOARD_SDHC_IRQ SDHC_IRQn #define BOARD_SDHC_CD_GPIO_BASE GPIOE #ifndef BOARD_SDHC_CD_GPIO_PIN #define BOARD_SDHC_CD_GPIO_PIN 6U #endif #define BOARD_SDHC_CD_PORT_BASE PORTE #define BOARD_SDHC_CD_PORT_IRQ PORTE_IRQn #define BOARD_SDHC_CD_PORT_IRQ_HANDLER PORTE_IRQHandler #define BOARD_SDHC_CD_LOGIC_RISING #define BOARD_ACCEL_I2C_BASEADDR I2C0 /* ERPC DSPI configuration */ #define ERPC_BOARD_DSPI_BASEADDR SPI0 #define ERPC_BOARD_DSPI_BAUDRATE 500000U #define ERPC_BOARD_DSPI_CLKSRC DSPI0_CLK_SRC #define ERPC_BOARD_DSPI_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC) #define ERPC_BOARD_DSPI_INT_GPIO GPIOB #define ERPC_BOARD_DSPI_INT_PORT PORTB #define ERPC_BOARD_DSPI_INT_PIN 2U #define ERPC_BOARD_DSPI_INT_PIN_IRQ PORTB_IRQn #define ERPC_BOARD_DSPI_INT_PIN_IRQ_HANDLER PORTB_IRQHandler /* DAC base address */ #define BOARD_DAC_BASEADDR DAC0 /* Board accelerometer driver */ #define BOARD_ACCEL_FXOS #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ /******************************************************************************* * API ******************************************************************************/ void BOARD_InitDebugConsole(void); #if defined(__cplusplus) } #endif /* __cplusplus */ #endif /* _BOARD_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/clock_config.c ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * How to setup clock using clock driver functions: * * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock * and flash clock are in allowed range during clock mode switch. * * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. * * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and * internal reference clock(MCGIRCLK). Follow the steps to setup: * * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. * * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig * explicitly to setup MCGIRCLK. * * 3). Don't need to configure FLL explicitly, because if target mode is FLL * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, * if the target mode is not FLL mode, the FLL is disabled. * * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. * * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. */ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!ClocksProfile product: Clocks v1.0 processor: MK64FN1M0xxx12 package_id: MK64FN1M0VLL12 mcu_data: ksdk2_0 processor_version: 1.0.1 board: FRDM-K64F * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ // #include "fsl_smc.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */ #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ /******************************************************************************* * Variables ******************************************************************************/ /* System clock frequency. */ // extern uint32_t SystemCoreClock; /******************************************************************************* * Code ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { // BOARD_BootClockRUN(); } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetFllExtRefDiv * Description : Configure FLL external reference divider (FRDIV). * Param frdiv : The value to set FRDIV. * *END**************************************************************************/ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) { // MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); } /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!Configuration name: BOARD_BootClockRUN outputs: - {id: Bus_clock.outFreq, value: 60 MHz} - {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'} - {id: Flash_clock.outFreq, value: 24 MHz} - {id: FlexBus_clock.outFreq, value: 40 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGFFCLK.outFreq, value: 1.5625 MHz} - {id: MCGIRCLK.outFreq, value: 32.768 kHz} - {id: OSCERCLK.outFreq, value: 50 MHz} - {id: PLLFLLCLK.outFreq, value: 120 MHz} - {id: System_clock.outFreq, value: 120 MHz} settings: - {id: MCGMode, value: PEE} - {id: MCG.FCRDIV.scale, value: '1', locked: true} - {id: MCG.FRDIV.scale, value: '32'} - {id: MCG.IREFS.sel, value: MCG.FRDIV} - {id: MCG.PLLS.sel, value: MCG.PLL} - {id: MCG.PRDIV.scale, value: '20', locked: true} - {id: MCG.VDIV.scale, value: '48', locked: true} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: OSC_CR_ERCLKEN_CFG, value: Enabled} - {id: RTCCLKOUTConfig, value: 'yes'} - {id: RTC_CR_OSCE_CFG, value: Enabled} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF} - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.OUTDIV2.scale, value: '2'} - {id: SIM.OUTDIV3.scale, value: '3'} - {id: SIM.OUTDIV4.scale, value: '5'} - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK} - {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK} - {id: SIM.USBDIV.scale, value: '5'} - {id: SIM.USBFRAC.scale, value: '2'} - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV} sources: - {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockRUN = { .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .prdiv = 0x13U, /* PLL Reference divider: divided by 20 */ .vdiv = 0x18U, /* VCO divider: multiplied by 48 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { .freq = 50000000U, /* Oscillator frequency: 50000000Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ } }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { // /* Set the system clock dividers in SIM to safe value. */ // CLOCK_SetSimSafeDivs(); // /* Initializes OSC0 according to board configuration. */ // CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); // CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); // /* Configure the Internal Reference clock (MCGIRCLK). */ // CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, // mcgConfig_BOARD_BootClockRUN.ircs, // mcgConfig_BOARD_BootClockRUN.fcrdiv); // /* Configure FLL external reference divider (FRDIV). */ // CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); // /* Set MCG to PEE mode. */ // CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, // kMCG_PllClkSelPll0, // &mcgConfig_BOARD_BootClockRUN.pll0Config); // /* Set the clock configuration in SIM module. */ // CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); // /* Set SystemCoreClock variable. */ // SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } /******************************************************************************* ********************* Configuration BOARD_BootClockVLPR *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!Configuration name: BOARD_BootClockVLPR outputs: - {id: Bus_clock.outFreq, value: 4 MHz} - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'} - {id: Flash_clock.outFreq, value: 800 kHz} - {id: FlexBus_clock.outFreq, value: 4 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGIRCLK.outFreq, value: 4 MHz} - {id: System_clock.outFreq, value: 4 MHz} settings: - {id: MCGMode, value: BLPI} - {id: powerMode, value: VLPR} - {id: MCG.CLKS.sel, value: MCG.IRCS} - {id: MCG.FCRDIV.scale, value: '1'} - {id: MCG.FRDIV.scale, value: '32'} - {id: MCG.IRCS.sel, value: MCG.FCRDIV} - {id: MCG_C1_IRCLKEN_CFG, value: Enabled} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: RTC_CR_OSCE_CFG, value: Enabled} - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF} - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK} - {id: SIM.OUTDIV3.scale, value: '1'} - {id: SIM.OUTDIV4.scale, value: '5'} - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK} - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK} sources: - {id: OSC.OSC.outFreq, value: 50 MHz} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ /******************************************************************************* * Variables for BOARD_BootClockVLPR configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockVLPR = { .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ .drs = kMCG_DrsLow, /* Low frequency range */ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ .pll0Config = { .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */ .vdiv = 0x0U, /* VCO divider: multiplied by 24 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockVLPR = { .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */ }; const osc_config_t oscConfig_BOARD_BootClockVLPR = { .freq = 0U, /* Oscillator frequency: 0Hz */ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ .workMode = kOSC_ModeExt, /* Use external clock */ .oscerConfig = { .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */ } }; /******************************************************************************* * Code for BOARD_BootClockVLPR configuration ******************************************************************************/ void BOARD_BootClockVLPR(void) { /* Set the system clock dividers in SIM to safe value. */ // CLOCK_SetSimSafeDivs(); // /* Set MCG to BLPI mode. */ // CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, // mcgConfig_BOARD_BootClockVLPR.ircs, // mcgConfig_BOARD_BootClockVLPR.irclkEnableMode); // /* Set the clock configuration in SIM module. */ // CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR); // /* Set VLPR power mode. */ // SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); // #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) // SMC_SetPowerModeVlpr(SMC, false); // #else // SMC_SetPowerModeVlpr(SMC); // #endif // while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) // { // } // /* Set SystemCoreClock variable. */ // SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Board_Support/clock_config.h ================================================ /* * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _CLOCK_CONFIG_H_ #define _CLOCK_CONFIG_H_ #include "fsl_common.h" /******************************************************************************* * Definitions ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes default configuration of clocks. * */ void BOARD_InitBootClocks(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ #define BOARD_XTAL0_CLK_HZ 50000000U /*!< Board xtal0 frequency in Hz */ /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /******************************************************************************* * Definitions for BOARD_BootClockRUN configuration ******************************************************************************/ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */ /*! @brief MCG set for BOARD_BootClockRUN configuration. */ extern const mcg_config_t mcgConfig_BOARD_BootClockRUN; /*! @brief SIM module set for BOARD_BootClockRUN configuration. */ extern const sim_clock_config_t simConfig_BOARD_BootClockRUN; /*! @brief OSC set for BOARD_BootClockRUN configuration. */ extern const osc_config_t oscConfig_BOARD_BootClockRUN; /******************************************************************************* * API for BOARD_BootClockRUN configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes configuration of clocks. * */ void BOARD_BootClockRUN(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ /******************************************************************************* ********************* Configuration BOARD_BootClockVLPR *********************** ******************************************************************************/ /******************************************************************************* * Definitions for BOARD_BootClockVLPR configuration ******************************************************************************/ #define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */ /*! @brief MCG set for BOARD_BootClockVLPR configuration. */ extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR; /*! @brief SIM module set for BOARD_BootClockVLPR configuration. */ extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR; /*! @brief OSC set for BOARD_BootClockVLPR configuration. */ extern const osc_config_t oscConfig_BOARD_BootClockVLPR; /******************************************************************************* * API for BOARD_BootClockVLPR configuration ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /* __cplusplus*/ /*! * @brief This function executes configuration of clocks. * */ void BOARD_BootClockVLPR(void); #if defined(__cplusplus) } #endif /* __cplusplus*/ #endif /* _CLOCK_CONFIG_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/peripherals.c ================================================ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Peripherals v1.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Included files ******************************************************************************/ #include "peripherals.h" /******************************************************************************* * BOARD_InitBootPeripherals function ******************************************************************************/ void BOARD_InitBootPeripherals(void) { } ================================================ FILE: example/build/mdk/RTE/Board_Support/peripherals.h ================================================ #ifndef _PERIPHERALS_H_ #define _PERIPHERALS_H_ #if defined(__cplusplus) extern "C" { #endif /*_cplusplus. */ /******************************************************************************* * BOARD_InitBootPeripherals function ******************************************************************************/ void BOARD_InitBootPeripherals(void); #if defined(__cplusplus) } #endif /*_cplusplus. */ #endif /* _PERIPHERALS_H_ */ ================================================ FILE: example/build/mdk/RTE/Board_Support/pin_mux.c ================================================ /* * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Pins v3.0 processor: MK64FN1M0xxx12 package_id: MK64FN1M0VLL12 mcu_data: ksdk2_0 processor_version: 2.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ #include "fsl_common.h" #include "fsl_port.h" #include "pin_mux.h" /*FUNCTION********************************************************************** * * Function Name : BOARD_InitBootPins * Description : Calls initialization functions. * *END**************************************************************************/ void BOARD_InitBootPins(void) { // BOARD_InitPins(); } #define PIN16_IDX 16u /*!< Pin number for pin 16 in a port */ #define PIN17_IDX 17u /*!< Pin number for pin 17 in a port */ #define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART 0 transmit data source select: UART0_TX pin */ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN} - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /*FUNCTION********************************************************************** * * Function Name : BOARD_InitPins * Description : Configures pin routing and optionally pin electrical features. * *END**************************************************************************/ void BOARD_InitPins(void) { // CLOCK_EnableClock(kCLOCK_PortB); /* Port B Clock Gate Control: Clock enabled */ // PORT_SetPinMux(PORTB, PIN16_IDX, kPORT_MuxAlt3); /* PORTB16 (pin 62) is configured as UART0_RX */ // PORT_SetPinMux(PORTB, PIN17_IDX, kPORT_MuxAlt3); /* PORTB17 (pin 63) is configured as UART0_TX */ // SIM->SOPT5 = ((SIM->SOPT5 & // (~(SIM_SOPT5_UART0TXSRC_MASK))) /* Mask bits to zero which are setting */ // | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX) /* UART 0 transmit data source select: UART0_TX pin */ // ); } /******************************************************************************* * EOF ******************************************************************************/ ================================================ FILE: example/build/mdk/RTE/Board_Support/pin_mux.h ================================================ /* * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ /******************************************************************************* * Definitions ******************************************************************************/ /*! @brief Direction type */ typedef enum _pin_mux_direction { kPIN_MUX_DirectionInput = 0U, /* Input direction */ kPIN_MUX_DirectionOutput = 1U, /* Output direction */ kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ } pin_mux_direction_t; /*! * @addtogroup pin_mux * @{ */ /******************************************************************************* * API ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif /*! * @brief Calls initialization functions. * */ void BOARD_InitBootPins(void); /*! * @brief Configures pin routing and optionally pin electrical features. * */ void BOARD_InitPins(void); #if defined(__cplusplus) } #endif /*! * @} */ #endif /* _PIN_MUX_H_ */ /******************************************************************************* * EOF ******************************************************************************/ ================================================ FILE: example/build/mdk/RTE/Device/ARMCM4_FP/startup_ARMCM4.s ================================================ ;/**************************************************************************//** ; * @file startup_CMSDK_CM7.s ; * @brief CMSIS Core Device Startup File for ; * CMSDK_CM7 Device ; * @version V3.05 ; * @date 09. November 2016 ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2016 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts ; we add these to bypass the one used by MPS2 system driver DCD USART0_RX_CPL_Handler ;DCD UART0RX_Handler ; 0 UART 0 receive interrupt DCD USART0_TX_CPL_Handler ;DCD UART0TX_Handler ; 1 UART 0 transmit interrupt DCD USART1_RX_CPL_Handler ;DCD UART0RX_Handler ; 2 UART 1 receive interrupt DCD USART1_TX_CPL_Handler ;DCD UART0TX_Handler ; 3 UART 1 transmit interrupt DCD UART2RX_Handler ; 4 UART 2 receive interrupt DCD UART2TX_Handler ; 5 UART 2 transmit interrupt DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt DCD TIMER0_Handler ; 8 Timer 0 interrupt DCD TIMER1_Handler ; 9 Timer 1 interrupt DCD DUALTIMER_Handler ; 10 Dual Timer interrupt DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt DCD ETHERNET_Handler ; 13 Ethernet interrupt DCD I2S_Handler ; 14 Audio I2S interrupt DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt DCD UART3RX_Handler ; 18 UART 3 receive interrupt DCD UART3TX_Handler ; 19 UART 3 transmit interrupt DCD UART4RX_Handler ; 20 UART 4 receive interrupt DCD UART4TX_Handler ; 21 UART 4 transmit interrupt DCD SPI_2_Handler ; 22 SPI #2 interrupt DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0) DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1) DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2) DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3) DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4) DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5) DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6) DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7) __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT UART0RX_Handler [WEAK] EXPORT USART0_RX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART0TX_Handler [WEAK] EXPORT USART0_TX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART1RX_Handler [WEAK] EXPORT USART1_RX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART1TX_Handler [WEAK] EXPORT USART1_TX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART2RX_Handler [WEAK] EXPORT UART2TX_Handler [WEAK] EXPORT GPIO0ALL_Handler [WEAK] EXPORT GPIO1ALL_Handler [WEAK] EXPORT TIMER0_Handler [WEAK] EXPORT TIMER1_Handler [WEAK] EXPORT DUALTIMER_Handler [WEAK] EXPORT SPI_0_1_Handler [WEAK] EXPORT UART_0_1_2_OVF_Handler [WEAK] EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TOUCHSCREEN_Handler [WEAK] EXPORT GPIO2_Handler [WEAK] EXPORT GPIO3_Handler [WEAK] EXPORT UART3RX_Handler [WEAK] EXPORT UART3TX_Handler [WEAK] EXPORT UART4RX_Handler [WEAK] EXPORT UART4TX_Handler [WEAK] EXPORT SPI_2_Handler [WEAK] EXPORT SPI_3_4_Handler [WEAK] EXPORT GPIO0_0_Handler [WEAK] EXPORT GPIO0_1_Handler [WEAK] EXPORT GPIO0_2_Handler [WEAK] EXPORT GPIO0_3_Handler [WEAK] EXPORT GPIO0_4_Handler [WEAK] EXPORT GPIO0_5_Handler [WEAK] EXPORT GPIO0_6_Handler [WEAK] EXPORT GPIO0_7_Handler [WEAK] UART0RX_Handler USART0_RX_CPL_Handler UART0TX_Handler USART0_TX_CPL_Handler UART1RX_Handler USART1_RX_CPL_Handler UART1TX_Handler USART1_TX_CPL_Handler UART2RX_Handler UART2TX_Handler GPIO0ALL_Handler GPIO1ALL_Handler TIMER0_Handler TIMER1_Handler DUALTIMER_Handler SPI_0_1_Handler UART_0_1_2_OVF_Handler ETHERNET_Handler I2S_Handler TOUCHSCREEN_Handler GPIO2_Handler GPIO3_Handler UART3RX_Handler UART3TX_Handler UART4RX_Handler UART4TX_Handler SPI_2_Handler SPI_3_4_Handler GPIO0_0_Handler GPIO0_1_Handler GPIO0_2_Handler GPIO0_3_Handler GPIO0_4_Handler GPIO0_5_Handler GPIO0_6_Handler GPIO0_7_Handler B . ENDP ALIGN END ================================================ FILE: example/build/mdk/RTE/Device/ARMCM4_FP/system_ARMCM4.c ================================================ /**************************************************************************//** * @file system_ARMCM4.c * @brief CMSIS Device System Source File for * ARMCM4 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM4_FP/RTE_Device.h ================================================ /* ----------------------------------------------------------------------------- * Copyright (c) 2016 ARM Ltd. * * This software is provided 'as-is', without any express or implied warranty. * In no event will the authors be held liable for any damages arising from * the use of this software. Permission is granted to anyone to use this * software for any purpose, including commercial applications, and to alter * it and redistribute it freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software in * a product, an acknowledgment in the product documentation would be * appreciated but is not required. * * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * * 3. This notice may not be removed or altered from any source distribution. * * $Date: 25. April 2016 * $Revision: V1.0.0 * * Project: RTE Device Configuration for ARM CMSDK_CM device * -------------------------------------------------------------------------- */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_USART0 1 // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART #define RTE_USART1 0 // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART #define RTE_UART2 0 // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART #define RTE_UART3 0 #endif /* __RTE_DEVICE_H */ ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM4_FP/startup_CMSDK_CM4.s ================================================ ;/**************************************************************************//** ; * @file startup_CMSDK_CM4.s ; * @brief CMSIS Core Device Startup File for ; * CMSDK_CM4 Device ; * @version V3.05 ; * @date 09. November 2016 ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2016 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD UART0RX_Handler ; 0 UART 0 receive interrupt DCD UART0TX_Handler ; 1 UART 0 transmit interrupt DCD UART1RX_Handler ; 2 UART 1 receive interrupt DCD UART1TX_Handler ; 3 UART 1 transmit interrupt DCD UART2RX_Handler ; 4 UART 2 receive interrupt DCD UART2TX_Handler ; 5 UART 2 transmit interrupt DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt DCD TIMER0_Handler ; 8 Timer 0 interrupt DCD TIMER1_Handler ; 9 Timer 1 interrupt DCD DUALTIMER_Handler ; 10 Dual Timer interrupt DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt DCD ETHERNET_Handler ; 13 Ethernet interrupt DCD I2S_Handler ; 14 Audio I2S interrupt DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt DCD UART3RX_Handler ; 18 UART 3 receive interrupt DCD UART3TX_Handler ; 19 UART 3 transmit interrupt DCD UART4RX_Handler ; 20 UART 4 receive interrupt DCD UART4TX_Handler ; 21 UART 4 transmit interrupt DCD SPI_2_Handler ; 22 SPI #2 interrupt DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0) DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1) DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2) DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3) DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4) DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5) DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6) DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7) __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT UART0RX_Handler [WEAK] EXPORT UART0TX_Handler [WEAK] EXPORT UART1RX_Handler [WEAK] EXPORT UART1TX_Handler [WEAK] EXPORT UART2RX_Handler [WEAK] EXPORT UART2TX_Handler [WEAK] EXPORT GPIO0ALL_Handler [WEAK] EXPORT GPIO1ALL_Handler [WEAK] EXPORT TIMER0_Handler [WEAK] EXPORT TIMER1_Handler [WEAK] EXPORT DUALTIMER_Handler [WEAK] EXPORT SPI_0_1_Handler [WEAK] EXPORT UART_0_1_2_OVF_Handler [WEAK] EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TOUCHSCREEN_Handler [WEAK] EXPORT GPIO2_Handler [WEAK] EXPORT GPIO3_Handler [WEAK] EXPORT UART3RX_Handler [WEAK] EXPORT UART3TX_Handler [WEAK] EXPORT UART4RX_Handler [WEAK] EXPORT UART4TX_Handler [WEAK] EXPORT SPI_2_Handler [WEAK] EXPORT SPI_3_4_Handler [WEAK] EXPORT GPIO0_0_Handler [WEAK] EXPORT GPIO0_1_Handler [WEAK] EXPORT GPIO0_2_Handler [WEAK] EXPORT GPIO0_3_Handler [WEAK] EXPORT GPIO0_4_Handler [WEAK] EXPORT GPIO0_5_Handler [WEAK] EXPORT GPIO0_6_Handler [WEAK] EXPORT GPIO0_7_Handler [WEAK] UART0RX_Handler UART0TX_Handler UART1RX_Handler UART1TX_Handler UART2RX_Handler UART2TX_Handler GPIO0ALL_Handler GPIO1ALL_Handler TIMER0_Handler TIMER1_Handler DUALTIMER_Handler SPI_0_1_Handler UART_0_1_2_OVF_Handler ETHERNET_Handler I2S_Handler TOUCHSCREEN_Handler GPIO2_Handler GPIO3_Handler UART3RX_Handler UART3TX_Handler UART4RX_Handler UART4TX_Handler SPI_2_Handler SPI_3_4_Handler GPIO0_0_Handler GPIO0_1_Handler GPIO0_2_Handler GPIO0_3_Handler GPIO0_4_Handler GPIO0_5_Handler GPIO0_6_Handler GPIO0_7_Handler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM4_FP/system_CMSDK_CM4.c ================================================ /**************************************************************************//** * @file system_CMSDK_CM4.c * @brief CMSIS Device System Source File for * CMSDK_M4 Device * @version V4.00 * @date 02. November 2015 ******************************************************************************/ /* Copyright (c) 2011 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined (CMSDK_CM4) #include "CMSDK_CM4.h" #elif defined (CMSDK_CM4_FP) #include "CMSDK_CM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } void SystemInit (void) { #if (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_DP/RTE_Device.h ================================================ /* ----------------------------------------------------------------------------- * Copyright (c) 2016 ARM Ltd. * * This software is provided 'as-is', without any express or implied warranty. * In no event will the authors be held liable for any damages arising from * the use of this software. Permission is granted to anyone to use this * software for any purpose, including commercial applications, and to alter * it and redistribute it freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software in * a product, an acknowledgment in the product documentation would be * appreciated but is not required. * * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * * 3. This notice may not be removed or altered from any source distribution. * * $Date: 25. April 2016 * $Revision: V1.0.0 * * Project: RTE Device Configuration for ARM CMSDK_CM device * -------------------------------------------------------------------------- */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_USART0 0 // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART #define RTE_USART1 0 // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART #define RTE_UART2 0 // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART #define RTE_UART3 0 #endif /* __RTE_DEVICE_H */ ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_DP/startup_CMSDK_CM7.s ================================================ ;/**************************************************************************//** ; * @file startup_CMSDK_CM7.s ; * @brief CMSIS Core Device Startup File for ; * CMSDK_CM7 Device ; * @version V3.05 ; * @date 09. November 2016 ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2016 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000C00 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD UART0RX_Handler ; 0 UART 0 receive interrupt DCD UART0TX_Handler ; 1 UART 0 transmit interrupt DCD UART1RX_Handler ; 2 UART 1 receive interrupt DCD UART1TX_Handler ; 3 UART 1 transmit interrupt DCD UART2RX_Handler ; 4 UART 2 receive interrupt DCD UART2TX_Handler ; 5 UART 2 transmit interrupt DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt DCD TIMER0_Handler ; 8 Timer 0 interrupt DCD TIMER1_Handler ; 9 Timer 1 interrupt DCD DUALTIMER_Handler ; 10 Dual Timer interrupt DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt DCD ETHERNET_Handler ; 13 Ethernet interrupt DCD I2S_Handler ; 14 Audio I2S interrupt DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt DCD UART3RX_Handler ; 18 UART 3 receive interrupt DCD UART3TX_Handler ; 19 UART 3 transmit interrupt DCD UART4RX_Handler ; 20 UART 4 receive interrupt DCD UART4TX_Handler ; 21 UART 4 transmit interrupt DCD SPI_2_Handler ; 22 SPI #2 interrupt DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0) DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1) DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2) DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3) DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4) DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5) DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6) DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7) __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT UART0RX_Handler [WEAK] EXPORT UART0TX_Handler [WEAK] EXPORT UART1RX_Handler [WEAK] EXPORT UART1TX_Handler [WEAK] EXPORT UART2RX_Handler [WEAK] EXPORT UART2TX_Handler [WEAK] EXPORT GPIO0ALL_Handler [WEAK] EXPORT GPIO1ALL_Handler [WEAK] EXPORT TIMER0_Handler [WEAK] EXPORT TIMER1_Handler [WEAK] EXPORT DUALTIMER_Handler [WEAK] EXPORT SPI_0_1_Handler [WEAK] EXPORT UART_0_1_2_OVF_Handler [WEAK] EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TOUCHSCREEN_Handler [WEAK] EXPORT GPIO2_Handler [WEAK] EXPORT GPIO3_Handler [WEAK] EXPORT UART3RX_Handler [WEAK] EXPORT UART3TX_Handler [WEAK] EXPORT UART4RX_Handler [WEAK] EXPORT UART4TX_Handler [WEAK] EXPORT SPI_2_Handler [WEAK] EXPORT SPI_3_4_Handler [WEAK] EXPORT GPIO0_0_Handler [WEAK] EXPORT GPIO0_1_Handler [WEAK] EXPORT GPIO0_2_Handler [WEAK] EXPORT GPIO0_3_Handler [WEAK] EXPORT GPIO0_4_Handler [WEAK] EXPORT GPIO0_5_Handler [WEAK] EXPORT GPIO0_6_Handler [WEAK] EXPORT GPIO0_7_Handler [WEAK] UART0RX_Handler UART0TX_Handler UART1RX_Handler UART1TX_Handler UART2RX_Handler UART2TX_Handler GPIO0ALL_Handler GPIO1ALL_Handler TIMER0_Handler TIMER1_Handler DUALTIMER_Handler SPI_0_1_Handler UART_0_1_2_OVF_Handler ETHERNET_Handler I2S_Handler TOUCHSCREEN_Handler GPIO2_Handler GPIO3_Handler UART3RX_Handler UART3TX_Handler UART4RX_Handler UART4TX_Handler SPI_2_Handler SPI_3_4_Handler GPIO0_0_Handler GPIO0_1_Handler GPIO0_2_Handler GPIO0_3_Handler GPIO0_4_Handler GPIO0_5_Handler GPIO0_6_Handler GPIO0_7_Handler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_DP/system_CMSDK_CM7.c ================================================ /**************************************************************************//** * @file system_CMSDK_CM7.c * @brief CMSIS Device System Source File for * CMSDK_CM7 Device * @version V4.00 * @date 02. November 2015 ******************************************************************************/ /* Copyright (c) 2011 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined (CMSDK_CM7) #include "CMSDK_CM7.h" #elif defined (CMSDK_CM7_SP) #include "CMSDK_CM7_SP.h" #elif defined (CMSDK_CM7_DP) #include "CMSDK_CM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } void SystemInit (void) { #if (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_SP/RTE_Device.h ================================================ /* ----------------------------------------------------------------------------- * Copyright (c) 2016 ARM Ltd. * * This software is provided 'as-is', without any express or implied warranty. * In no event will the authors be held liable for any damages arising from * the use of this software. Permission is granted to anyone to use this * software for any purpose, including commercial applications, and to alter * it and redistribute it freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software in * a product, an acknowledgment in the product documentation would be * appreciated but is not required. * * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * * 3. This notice may not be removed or altered from any source distribution. * * $Date: 25. April 2016 * $Revision: V1.0.0 * * Project: RTE Device Configuration for ARM CMSDK_CM device * -------------------------------------------------------------------------- */ //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_USART0 1 // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART #define RTE_USART1 0 // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART #define RTE_UART2 0 // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART #define RTE_UART3 0 #endif /* __RTE_DEVICE_H */ ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s ================================================ ;/**************************************************************************//** ; * @file startup_CMSDK_CM7.s ; * @brief CMSIS Core Device Startup File for ; * CMSDK_CM7 Device ; * @version V3.05 ; * @date 09. November 2016 ; ******************************************************************************/ ;/* Copyright (c) 2011 - 2016 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; - Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; - Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; - Neither the name of ARM nor the names of its contributors may be used ; to endorse or promote products derived from this software without ; specific prior written permission. ; * ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ; POSSIBILITY OF SUCH DAMAGE. ; ---------------------------------------------------------------------------*/ ;/* ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000800 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000100 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts ; we add these to bypass the one used by MPS2 system driver DCD USART0_RX_CPL_Handler ;DCD UART0RX_Handler ; 0 UART 0 receive interrupt DCD USART0_TX_CPL_Handler ;DCD UART0TX_Handler ; 1 UART 0 transmit interrupt DCD USART1_RX_CPL_Handler ;DCD UART0RX_Handler ; 2 UART 1 receive interrupt DCD USART1_TX_CPL_Handler ;DCD UART0TX_Handler ; 3 UART 1 transmit interrupt DCD UART2RX_Handler ; 4 UART 2 receive interrupt DCD UART2TX_Handler ; 5 UART 2 transmit interrupt DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt DCD TIMER0_Handler ; 8 Timer 0 interrupt DCD TIMER1_Handler ; 9 Timer 1 interrupt DCD DUALTIMER_Handler ; 10 Dual Timer interrupt DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt DCD ETHERNET_Handler ; 13 Ethernet interrupt DCD I2S_Handler ; 14 Audio I2S interrupt DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt DCD UART3RX_Handler ; 18 UART 3 receive interrupt DCD UART3TX_Handler ; 19 UART 3 transmit interrupt DCD UART4RX_Handler ; 20 UART 4 receive interrupt DCD UART4TX_Handler ; 21 UART 4 transmit interrupt DCD SPI_2_Handler ; 22 SPI #2 interrupt DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0) DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1) DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2) DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3) DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4) DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5) DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6) DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7) __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT UART0RX_Handler [WEAK] EXPORT USART0_RX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART0TX_Handler [WEAK] EXPORT USART0_TX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART1RX_Handler [WEAK] EXPORT USART1_RX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART1TX_Handler [WEAK] EXPORT USART1_TX_CPL_Handler [WEAK] ; we add this to bypass the one used by MPS2 system driver EXPORT UART2RX_Handler [WEAK] EXPORT UART2TX_Handler [WEAK] EXPORT GPIO0ALL_Handler [WEAK] EXPORT GPIO1ALL_Handler [WEAK] EXPORT TIMER0_Handler [WEAK] EXPORT TIMER1_Handler [WEAK] EXPORT DUALTIMER_Handler [WEAK] EXPORT SPI_0_1_Handler [WEAK] EXPORT UART_0_1_2_OVF_Handler [WEAK] EXPORT ETHERNET_Handler [WEAK] EXPORT I2S_Handler [WEAK] EXPORT TOUCHSCREEN_Handler [WEAK] EXPORT GPIO2_Handler [WEAK] EXPORT GPIO3_Handler [WEAK] EXPORT UART3RX_Handler [WEAK] EXPORT UART3TX_Handler [WEAK] EXPORT UART4RX_Handler [WEAK] EXPORT UART4TX_Handler [WEAK] EXPORT SPI_2_Handler [WEAK] EXPORT SPI_3_4_Handler [WEAK] EXPORT GPIO0_0_Handler [WEAK] EXPORT GPIO0_1_Handler [WEAK] EXPORT GPIO0_2_Handler [WEAK] EXPORT GPIO0_3_Handler [WEAK] EXPORT GPIO0_4_Handler [WEAK] EXPORT GPIO0_5_Handler [WEAK] EXPORT GPIO0_6_Handler [WEAK] EXPORT GPIO0_7_Handler [WEAK] UART0RX_Handler USART0_RX_CPL_Handler UART0TX_Handler USART0_TX_CPL_Handler UART1RX_Handler USART1_RX_CPL_Handler UART1TX_Handler USART1_TX_CPL_Handler UART2RX_Handler UART2TX_Handler GPIO0ALL_Handler GPIO1ALL_Handler TIMER0_Handler TIMER1_Handler DUALTIMER_Handler SPI_0_1_Handler UART_0_1_2_OVF_Handler ETHERNET_Handler I2S_Handler TOUCHSCREEN_Handler GPIO2_Handler GPIO3_Handler UART3RX_Handler UART3TX_Handler UART4RX_Handler UART4TX_Handler SPI_2_Handler SPI_3_4_Handler GPIO0_0_Handler GPIO0_1_Handler GPIO0_2_Handler GPIO0_3_Handler GPIO0_4_Handler GPIO0_5_Handler GPIO0_6_Handler GPIO0_7_Handler B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap PROC LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDP ALIGN ENDIF END ================================================ FILE: example/build/mdk/RTE/Device/CMSDK_CM7_SP/system_CMSDK_CM7.c ================================================ /**************************************************************************//** * @file system_CMSDK_CM7.c * @brief CMSIS Device System Source File for * CMSDK_CM7 Device * @version V4.00 * @date 02. November 2015 ******************************************************************************/ /* Copyright (c) 2011 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined (CMSDK_CM7) #include "CMSDK_CM7.h" #elif defined (CMSDK_CM7_SP) #include "CMSDK_CM7_SP.h" #elif defined (CMSDK_CM7_DP) #include "CMSDK_CM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } void SystemInit (void) { #if (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/MK64F12.h ================================================ /* ** ################################################################### ** Processors: MK64FN1M0CAJ12 ** MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** MK64FX512VDC12 ** MK64FX512VLL12 ** MK64FX512VLQ12 ** MK64FX512VMD12 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 ** Build: b170811 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK64F12 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** - rev. 2.4 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** - rev. 2.5 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** Module access macro module_BASES replaced by module_BASE_PTRS. ** - rev. 2.6 (2014-08-28) ** Update of system files - default clock configuration changed. ** Update of startup files - possibility to override DefaultISR added. ** - rev. 2.7 (2014-10-14) ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. ** - rev. 2.8 (2015-02-19) ** Renamed interrupt vector LLW to LLWU. ** - rev. 2.9 (2016-03-21) ** Added MK64FN1M0CAJ12 part. ** GPIO - renamed port instances: PTx -> GPIOx. ** ** ################################################################### */ /*! * @file MK64F12.h * @version 2.9 * @date 2016-03-21 * @brief CMSIS Peripheral Access Layer for MK64F12 * * CMSIS Peripheral Access Layer for MK64F12 */ #ifndef _MK64F12_H_ #define _MK64F12_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0200U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0009U /** * @brief Macro to calculate address of an aliased word in the peripheral * bitband area for a peripheral register and bit (bit band region 0x40000000 to * 0x400FFFFF). * @param Reg Register to access. * @param Bit Bit number to access. * @return Address of the aliased word in the peripheral bitband area. */ #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 32bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 16bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 8bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ MCM_IRQn = 17, /**< Normal Interrupt */ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ RNG_IRQn = 23, /**< RNG Interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ SPI0_IRQn = 26, /**< SPI0 Interrupt */ SPI1_IRQn = 27, /**< SPI1 Interrupt */ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ ADC0_IRQn = 39, /**< ADC0 interrupt */ CMP0_IRQn = 40, /**< CMP0 interrupt */ CMP1_IRQn = 41, /**< CMP1 interrupt */ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ CMT_IRQn = 45, /**< CMT interrupt */ RTC_IRQn = 46, /**< RTC interrupt */ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ PDB0_IRQn = 52, /**< PDB0 Interrupt */ USB0_IRQn = 53, /**< USB0 interrupt */ USBDCD_IRQn = 54, /**< USBDCD Interrupt */ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ DAC0_IRQn = 56, /**< DAC0 interrupt */ MCG_IRQn = 57, /**< MCG Interrupt */ LPTMR0_IRQn = 58, /**< LPTimer interrupt */ PORTA_IRQn = 59, /**< Port A interrupt */ PORTB_IRQn = 60, /**< Port B interrupt */ PORTC_IRQn = 61, /**< Port C interrupt */ PORTD_IRQn = 62, /**< Port D interrupt */ PORTE_IRQn = 63, /**< Port E interrupt */ SWI_IRQn = 64, /**< Software interrupt */ SPI2_IRQn = 65, /**< SPI2 Interrupt */ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ CMP2_IRQn = 70, /**< CMP2 interrupt */ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ DAC1_IRQn = 72, /**< DAC1 interrupt */ ADC1_IRQn = 73, /**< ADC1 interrupt */ I2C2_IRQn = 74, /**< I2C2 interrupt */ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ SDHC_IRQn = 81, /**< SDHC interrupt */ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration * @{ */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MK64F12.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Mapping Information ---------------------------------------------------------------------------- */ /*! * @addtogroup Mapping_Information Mapping Information * @{ */ /** Mapping Information */ /*! * @addtogroup edma_request * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the DMA hardware request * * Defines the structure for the DMA hardware request collections. The user can configure the * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index * of the hardware request varies according to the to SoC. */ typedef enum _dma_request_source { kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */ kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */ kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */ kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */ kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */ kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */ kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ } dma_request_source_t; /* @} */ /*! * @} */ /* end of group Mapping_Information */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ uint8_t RESERVED_0[4]; __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name SC1 - ADC Status and Control Registers 1 */ #define ADC_SC1_ADCH_MASK (0x1FU) #define ADC_SC1_ADCH_SHIFT (0U) #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) #define ADC_SC1_DIFF_MASK (0x20U) #define ADC_SC1_DIFF_SHIFT (5U) #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) #define ADC_SC1_AIEN_MASK (0x40U) #define ADC_SC1_AIEN_SHIFT (6U) #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) #define ADC_SC1_COCO_MASK (0x80U) #define ADC_SC1_COCO_SHIFT (7U) #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) /* The count of ADC_SC1 */ #define ADC_SC1_COUNT (2U) /*! @name CFG1 - ADC Configuration Register 1 */ #define ADC_CFG1_ADICLK_MASK (0x3U) #define ADC_CFG1_ADICLK_SHIFT (0U) #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) #define ADC_CFG1_MODE_MASK (0xCU) #define ADC_CFG1_MODE_SHIFT (2U) #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) #define ADC_CFG1_ADLSMP_MASK (0x10U) #define ADC_CFG1_ADLSMP_SHIFT (4U) #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) #define ADC_CFG1_ADIV_MASK (0x60U) #define ADC_CFG1_ADIV_SHIFT (5U) #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) #define ADC_CFG1_ADLPC_MASK (0x80U) #define ADC_CFG1_ADLPC_SHIFT (7U) #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) /*! @name CFG2 - ADC Configuration Register 2 */ #define ADC_CFG2_ADLSTS_MASK (0x3U) #define ADC_CFG2_ADLSTS_SHIFT (0U) #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) #define ADC_CFG2_ADHSC_MASK (0x4U) #define ADC_CFG2_ADHSC_SHIFT (2U) #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) #define ADC_CFG2_ADACKEN_MASK (0x8U) #define ADC_CFG2_ADACKEN_SHIFT (3U) #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) #define ADC_CFG2_MUXSEL_MASK (0x10U) #define ADC_CFG2_MUXSEL_SHIFT (4U) #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) /*! @name R - ADC Data Result Register */ #define ADC_R_D_MASK (0xFFFFU) #define ADC_R_D_SHIFT (0U) #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) /* The count of ADC_R */ #define ADC_R_COUNT (2U) /*! @name CV1 - Compare Value Registers */ #define ADC_CV1_CV_MASK (0xFFFFU) #define ADC_CV1_CV_SHIFT (0U) #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) /*! @name CV2 - Compare Value Registers */ #define ADC_CV2_CV_MASK (0xFFFFU) #define ADC_CV2_CV_SHIFT (0U) #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) /*! @name SC2 - Status and Control Register 2 */ #define ADC_SC2_REFSEL_MASK (0x3U) #define ADC_SC2_REFSEL_SHIFT (0U) #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) #define ADC_SC2_DMAEN_MASK (0x4U) #define ADC_SC2_DMAEN_SHIFT (2U) #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) #define ADC_SC2_ACREN_MASK (0x8U) #define ADC_SC2_ACREN_SHIFT (3U) #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) #define ADC_SC2_ACFGT_MASK (0x10U) #define ADC_SC2_ACFGT_SHIFT (4U) #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) #define ADC_SC2_ACFE_MASK (0x20U) #define ADC_SC2_ACFE_SHIFT (5U) #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) #define ADC_SC2_ADTRG_MASK (0x40U) #define ADC_SC2_ADTRG_SHIFT (6U) #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) #define ADC_SC2_ADACT_MASK (0x80U) #define ADC_SC2_ADACT_SHIFT (7U) #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) /*! @name SC3 - Status and Control Register 3 */ #define ADC_SC3_AVGS_MASK (0x3U) #define ADC_SC3_AVGS_SHIFT (0U) #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) #define ADC_SC3_AVGE_MASK (0x4U) #define ADC_SC3_AVGE_SHIFT (2U) #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) #define ADC_SC3_ADCO_MASK (0x8U) #define ADC_SC3_ADCO_SHIFT (3U) #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) #define ADC_SC3_CALF_MASK (0x40U) #define ADC_SC3_CALF_SHIFT (6U) #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) #define ADC_SC3_CAL_MASK (0x80U) #define ADC_SC3_CAL_SHIFT (7U) #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) /*! @name OFS - ADC Offset Correction Register */ #define ADC_OFS_OFS_MASK (0xFFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) /*! @name PG - ADC Plus-Side Gain Register */ #define ADC_PG_PG_MASK (0xFFFFU) #define ADC_PG_PG_SHIFT (0U) #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) /*! @name MG - ADC Minus-Side Gain Register */ #define ADC_MG_MG_MASK (0xFFFFU) #define ADC_MG_MG_SHIFT (0U) #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ #define ADC_CLPD_CLPD_MASK (0x3FU) #define ADC_CLPD_CLPD_SHIFT (0U) #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ #define ADC_CLPS_CLPS_MASK (0x3FU) #define ADC_CLPS_CLPS_SHIFT (0U) #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ #define ADC_CLP4_CLP4_MASK (0x3FFU) #define ADC_CLP4_CLP4_SHIFT (0U) #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ #define ADC_CLP3_CLP3_MASK (0x1FFU) #define ADC_CLP3_CLP3_SHIFT (0U) #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ #define ADC_CLP2_CLP2_MASK (0xFFU) #define ADC_CLP2_CLP2_SHIFT (0U) #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ #define ADC_CLP1_CLP1_MASK (0x7FU) #define ADC_CLP1_CLP1_SHIFT (0U) #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ #define ADC_CLP0_CLP0_MASK (0x3FU) #define ADC_CLP0_CLP0_SHIFT (0U) #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ #define ADC_CLMD_CLMD_MASK (0x3FU) #define ADC_CLMD_CLMD_SHIFT (0U) #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ #define ADC_CLMS_CLMS_MASK (0x3FU) #define ADC_CLMS_CLMS_SHIFT (0U) #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ #define ADC_CLM4_CLM4_MASK (0x3FFU) #define ADC_CLM4_CLM4_SHIFT (0U) #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ #define ADC_CLM3_CLM3_MASK (0x1FFU) #define ADC_CLM3_CLM3_SHIFT (0U) #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ #define ADC_CLM2_CLM2_MASK (0xFFU) #define ADC_CLM2_CLM2_SHIFT (0U) #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ #define ADC_CLM1_CLM1_MASK (0x7FU) #define ADC_CLM1_CLM1_SHIFT (0U) #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ #define ADC_CLM0_CLM0_MASK (0x3FU) #define ADC_CLM0_CLM0_SHIFT (0U) #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define ADC0_BASE (0x4003B000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x400BB000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AIPS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer * @{ */ /** AIPS - Register Layout Typedef */ typedef struct { __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ uint8_t RESERVED_0[28]; __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ uint8_t RESERVED_2[16]; __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */ } AIPS_Type; /* ---------------------------------------------------------------------------- -- AIPS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPS_Register_Masks AIPS Register Masks * @{ */ /*! @name MPRA - Master Privilege Register A */ #define AIPS_MPRA_MPL5_MASK (0x100U) #define AIPS_MPRA_MPL5_SHIFT (8U) #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) #define AIPS_MPRA_MTW5_MASK (0x200U) #define AIPS_MPRA_MTW5_SHIFT (9U) #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) #define AIPS_MPRA_MTR5_MASK (0x400U) #define AIPS_MPRA_MTR5_SHIFT (10U) #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) #define AIPS_MPRA_MPL4_MASK (0x1000U) #define AIPS_MPRA_MPL4_SHIFT (12U) #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) #define AIPS_MPRA_MTW4_MASK (0x2000U) #define AIPS_MPRA_MTW4_SHIFT (13U) #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) #define AIPS_MPRA_MTR4_MASK (0x4000U) #define AIPS_MPRA_MTR4_SHIFT (14U) #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) #define AIPS_MPRA_MPL3_MASK (0x10000U) #define AIPS_MPRA_MPL3_SHIFT (16U) #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) #define AIPS_MPRA_MTW3_MASK (0x20000U) #define AIPS_MPRA_MTW3_SHIFT (17U) #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) #define AIPS_MPRA_MTR3_MASK (0x40000U) #define AIPS_MPRA_MTR3_SHIFT (18U) #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) #define AIPS_MPRA_MPL2_MASK (0x100000U) #define AIPS_MPRA_MPL2_SHIFT (20U) #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) #define AIPS_MPRA_MTW2_MASK (0x200000U) #define AIPS_MPRA_MTW2_SHIFT (21U) #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) #define AIPS_MPRA_MTR2_MASK (0x400000U) #define AIPS_MPRA_MTR2_SHIFT (22U) #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) #define AIPS_MPRA_MPL1_MASK (0x1000000U) #define AIPS_MPRA_MPL1_SHIFT (24U) #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) #define AIPS_MPRA_MTW1_MASK (0x2000000U) #define AIPS_MPRA_MTW1_SHIFT (25U) #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) #define AIPS_MPRA_MTR1_MASK (0x4000000U) #define AIPS_MPRA_MTR1_SHIFT (26U) #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) #define AIPS_MPRA_MPL0_MASK (0x10000000U) #define AIPS_MPRA_MPL0_SHIFT (28U) #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) #define AIPS_MPRA_MTW0_MASK (0x20000000U) #define AIPS_MPRA_MTW0_SHIFT (29U) #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) #define AIPS_MPRA_MTR0_MASK (0x40000000U) #define AIPS_MPRA_MTR0_SHIFT (30U) #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) /*! @name PACRA - Peripheral Access Control Register */ #define AIPS_PACRA_TP7_MASK (0x1U) #define AIPS_PACRA_TP7_SHIFT (0U) #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) #define AIPS_PACRA_WP7_MASK (0x2U) #define AIPS_PACRA_WP7_SHIFT (1U) #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) #define AIPS_PACRA_SP7_MASK (0x4U) #define AIPS_PACRA_SP7_SHIFT (2U) #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) #define AIPS_PACRA_TP6_MASK (0x10U) #define AIPS_PACRA_TP6_SHIFT (4U) #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) #define AIPS_PACRA_WP6_MASK (0x20U) #define AIPS_PACRA_WP6_SHIFT (5U) #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) #define AIPS_PACRA_SP6_MASK (0x40U) #define AIPS_PACRA_SP6_SHIFT (6U) #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) #define AIPS_PACRA_TP5_MASK (0x100U) #define AIPS_PACRA_TP5_SHIFT (8U) #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) #define AIPS_PACRA_WP5_MASK (0x200U) #define AIPS_PACRA_WP5_SHIFT (9U) #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) #define AIPS_PACRA_SP5_MASK (0x400U) #define AIPS_PACRA_SP5_SHIFT (10U) #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) #define AIPS_PACRA_TP4_MASK (0x1000U) #define AIPS_PACRA_TP4_SHIFT (12U) #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) #define AIPS_PACRA_WP4_MASK (0x2000U) #define AIPS_PACRA_WP4_SHIFT (13U) #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) #define AIPS_PACRA_SP4_MASK (0x4000U) #define AIPS_PACRA_SP4_SHIFT (14U) #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) #define AIPS_PACRA_TP3_MASK (0x10000U) #define AIPS_PACRA_TP3_SHIFT (16U) #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) #define AIPS_PACRA_WP3_MASK (0x20000U) #define AIPS_PACRA_WP3_SHIFT (17U) #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) #define AIPS_PACRA_SP3_MASK (0x40000U) #define AIPS_PACRA_SP3_SHIFT (18U) #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) #define AIPS_PACRA_TP2_MASK (0x100000U) #define AIPS_PACRA_TP2_SHIFT (20U) #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) #define AIPS_PACRA_WP2_MASK (0x200000U) #define AIPS_PACRA_WP2_SHIFT (21U) #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) #define AIPS_PACRA_SP2_MASK (0x400000U) #define AIPS_PACRA_SP2_SHIFT (22U) #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) #define AIPS_PACRA_TP1_MASK (0x1000000U) #define AIPS_PACRA_TP1_SHIFT (24U) #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) #define AIPS_PACRA_WP1_MASK (0x2000000U) #define AIPS_PACRA_WP1_SHIFT (25U) #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) #define AIPS_PACRA_SP1_MASK (0x4000000U) #define AIPS_PACRA_SP1_SHIFT (26U) #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) #define AIPS_PACRA_TP0_MASK (0x10000000U) #define AIPS_PACRA_TP0_SHIFT (28U) #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) #define AIPS_PACRA_WP0_MASK (0x20000000U) #define AIPS_PACRA_WP0_SHIFT (29U) #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) #define AIPS_PACRA_SP0_MASK (0x40000000U) #define AIPS_PACRA_SP0_SHIFT (30U) #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) /*! @name PACRB - Peripheral Access Control Register */ #define AIPS_PACRB_TP7_MASK (0x1U) #define AIPS_PACRB_TP7_SHIFT (0U) #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) #define AIPS_PACRB_WP7_MASK (0x2U) #define AIPS_PACRB_WP7_SHIFT (1U) #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) #define AIPS_PACRB_SP7_MASK (0x4U) #define AIPS_PACRB_SP7_SHIFT (2U) #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) #define AIPS_PACRB_TP6_MASK (0x10U) #define AIPS_PACRB_TP6_SHIFT (4U) #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) #define AIPS_PACRB_WP6_MASK (0x20U) #define AIPS_PACRB_WP6_SHIFT (5U) #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) #define AIPS_PACRB_SP6_MASK (0x40U) #define AIPS_PACRB_SP6_SHIFT (6U) #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) #define AIPS_PACRB_TP5_MASK (0x100U) #define AIPS_PACRB_TP5_SHIFT (8U) #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) #define AIPS_PACRB_WP5_MASK (0x200U) #define AIPS_PACRB_WP5_SHIFT (9U) #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) #define AIPS_PACRB_SP5_MASK (0x400U) #define AIPS_PACRB_SP5_SHIFT (10U) #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) #define AIPS_PACRB_TP4_MASK (0x1000U) #define AIPS_PACRB_TP4_SHIFT (12U) #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) #define AIPS_PACRB_WP4_MASK (0x2000U) #define AIPS_PACRB_WP4_SHIFT (13U) #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) #define AIPS_PACRB_SP4_MASK (0x4000U) #define AIPS_PACRB_SP4_SHIFT (14U) #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) #define AIPS_PACRB_TP3_MASK (0x10000U) #define AIPS_PACRB_TP3_SHIFT (16U) #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) #define AIPS_PACRB_WP3_MASK (0x20000U) #define AIPS_PACRB_WP3_SHIFT (17U) #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) #define AIPS_PACRB_SP3_MASK (0x40000U) #define AIPS_PACRB_SP3_SHIFT (18U) #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) #define AIPS_PACRB_TP2_MASK (0x100000U) #define AIPS_PACRB_TP2_SHIFT (20U) #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) #define AIPS_PACRB_WP2_MASK (0x200000U) #define AIPS_PACRB_WP2_SHIFT (21U) #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) #define AIPS_PACRB_SP2_MASK (0x400000U) #define AIPS_PACRB_SP2_SHIFT (22U) #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) #define AIPS_PACRB_TP1_MASK (0x1000000U) #define AIPS_PACRB_TP1_SHIFT (24U) #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) #define AIPS_PACRB_WP1_MASK (0x2000000U) #define AIPS_PACRB_WP1_SHIFT (25U) #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) #define AIPS_PACRB_SP1_MASK (0x4000000U) #define AIPS_PACRB_SP1_SHIFT (26U) #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) #define AIPS_PACRB_TP0_MASK (0x10000000U) #define AIPS_PACRB_TP0_SHIFT (28U) #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) #define AIPS_PACRB_WP0_MASK (0x20000000U) #define AIPS_PACRB_WP0_SHIFT (29U) #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) #define AIPS_PACRB_SP0_MASK (0x40000000U) #define AIPS_PACRB_SP0_SHIFT (30U) #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) /*! @name PACRC - Peripheral Access Control Register */ #define AIPS_PACRC_TP7_MASK (0x1U) #define AIPS_PACRC_TP7_SHIFT (0U) #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) #define AIPS_PACRC_WP7_MASK (0x2U) #define AIPS_PACRC_WP7_SHIFT (1U) #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) #define AIPS_PACRC_SP7_MASK (0x4U) #define AIPS_PACRC_SP7_SHIFT (2U) #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) #define AIPS_PACRC_TP6_MASK (0x10U) #define AIPS_PACRC_TP6_SHIFT (4U) #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) #define AIPS_PACRC_WP6_MASK (0x20U) #define AIPS_PACRC_WP6_SHIFT (5U) #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) #define AIPS_PACRC_SP6_MASK (0x40U) #define AIPS_PACRC_SP6_SHIFT (6U) #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) #define AIPS_PACRC_TP5_MASK (0x100U) #define AIPS_PACRC_TP5_SHIFT (8U) #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) #define AIPS_PACRC_WP5_MASK (0x200U) #define AIPS_PACRC_WP5_SHIFT (9U) #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) #define AIPS_PACRC_SP5_MASK (0x400U) #define AIPS_PACRC_SP5_SHIFT (10U) #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) #define AIPS_PACRC_TP4_MASK (0x1000U) #define AIPS_PACRC_TP4_SHIFT (12U) #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) #define AIPS_PACRC_WP4_MASK (0x2000U) #define AIPS_PACRC_WP4_SHIFT (13U) #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) #define AIPS_PACRC_SP4_MASK (0x4000U) #define AIPS_PACRC_SP4_SHIFT (14U) #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) #define AIPS_PACRC_TP3_MASK (0x10000U) #define AIPS_PACRC_TP3_SHIFT (16U) #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) #define AIPS_PACRC_WP3_MASK (0x20000U) #define AIPS_PACRC_WP3_SHIFT (17U) #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) #define AIPS_PACRC_SP3_MASK (0x40000U) #define AIPS_PACRC_SP3_SHIFT (18U) #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) #define AIPS_PACRC_TP2_MASK (0x100000U) #define AIPS_PACRC_TP2_SHIFT (20U) #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) #define AIPS_PACRC_WP2_MASK (0x200000U) #define AIPS_PACRC_WP2_SHIFT (21U) #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) #define AIPS_PACRC_SP2_MASK (0x400000U) #define AIPS_PACRC_SP2_SHIFT (22U) #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) #define AIPS_PACRC_TP1_MASK (0x1000000U) #define AIPS_PACRC_TP1_SHIFT (24U) #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) #define AIPS_PACRC_WP1_MASK (0x2000000U) #define AIPS_PACRC_WP1_SHIFT (25U) #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) #define AIPS_PACRC_SP1_MASK (0x4000000U) #define AIPS_PACRC_SP1_SHIFT (26U) #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) #define AIPS_PACRC_TP0_MASK (0x10000000U) #define AIPS_PACRC_TP0_SHIFT (28U) #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) #define AIPS_PACRC_WP0_MASK (0x20000000U) #define AIPS_PACRC_WP0_SHIFT (29U) #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) #define AIPS_PACRC_SP0_MASK (0x40000000U) #define AIPS_PACRC_SP0_SHIFT (30U) #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) /*! @name PACRD - Peripheral Access Control Register */ #define AIPS_PACRD_TP7_MASK (0x1U) #define AIPS_PACRD_TP7_SHIFT (0U) #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) #define AIPS_PACRD_WP7_MASK (0x2U) #define AIPS_PACRD_WP7_SHIFT (1U) #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) #define AIPS_PACRD_SP7_MASK (0x4U) #define AIPS_PACRD_SP7_SHIFT (2U) #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) #define AIPS_PACRD_TP6_MASK (0x10U) #define AIPS_PACRD_TP6_SHIFT (4U) #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) #define AIPS_PACRD_WP6_MASK (0x20U) #define AIPS_PACRD_WP6_SHIFT (5U) #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) #define AIPS_PACRD_SP6_MASK (0x40U) #define AIPS_PACRD_SP6_SHIFT (6U) #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) #define AIPS_PACRD_TP5_MASK (0x100U) #define AIPS_PACRD_TP5_SHIFT (8U) #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) #define AIPS_PACRD_WP5_MASK (0x200U) #define AIPS_PACRD_WP5_SHIFT (9U) #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) #define AIPS_PACRD_SP5_MASK (0x400U) #define AIPS_PACRD_SP5_SHIFT (10U) #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) #define AIPS_PACRD_TP4_MASK (0x1000U) #define AIPS_PACRD_TP4_SHIFT (12U) #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) #define AIPS_PACRD_WP4_MASK (0x2000U) #define AIPS_PACRD_WP4_SHIFT (13U) #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) #define AIPS_PACRD_SP4_MASK (0x4000U) #define AIPS_PACRD_SP4_SHIFT (14U) #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) #define AIPS_PACRD_TP3_MASK (0x10000U) #define AIPS_PACRD_TP3_SHIFT (16U) #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) #define AIPS_PACRD_WP3_MASK (0x20000U) #define AIPS_PACRD_WP3_SHIFT (17U) #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) #define AIPS_PACRD_SP3_MASK (0x40000U) #define AIPS_PACRD_SP3_SHIFT (18U) #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) #define AIPS_PACRD_TP2_MASK (0x100000U) #define AIPS_PACRD_TP2_SHIFT (20U) #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) #define AIPS_PACRD_WP2_MASK (0x200000U) #define AIPS_PACRD_WP2_SHIFT (21U) #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) #define AIPS_PACRD_SP2_MASK (0x400000U) #define AIPS_PACRD_SP2_SHIFT (22U) #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) #define AIPS_PACRD_TP1_MASK (0x1000000U) #define AIPS_PACRD_TP1_SHIFT (24U) #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) #define AIPS_PACRD_WP1_MASK (0x2000000U) #define AIPS_PACRD_WP1_SHIFT (25U) #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) #define AIPS_PACRD_SP1_MASK (0x4000000U) #define AIPS_PACRD_SP1_SHIFT (26U) #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) #define AIPS_PACRD_TP0_MASK (0x10000000U) #define AIPS_PACRD_TP0_SHIFT (28U) #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) #define AIPS_PACRD_WP0_MASK (0x20000000U) #define AIPS_PACRD_WP0_SHIFT (29U) #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) #define AIPS_PACRD_SP0_MASK (0x40000000U) #define AIPS_PACRD_SP0_SHIFT (30U) #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) /*! @name PACRE - Peripheral Access Control Register */ #define AIPS_PACRE_TP7_MASK (0x1U) #define AIPS_PACRE_TP7_SHIFT (0U) #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) #define AIPS_PACRE_WP7_MASK (0x2U) #define AIPS_PACRE_WP7_SHIFT (1U) #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) #define AIPS_PACRE_SP7_MASK (0x4U) #define AIPS_PACRE_SP7_SHIFT (2U) #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) #define AIPS_PACRE_TP6_MASK (0x10U) #define AIPS_PACRE_TP6_SHIFT (4U) #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) #define AIPS_PACRE_WP6_MASK (0x20U) #define AIPS_PACRE_WP6_SHIFT (5U) #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) #define AIPS_PACRE_SP6_MASK (0x40U) #define AIPS_PACRE_SP6_SHIFT (6U) #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) #define AIPS_PACRE_TP5_MASK (0x100U) #define AIPS_PACRE_TP5_SHIFT (8U) #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) #define AIPS_PACRE_WP5_MASK (0x200U) #define AIPS_PACRE_WP5_SHIFT (9U) #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) #define AIPS_PACRE_SP5_MASK (0x400U) #define AIPS_PACRE_SP5_SHIFT (10U) #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) #define AIPS_PACRE_TP4_MASK (0x1000U) #define AIPS_PACRE_TP4_SHIFT (12U) #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) #define AIPS_PACRE_WP4_MASK (0x2000U) #define AIPS_PACRE_WP4_SHIFT (13U) #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) #define AIPS_PACRE_SP4_MASK (0x4000U) #define AIPS_PACRE_SP4_SHIFT (14U) #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) #define AIPS_PACRE_TP3_MASK (0x10000U) #define AIPS_PACRE_TP3_SHIFT (16U) #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) #define AIPS_PACRE_WP3_MASK (0x20000U) #define AIPS_PACRE_WP3_SHIFT (17U) #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) #define AIPS_PACRE_SP3_MASK (0x40000U) #define AIPS_PACRE_SP3_SHIFT (18U) #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) #define AIPS_PACRE_TP2_MASK (0x100000U) #define AIPS_PACRE_TP2_SHIFT (20U) #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) #define AIPS_PACRE_WP2_MASK (0x200000U) #define AIPS_PACRE_WP2_SHIFT (21U) #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) #define AIPS_PACRE_SP2_MASK (0x400000U) #define AIPS_PACRE_SP2_SHIFT (22U) #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) #define AIPS_PACRE_TP1_MASK (0x1000000U) #define AIPS_PACRE_TP1_SHIFT (24U) #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) #define AIPS_PACRE_WP1_MASK (0x2000000U) #define AIPS_PACRE_WP1_SHIFT (25U) #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) #define AIPS_PACRE_SP1_MASK (0x4000000U) #define AIPS_PACRE_SP1_SHIFT (26U) #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) #define AIPS_PACRE_TP0_MASK (0x10000000U) #define AIPS_PACRE_TP0_SHIFT (28U) #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) #define AIPS_PACRE_WP0_MASK (0x20000000U) #define AIPS_PACRE_WP0_SHIFT (29U) #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) #define AIPS_PACRE_SP0_MASK (0x40000000U) #define AIPS_PACRE_SP0_SHIFT (30U) #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) /*! @name PACRF - Peripheral Access Control Register */ #define AIPS_PACRF_TP7_MASK (0x1U) #define AIPS_PACRF_TP7_SHIFT (0U) #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) #define AIPS_PACRF_WP7_MASK (0x2U) #define AIPS_PACRF_WP7_SHIFT (1U) #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) #define AIPS_PACRF_SP7_MASK (0x4U) #define AIPS_PACRF_SP7_SHIFT (2U) #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) #define AIPS_PACRF_TP6_MASK (0x10U) #define AIPS_PACRF_TP6_SHIFT (4U) #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) #define AIPS_PACRF_WP6_MASK (0x20U) #define AIPS_PACRF_WP6_SHIFT (5U) #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) #define AIPS_PACRF_SP6_MASK (0x40U) #define AIPS_PACRF_SP6_SHIFT (6U) #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) #define AIPS_PACRF_TP5_MASK (0x100U) #define AIPS_PACRF_TP5_SHIFT (8U) #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) #define AIPS_PACRF_WP5_MASK (0x200U) #define AIPS_PACRF_WP5_SHIFT (9U) #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) #define AIPS_PACRF_SP5_MASK (0x400U) #define AIPS_PACRF_SP5_SHIFT (10U) #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) #define AIPS_PACRF_TP4_MASK (0x1000U) #define AIPS_PACRF_TP4_SHIFT (12U) #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) #define AIPS_PACRF_WP4_MASK (0x2000U) #define AIPS_PACRF_WP4_SHIFT (13U) #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) #define AIPS_PACRF_SP4_MASK (0x4000U) #define AIPS_PACRF_SP4_SHIFT (14U) #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) #define AIPS_PACRF_TP3_MASK (0x10000U) #define AIPS_PACRF_TP3_SHIFT (16U) #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) #define AIPS_PACRF_WP3_MASK (0x20000U) #define AIPS_PACRF_WP3_SHIFT (17U) #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) #define AIPS_PACRF_SP3_MASK (0x40000U) #define AIPS_PACRF_SP3_SHIFT (18U) #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) #define AIPS_PACRF_TP2_MASK (0x100000U) #define AIPS_PACRF_TP2_SHIFT (20U) #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) #define AIPS_PACRF_WP2_MASK (0x200000U) #define AIPS_PACRF_WP2_SHIFT (21U) #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) #define AIPS_PACRF_SP2_MASK (0x400000U) #define AIPS_PACRF_SP2_SHIFT (22U) #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) #define AIPS_PACRF_TP1_MASK (0x1000000U) #define AIPS_PACRF_TP1_SHIFT (24U) #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) #define AIPS_PACRF_WP1_MASK (0x2000000U) #define AIPS_PACRF_WP1_SHIFT (25U) #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) #define AIPS_PACRF_SP1_MASK (0x4000000U) #define AIPS_PACRF_SP1_SHIFT (26U) #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) #define AIPS_PACRF_TP0_MASK (0x10000000U) #define AIPS_PACRF_TP0_SHIFT (28U) #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) #define AIPS_PACRF_WP0_MASK (0x20000000U) #define AIPS_PACRF_WP0_SHIFT (29U) #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) #define AIPS_PACRF_SP0_MASK (0x40000000U) #define AIPS_PACRF_SP0_SHIFT (30U) #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) /*! @name PACRG - Peripheral Access Control Register */ #define AIPS_PACRG_TP7_MASK (0x1U) #define AIPS_PACRG_TP7_SHIFT (0U) #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) #define AIPS_PACRG_WP7_MASK (0x2U) #define AIPS_PACRG_WP7_SHIFT (1U) #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) #define AIPS_PACRG_SP7_MASK (0x4U) #define AIPS_PACRG_SP7_SHIFT (2U) #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) #define AIPS_PACRG_TP6_MASK (0x10U) #define AIPS_PACRG_TP6_SHIFT (4U) #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) #define AIPS_PACRG_WP6_MASK (0x20U) #define AIPS_PACRG_WP6_SHIFT (5U) #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) #define AIPS_PACRG_SP6_MASK (0x40U) #define AIPS_PACRG_SP6_SHIFT (6U) #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) #define AIPS_PACRG_TP5_MASK (0x100U) #define AIPS_PACRG_TP5_SHIFT (8U) #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) #define AIPS_PACRG_WP5_MASK (0x200U) #define AIPS_PACRG_WP5_SHIFT (9U) #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) #define AIPS_PACRG_SP5_MASK (0x400U) #define AIPS_PACRG_SP5_SHIFT (10U) #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) #define AIPS_PACRG_TP4_MASK (0x1000U) #define AIPS_PACRG_TP4_SHIFT (12U) #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) #define AIPS_PACRG_WP4_MASK (0x2000U) #define AIPS_PACRG_WP4_SHIFT (13U) #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) #define AIPS_PACRG_SP4_MASK (0x4000U) #define AIPS_PACRG_SP4_SHIFT (14U) #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) #define AIPS_PACRG_TP3_MASK (0x10000U) #define AIPS_PACRG_TP3_SHIFT (16U) #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) #define AIPS_PACRG_WP3_MASK (0x20000U) #define AIPS_PACRG_WP3_SHIFT (17U) #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) #define AIPS_PACRG_SP3_MASK (0x40000U) #define AIPS_PACRG_SP3_SHIFT (18U) #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) #define AIPS_PACRG_TP2_MASK (0x100000U) #define AIPS_PACRG_TP2_SHIFT (20U) #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) #define AIPS_PACRG_WP2_MASK (0x200000U) #define AIPS_PACRG_WP2_SHIFT (21U) #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) #define AIPS_PACRG_SP2_MASK (0x400000U) #define AIPS_PACRG_SP2_SHIFT (22U) #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) #define AIPS_PACRG_TP1_MASK (0x1000000U) #define AIPS_PACRG_TP1_SHIFT (24U) #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) #define AIPS_PACRG_WP1_MASK (0x2000000U) #define AIPS_PACRG_WP1_SHIFT (25U) #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) #define AIPS_PACRG_SP1_MASK (0x4000000U) #define AIPS_PACRG_SP1_SHIFT (26U) #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) #define AIPS_PACRG_TP0_MASK (0x10000000U) #define AIPS_PACRG_TP0_SHIFT (28U) #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) #define AIPS_PACRG_WP0_MASK (0x20000000U) #define AIPS_PACRG_WP0_SHIFT (29U) #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) #define AIPS_PACRG_SP0_MASK (0x40000000U) #define AIPS_PACRG_SP0_SHIFT (30U) #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) /*! @name PACRH - Peripheral Access Control Register */ #define AIPS_PACRH_TP7_MASK (0x1U) #define AIPS_PACRH_TP7_SHIFT (0U) #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) #define AIPS_PACRH_WP7_MASK (0x2U) #define AIPS_PACRH_WP7_SHIFT (1U) #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) #define AIPS_PACRH_SP7_MASK (0x4U) #define AIPS_PACRH_SP7_SHIFT (2U) #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) #define AIPS_PACRH_TP6_MASK (0x10U) #define AIPS_PACRH_TP6_SHIFT (4U) #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) #define AIPS_PACRH_WP6_MASK (0x20U) #define AIPS_PACRH_WP6_SHIFT (5U) #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) #define AIPS_PACRH_SP6_MASK (0x40U) #define AIPS_PACRH_SP6_SHIFT (6U) #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) #define AIPS_PACRH_TP5_MASK (0x100U) #define AIPS_PACRH_TP5_SHIFT (8U) #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) #define AIPS_PACRH_WP5_MASK (0x200U) #define AIPS_PACRH_WP5_SHIFT (9U) #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) #define AIPS_PACRH_SP5_MASK (0x400U) #define AIPS_PACRH_SP5_SHIFT (10U) #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) #define AIPS_PACRH_TP4_MASK (0x1000U) #define AIPS_PACRH_TP4_SHIFT (12U) #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) #define AIPS_PACRH_WP4_MASK (0x2000U) #define AIPS_PACRH_WP4_SHIFT (13U) #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) #define AIPS_PACRH_SP4_MASK (0x4000U) #define AIPS_PACRH_SP4_SHIFT (14U) #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) #define AIPS_PACRH_TP3_MASK (0x10000U) #define AIPS_PACRH_TP3_SHIFT (16U) #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) #define AIPS_PACRH_WP3_MASK (0x20000U) #define AIPS_PACRH_WP3_SHIFT (17U) #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) #define AIPS_PACRH_SP3_MASK (0x40000U) #define AIPS_PACRH_SP3_SHIFT (18U) #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) #define AIPS_PACRH_TP2_MASK (0x100000U) #define AIPS_PACRH_TP2_SHIFT (20U) #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) #define AIPS_PACRH_WP2_MASK (0x200000U) #define AIPS_PACRH_WP2_SHIFT (21U) #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) #define AIPS_PACRH_SP2_MASK (0x400000U) #define AIPS_PACRH_SP2_SHIFT (22U) #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) #define AIPS_PACRH_TP1_MASK (0x1000000U) #define AIPS_PACRH_TP1_SHIFT (24U) #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) #define AIPS_PACRH_WP1_MASK (0x2000000U) #define AIPS_PACRH_WP1_SHIFT (25U) #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) #define AIPS_PACRH_SP1_MASK (0x4000000U) #define AIPS_PACRH_SP1_SHIFT (26U) #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) #define AIPS_PACRH_TP0_MASK (0x10000000U) #define AIPS_PACRH_TP0_SHIFT (28U) #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) #define AIPS_PACRH_WP0_MASK (0x20000000U) #define AIPS_PACRH_WP0_SHIFT (29U) #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) #define AIPS_PACRH_SP0_MASK (0x40000000U) #define AIPS_PACRH_SP0_SHIFT (30U) #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) /*! @name PACRI - Peripheral Access Control Register */ #define AIPS_PACRI_TP7_MASK (0x1U) #define AIPS_PACRI_TP7_SHIFT (0U) #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) #define AIPS_PACRI_WP7_MASK (0x2U) #define AIPS_PACRI_WP7_SHIFT (1U) #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) #define AIPS_PACRI_SP7_MASK (0x4U) #define AIPS_PACRI_SP7_SHIFT (2U) #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) #define AIPS_PACRI_TP6_MASK (0x10U) #define AIPS_PACRI_TP6_SHIFT (4U) #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) #define AIPS_PACRI_WP6_MASK (0x20U) #define AIPS_PACRI_WP6_SHIFT (5U) #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) #define AIPS_PACRI_SP6_MASK (0x40U) #define AIPS_PACRI_SP6_SHIFT (6U) #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) #define AIPS_PACRI_TP5_MASK (0x100U) #define AIPS_PACRI_TP5_SHIFT (8U) #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) #define AIPS_PACRI_WP5_MASK (0x200U) #define AIPS_PACRI_WP5_SHIFT (9U) #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) #define AIPS_PACRI_SP5_MASK (0x400U) #define AIPS_PACRI_SP5_SHIFT (10U) #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) #define AIPS_PACRI_TP4_MASK (0x1000U) #define AIPS_PACRI_TP4_SHIFT (12U) #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) #define AIPS_PACRI_WP4_MASK (0x2000U) #define AIPS_PACRI_WP4_SHIFT (13U) #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) #define AIPS_PACRI_SP4_MASK (0x4000U) #define AIPS_PACRI_SP4_SHIFT (14U) #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) #define AIPS_PACRI_TP3_MASK (0x10000U) #define AIPS_PACRI_TP3_SHIFT (16U) #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) #define AIPS_PACRI_WP3_MASK (0x20000U) #define AIPS_PACRI_WP3_SHIFT (17U) #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) #define AIPS_PACRI_SP3_MASK (0x40000U) #define AIPS_PACRI_SP3_SHIFT (18U) #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) #define AIPS_PACRI_TP2_MASK (0x100000U) #define AIPS_PACRI_TP2_SHIFT (20U) #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) #define AIPS_PACRI_WP2_MASK (0x200000U) #define AIPS_PACRI_WP2_SHIFT (21U) #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) #define AIPS_PACRI_SP2_MASK (0x400000U) #define AIPS_PACRI_SP2_SHIFT (22U) #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) #define AIPS_PACRI_TP1_MASK (0x1000000U) #define AIPS_PACRI_TP1_SHIFT (24U) #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) #define AIPS_PACRI_WP1_MASK (0x2000000U) #define AIPS_PACRI_WP1_SHIFT (25U) #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) #define AIPS_PACRI_SP1_MASK (0x4000000U) #define AIPS_PACRI_SP1_SHIFT (26U) #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) #define AIPS_PACRI_TP0_MASK (0x10000000U) #define AIPS_PACRI_TP0_SHIFT (28U) #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) #define AIPS_PACRI_WP0_MASK (0x20000000U) #define AIPS_PACRI_WP0_SHIFT (29U) #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) #define AIPS_PACRI_SP0_MASK (0x40000000U) #define AIPS_PACRI_SP0_SHIFT (30U) #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) /*! @name PACRJ - Peripheral Access Control Register */ #define AIPS_PACRJ_TP7_MASK (0x1U) #define AIPS_PACRJ_TP7_SHIFT (0U) #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) #define AIPS_PACRJ_WP7_MASK (0x2U) #define AIPS_PACRJ_WP7_SHIFT (1U) #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) #define AIPS_PACRJ_SP7_MASK (0x4U) #define AIPS_PACRJ_SP7_SHIFT (2U) #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) #define AIPS_PACRJ_TP6_MASK (0x10U) #define AIPS_PACRJ_TP6_SHIFT (4U) #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) #define AIPS_PACRJ_WP6_MASK (0x20U) #define AIPS_PACRJ_WP6_SHIFT (5U) #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) #define AIPS_PACRJ_SP6_MASK (0x40U) #define AIPS_PACRJ_SP6_SHIFT (6U) #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) #define AIPS_PACRJ_TP5_MASK (0x100U) #define AIPS_PACRJ_TP5_SHIFT (8U) #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) #define AIPS_PACRJ_WP5_MASK (0x200U) #define AIPS_PACRJ_WP5_SHIFT (9U) #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) #define AIPS_PACRJ_SP5_MASK (0x400U) #define AIPS_PACRJ_SP5_SHIFT (10U) #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) #define AIPS_PACRJ_TP4_MASK (0x1000U) #define AIPS_PACRJ_TP4_SHIFT (12U) #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) #define AIPS_PACRJ_WP4_MASK (0x2000U) #define AIPS_PACRJ_WP4_SHIFT (13U) #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) #define AIPS_PACRJ_SP4_MASK (0x4000U) #define AIPS_PACRJ_SP4_SHIFT (14U) #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) #define AIPS_PACRJ_TP3_MASK (0x10000U) #define AIPS_PACRJ_TP3_SHIFT (16U) #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) #define AIPS_PACRJ_WP3_MASK (0x20000U) #define AIPS_PACRJ_WP3_SHIFT (17U) #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) #define AIPS_PACRJ_SP3_MASK (0x40000U) #define AIPS_PACRJ_SP3_SHIFT (18U) #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) #define AIPS_PACRJ_TP2_MASK (0x100000U) #define AIPS_PACRJ_TP2_SHIFT (20U) #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) #define AIPS_PACRJ_WP2_MASK (0x200000U) #define AIPS_PACRJ_WP2_SHIFT (21U) #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) #define AIPS_PACRJ_SP2_MASK (0x400000U) #define AIPS_PACRJ_SP2_SHIFT (22U) #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) #define AIPS_PACRJ_TP1_MASK (0x1000000U) #define AIPS_PACRJ_TP1_SHIFT (24U) #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) #define AIPS_PACRJ_WP1_MASK (0x2000000U) #define AIPS_PACRJ_WP1_SHIFT (25U) #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) #define AIPS_PACRJ_SP1_MASK (0x4000000U) #define AIPS_PACRJ_SP1_SHIFT (26U) #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) #define AIPS_PACRJ_TP0_MASK (0x10000000U) #define AIPS_PACRJ_TP0_SHIFT (28U) #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) #define AIPS_PACRJ_WP0_MASK (0x20000000U) #define AIPS_PACRJ_WP0_SHIFT (29U) #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) #define AIPS_PACRJ_SP0_MASK (0x40000000U) #define AIPS_PACRJ_SP0_SHIFT (30U) #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) /*! @name PACRK - Peripheral Access Control Register */ #define AIPS_PACRK_TP7_MASK (0x1U) #define AIPS_PACRK_TP7_SHIFT (0U) #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) #define AIPS_PACRK_WP7_MASK (0x2U) #define AIPS_PACRK_WP7_SHIFT (1U) #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) #define AIPS_PACRK_SP7_MASK (0x4U) #define AIPS_PACRK_SP7_SHIFT (2U) #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) #define AIPS_PACRK_TP6_MASK (0x10U) #define AIPS_PACRK_TP6_SHIFT (4U) #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) #define AIPS_PACRK_WP6_MASK (0x20U) #define AIPS_PACRK_WP6_SHIFT (5U) #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) #define AIPS_PACRK_SP6_MASK (0x40U) #define AIPS_PACRK_SP6_SHIFT (6U) #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) #define AIPS_PACRK_TP5_MASK (0x100U) #define AIPS_PACRK_TP5_SHIFT (8U) #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) #define AIPS_PACRK_WP5_MASK (0x200U) #define AIPS_PACRK_WP5_SHIFT (9U) #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) #define AIPS_PACRK_SP5_MASK (0x400U) #define AIPS_PACRK_SP5_SHIFT (10U) #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) #define AIPS_PACRK_TP4_MASK (0x1000U) #define AIPS_PACRK_TP4_SHIFT (12U) #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) #define AIPS_PACRK_WP4_MASK (0x2000U) #define AIPS_PACRK_WP4_SHIFT (13U) #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) #define AIPS_PACRK_SP4_MASK (0x4000U) #define AIPS_PACRK_SP4_SHIFT (14U) #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) #define AIPS_PACRK_TP3_MASK (0x10000U) #define AIPS_PACRK_TP3_SHIFT (16U) #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) #define AIPS_PACRK_WP3_MASK (0x20000U) #define AIPS_PACRK_WP3_SHIFT (17U) #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) #define AIPS_PACRK_SP3_MASK (0x40000U) #define AIPS_PACRK_SP3_SHIFT (18U) #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) #define AIPS_PACRK_TP2_MASK (0x100000U) #define AIPS_PACRK_TP2_SHIFT (20U) #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) #define AIPS_PACRK_WP2_MASK (0x200000U) #define AIPS_PACRK_WP2_SHIFT (21U) #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) #define AIPS_PACRK_SP2_MASK (0x400000U) #define AIPS_PACRK_SP2_SHIFT (22U) #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) #define AIPS_PACRK_TP1_MASK (0x1000000U) #define AIPS_PACRK_TP1_SHIFT (24U) #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) #define AIPS_PACRK_WP1_MASK (0x2000000U) #define AIPS_PACRK_WP1_SHIFT (25U) #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) #define AIPS_PACRK_SP1_MASK (0x4000000U) #define AIPS_PACRK_SP1_SHIFT (26U) #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) #define AIPS_PACRK_TP0_MASK (0x10000000U) #define AIPS_PACRK_TP0_SHIFT (28U) #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) #define AIPS_PACRK_WP0_MASK (0x20000000U) #define AIPS_PACRK_WP0_SHIFT (29U) #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) #define AIPS_PACRK_SP0_MASK (0x40000000U) #define AIPS_PACRK_SP0_SHIFT (30U) #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) /*! @name PACRL - Peripheral Access Control Register */ #define AIPS_PACRL_TP7_MASK (0x1U) #define AIPS_PACRL_TP7_SHIFT (0U) #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) #define AIPS_PACRL_WP7_MASK (0x2U) #define AIPS_PACRL_WP7_SHIFT (1U) #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) #define AIPS_PACRL_SP7_MASK (0x4U) #define AIPS_PACRL_SP7_SHIFT (2U) #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) #define AIPS_PACRL_TP6_MASK (0x10U) #define AIPS_PACRL_TP6_SHIFT (4U) #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) #define AIPS_PACRL_WP6_MASK (0x20U) #define AIPS_PACRL_WP6_SHIFT (5U) #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) #define AIPS_PACRL_SP6_MASK (0x40U) #define AIPS_PACRL_SP6_SHIFT (6U) #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) #define AIPS_PACRL_TP5_MASK (0x100U) #define AIPS_PACRL_TP5_SHIFT (8U) #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) #define AIPS_PACRL_WP5_MASK (0x200U) #define AIPS_PACRL_WP5_SHIFT (9U) #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) #define AIPS_PACRL_SP5_MASK (0x400U) #define AIPS_PACRL_SP5_SHIFT (10U) #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) #define AIPS_PACRL_TP4_MASK (0x1000U) #define AIPS_PACRL_TP4_SHIFT (12U) #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) #define AIPS_PACRL_WP4_MASK (0x2000U) #define AIPS_PACRL_WP4_SHIFT (13U) #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) #define AIPS_PACRL_SP4_MASK (0x4000U) #define AIPS_PACRL_SP4_SHIFT (14U) #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) #define AIPS_PACRL_TP3_MASK (0x10000U) #define AIPS_PACRL_TP3_SHIFT (16U) #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) #define AIPS_PACRL_WP3_MASK (0x20000U) #define AIPS_PACRL_WP3_SHIFT (17U) #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) #define AIPS_PACRL_SP3_MASK (0x40000U) #define AIPS_PACRL_SP3_SHIFT (18U) #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) #define AIPS_PACRL_TP2_MASK (0x100000U) #define AIPS_PACRL_TP2_SHIFT (20U) #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) #define AIPS_PACRL_WP2_MASK (0x200000U) #define AIPS_PACRL_WP2_SHIFT (21U) #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) #define AIPS_PACRL_SP2_MASK (0x400000U) #define AIPS_PACRL_SP2_SHIFT (22U) #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) #define AIPS_PACRL_TP1_MASK (0x1000000U) #define AIPS_PACRL_TP1_SHIFT (24U) #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) #define AIPS_PACRL_WP1_MASK (0x2000000U) #define AIPS_PACRL_WP1_SHIFT (25U) #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) #define AIPS_PACRL_SP1_MASK (0x4000000U) #define AIPS_PACRL_SP1_SHIFT (26U) #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) #define AIPS_PACRL_TP0_MASK (0x10000000U) #define AIPS_PACRL_TP0_SHIFT (28U) #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) #define AIPS_PACRL_WP0_MASK (0x20000000U) #define AIPS_PACRL_WP0_SHIFT (29U) #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) #define AIPS_PACRL_SP0_MASK (0x40000000U) #define AIPS_PACRL_SP0_SHIFT (30U) #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) /*! @name PACRM - Peripheral Access Control Register */ #define AIPS_PACRM_TP7_MASK (0x1U) #define AIPS_PACRM_TP7_SHIFT (0U) #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) #define AIPS_PACRM_WP7_MASK (0x2U) #define AIPS_PACRM_WP7_SHIFT (1U) #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) #define AIPS_PACRM_SP7_MASK (0x4U) #define AIPS_PACRM_SP7_SHIFT (2U) #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) #define AIPS_PACRM_TP6_MASK (0x10U) #define AIPS_PACRM_TP6_SHIFT (4U) #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) #define AIPS_PACRM_WP6_MASK (0x20U) #define AIPS_PACRM_WP6_SHIFT (5U) #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) #define AIPS_PACRM_SP6_MASK (0x40U) #define AIPS_PACRM_SP6_SHIFT (6U) #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) #define AIPS_PACRM_TP5_MASK (0x100U) #define AIPS_PACRM_TP5_SHIFT (8U) #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) #define AIPS_PACRM_WP5_MASK (0x200U) #define AIPS_PACRM_WP5_SHIFT (9U) #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) #define AIPS_PACRM_SP5_MASK (0x400U) #define AIPS_PACRM_SP5_SHIFT (10U) #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) #define AIPS_PACRM_TP4_MASK (0x1000U) #define AIPS_PACRM_TP4_SHIFT (12U) #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) #define AIPS_PACRM_WP4_MASK (0x2000U) #define AIPS_PACRM_WP4_SHIFT (13U) #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) #define AIPS_PACRM_SP4_MASK (0x4000U) #define AIPS_PACRM_SP4_SHIFT (14U) #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) #define AIPS_PACRM_TP3_MASK (0x10000U) #define AIPS_PACRM_TP3_SHIFT (16U) #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) #define AIPS_PACRM_WP3_MASK (0x20000U) #define AIPS_PACRM_WP3_SHIFT (17U) #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) #define AIPS_PACRM_SP3_MASK (0x40000U) #define AIPS_PACRM_SP3_SHIFT (18U) #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) #define AIPS_PACRM_TP2_MASK (0x100000U) #define AIPS_PACRM_TP2_SHIFT (20U) #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) #define AIPS_PACRM_WP2_MASK (0x200000U) #define AIPS_PACRM_WP2_SHIFT (21U) #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) #define AIPS_PACRM_SP2_MASK (0x400000U) #define AIPS_PACRM_SP2_SHIFT (22U) #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) #define AIPS_PACRM_TP1_MASK (0x1000000U) #define AIPS_PACRM_TP1_SHIFT (24U) #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) #define AIPS_PACRM_WP1_MASK (0x2000000U) #define AIPS_PACRM_WP1_SHIFT (25U) #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) #define AIPS_PACRM_SP1_MASK (0x4000000U) #define AIPS_PACRM_SP1_SHIFT (26U) #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) #define AIPS_PACRM_TP0_MASK (0x10000000U) #define AIPS_PACRM_TP0_SHIFT (28U) #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) #define AIPS_PACRM_WP0_MASK (0x20000000U) #define AIPS_PACRM_WP0_SHIFT (29U) #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) #define AIPS_PACRM_SP0_MASK (0x40000000U) #define AIPS_PACRM_SP0_SHIFT (30U) #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) /*! @name PACRN - Peripheral Access Control Register */ #define AIPS_PACRN_TP7_MASK (0x1U) #define AIPS_PACRN_TP7_SHIFT (0U) #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) #define AIPS_PACRN_WP7_MASK (0x2U) #define AIPS_PACRN_WP7_SHIFT (1U) #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) #define AIPS_PACRN_SP7_MASK (0x4U) #define AIPS_PACRN_SP7_SHIFT (2U) #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) #define AIPS_PACRN_TP6_MASK (0x10U) #define AIPS_PACRN_TP6_SHIFT (4U) #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) #define AIPS_PACRN_WP6_MASK (0x20U) #define AIPS_PACRN_WP6_SHIFT (5U) #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) #define AIPS_PACRN_SP6_MASK (0x40U) #define AIPS_PACRN_SP6_SHIFT (6U) #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) #define AIPS_PACRN_TP5_MASK (0x100U) #define AIPS_PACRN_TP5_SHIFT (8U) #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) #define AIPS_PACRN_WP5_MASK (0x200U) #define AIPS_PACRN_WP5_SHIFT (9U) #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) #define AIPS_PACRN_SP5_MASK (0x400U) #define AIPS_PACRN_SP5_SHIFT (10U) #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) #define AIPS_PACRN_TP4_MASK (0x1000U) #define AIPS_PACRN_TP4_SHIFT (12U) #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) #define AIPS_PACRN_WP4_MASK (0x2000U) #define AIPS_PACRN_WP4_SHIFT (13U) #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) #define AIPS_PACRN_SP4_MASK (0x4000U) #define AIPS_PACRN_SP4_SHIFT (14U) #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) #define AIPS_PACRN_TP3_MASK (0x10000U) #define AIPS_PACRN_TP3_SHIFT (16U) #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) #define AIPS_PACRN_WP3_MASK (0x20000U) #define AIPS_PACRN_WP3_SHIFT (17U) #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) #define AIPS_PACRN_SP3_MASK (0x40000U) #define AIPS_PACRN_SP3_SHIFT (18U) #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) #define AIPS_PACRN_TP2_MASK (0x100000U) #define AIPS_PACRN_TP2_SHIFT (20U) #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) #define AIPS_PACRN_WP2_MASK (0x200000U) #define AIPS_PACRN_WP2_SHIFT (21U) #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) #define AIPS_PACRN_SP2_MASK (0x400000U) #define AIPS_PACRN_SP2_SHIFT (22U) #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) #define AIPS_PACRN_TP1_MASK (0x1000000U) #define AIPS_PACRN_TP1_SHIFT (24U) #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) #define AIPS_PACRN_WP1_MASK (0x2000000U) #define AIPS_PACRN_WP1_SHIFT (25U) #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) #define AIPS_PACRN_SP1_MASK (0x4000000U) #define AIPS_PACRN_SP1_SHIFT (26U) #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) #define AIPS_PACRN_TP0_MASK (0x10000000U) #define AIPS_PACRN_TP0_SHIFT (28U) #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) #define AIPS_PACRN_WP0_MASK (0x20000000U) #define AIPS_PACRN_WP0_SHIFT (29U) #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) #define AIPS_PACRN_SP0_MASK (0x40000000U) #define AIPS_PACRN_SP0_SHIFT (30U) #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) /*! @name PACRO - Peripheral Access Control Register */ #define AIPS_PACRO_TP7_MASK (0x1U) #define AIPS_PACRO_TP7_SHIFT (0U) #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) #define AIPS_PACRO_WP7_MASK (0x2U) #define AIPS_PACRO_WP7_SHIFT (1U) #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) #define AIPS_PACRO_SP7_MASK (0x4U) #define AIPS_PACRO_SP7_SHIFT (2U) #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) #define AIPS_PACRO_TP6_MASK (0x10U) #define AIPS_PACRO_TP6_SHIFT (4U) #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) #define AIPS_PACRO_WP6_MASK (0x20U) #define AIPS_PACRO_WP6_SHIFT (5U) #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) #define AIPS_PACRO_SP6_MASK (0x40U) #define AIPS_PACRO_SP6_SHIFT (6U) #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) #define AIPS_PACRO_TP5_MASK (0x100U) #define AIPS_PACRO_TP5_SHIFT (8U) #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) #define AIPS_PACRO_WP5_MASK (0x200U) #define AIPS_PACRO_WP5_SHIFT (9U) #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) #define AIPS_PACRO_SP5_MASK (0x400U) #define AIPS_PACRO_SP5_SHIFT (10U) #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) #define AIPS_PACRO_TP4_MASK (0x1000U) #define AIPS_PACRO_TP4_SHIFT (12U) #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) #define AIPS_PACRO_WP4_MASK (0x2000U) #define AIPS_PACRO_WP4_SHIFT (13U) #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) #define AIPS_PACRO_SP4_MASK (0x4000U) #define AIPS_PACRO_SP4_SHIFT (14U) #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) #define AIPS_PACRO_TP3_MASK (0x10000U) #define AIPS_PACRO_TP3_SHIFT (16U) #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) #define AIPS_PACRO_WP3_MASK (0x20000U) #define AIPS_PACRO_WP3_SHIFT (17U) #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) #define AIPS_PACRO_SP3_MASK (0x40000U) #define AIPS_PACRO_SP3_SHIFT (18U) #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) #define AIPS_PACRO_TP2_MASK (0x100000U) #define AIPS_PACRO_TP2_SHIFT (20U) #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) #define AIPS_PACRO_WP2_MASK (0x200000U) #define AIPS_PACRO_WP2_SHIFT (21U) #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) #define AIPS_PACRO_SP2_MASK (0x400000U) #define AIPS_PACRO_SP2_SHIFT (22U) #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) #define AIPS_PACRO_TP1_MASK (0x1000000U) #define AIPS_PACRO_TP1_SHIFT (24U) #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) #define AIPS_PACRO_WP1_MASK (0x2000000U) #define AIPS_PACRO_WP1_SHIFT (25U) #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) #define AIPS_PACRO_SP1_MASK (0x4000000U) #define AIPS_PACRO_SP1_SHIFT (26U) #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) #define AIPS_PACRO_TP0_MASK (0x10000000U) #define AIPS_PACRO_TP0_SHIFT (28U) #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) #define AIPS_PACRO_WP0_MASK (0x20000000U) #define AIPS_PACRO_WP0_SHIFT (29U) #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) #define AIPS_PACRO_SP0_MASK (0x40000000U) #define AIPS_PACRO_SP0_SHIFT (30U) #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) /*! @name PACRP - Peripheral Access Control Register */ #define AIPS_PACRP_TP7_MASK (0x1U) #define AIPS_PACRP_TP7_SHIFT (0U) #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) #define AIPS_PACRP_WP7_MASK (0x2U) #define AIPS_PACRP_WP7_SHIFT (1U) #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) #define AIPS_PACRP_SP7_MASK (0x4U) #define AIPS_PACRP_SP7_SHIFT (2U) #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) #define AIPS_PACRP_TP6_MASK (0x10U) #define AIPS_PACRP_TP6_SHIFT (4U) #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) #define AIPS_PACRP_WP6_MASK (0x20U) #define AIPS_PACRP_WP6_SHIFT (5U) #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) #define AIPS_PACRP_SP6_MASK (0x40U) #define AIPS_PACRP_SP6_SHIFT (6U) #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) #define AIPS_PACRP_TP5_MASK (0x100U) #define AIPS_PACRP_TP5_SHIFT (8U) #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) #define AIPS_PACRP_WP5_MASK (0x200U) #define AIPS_PACRP_WP5_SHIFT (9U) #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) #define AIPS_PACRP_SP5_MASK (0x400U) #define AIPS_PACRP_SP5_SHIFT (10U) #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) #define AIPS_PACRP_TP4_MASK (0x1000U) #define AIPS_PACRP_TP4_SHIFT (12U) #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) #define AIPS_PACRP_WP4_MASK (0x2000U) #define AIPS_PACRP_WP4_SHIFT (13U) #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) #define AIPS_PACRP_SP4_MASK (0x4000U) #define AIPS_PACRP_SP4_SHIFT (14U) #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) #define AIPS_PACRP_TP3_MASK (0x10000U) #define AIPS_PACRP_TP3_SHIFT (16U) #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) #define AIPS_PACRP_WP3_MASK (0x20000U) #define AIPS_PACRP_WP3_SHIFT (17U) #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) #define AIPS_PACRP_SP3_MASK (0x40000U) #define AIPS_PACRP_SP3_SHIFT (18U) #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) #define AIPS_PACRP_TP2_MASK (0x100000U) #define AIPS_PACRP_TP2_SHIFT (20U) #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) #define AIPS_PACRP_WP2_MASK (0x200000U) #define AIPS_PACRP_WP2_SHIFT (21U) #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) #define AIPS_PACRP_SP2_MASK (0x400000U) #define AIPS_PACRP_SP2_SHIFT (22U) #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) #define AIPS_PACRP_TP1_MASK (0x1000000U) #define AIPS_PACRP_TP1_SHIFT (24U) #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) #define AIPS_PACRP_WP1_MASK (0x2000000U) #define AIPS_PACRP_WP1_SHIFT (25U) #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) #define AIPS_PACRP_SP1_MASK (0x4000000U) #define AIPS_PACRP_SP1_SHIFT (26U) #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) #define AIPS_PACRP_TP0_MASK (0x10000000U) #define AIPS_PACRP_TP0_SHIFT (28U) #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) #define AIPS_PACRP_WP0_MASK (0x20000000U) #define AIPS_PACRP_WP0_SHIFT (29U) #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) #define AIPS_PACRP_SP0_MASK (0x40000000U) #define AIPS_PACRP_SP0_SHIFT (30U) #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) /*! @name PACRU - Peripheral Access Control Register */ #define AIPS_PACRU_TP1_MASK (0x1000000U) #define AIPS_PACRU_TP1_SHIFT (24U) #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK) #define AIPS_PACRU_WP1_MASK (0x2000000U) #define AIPS_PACRU_WP1_SHIFT (25U) #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK) #define AIPS_PACRU_SP1_MASK (0x4000000U) #define AIPS_PACRU_SP1_SHIFT (26U) #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK) #define AIPS_PACRU_TP0_MASK (0x10000000U) #define AIPS_PACRU_TP0_SHIFT (28U) #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK) #define AIPS_PACRU_WP0_MASK (0x20000000U) #define AIPS_PACRU_WP0_SHIFT (29U) #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK) #define AIPS_PACRU_SP0_MASK (0x40000000U) #define AIPS_PACRU_SP0_SHIFT (30U) #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK) /*! * @} */ /* end of group AIPS_Register_Masks */ /* AIPS - Peripheral instance base addresses */ /** Peripheral AIPS0 base address */ #define AIPS0_BASE (0x40000000u) /** Peripheral AIPS0 base pointer */ #define AIPS0 ((AIPS_Type *)AIPS0_BASE) /** Peripheral AIPS1 base address */ #define AIPS1_BASE (0x40080000u) /** Peripheral AIPS1 base pointer */ #define AIPS1 ((AIPS_Type *)AIPS1_BASE) /** Array initializer of AIPS peripheral base addresses */ #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } /** Array initializer of AIPS peripheral base pointers */ #define AIPS_BASE_PTRS { AIPS0, AIPS1 } /*! * @} */ /* end of group AIPS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AXBS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer * @{ */ /** AXBS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x100 */ __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ uint8_t RESERVED_0[12]; __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ uint8_t RESERVED_1[236]; } SLAVE[5]; uint8_t RESERVED_0[768]; __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ uint8_t RESERVED_1[252]; __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ uint8_t RESERVED_2[252]; __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ uint8_t RESERVED_3[252]; __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ uint8_t RESERVED_4[252]; __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_5[252]; __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ } AXBS_Type; /* ---------------------------------------------------------------------------- -- AXBS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AXBS_Register_Masks AXBS Register Masks * @{ */ /*! @name PRS - Priority Registers Slave */ #define AXBS_PRS_M0_MASK (0x7U) #define AXBS_PRS_M0_SHIFT (0U) #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) #define AXBS_PRS_M1_MASK (0x70U) #define AXBS_PRS_M1_SHIFT (4U) #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) #define AXBS_PRS_M2_MASK (0x700U) #define AXBS_PRS_M2_SHIFT (8U) #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) #define AXBS_PRS_M3_MASK (0x7000U) #define AXBS_PRS_M3_SHIFT (12U) #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) #define AXBS_PRS_M4_MASK (0x70000U) #define AXBS_PRS_M4_SHIFT (16U) #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) #define AXBS_PRS_M5_MASK (0x700000U) #define AXBS_PRS_M5_SHIFT (20U) #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) /* The count of AXBS_PRS */ #define AXBS_PRS_COUNT (5U) /*! @name CRS - Control Register */ #define AXBS_CRS_PARK_MASK (0x7U) #define AXBS_CRS_PARK_SHIFT (0U) #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) #define AXBS_CRS_PCTL_MASK (0x30U) #define AXBS_CRS_PCTL_SHIFT (4U) #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) #define AXBS_CRS_ARB_MASK (0x300U) #define AXBS_CRS_ARB_SHIFT (8U) #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) #define AXBS_CRS_HLP_MASK (0x40000000U) #define AXBS_CRS_HLP_SHIFT (30U) #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) #define AXBS_CRS_RO_MASK (0x80000000U) #define AXBS_CRS_RO_SHIFT (31U) #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) /* The count of AXBS_CRS */ #define AXBS_CRS_COUNT (5U) /*! @name MGPCR0 - Master General Purpose Control Register */ #define AXBS_MGPCR0_AULB_MASK (0x7U) #define AXBS_MGPCR0_AULB_SHIFT (0U) #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) /*! @name MGPCR1 - Master General Purpose Control Register */ #define AXBS_MGPCR1_AULB_MASK (0x7U) #define AXBS_MGPCR1_AULB_SHIFT (0U) #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) /*! @name MGPCR2 - Master General Purpose Control Register */ #define AXBS_MGPCR2_AULB_MASK (0x7U) #define AXBS_MGPCR2_AULB_SHIFT (0U) #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) /*! @name MGPCR3 - Master General Purpose Control Register */ #define AXBS_MGPCR3_AULB_MASK (0x7U) #define AXBS_MGPCR3_AULB_SHIFT (0U) #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) /*! @name MGPCR4 - Master General Purpose Control Register */ #define AXBS_MGPCR4_AULB_MASK (0x7U) #define AXBS_MGPCR4_AULB_SHIFT (0U) #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) /*! @name MGPCR5 - Master General Purpose Control Register */ #define AXBS_MGPCR5_AULB_MASK (0x7U) #define AXBS_MGPCR5_AULB_SHIFT (0U) #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) /*! * @} */ /* end of group AXBS_Register_Masks */ /* AXBS - Peripheral instance base addresses */ /** Peripheral AXBS base address */ #define AXBS_BASE (0x40004000u) /** Peripheral AXBS base pointer */ #define AXBS ((AXBS_Type *)AXBS_BASE) /** Array initializer of AXBS peripheral base addresses */ #define AXBS_BASE_ADDRS { AXBS_BASE } /** Array initializer of AXBS peripheral base pointers */ #define AXBS_BASE_PTRS { AXBS } /*! * @} */ /* end of group AXBS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer * @{ */ /** CAN - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ uint8_t RESERVED_1[4]; __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ uint8_t RESERVED_3[8]; __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ uint8_t RESERVED_4[48]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[16]; uint8_t RESERVED_5[1792]; __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ } CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /*! @name MCR - Module Configuration Register */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @name CTRL1 - Control 1 register */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_CLKSRC_MASK (0x2000U) #define CAN_CTRL1_CLKSRC_SHIFT (13U) #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @name TIMER - Free Running Timer */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @name RX14MASK - Rx 14 Mask register */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @name RX15MASK - Rx 15 Mask register */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @name ECR - Error Counter */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) /*! @name ESR1 - Error and Status 1 register */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) /*! @name IMASK1 - Interrupt Masks 1 register */ #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUFLM_SHIFT (0U) #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) /*! @name IFLAG1 - Interrupt Flags 1 register */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @name CTRL2 - Control 2 register */ #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) /*! @name ESR2 - Error and Status 2 register */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @name CRCR - CRC Register */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @name RXFGMASK - Rx FIFO Global Mask register */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @name RXFIR - Rx FIFO Information Register */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) /* The count of CAN_CS */ #define CAN_CS_COUNT (16U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) /* The count of CAN_ID */ #define CAN_ID_COUNT (16U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (16U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (16U) /*! @name RXIMR - Rx Individual Mask Registers */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (16U) /*! * @} */ /* end of group CAN_Register_Masks */ /* CAN - Peripheral instance base addresses */ /** Peripheral CAN0 base address */ #define CAN0_BASE (0x40024000u) /** Peripheral CAN0 base pointer */ #define CAN0 ((CAN_Type *)CAN0_BASE) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { CAN0_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { CAN0 } /** Interrupt vectors for the CAN peripheral type */ #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn } #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn } #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn } #define CAN_Error_IRQS { CAN0_Error_IRQn } #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn } #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn } /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer * @{ */ /** CAU - Register Layout Typedef */ typedef struct { __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[2048]; __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ uint8_t RESERVED_1[20]; __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ uint8_t RESERVED_2[20]; __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ uint8_t RESERVED_3[20]; __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ uint8_t RESERVED_4[84]; __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ uint8_t RESERVED_5[20]; __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ uint8_t RESERVED_6[276]; __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ uint8_t RESERVED_7[20]; __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ } CAU_Type; /* ---------------------------------------------------------------------------- -- CAU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAU_Register_Masks CAU Register Masks * @{ */ /*! @name DIRECT - Direct access register 0..Direct access register 15 */ #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) /* The count of CAU_DIRECT */ #define CAU_DIRECT_COUNT (16U) /*! @name LDR_CASR - Status register - Load Register command */ #define CAU_LDR_CASR_IC_MASK (0x1U) #define CAU_LDR_CASR_IC_SHIFT (0U) #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) #define CAU_LDR_CASR_DPE_MASK (0x2U) #define CAU_LDR_CASR_DPE_SHIFT (1U) #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) #define CAU_LDR_CASR_VER_MASK (0xF0000000U) #define CAU_LDR_CASR_VER_SHIFT (28U) #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) /*! @name LDR_CAA - Accumulator register - Load Register command */ #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_LDR_CAA_ACC_SHIFT (0U) #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA0_SHIFT (0U) #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA1_SHIFT (0U) #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA2_SHIFT (0U) #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA3_SHIFT (0U) #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA4_SHIFT (0U) #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA5_SHIFT (0U) #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA6_SHIFT (0U) #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA7_SHIFT (0U) #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_LDR_CA_CA8_SHIFT (0U) #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) /* The count of CAU_LDR_CA */ #define CAU_LDR_CA_COUNT (9U) /*! @name STR_CASR - Status register - Store Register command */ #define CAU_STR_CASR_IC_MASK (0x1U) #define CAU_STR_CASR_IC_SHIFT (0U) #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) #define CAU_STR_CASR_DPE_MASK (0x2U) #define CAU_STR_CASR_DPE_SHIFT (1U) #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) #define CAU_STR_CASR_VER_MASK (0xF0000000U) #define CAU_STR_CASR_VER_SHIFT (28U) #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) /*! @name STR_CAA - Accumulator register - Store Register command */ #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_STR_CAA_ACC_SHIFT (0U) #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA0_SHIFT (0U) #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA1_SHIFT (0U) #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA2_SHIFT (0U) #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA3_SHIFT (0U) #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA4_SHIFT (0U) #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA5_SHIFT (0U) #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA6_SHIFT (0U) #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA7_SHIFT (0U) #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_STR_CA_CA8_SHIFT (0U) #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) /* The count of CAU_STR_CA */ #define CAU_STR_CA_COUNT (9U) /*! @name ADR_CASR - Status register - Add Register command */ #define CAU_ADR_CASR_IC_MASK (0x1U) #define CAU_ADR_CASR_IC_SHIFT (0U) #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) #define CAU_ADR_CASR_DPE_MASK (0x2U) #define CAU_ADR_CASR_DPE_SHIFT (1U) #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) #define CAU_ADR_CASR_VER_MASK (0xF0000000U) #define CAU_ADR_CASR_VER_SHIFT (28U) #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) /*! @name ADR_CAA - Accumulator register - Add to register command */ #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_ADR_CAA_ACC_SHIFT (0U) #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA0_SHIFT (0U) #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA1_SHIFT (0U) #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA2_SHIFT (0U) #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA3_SHIFT (0U) #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA4_SHIFT (0U) #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA5_SHIFT (0U) #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA6_SHIFT (0U) #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA7_SHIFT (0U) #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_ADR_CA_CA8_SHIFT (0U) #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) /* The count of CAU_ADR_CA */ #define CAU_ADR_CA_COUNT (9U) /*! @name RADR_CASR - Status register - Reverse and Add to Register command */ #define CAU_RADR_CASR_IC_MASK (0x1U) #define CAU_RADR_CASR_IC_SHIFT (0U) #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) #define CAU_RADR_CASR_DPE_MASK (0x2U) #define CAU_RADR_CASR_DPE_SHIFT (1U) #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) #define CAU_RADR_CASR_VER_MASK (0xF0000000U) #define CAU_RADR_CASR_VER_SHIFT (28U) #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_RADR_CAA_ACC_SHIFT (0U) #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA0_SHIFT (0U) #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA1_SHIFT (0U) #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA2_SHIFT (0U) #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA3_SHIFT (0U) #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA4_SHIFT (0U) #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA5_SHIFT (0U) #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA6_SHIFT (0U) #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA7_SHIFT (0U) #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_RADR_CA_CA8_SHIFT (0U) #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) /* The count of CAU_RADR_CA */ #define CAU_RADR_CA_COUNT (9U) /*! @name XOR_CASR - Status register - Exclusive Or command */ #define CAU_XOR_CASR_IC_MASK (0x1U) #define CAU_XOR_CASR_IC_SHIFT (0U) #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) #define CAU_XOR_CASR_DPE_MASK (0x2U) #define CAU_XOR_CASR_DPE_SHIFT (1U) #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) #define CAU_XOR_CASR_VER_MASK (0xF0000000U) #define CAU_XOR_CASR_VER_SHIFT (28U) #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) /*! @name XOR_CAA - Accumulator register - Exclusive Or command */ #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_XOR_CAA_ACC_SHIFT (0U) #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA0_SHIFT (0U) #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA1_SHIFT (0U) #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA2_SHIFT (0U) #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA3_SHIFT (0U) #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA4_SHIFT (0U) #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA5_SHIFT (0U) #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA6_SHIFT (0U) #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA7_SHIFT (0U) #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_XOR_CA_CA8_SHIFT (0U) #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) /* The count of CAU_XOR_CA */ #define CAU_XOR_CA_COUNT (9U) /*! @name ROTL_CASR - Status register - Rotate Left command */ #define CAU_ROTL_CASR_IC_MASK (0x1U) #define CAU_ROTL_CASR_IC_SHIFT (0U) #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) #define CAU_ROTL_CASR_DPE_MASK (0x2U) #define CAU_ROTL_CASR_DPE_SHIFT (1U) #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) #define CAU_ROTL_CASR_VER_MASK (0xF0000000U) #define CAU_ROTL_CASR_VER_SHIFT (28U) #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) /*! @name ROTL_CAA - Accumulator register - Rotate Left command */ #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_ROTL_CAA_ACC_SHIFT (0U) #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA0_SHIFT (0U) #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA1_SHIFT (0U) #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA2_SHIFT (0U) #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA3_SHIFT (0U) #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA4_SHIFT (0U) #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA5_SHIFT (0U) #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA6_SHIFT (0U) #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA7_SHIFT (0U) #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_ROTL_CA_CA8_SHIFT (0U) #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) /* The count of CAU_ROTL_CA */ #define CAU_ROTL_CA_COUNT (9U) /*! @name AESC_CASR - Status register - AES Column Operation command */ #define CAU_AESC_CASR_IC_MASK (0x1U) #define CAU_AESC_CASR_IC_SHIFT (0U) #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) #define CAU_AESC_CASR_DPE_MASK (0x2U) #define CAU_AESC_CASR_DPE_SHIFT (1U) #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) #define CAU_AESC_CASR_VER_MASK (0xF0000000U) #define CAU_AESC_CASR_VER_SHIFT (28U) #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) /*! @name AESC_CAA - Accumulator register - AES Column Operation command */ #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_AESC_CAA_ACC_SHIFT (0U) #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA0_SHIFT (0U) #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA1_SHIFT (0U) #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA2_SHIFT (0U) #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA3_SHIFT (0U) #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA4_SHIFT (0U) #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA5_SHIFT (0U) #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA6_SHIFT (0U) #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA7_SHIFT (0U) #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_AESC_CA_CA8_SHIFT (0U) #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) /* The count of CAU_AESC_CA */ #define CAU_AESC_CA_COUNT (9U) /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ #define CAU_AESIC_CASR_IC_MASK (0x1U) #define CAU_AESIC_CASR_IC_SHIFT (0U) #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) #define CAU_AESIC_CASR_DPE_MASK (0x2U) #define CAU_AESIC_CASR_DPE_SHIFT (1U) #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) #define CAU_AESIC_CASR_VER_MASK (0xF0000000U) #define CAU_AESIC_CASR_VER_SHIFT (28U) #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) #define CAU_AESIC_CAA_ACC_SHIFT (0U) #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA0_SHIFT (0U) #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA1_SHIFT (0U) #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA2_SHIFT (0U) #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA3_SHIFT (0U) #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA4_SHIFT (0U) #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA5_SHIFT (0U) #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA6_SHIFT (0U) #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA7_SHIFT (0U) #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) #define CAU_AESIC_CA_CA8_SHIFT (0U) #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) /* The count of CAU_AESIC_CA */ #define CAU_AESIC_CA_COUNT (9U) /*! * @} */ /* end of group CAU_Register_Masks */ /* CAU - Peripheral instance base addresses */ /** Peripheral CAU base address */ #define CAU_BASE (0xE0081000u) /** Peripheral CAU base pointer */ #define CAU ((CAU_Type *)CAU_BASE) /** Array initializer of CAU peripheral base addresses */ #define CAU_BASE_ADDRS { CAU_BASE } /** Array initializer of CAU peripheral base pointers */ #define CAU_BASE_PTRS { CAU } /*! * @} */ /* end of group CAU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ /** CMP - Register Layout Typedef */ typedef struct { __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ } CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /*! @name CR0 - CMP Control Register 0 */ #define CMP_CR0_HYSTCTR_MASK (0x3U) #define CMP_CR0_HYSTCTR_SHIFT (0U) #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK (0x70U) #define CMP_CR0_FILTER_CNT_SHIFT (4U) #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) /*! @name CR1 - CMP Control Register 1 */ #define CMP_CR1_EN_MASK (0x1U) #define CMP_CR1_EN_SHIFT (0U) #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) #define CMP_CR1_OPE_MASK (0x2U) #define CMP_CR1_OPE_SHIFT (1U) #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) #define CMP_CR1_COS_MASK (0x4U) #define CMP_CR1_COS_SHIFT (2U) #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) #define CMP_CR1_INV_MASK (0x8U) #define CMP_CR1_INV_SHIFT (3U) #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) #define CMP_CR1_PMODE_MASK (0x10U) #define CMP_CR1_PMODE_SHIFT (4U) #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) #define CMP_CR1_WE_MASK (0x40U) #define CMP_CR1_WE_SHIFT (6U) #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) #define CMP_CR1_SE_MASK (0x80U) #define CMP_CR1_SE_SHIFT (7U) #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) /*! @name FPR - CMP Filter Period Register */ #define CMP_FPR_FILT_PER_MASK (0xFFU) #define CMP_FPR_FILT_PER_SHIFT (0U) #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) /*! @name SCR - CMP Status and Control Register */ #define CMP_SCR_COUT_MASK (0x1U) #define CMP_SCR_COUT_SHIFT (0U) #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) #define CMP_SCR_CFF_MASK (0x2U) #define CMP_SCR_CFF_SHIFT (1U) #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) #define CMP_SCR_CFR_MASK (0x4U) #define CMP_SCR_CFR_SHIFT (2U) #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) #define CMP_SCR_IEF_MASK (0x8U) #define CMP_SCR_IEF_SHIFT (3U) #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) #define CMP_SCR_IER_MASK (0x10U) #define CMP_SCR_IER_SHIFT (4U) #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) #define CMP_SCR_DMAEN_MASK (0x40U) #define CMP_SCR_DMAEN_SHIFT (6U) #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) /*! @name DACCR - DAC Control Register */ #define CMP_DACCR_VOSEL_MASK (0x3FU) #define CMP_DACCR_VOSEL_SHIFT (0U) #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) #define CMP_DACCR_VRSEL_MASK (0x40U) #define CMP_DACCR_VRSEL_SHIFT (6U) #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) #define CMP_DACCR_DACEN_MASK (0x80U) #define CMP_DACCR_DACEN_SHIFT (7U) #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) /*! @name MUXCR - MUX Control Register */ #define CMP_MUXCR_MSEL_MASK (0x7U) #define CMP_MUXCR_MSEL_SHIFT (0U) #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK (0x38U) #define CMP_MUXCR_PSEL_SHIFT (3U) #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) #define CMP_MUXCR_PSTM_MASK (0x80U) #define CMP_MUXCR_PSTM_SHIFT (7U) #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) /*! * @} */ /* end of group CMP_Register_Masks */ /* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define CMP0_BASE (0x40073000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((CMP_Type *)CMP0_BASE) /** Peripheral CMP1 base address */ #define CMP1_BASE (0x40073008u) /** Peripheral CMP1 base pointer */ #define CMP1 ((CMP_Type *)CMP1_BASE) /** Peripheral CMP2 base address */ #define CMP2_BASE (0x40073010u) /** Peripheral CMP2 base pointer */ #define CMP2 ((CMP_Type *)CMP2_BASE) /** Array initializer of CMP peripheral base addresses */ #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 } /** Interrupt vectors for the CMP peripheral type */ #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn } /*! * @} */ /* end of group CMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer * @{ */ /** CMT - Register Layout Typedef */ typedef struct { __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ } CMT_Type; /* ---------------------------------------------------------------------------- -- CMT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMT_Register_Masks CMT Register Masks * @{ */ /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ #define CMT_CGH1_PH_MASK (0xFFU) #define CMT_CGH1_PH_SHIFT (0U) #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ #define CMT_CGL1_PL_MASK (0xFFU) #define CMT_CGL1_PL_SHIFT (0U) #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ #define CMT_CGH2_SH_MASK (0xFFU) #define CMT_CGH2_SH_SHIFT (0U) #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ #define CMT_CGL2_SL_MASK (0xFFU) #define CMT_CGL2_SL_SHIFT (0U) #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) /*! @name OC - CMT Output Control Register */ #define CMT_OC_IROPEN_MASK (0x20U) #define CMT_OC_IROPEN_SHIFT (5U) #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) #define CMT_OC_CMTPOL_MASK (0x40U) #define CMT_OC_CMTPOL_SHIFT (6U) #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) #define CMT_OC_IROL_MASK (0x80U) #define CMT_OC_IROL_SHIFT (7U) #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) /*! @name MSC - CMT Modulator Status and Control Register */ #define CMT_MSC_MCGEN_MASK (0x1U) #define CMT_MSC_MCGEN_SHIFT (0U) #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) #define CMT_MSC_EOCIE_MASK (0x2U) #define CMT_MSC_EOCIE_SHIFT (1U) #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) #define CMT_MSC_FSK_MASK (0x4U) #define CMT_MSC_FSK_SHIFT (2U) #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) #define CMT_MSC_BASE_MASK (0x8U) #define CMT_MSC_BASE_SHIFT (3U) #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) #define CMT_MSC_EXSPC_MASK (0x10U) #define CMT_MSC_EXSPC_SHIFT (4U) #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) #define CMT_MSC_CMTDIV_MASK (0x60U) #define CMT_MSC_CMTDIV_SHIFT (5U) #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) #define CMT_MSC_EOCF_MASK (0x80U) #define CMT_MSC_EOCF_SHIFT (7U) #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) /*! @name CMD1 - CMT Modulator Data Register Mark High */ #define CMT_CMD1_MB_MASK (0xFFU) #define CMT_CMD1_MB_SHIFT (0U) #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) /*! @name CMD2 - CMT Modulator Data Register Mark Low */ #define CMT_CMD2_MB_MASK (0xFFU) #define CMT_CMD2_MB_SHIFT (0U) #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) /*! @name CMD3 - CMT Modulator Data Register Space High */ #define CMT_CMD3_SB_MASK (0xFFU) #define CMT_CMD3_SB_SHIFT (0U) #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) /*! @name CMD4 - CMT Modulator Data Register Space Low */ #define CMT_CMD4_SB_MASK (0xFFU) #define CMT_CMD4_SB_SHIFT (0U) #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) /*! @name PPS - CMT Primary Prescaler Register */ #define CMT_PPS_PPSDIV_MASK (0xFU) #define CMT_PPS_PPSDIV_SHIFT (0U) #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) /*! @name DMA - CMT Direct Memory Access Register */ #define CMT_DMA_DMA_MASK (0x1U) #define CMT_DMA_DMA_SHIFT (0U) #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) /*! * @} */ /* end of group CMT_Register_Masks */ /* CMT - Peripheral instance base addresses */ /** Peripheral CMT base address */ #define CMT_BASE (0x40062000u) /** Peripheral CMT base pointer */ #define CMT ((CMT_Type *)CMT_BASE) /** Array initializer of CMT peripheral base addresses */ #define CMT_BASE_ADDRS { CMT_BASE } /** Array initializer of CMT peripheral base pointers */ #define CMT_BASE_PTRS { CMT } /** Interrupt vectors for the CMT peripheral type */ #define CMT_IRQS { CMT_IRQn } /*! * @} */ /* end of group CMT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer * @{ */ /** CRC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ } ACCESS16BIT; __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ } ACCESS8BIT; }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ } GPOLY_ACCESS16BIT; __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ } GPOLY_ACCESS8BIT; }; union { /* offset: 0x8 */ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ } CTRL_ACCESS8BIT; }; } CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /*! @name DATAL - CRC_DATAL register. */ #define CRC_DATAL_DATAL_MASK (0xFFFFU) #define CRC_DATAL_DATAL_SHIFT (0U) #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) /*! @name DATAH - CRC_DATAH register. */ #define CRC_DATAH_DATAH_MASK (0xFFFFU) #define CRC_DATAH_DATAH_SHIFT (0U) #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @name DATA - CRC Data register */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @name DATALL - CRC_DATALL register. */ #define CRC_DATALL_DATALL_MASK (0xFFU) #define CRC_DATALL_DATALL_SHIFT (0U) #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) /*! @name DATALU - CRC_DATALU register. */ #define CRC_DATALU_DATALU_MASK (0xFFU) #define CRC_DATALU_DATALU_SHIFT (0U) #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) /*! @name DATAHL - CRC_DATAHL register. */ #define CRC_DATAHL_DATAHL_MASK (0xFFU) #define CRC_DATAHL_DATAHL_SHIFT (0U) #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) /*! @name DATAHU - CRC_DATAHU register. */ #define CRC_DATAHU_DATAHU_MASK (0xFFU) #define CRC_DATAHU_DATAHU_SHIFT (0U) #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) /*! @name GPOLYL - CRC_GPOLYL register. */ #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) #define CRC_GPOLYL_GPOLYL_SHIFT (0U) #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) /*! @name GPOLYH - CRC_GPOLYH register. */ #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) #define CRC_GPOLYH_GPOLYH_SHIFT (0U) #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @name GPOLY - CRC Polynomial register */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @name GPOLYLL - CRC_GPOLYLL register. */ #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) /*! @name GPOLYLU - CRC_GPOLYLU register. */ #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) /*! @name GPOLYHL - CRC_GPOLYHL register. */ #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) /*! @name GPOLYHU - CRC_GPOLYHU register. */ #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) /*! @name CTRL - CRC Control register */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) #define CRC_CTRL_WAS_MASK (0x2000000U) #define CRC_CTRL_WAS_SHIFT (25U) #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) #define CRC_CTRL_TOTR_MASK (0x30000000U) #define CRC_CTRL_TOTR_SHIFT (28U) #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @name CTRLHU - CRC_CTRLHU register. */ #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) #define CRC_CTRLHU_WAS_MASK (0x2U) #define CRC_CTRLHU_WAS_SHIFT (1U) #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) #define CRC_CTRLHU_TOTR_MASK (0x30U) #define CRC_CTRLHU_TOTR_SHIFT (4U) #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! * @} */ /* end of group CRC_Register_Masks */ /* CRC - Peripheral instance base addresses */ /** Peripheral CRC base address */ #define CRC_BASE (0x40032000u) /** Peripheral CRC base pointer */ #define CRC0 ((CRC_Type *)CRC_BASE) /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS { CRC_BASE } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS { CRC0 } /*! * @} */ /* end of group CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DAC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer * @{ */ /** DAC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x2 */ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ } DAT[16]; __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ } DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /*! @name DATL - DAC Data Low Register */ #define DAC_DATL_DATA0_MASK (0xFFU) #define DAC_DATL_DATA0_SHIFT (0U) #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) /* The count of DAC_DATL */ #define DAC_DATL_COUNT (16U) /*! @name DATH - DAC Data High Register */ #define DAC_DATH_DATA1_MASK (0xFU) #define DAC_DATH_DATA1_SHIFT (0U) #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) /* The count of DAC_DATH */ #define DAC_DATH_COUNT (16U) /*! @name SR - DAC Status Register */ #define DAC_SR_DACBFRPBF_MASK (0x1U) #define DAC_SR_DACBFRPBF_SHIFT (0U) #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) #define DAC_SR_DACBFRPTF_MASK (0x2U) #define DAC_SR_DACBFRPTF_SHIFT (1U) #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) #define DAC_SR_DACBFWMF_MASK (0x4U) #define DAC_SR_DACBFWMF_SHIFT (2U) #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) /*! @name C0 - DAC Control Register */ #define DAC_C0_DACBBIEN_MASK (0x1U) #define DAC_C0_DACBBIEN_SHIFT (0U) #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) #define DAC_C0_DACBTIEN_MASK (0x2U) #define DAC_C0_DACBTIEN_SHIFT (1U) #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) #define DAC_C0_DACBWIEN_MASK (0x4U) #define DAC_C0_DACBWIEN_SHIFT (2U) #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) #define DAC_C0_LPEN_MASK (0x8U) #define DAC_C0_LPEN_SHIFT (3U) #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) #define DAC_C0_DACSWTRG_MASK (0x10U) #define DAC_C0_DACSWTRG_SHIFT (4U) #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) #define DAC_C0_DACTRGSEL_MASK (0x20U) #define DAC_C0_DACTRGSEL_SHIFT (5U) #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) #define DAC_C0_DACRFS_MASK (0x40U) #define DAC_C0_DACRFS_SHIFT (6U) #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) #define DAC_C0_DACEN_MASK (0x80U) #define DAC_C0_DACEN_SHIFT (7U) #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) /*! @name C1 - DAC Control Register 1 */ #define DAC_C1_DACBFEN_MASK (0x1U) #define DAC_C1_DACBFEN_SHIFT (0U) #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) #define DAC_C1_DACBFMD_MASK (0x6U) #define DAC_C1_DACBFMD_SHIFT (1U) #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) #define DAC_C1_DACBFWM_MASK (0x18U) #define DAC_C1_DACBFWM_SHIFT (3U) #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) #define DAC_C1_DMAEN_MASK (0x80U) #define DAC_C1_DMAEN_SHIFT (7U) #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) /*! @name C2 - DAC Control Register 2 */ #define DAC_C2_DACBFUP_MASK (0xFU) #define DAC_C2_DACBFUP_SHIFT (0U) #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) #define DAC_C2_DACBFRP_MASK (0xF0U) #define DAC_C2_DACBFRP_SHIFT (4U) #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) /*! * @} */ /* end of group DAC_Register_Masks */ /* DAC - Peripheral instance base addresses */ /** Peripheral DAC0 base address */ #define DAC0_BASE (0x400CC000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE) /** Peripheral DAC1 base address */ #define DAC1_BASE (0x400CD000u) /** Peripheral DAC1 base pointer */ #define DAC1 ((DAC_Type *)DAC1_BASE) /** Array initializer of DAC peripheral base addresses */ #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0, DAC1 } /** Interrupt vectors for the DAC peripheral type */ #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } /*! * @} */ /* end of group DAC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control Register, offset: 0x0 */ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ uint8_t RESERVED_1[4]; __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ uint8_t RESERVED_2[4]; __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ uint8_t RESERVED_3[4]; __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ uint8_t RESERVED_4[4]; __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ uint8_t RESERVED_5[200]; __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ uint8_t RESERVED_6[3824]; struct { /* offset: 0x1000, array step: 0x20 */ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ union { /* offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ }; __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ union { /* offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ }; __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ union { /* offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ }; } TCD[16]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name CR - Control Register */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) /*! @name ES - Error Status Register */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0xF00U) #define DMA_ES_ERRCHN_SHIFT (8U) #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) /*! @name ERQ - Enable Request Register */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) #define DMA_ERQ_ERQ8_MASK (0x100U) #define DMA_ERQ_ERQ8_SHIFT (8U) #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) #define DMA_ERQ_ERQ9_MASK (0x200U) #define DMA_ERQ_ERQ9_SHIFT (9U) #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) #define DMA_ERQ_ERQ10_MASK (0x400U) #define DMA_ERQ_ERQ10_SHIFT (10U) #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) #define DMA_ERQ_ERQ11_MASK (0x800U) #define DMA_ERQ_ERQ11_SHIFT (11U) #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) #define DMA_ERQ_ERQ12_MASK (0x1000U) #define DMA_ERQ_ERQ12_SHIFT (12U) #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) #define DMA_ERQ_ERQ13_MASK (0x2000U) #define DMA_ERQ_ERQ13_SHIFT (13U) #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) #define DMA_ERQ_ERQ14_MASK (0x4000U) #define DMA_ERQ_ERQ14_SHIFT (14U) #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) #define DMA_ERQ_ERQ15_MASK (0x8000U) #define DMA_ERQ_ERQ15_SHIFT (15U) #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) /*! @name EEI - Enable Error Interrupt Register */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) #define DMA_EEI_EEI8_MASK (0x100U) #define DMA_EEI_EEI8_SHIFT (8U) #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) #define DMA_EEI_EEI9_MASK (0x200U) #define DMA_EEI_EEI9_SHIFT (9U) #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) #define DMA_EEI_EEI10_MASK (0x400U) #define DMA_EEI_EEI10_SHIFT (10U) #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) #define DMA_EEI_EEI11_MASK (0x800U) #define DMA_EEI_EEI11_SHIFT (11U) #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) #define DMA_EEI_EEI12_MASK (0x1000U) #define DMA_EEI_EEI12_SHIFT (12U) #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) #define DMA_EEI_EEI13_MASK (0x2000U) #define DMA_EEI_EEI13_SHIFT (13U) #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) #define DMA_EEI_EEI14_MASK (0x4000U) #define DMA_EEI_EEI14_SHIFT (14U) #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) #define DMA_EEI_EEI15_MASK (0x8000U) #define DMA_EEI_EEI15_SHIFT (15U) #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) /*! @name CEEI - Clear Enable Error Interrupt Register */ #define DMA_CEEI_CEEI_MASK (0xFU) #define DMA_CEEI_CEEI_SHIFT (0U) #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) /*! @name SEEI - Set Enable Error Interrupt Register */ #define DMA_SEEI_SEEI_MASK (0xFU) #define DMA_SEEI_SEEI_SHIFT (0U) #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) /*! @name CERQ - Clear Enable Request Register */ #define DMA_CERQ_CERQ_MASK (0xFU) #define DMA_CERQ_CERQ_SHIFT (0U) #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) /*! @name SERQ - Set Enable Request Register */ #define DMA_SERQ_SERQ_MASK (0xFU) #define DMA_SERQ_SERQ_SHIFT (0U) #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) /*! @name CDNE - Clear DONE Status Bit Register */ #define DMA_CDNE_CDNE_MASK (0xFU) #define DMA_CDNE_CDNE_SHIFT (0U) #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) /*! @name SSRT - Set START Bit Register */ #define DMA_SSRT_SSRT_MASK (0xFU) #define DMA_SSRT_SSRT_SHIFT (0U) #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) /*! @name CERR - Clear Error Register */ #define DMA_CERR_CERR_MASK (0xFU) #define DMA_CERR_CERR_SHIFT (0U) #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) /*! @name CINT - Clear Interrupt Request Register */ #define DMA_CINT_CINT_MASK (0xFU) #define DMA_CINT_CINT_SHIFT (0U) #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) /*! @name INT - Interrupt Request Register */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) #define DMA_INT_INT8_MASK (0x100U) #define DMA_INT_INT8_SHIFT (8U) #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) #define DMA_INT_INT9_MASK (0x200U) #define DMA_INT_INT9_SHIFT (9U) #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) #define DMA_INT_INT10_MASK (0x400U) #define DMA_INT_INT10_SHIFT (10U) #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) #define DMA_INT_INT11_MASK (0x800U) #define DMA_INT_INT11_SHIFT (11U) #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) #define DMA_INT_INT12_MASK (0x1000U) #define DMA_INT_INT12_SHIFT (12U) #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) #define DMA_INT_INT13_MASK (0x2000U) #define DMA_INT_INT13_SHIFT (13U) #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) #define DMA_INT_INT14_MASK (0x4000U) #define DMA_INT_INT14_SHIFT (14U) #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) #define DMA_INT_INT15_MASK (0x8000U) #define DMA_INT_INT15_SHIFT (15U) #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) /*! @name ERR - Error Register */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) #define DMA_ERR_ERR8_MASK (0x100U) #define DMA_ERR_ERR8_SHIFT (8U) #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) #define DMA_ERR_ERR9_MASK (0x200U) #define DMA_ERR_ERR9_SHIFT (9U) #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) #define DMA_ERR_ERR10_MASK (0x400U) #define DMA_ERR_ERR10_SHIFT (10U) #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) #define DMA_ERR_ERR11_MASK (0x800U) #define DMA_ERR_ERR11_SHIFT (11U) #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) #define DMA_ERR_ERR12_MASK (0x1000U) #define DMA_ERR_ERR12_SHIFT (12U) #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) #define DMA_ERR_ERR13_MASK (0x2000U) #define DMA_ERR_ERR13_SHIFT (13U) #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) #define DMA_ERR_ERR14_MASK (0x4000U) #define DMA_ERR_ERR14_SHIFT (14U) #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) #define DMA_ERR_ERR15_MASK (0x8000U) #define DMA_ERR_ERR15_SHIFT (15U) #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) /*! @name HRS - Hardware Request Status Register */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) #define DMA_HRS_HRS8_MASK (0x100U) #define DMA_HRS_HRS8_SHIFT (8U) #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) #define DMA_HRS_HRS9_MASK (0x200U) #define DMA_HRS_HRS9_SHIFT (9U) #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) #define DMA_HRS_HRS10_MASK (0x400U) #define DMA_HRS_HRS10_SHIFT (10U) #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) #define DMA_HRS_HRS11_MASK (0x800U) #define DMA_HRS_HRS11_SHIFT (11U) #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) #define DMA_HRS_HRS12_MASK (0x1000U) #define DMA_HRS_HRS12_SHIFT (12U) #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) #define DMA_HRS_HRS13_MASK (0x2000U) #define DMA_HRS_HRS13_SHIFT (13U) #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) #define DMA_HRS_HRS14_MASK (0x4000U) #define DMA_HRS_HRS14_SHIFT (14U) #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) #define DMA_HRS_HRS15_MASK (0x8000U) #define DMA_HRS_HRS15_SHIFT (15U) #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) /*! @name DCHPRI3 - Channel n Priority Register */ #define DMA_DCHPRI3_CHPRI_MASK (0xFU) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) /*! @name DCHPRI2 - Channel n Priority Register */ #define DMA_DCHPRI2_CHPRI_MASK (0xFU) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) /*! @name DCHPRI1 - Channel n Priority Register */ #define DMA_DCHPRI1_CHPRI_MASK (0xFU) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) /*! @name DCHPRI0 - Channel n Priority Register */ #define DMA_DCHPRI0_CHPRI_MASK (0xFU) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) /*! @name DCHPRI7 - Channel n Priority Register */ #define DMA_DCHPRI7_CHPRI_MASK (0xFU) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) /*! @name DCHPRI6 - Channel n Priority Register */ #define DMA_DCHPRI6_CHPRI_MASK (0xFU) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) /*! @name DCHPRI5 - Channel n Priority Register */ #define DMA_DCHPRI5_CHPRI_MASK (0xFU) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) /*! @name DCHPRI4 - Channel n Priority Register */ #define DMA_DCHPRI4_CHPRI_MASK (0xFU) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) /*! @name DCHPRI11 - Channel n Priority Register */ #define DMA_DCHPRI11_CHPRI_MASK (0xFU) #define DMA_DCHPRI11_CHPRI_SHIFT (0U) #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) #define DMA_DCHPRI11_DPA_MASK (0x40U) #define DMA_DCHPRI11_DPA_SHIFT (6U) #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) #define DMA_DCHPRI11_ECP_MASK (0x80U) #define DMA_DCHPRI11_ECP_SHIFT (7U) #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) /*! @name DCHPRI10 - Channel n Priority Register */ #define DMA_DCHPRI10_CHPRI_MASK (0xFU) #define DMA_DCHPRI10_CHPRI_SHIFT (0U) #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) #define DMA_DCHPRI10_DPA_MASK (0x40U) #define DMA_DCHPRI10_DPA_SHIFT (6U) #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) #define DMA_DCHPRI10_ECP_MASK (0x80U) #define DMA_DCHPRI10_ECP_SHIFT (7U) #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) /*! @name DCHPRI9 - Channel n Priority Register */ #define DMA_DCHPRI9_CHPRI_MASK (0xFU) #define DMA_DCHPRI9_CHPRI_SHIFT (0U) #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) #define DMA_DCHPRI9_DPA_MASK (0x40U) #define DMA_DCHPRI9_DPA_SHIFT (6U) #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) #define DMA_DCHPRI9_ECP_MASK (0x80U) #define DMA_DCHPRI9_ECP_SHIFT (7U) #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) /*! @name DCHPRI8 - Channel n Priority Register */ #define DMA_DCHPRI8_CHPRI_MASK (0xFU) #define DMA_DCHPRI8_CHPRI_SHIFT (0U) #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) #define DMA_DCHPRI8_DPA_MASK (0x40U) #define DMA_DCHPRI8_DPA_SHIFT (6U) #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) #define DMA_DCHPRI8_ECP_MASK (0x80U) #define DMA_DCHPRI8_ECP_SHIFT (7U) #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) /*! @name DCHPRI15 - Channel n Priority Register */ #define DMA_DCHPRI15_CHPRI_MASK (0xFU) #define DMA_DCHPRI15_CHPRI_SHIFT (0U) #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) #define DMA_DCHPRI15_DPA_MASK (0x40U) #define DMA_DCHPRI15_DPA_SHIFT (6U) #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) #define DMA_DCHPRI15_ECP_MASK (0x80U) #define DMA_DCHPRI15_ECP_SHIFT (7U) #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) /*! @name DCHPRI14 - Channel n Priority Register */ #define DMA_DCHPRI14_CHPRI_MASK (0xFU) #define DMA_DCHPRI14_CHPRI_SHIFT (0U) #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) #define DMA_DCHPRI14_DPA_MASK (0x40U) #define DMA_DCHPRI14_DPA_SHIFT (6U) #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) #define DMA_DCHPRI14_ECP_MASK (0x80U) #define DMA_DCHPRI14_ECP_SHIFT (7U) #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) /*! @name DCHPRI13 - Channel n Priority Register */ #define DMA_DCHPRI13_CHPRI_MASK (0xFU) #define DMA_DCHPRI13_CHPRI_SHIFT (0U) #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) #define DMA_DCHPRI13_DPA_MASK (0x40U) #define DMA_DCHPRI13_DPA_SHIFT (6U) #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) #define DMA_DCHPRI13_ECP_MASK (0x80U) #define DMA_DCHPRI13_ECP_SHIFT (7U) #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) /*! @name DCHPRI12 - Channel n Priority Register */ #define DMA_DCHPRI12_CHPRI_MASK (0xFU) #define DMA_DCHPRI12_CHPRI_SHIFT (0U) #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) #define DMA_DCHPRI12_DPA_MASK (0x40U) #define DMA_DCHPRI12_DPA_SHIFT (6U) #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) #define DMA_DCHPRI12_ECP_MASK (0x80U) #define DMA_DCHPRI12_ECP_SHIFT (7U) #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) /*! @name SADDR - TCD Source Address */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (16U) /*! @name SOFF - TCD Signed Source Address Offset */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (16U) /*! @name ATTR - TCD Transfer Attributes */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) #define DMA_ATTR_DMOD_MASK (0xF8U) #define DMA_ATTR_DMOD_SHIFT (3U) #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (16U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (16U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (16U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (16U) /*! @name SLAST - TCD Last Source Address Adjustment */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (16U) /*! @name DADDR - TCD Destination Address */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (16U) /*! @name DOFF - TCD Signed Destination Address Offset */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (16U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (16U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (16U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (16U) /*! @name CSR - TCD Control and Status */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) #define DMA_CSR_DONE_MASK (0x80U) #define DMA_CSR_DONE_SHIFT (7U) #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) #define DMA_CSR_MAJORLINKCH_MASK (0xF00U) #define DMA_CSR_MAJORLINKCH_SHIFT (8U) #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) /* The count of DMA_CSR */ #define DMA_CSR_COUNT (16U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (16U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (16U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral DMA base address */ #define DMA_BASE (0x40008000u) /** Peripheral DMA base pointer */ #define DMA0 ((DMA_Type *)DMA_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } } #define DMA_ERROR_IRQS { DMA_Error_IRQn } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMAMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer * @{ */ /** DMAMUX - Register Layout Typedef */ typedef struct { __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /*! @name CHCFG - Channel Configuration register */ #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40U) #define DMAMUX_CHCFG_TRIG_SHIFT (6U) #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80U) #define DMAMUX_CHCFG_ENBL_SHIFT (7U) #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (16U) /*! * @} */ /* end of group DMAMUX_Register_Masks */ /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX base address */ #define DMAMUX_BASE (0x40021000u) /** Peripheral DMAMUX base pointer */ #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) /** Array initializer of DMAMUX peripheral base addresses */ #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } /** Array initializer of DMAMUX peripheral base pointers */ #define DMAMUX_BASE_PTRS { DMAMUX } /*! * @} */ /* end of group DMAMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer * @{ */ /** ENET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ uint8_t RESERVED_3[24]; __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ uint8_t RESERVED_4[28]; __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ uint8_t RESERVED_5[28]; __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ uint8_t RESERVED_6[60]; __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ uint8_t RESERVED_7[28]; __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ uint8_t RESERVED_8[40]; __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ uint8_t RESERVED_9[28]; __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ uint8_t RESERVED_10[56]; __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ uint8_t RESERVED_11[4]; __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ uint8_t RESERVED_12[12]; __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ uint8_t RESERVED_13[60]; __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ uint8_t RESERVED_14[4]; __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ uint8_t RESERVED_15[4]; __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ uint8_t RESERVED_16[12]; __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ uint8_t RESERVED_17[4]; __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ uint8_t RESERVED_18[284]; __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ uint8_t RESERVED_19[488]; __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ } CHANNEL[4]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /*! @name EIR - Interrupt Event Register */ #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) #define ENET_EIR_TS_AVAIL_MASK (0x10000U) #define ENET_EIR_TS_AVAIL_SHIFT (16U) #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) #define ENET_EIR_WAKEUP_MASK (0x20000U) #define ENET_EIR_WAKEUP_SHIFT (17U) #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) #define ENET_EIR_PLR_MASK (0x40000U) #define ENET_EIR_PLR_SHIFT (18U) #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) #define ENET_EIR_UN_MASK (0x80000U) #define ENET_EIR_UN_SHIFT (19U) #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) #define ENET_EIR_RL_MASK (0x100000U) #define ENET_EIR_RL_SHIFT (20U) #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) #define ENET_EIR_LC_MASK (0x200000U) #define ENET_EIR_LC_SHIFT (21U) #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) #define ENET_EIR_EBERR_MASK (0x400000U) #define ENET_EIR_EBERR_SHIFT (22U) #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) #define ENET_EIR_MII_MASK (0x800000U) #define ENET_EIR_MII_SHIFT (23U) #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) #define ENET_EIR_RXB_MASK (0x1000000U) #define ENET_EIR_RXB_SHIFT (24U) #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) #define ENET_EIR_RXF_MASK (0x2000000U) #define ENET_EIR_RXF_SHIFT (25U) #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) #define ENET_EIR_TXB_MASK (0x4000000U) #define ENET_EIR_TXB_SHIFT (26U) #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) #define ENET_EIR_TXF_MASK (0x8000000U) #define ENET_EIR_TXF_SHIFT (27U) #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) #define ENET_EIR_GRA_MASK (0x10000000U) #define ENET_EIR_GRA_SHIFT (28U) #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) #define ENET_EIR_BABT_MASK (0x20000000U) #define ENET_EIR_BABT_SHIFT (29U) #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) /*! @name EIMR - Interrupt Mask Register */ #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) #define ENET_EIMR_TS_AVAIL_SHIFT (16U) #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) #define ENET_EIMR_WAKEUP_MASK (0x20000U) #define ENET_EIMR_WAKEUP_SHIFT (17U) #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) #define ENET_EIMR_PLR_MASK (0x40000U) #define ENET_EIMR_PLR_SHIFT (18U) #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) #define ENET_EIMR_UN_MASK (0x80000U) #define ENET_EIMR_UN_SHIFT (19U) #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) #define ENET_EIMR_RL_MASK (0x100000U) #define ENET_EIMR_RL_SHIFT (20U) #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) #define ENET_EIMR_LC_MASK (0x200000U) #define ENET_EIMR_LC_SHIFT (21U) #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) #define ENET_EIMR_EBERR_MASK (0x400000U) #define ENET_EIMR_EBERR_SHIFT (22U) #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) #define ENET_EIMR_MII_MASK (0x800000U) #define ENET_EIMR_MII_SHIFT (23U) #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) #define ENET_EIMR_RXB_MASK (0x1000000U) #define ENET_EIMR_RXB_SHIFT (24U) #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) #define ENET_EIMR_RXF_MASK (0x2000000U) #define ENET_EIMR_RXF_SHIFT (25U) #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) /*! @name RDAR - Receive Descriptor Active Register */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) /*! @name TDAR - Transmit Descriptor Active Register */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) /*! @name ECR - Ethernet Control Register */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_STOPEN_MASK (0x80U) #define ENET_ECR_STOPEN_SHIFT (7U) #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) /*! @name MMFR - MII Management Frame Register */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) #define ENET_MMFR_TA_MASK (0x30000U) #define ENET_MMFR_TA_SHIFT (16U) #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) #define ENET_MMFR_RA_MASK (0x7C0000U) #define ENET_MMFR_RA_SHIFT (18U) #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) #define ENET_MMFR_PA_MASK (0xF800000U) #define ENET_MMFR_PA_SHIFT (23U) #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) #define ENET_MMFR_OP_MASK (0x30000000U) #define ENET_MMFR_OP_SHIFT (28U) #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) /*! @name MSCR - MII Speed Control Register */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) /*! @name MIBC - MIB Control Register */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) /*! @name RCR - Receive Control Register */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) #define ENET_RCR_FCE_MASK (0x20U) #define ENET_RCR_FCE_SHIFT (5U) #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) /*! @name TCR - Transmit Control Register */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) #define ENET_TCR_FDEN_MASK (0x4U) #define ENET_TCR_FDEN_SHIFT (2U) #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) /*! @name PALR - Physical Address Lower Register */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) /*! @name PAUR - Physical Address Upper Register */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) /*! @name OPD - Opcode/Pause Duration Register */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) /*! @name IAUR - Descriptor Individual Upper Address Register */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) /*! @name IALR - Descriptor Individual Lower Address Register */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) /*! @name GAUR - Descriptor Group Upper Address Register */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) /*! @name GALR - Descriptor Group Lower Address Register */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) /*! @name TFWR - Transmit FIFO Watermark Register */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) /*! @name RDSR - Receive Descriptor Ring Start Register */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) /*! @name MRBR - Maximum Receive Buffer Size Register */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /*! @name RSFL - Receive FIFO Section Full Threshold */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /*! @name RSEM - Receive FIFO Section Empty Threshold */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) /*! @name RAEM - Receive FIFO Almost Empty Threshold */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /*! @name RAFL - Receive FIFO Almost Full Threshold */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /*! @name TSEM - Transmit FIFO Section Empty Threshold */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /*! @name TAFL - Transmit FIFO Almost Full Threshold */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /*! @name TIPG - Transmit Inter-Packet Gap */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) /*! @name FTRL - Frame Truncation Length */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) /*! @name TACC - Transmit Accelerator Function Configuration */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) /*! @name RACC - Receive Accelerator Function Configuration */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) /*! @name ATCR - Adjustable Timer Control Register */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) /*! @name ATVR - Timer Value Register */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) /*! @name ATOFF - Timer Offset Register */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) /*! @name ATPER - Timer Period Register */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) /*! @name ATCOR - Timer Correction Register */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) /*! @name ATINC - Time-Stamping Clock Period Register */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) /*! @name TGSR - Timer Global Status Register */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) /*! @name TCSR - Timer Control Status Register */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) /*! * @} */ /* end of group ENET_Register_Masks */ /* ENET - Peripheral instance base addresses */ /** Peripheral ENET base address */ #define ENET_BASE (0x400C0000u) /** Peripheral ENET base pointer */ #define ENET ((ENET_Type *)ENET_BASE) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET } /** Interrupt vectors for the ENET peripheral type */ #define ENET_Transmit_IRQS { ENET_Transmit_IRQn } #define ENET_Receive_IRQS { ENET_Receive_IRQn } #define ENET_Error_IRQS { ENET_Error_IRQn } #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } /* ENET Buffer Descriptor and Buffer Address Alignment. */ #define ENET_BUFF_ALIGNMENT (16U) /*! * @} */ /* end of group ENET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer * @{ */ /** EWM - Register Layout Typedef */ typedef struct { __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ __O uint8_t SERV; /**< Service Register, offset: 0x1 */ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ } EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /*! @name CTRL - Control Register */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) #define EWM_CTRL_ASSIN_MASK (0x2U) #define EWM_CTRL_ASSIN_SHIFT (1U) #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) #define EWM_CTRL_INEN_MASK (0x4U) #define EWM_CTRL_INEN_SHIFT (2U) #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) /*! @name SERV - Service Register */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) /*! @name CMPL - Compare Low Register */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) /*! @name CMPH - Compare High Register */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) /*! * @} */ /* end of group EWM_Register_Masks */ /* EWM - Peripheral instance base addresses */ /** Peripheral EWM base address */ #define EWM_BASE (0x40061000u) /** Peripheral EWM base pointer */ #define EWM ((EWM_Type *)EWM_BASE) /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } /** Interrupt vectors for the EWM peripheral type */ #define EWM_IRQS { WDOG_EWM_IRQn } /*! * @} */ /* end of group EWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer * @{ */ /** FB - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0xC */ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ } CS[6]; uint8_t RESERVED_0[24]; __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ } FB_Type; /* ---------------------------------------------------------------------------- -- FB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FB_Register_Masks FB Register Masks * @{ */ /*! @name CSAR - Chip Select Address Register */ #define FB_CSAR_BA_MASK (0xFFFF0000U) #define FB_CSAR_BA_SHIFT (16U) #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) /* The count of FB_CSAR */ #define FB_CSAR_COUNT (6U) /*! @name CSMR - Chip Select Mask Register */ #define FB_CSMR_V_MASK (0x1U) #define FB_CSMR_V_SHIFT (0U) #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) #define FB_CSMR_WP_MASK (0x100U) #define FB_CSMR_WP_SHIFT (8U) #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) #define FB_CSMR_BAM_MASK (0xFFFF0000U) #define FB_CSMR_BAM_SHIFT (16U) #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) /* The count of FB_CSMR */ #define FB_CSMR_COUNT (6U) /*! @name CSCR - Chip Select Control Register */ #define FB_CSCR_BSTW_MASK (0x8U) #define FB_CSCR_BSTW_SHIFT (3U) #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) #define FB_CSCR_BSTR_MASK (0x10U) #define FB_CSCR_BSTR_SHIFT (4U) #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) #define FB_CSCR_BEM_MASK (0x20U) #define FB_CSCR_BEM_SHIFT (5U) #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) #define FB_CSCR_PS_MASK (0xC0U) #define FB_CSCR_PS_SHIFT (6U) #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) #define FB_CSCR_AA_MASK (0x100U) #define FB_CSCR_AA_SHIFT (8U) #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) #define FB_CSCR_BLS_MASK (0x200U) #define FB_CSCR_BLS_SHIFT (9U) #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) #define FB_CSCR_WS_MASK (0xFC00U) #define FB_CSCR_WS_SHIFT (10U) #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) #define FB_CSCR_WRAH_MASK (0x30000U) #define FB_CSCR_WRAH_SHIFT (16U) #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) #define FB_CSCR_RDAH_MASK (0xC0000U) #define FB_CSCR_RDAH_SHIFT (18U) #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) #define FB_CSCR_ASET_MASK (0x300000U) #define FB_CSCR_ASET_SHIFT (20U) #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) #define FB_CSCR_EXTS_MASK (0x400000U) #define FB_CSCR_EXTS_SHIFT (22U) #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) #define FB_CSCR_SWSEN_MASK (0x800000U) #define FB_CSCR_SWSEN_SHIFT (23U) #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) #define FB_CSCR_SWS_MASK (0xFC000000U) #define FB_CSCR_SWS_SHIFT (26U) #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) /* The count of FB_CSCR */ #define FB_CSCR_COUNT (6U) /*! @name CSPMCR - Chip Select port Multiplexing Control Register */ #define FB_CSPMCR_GROUP5_MASK (0xF000U) #define FB_CSPMCR_GROUP5_SHIFT (12U) #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) #define FB_CSPMCR_GROUP4_MASK (0xF0000U) #define FB_CSPMCR_GROUP4_SHIFT (16U) #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) #define FB_CSPMCR_GROUP3_MASK (0xF00000U) #define FB_CSPMCR_GROUP3_SHIFT (20U) #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) #define FB_CSPMCR_GROUP2_MASK (0xF000000U) #define FB_CSPMCR_GROUP2_SHIFT (24U) #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) #define FB_CSPMCR_GROUP1_MASK (0xF0000000U) #define FB_CSPMCR_GROUP1_SHIFT (28U) #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) /*! * @} */ /* end of group FB_Register_Masks */ /* FB - Peripheral instance base addresses */ /** Peripheral FB base address */ #define FB_BASE (0x4000C000u) /** Peripheral FB base pointer */ #define FB ((FB_Type *)FB_BASE) /** Array initializer of FB peripheral base addresses */ #define FB_BASE_ADDRS { FB_BASE } /** Array initializer of FB peripheral base pointers */ #define FB_BASE_PTRS { FB } /*! * @} */ /* end of group FB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer * @{ */ /** FMC - Register Layout Typedef */ typedef struct { __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ uint8_t RESERVED_0[244]; __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */ __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */ uint8_t RESERVED_1[192]; struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */ __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */ __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */ } SET[4][4]; } FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FMC_Register_Masks FMC Register Masks * @{ */ /*! @name PFAPR - Flash Access Protection Register */ #define FMC_PFAPR_M0AP_MASK (0x3U) #define FMC_PFAPR_M0AP_SHIFT (0U) #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) #define FMC_PFAPR_M1AP_MASK (0xCU) #define FMC_PFAPR_M1AP_SHIFT (2U) #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) #define FMC_PFAPR_M2AP_MASK (0x30U) #define FMC_PFAPR_M2AP_SHIFT (4U) #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) #define FMC_PFAPR_M3AP_MASK (0xC0U) #define FMC_PFAPR_M3AP_SHIFT (6U) #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) #define FMC_PFAPR_M4AP_MASK (0x300U) #define FMC_PFAPR_M4AP_SHIFT (8U) #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) #define FMC_PFAPR_M5AP_MASK (0xC00U) #define FMC_PFAPR_M5AP_SHIFT (10U) #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) #define FMC_PFAPR_M6AP_MASK (0x3000U) #define FMC_PFAPR_M6AP_SHIFT (12U) #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) #define FMC_PFAPR_M7AP_MASK (0xC000U) #define FMC_PFAPR_M7AP_SHIFT (14U) #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) #define FMC_PFAPR_M0PFD_MASK (0x10000U) #define FMC_PFAPR_M0PFD_SHIFT (16U) #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) #define FMC_PFAPR_M1PFD_MASK (0x20000U) #define FMC_PFAPR_M1PFD_SHIFT (17U) #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) #define FMC_PFAPR_M2PFD_MASK (0x40000U) #define FMC_PFAPR_M2PFD_SHIFT (18U) #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) #define FMC_PFAPR_M3PFD_MASK (0x80000U) #define FMC_PFAPR_M3PFD_SHIFT (19U) #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) #define FMC_PFAPR_M4PFD_MASK (0x100000U) #define FMC_PFAPR_M4PFD_SHIFT (20U) #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) #define FMC_PFAPR_M5PFD_MASK (0x200000U) #define FMC_PFAPR_M5PFD_SHIFT (21U) #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) #define FMC_PFAPR_M6PFD_MASK (0x400000U) #define FMC_PFAPR_M6PFD_SHIFT (22U) #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) #define FMC_PFAPR_M7PFD_MASK (0x800000U) #define FMC_PFAPR_M7PFD_SHIFT (23U) #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) /*! @name PFB0CR - Flash Bank 0 Control Register */ #define FMC_PFB0CR_B0SEBE_MASK (0x1U) #define FMC_PFB0CR_B0SEBE_SHIFT (0U) #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) #define FMC_PFB0CR_B0IPE_MASK (0x2U) #define FMC_PFB0CR_B0IPE_SHIFT (1U) #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) #define FMC_PFB0CR_B0DPE_MASK (0x4U) #define FMC_PFB0CR_B0DPE_SHIFT (2U) #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) #define FMC_PFB0CR_B0ICE_MASK (0x8U) #define FMC_PFB0CR_B0ICE_SHIFT (3U) #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) #define FMC_PFB0CR_B0DCE_MASK (0x10U) #define FMC_PFB0CR_B0DCE_SHIFT (4U) #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) #define FMC_PFB0CR_CRC_MASK (0xE0U) #define FMC_PFB0CR_CRC_SHIFT (5U) #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) #define FMC_PFB0CR_B0MW_MASK (0x60000U) #define FMC_PFB0CR_B0MW_SHIFT (17U) #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) #define FMC_PFB0CR_S_B_INV_MASK (0x80000U) #define FMC_PFB0CR_S_B_INV_SHIFT (19U) #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) #define FMC_PFB0CR_CINV_WAY_SHIFT (20U) #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) #define FMC_PFB0CR_B0RWSC_SHIFT (28U) #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) /*! @name PFB1CR - Flash Bank 1 Control Register */ #define FMC_PFB1CR_B1SEBE_MASK (0x1U) #define FMC_PFB1CR_B1SEBE_SHIFT (0U) #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) #define FMC_PFB1CR_B1IPE_MASK (0x2U) #define FMC_PFB1CR_B1IPE_SHIFT (1U) #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) #define FMC_PFB1CR_B1DPE_MASK (0x4U) #define FMC_PFB1CR_B1DPE_SHIFT (2U) #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) #define FMC_PFB1CR_B1ICE_MASK (0x8U) #define FMC_PFB1CR_B1ICE_SHIFT (3U) #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) #define FMC_PFB1CR_B1DCE_MASK (0x10U) #define FMC_PFB1CR_B1DCE_SHIFT (4U) #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) #define FMC_PFB1CR_B1MW_MASK (0x60000U) #define FMC_PFB1CR_B1MW_SHIFT (17U) #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) #define FMC_PFB1CR_B1RWSC_SHIFT (28U) #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) /*! @name TAGVDW0S - Cache Tag Storage */ #define FMC_TAGVDW0S_valid_MASK (0x1U) #define FMC_TAGVDW0S_valid_SHIFT (0U) #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) #define FMC_TAGVDW0S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW0S_tag_SHIFT (5U) #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK) /* The count of FMC_TAGVDW0S */ #define FMC_TAGVDW0S_COUNT (4U) /*! @name TAGVDW1S - Cache Tag Storage */ #define FMC_TAGVDW1S_valid_MASK (0x1U) #define FMC_TAGVDW1S_valid_SHIFT (0U) #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) #define FMC_TAGVDW1S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW1S_tag_SHIFT (5U) #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK) /* The count of FMC_TAGVDW1S */ #define FMC_TAGVDW1S_COUNT (4U) /*! @name TAGVDW2S - Cache Tag Storage */ #define FMC_TAGVDW2S_valid_MASK (0x1U) #define FMC_TAGVDW2S_valid_SHIFT (0U) #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) #define FMC_TAGVDW2S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW2S_tag_SHIFT (5U) #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK) /* The count of FMC_TAGVDW2S */ #define FMC_TAGVDW2S_COUNT (4U) /*! @name TAGVDW3S - Cache Tag Storage */ #define FMC_TAGVDW3S_valid_MASK (0x1U) #define FMC_TAGVDW3S_valid_SHIFT (0U) #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) #define FMC_TAGVDW3S_tag_MASK (0x7FFE0U) #define FMC_TAGVDW3S_tag_SHIFT (5U) #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK) /* The count of FMC_TAGVDW3S */ #define FMC_TAGVDW3S_COUNT (4U) /*! @name DATA_U - Cache Data Storage (upper word) */ #define FMC_DATA_U_data_MASK (0xFFFFFFFFU) #define FMC_DATA_U_data_SHIFT (0U) #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) /* The count of FMC_DATA_U */ #define FMC_DATA_U_COUNT (4U) /* The count of FMC_DATA_U */ #define FMC_DATA_U_COUNT2 (4U) /*! @name DATA_L - Cache Data Storage (lower word) */ #define FMC_DATA_L_data_MASK (0xFFFFFFFFU) #define FMC_DATA_L_data_SHIFT (0U) #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) /* The count of FMC_DATA_L */ #define FMC_DATA_L_COUNT (4U) /* The count of FMC_DATA_L */ #define FMC_DATA_L_COUNT2 (4U) /*! * @} */ /* end of group FMC_Register_Masks */ /* FMC - Peripheral instance base addresses */ /** Peripheral FMC base address */ #define FMC_BASE (0x4001F000u) /** Peripheral FMC base pointer */ #define FMC ((FMC_Type *)FMC_BASE) /** Array initializer of FMC peripheral base addresses */ #define FMC_BASE_ADDRS { FMC_BASE } /** Array initializer of FMC peripheral base pointers */ #define FMC_BASE_PTRS { FMC } /*! * @} */ /* end of group FMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTFE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer * @{ */ /** FTFE - Register Layout Typedef */ typedef struct { __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ uint8_t RESERVED_0[2]; __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ } FTFE_Type; /* ---------------------------------------------------------------------------- -- FTFE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFE_Register_Masks FTFE Register Masks * @{ */ /*! @name FSTAT - Flash Status Register */ #define FTFE_FSTAT_MGSTAT0_MASK (0x1U) #define FTFE_FSTAT_MGSTAT0_SHIFT (0U) #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) #define FTFE_FSTAT_FPVIOL_MASK (0x10U) #define FTFE_FSTAT_FPVIOL_SHIFT (4U) #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) #define FTFE_FSTAT_ACCERR_MASK (0x20U) #define FTFE_FSTAT_ACCERR_SHIFT (5U) #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) #define FTFE_FSTAT_RDCOLERR_MASK (0x40U) #define FTFE_FSTAT_RDCOLERR_SHIFT (6U) #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) #define FTFE_FSTAT_CCIF_MASK (0x80U) #define FTFE_FSTAT_CCIF_SHIFT (7U) #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) /*! @name FCNFG - Flash Configuration Register */ #define FTFE_FCNFG_EEERDY_MASK (0x1U) #define FTFE_FCNFG_EEERDY_SHIFT (0U) #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK) #define FTFE_FCNFG_RAMRDY_MASK (0x2U) #define FTFE_FCNFG_RAMRDY_SHIFT (1U) #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) #define FTFE_FCNFG_PFLSH_MASK (0x4U) #define FTFE_FCNFG_PFLSH_SHIFT (2U) #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK) #define FTFE_FCNFG_SWAP_MASK (0x8U) #define FTFE_FCNFG_SWAP_SHIFT (3U) #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) #define FTFE_FCNFG_ERSSUSP_MASK (0x10U) #define FTFE_FCNFG_ERSSUSP_SHIFT (4U) #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) #define FTFE_FCNFG_ERSAREQ_MASK (0x20U) #define FTFE_FCNFG_ERSAREQ_SHIFT (5U) #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) #define FTFE_FCNFG_CCIE_MASK (0x80U) #define FTFE_FCNFG_CCIE_SHIFT (7U) #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) /*! @name FSEC - Flash Security Register */ #define FTFE_FSEC_SEC_MASK (0x3U) #define FTFE_FSEC_SEC_SHIFT (0U) #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) #define FTFE_FSEC_FSLACC_MASK (0xCU) #define FTFE_FSEC_FSLACC_SHIFT (2U) #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) #define FTFE_FSEC_MEEN_MASK (0x30U) #define FTFE_FSEC_MEEN_SHIFT (4U) #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) #define FTFE_FSEC_KEYEN_MASK (0xC0U) #define FTFE_FSEC_KEYEN_SHIFT (6U) #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) /*! @name FOPT - Flash Option Register */ #define FTFE_FOPT_OPT_MASK (0xFFU) #define FTFE_FOPT_OPT_SHIFT (0U) #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK) /*! @name FCCOB3 - Flash Common Command Object Registers */ #define FTFE_FCCOB3_CCOBn_MASK (0xFFU) #define FTFE_FCCOB3_CCOBn_SHIFT (0U) #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) /*! @name FCCOB2 - Flash Common Command Object Registers */ #define FTFE_FCCOB2_CCOBn_MASK (0xFFU) #define FTFE_FCCOB2_CCOBn_SHIFT (0U) #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) /*! @name FCCOB1 - Flash Common Command Object Registers */ #define FTFE_FCCOB1_CCOBn_MASK (0xFFU) #define FTFE_FCCOB1_CCOBn_SHIFT (0U) #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) /*! @name FCCOB0 - Flash Common Command Object Registers */ #define FTFE_FCCOB0_CCOBn_MASK (0xFFU) #define FTFE_FCCOB0_CCOBn_SHIFT (0U) #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) /*! @name FCCOB7 - Flash Common Command Object Registers */ #define FTFE_FCCOB7_CCOBn_MASK (0xFFU) #define FTFE_FCCOB7_CCOBn_SHIFT (0U) #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) /*! @name FCCOB6 - Flash Common Command Object Registers */ #define FTFE_FCCOB6_CCOBn_MASK (0xFFU) #define FTFE_FCCOB6_CCOBn_SHIFT (0U) #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) /*! @name FCCOB5 - Flash Common Command Object Registers */ #define FTFE_FCCOB5_CCOBn_MASK (0xFFU) #define FTFE_FCCOB5_CCOBn_SHIFT (0U) #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) /*! @name FCCOB4 - Flash Common Command Object Registers */ #define FTFE_FCCOB4_CCOBn_MASK (0xFFU) #define FTFE_FCCOB4_CCOBn_SHIFT (0U) #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) /*! @name FCCOBB - Flash Common Command Object Registers */ #define FTFE_FCCOBB_CCOBn_MASK (0xFFU) #define FTFE_FCCOBB_CCOBn_SHIFT (0U) #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) /*! @name FCCOBA - Flash Common Command Object Registers */ #define FTFE_FCCOBA_CCOBn_MASK (0xFFU) #define FTFE_FCCOBA_CCOBn_SHIFT (0U) #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) /*! @name FCCOB9 - Flash Common Command Object Registers */ #define FTFE_FCCOB9_CCOBn_MASK (0xFFU) #define FTFE_FCCOB9_CCOBn_SHIFT (0U) #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) /*! @name FCCOB8 - Flash Common Command Object Registers */ #define FTFE_FCCOB8_CCOBn_MASK (0xFFU) #define FTFE_FCCOB8_CCOBn_SHIFT (0U) #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) /*! @name FPROT3 - Program Flash Protection Registers */ #define FTFE_FPROT3_PROT_MASK (0xFFU) #define FTFE_FPROT3_PROT_SHIFT (0U) #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK) /*! @name FPROT2 - Program Flash Protection Registers */ #define FTFE_FPROT2_PROT_MASK (0xFFU) #define FTFE_FPROT2_PROT_SHIFT (0U) #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK) /*! @name FPROT1 - Program Flash Protection Registers */ #define FTFE_FPROT1_PROT_MASK (0xFFU) #define FTFE_FPROT1_PROT_SHIFT (0U) #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK) /*! @name FPROT0 - Program Flash Protection Registers */ #define FTFE_FPROT0_PROT_MASK (0xFFU) #define FTFE_FPROT0_PROT_SHIFT (0U) #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK) /*! @name FEPROT - EEPROM Protection Register */ #define FTFE_FEPROT_EPROT_MASK (0xFFU) #define FTFE_FEPROT_EPROT_SHIFT (0U) #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK) /*! @name FDPROT - Data Flash Protection Register */ #define FTFE_FDPROT_DPROT_MASK (0xFFU) #define FTFE_FDPROT_DPROT_SHIFT (0U) #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK) /*! * @} */ /* end of group FTFE_Register_Masks */ /* FTFE - Peripheral instance base addresses */ /** Peripheral FTFE base address */ #define FTFE_BASE (0x40020000u) /** Peripheral FTFE base pointer */ #define FTFE ((FTFE_Type *)FTFE_BASE) /** Array initializer of FTFE peripheral base addresses */ #define FTFE_BASE_ADDRS { FTFE_BASE } /** Array initializer of FTFE peripheral base pointers */ #define FTFE_BASE_PTRS { FTFE } /** Interrupt vectors for the FTFE peripheral type */ #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn } #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn } /*! * @} */ /* end of group FTFE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer * @{ */ /** FTM - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ __IO uint32_t CNT; /**< Counter, offset: 0x4 */ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ struct { /* offset: 0xC, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ } CONTROLS[8]; __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ } FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /*! @name SC - Status And Control */ #define FTM_SC_PS_MASK (0x7U) #define FTM_SC_PS_SHIFT (0U) #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) #define FTM_SC_CLKS_MASK (0x18U) #define FTM_SC_CLKS_SHIFT (3U) #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) #define FTM_SC_CPWMS_MASK (0x20U) #define FTM_SC_CPWMS_SHIFT (5U) #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) #define FTM_SC_TOIE_MASK (0x40U) #define FTM_SC_TOIE_SHIFT (6U) #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) #define FTM_SC_TOF_MASK (0x80U) #define FTM_SC_TOF_SHIFT (7U) #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) /*! @name CNT - Counter */ #define FTM_CNT_COUNT_MASK (0xFFFFU) #define FTM_CNT_COUNT_SHIFT (0U) #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) /*! @name MOD - Modulo */ #define FTM_MOD_MOD_MASK (0xFFFFU) #define FTM_MOD_MOD_SHIFT (0U) #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) /*! @name CnSC - Channel (n) Status And Control */ #define FTM_CnSC_DMA_MASK (0x1U) #define FTM_CnSC_DMA_SHIFT (0U) #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) #define FTM_CnSC_ELSA_MASK (0x4U) #define FTM_CnSC_ELSA_SHIFT (2U) #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) #define FTM_CnSC_ELSB_MASK (0x8U) #define FTM_CnSC_ELSB_SHIFT (3U) #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) #define FTM_CnSC_MSA_MASK (0x10U) #define FTM_CnSC_MSA_SHIFT (4U) #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) #define FTM_CnSC_MSB_MASK (0x20U) #define FTM_CnSC_MSB_SHIFT (5U) #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) #define FTM_CnSC_CHIE_MASK (0x40U) #define FTM_CnSC_CHIE_SHIFT (6U) #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) #define FTM_CnSC_CHF_MASK (0x80U) #define FTM_CnSC_CHF_SHIFT (7U) #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) /* The count of FTM_CnSC */ #define FTM_CnSC_COUNT (8U) /*! @name CnV - Channel (n) Value */ #define FTM_CnV_VAL_MASK (0xFFFFU) #define FTM_CnV_VAL_SHIFT (0U) #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) /* The count of FTM_CnV */ #define FTM_CnV_COUNT (8U) /*! @name CNTIN - Counter Initial Value */ #define FTM_CNTIN_INIT_MASK (0xFFFFU) #define FTM_CNTIN_INIT_SHIFT (0U) #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) /*! @name STATUS - Capture And Compare Status */ #define FTM_STATUS_CH0F_MASK (0x1U) #define FTM_STATUS_CH0F_SHIFT (0U) #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) #define FTM_STATUS_CH1F_MASK (0x2U) #define FTM_STATUS_CH1F_SHIFT (1U) #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) #define FTM_STATUS_CH2F_MASK (0x4U) #define FTM_STATUS_CH2F_SHIFT (2U) #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) #define FTM_STATUS_CH3F_MASK (0x8U) #define FTM_STATUS_CH3F_SHIFT (3U) #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) #define FTM_STATUS_CH4F_MASK (0x10U) #define FTM_STATUS_CH4F_SHIFT (4U) #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) #define FTM_STATUS_CH5F_MASK (0x20U) #define FTM_STATUS_CH5F_SHIFT (5U) #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) #define FTM_STATUS_CH6F_MASK (0x40U) #define FTM_STATUS_CH6F_SHIFT (6U) #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) #define FTM_STATUS_CH7F_MASK (0x80U) #define FTM_STATUS_CH7F_SHIFT (7U) #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) /*! @name MODE - Features Mode Selection */ #define FTM_MODE_FTMEN_MASK (0x1U) #define FTM_MODE_FTMEN_SHIFT (0U) #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) #define FTM_MODE_INIT_MASK (0x2U) #define FTM_MODE_INIT_SHIFT (1U) #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) #define FTM_MODE_WPDIS_MASK (0x4U) #define FTM_MODE_WPDIS_SHIFT (2U) #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) #define FTM_MODE_PWMSYNC_MASK (0x8U) #define FTM_MODE_PWMSYNC_SHIFT (3U) #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) #define FTM_MODE_CAPTEST_MASK (0x10U) #define FTM_MODE_CAPTEST_SHIFT (4U) #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) #define FTM_MODE_FAULTM_MASK (0x60U) #define FTM_MODE_FAULTM_SHIFT (5U) #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) #define FTM_MODE_FAULTIE_MASK (0x80U) #define FTM_MODE_FAULTIE_SHIFT (7U) #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) /*! @name SYNC - Synchronization */ #define FTM_SYNC_CNTMIN_MASK (0x1U) #define FTM_SYNC_CNTMIN_SHIFT (0U) #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) #define FTM_SYNC_CNTMAX_MASK (0x2U) #define FTM_SYNC_CNTMAX_SHIFT (1U) #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) #define FTM_SYNC_REINIT_MASK (0x4U) #define FTM_SYNC_REINIT_SHIFT (2U) #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) #define FTM_SYNC_SYNCHOM_MASK (0x8U) #define FTM_SYNC_SYNCHOM_SHIFT (3U) #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) #define FTM_SYNC_TRIG0_MASK (0x10U) #define FTM_SYNC_TRIG0_SHIFT (4U) #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) #define FTM_SYNC_TRIG1_MASK (0x20U) #define FTM_SYNC_TRIG1_SHIFT (5U) #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) #define FTM_SYNC_TRIG2_MASK (0x40U) #define FTM_SYNC_TRIG2_SHIFT (6U) #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) #define FTM_SYNC_SWSYNC_MASK (0x80U) #define FTM_SYNC_SWSYNC_SHIFT (7U) #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) /*! @name OUTINIT - Initial State For Channels Output */ #define FTM_OUTINIT_CH0OI_MASK (0x1U) #define FTM_OUTINIT_CH0OI_SHIFT (0U) #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) #define FTM_OUTINIT_CH1OI_MASK (0x2U) #define FTM_OUTINIT_CH1OI_SHIFT (1U) #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) #define FTM_OUTINIT_CH2OI_MASK (0x4U) #define FTM_OUTINIT_CH2OI_SHIFT (2U) #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) #define FTM_OUTINIT_CH3OI_MASK (0x8U) #define FTM_OUTINIT_CH3OI_SHIFT (3U) #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) #define FTM_OUTINIT_CH4OI_MASK (0x10U) #define FTM_OUTINIT_CH4OI_SHIFT (4U) #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) #define FTM_OUTINIT_CH5OI_MASK (0x20U) #define FTM_OUTINIT_CH5OI_SHIFT (5U) #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) #define FTM_OUTINIT_CH6OI_MASK (0x40U) #define FTM_OUTINIT_CH6OI_SHIFT (6U) #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) #define FTM_OUTINIT_CH7OI_MASK (0x80U) #define FTM_OUTINIT_CH7OI_SHIFT (7U) #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) /*! @name OUTMASK - Output Mask */ #define FTM_OUTMASK_CH0OM_MASK (0x1U) #define FTM_OUTMASK_CH0OM_SHIFT (0U) #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) #define FTM_OUTMASK_CH1OM_MASK (0x2U) #define FTM_OUTMASK_CH1OM_SHIFT (1U) #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) #define FTM_OUTMASK_CH2OM_MASK (0x4U) #define FTM_OUTMASK_CH2OM_SHIFT (2U) #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) #define FTM_OUTMASK_CH3OM_MASK (0x8U) #define FTM_OUTMASK_CH3OM_SHIFT (3U) #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) #define FTM_OUTMASK_CH4OM_MASK (0x10U) #define FTM_OUTMASK_CH4OM_SHIFT (4U) #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) #define FTM_OUTMASK_CH5OM_MASK (0x20U) #define FTM_OUTMASK_CH5OM_SHIFT (5U) #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) #define FTM_OUTMASK_CH6OM_MASK (0x40U) #define FTM_OUTMASK_CH6OM_SHIFT (6U) #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) #define FTM_OUTMASK_CH7OM_MASK (0x80U) #define FTM_OUTMASK_CH7OM_SHIFT (7U) #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) /*! @name COMBINE - Function For Linked Channels */ #define FTM_COMBINE_COMBINE0_MASK (0x1U) #define FTM_COMBINE_COMBINE0_SHIFT (0U) #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) #define FTM_COMBINE_COMP0_MASK (0x2U) #define FTM_COMBINE_COMP0_SHIFT (1U) #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) #define FTM_COMBINE_DECAPEN0_MASK (0x4U) #define FTM_COMBINE_DECAPEN0_SHIFT (2U) #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) #define FTM_COMBINE_DECAP0_MASK (0x8U) #define FTM_COMBINE_DECAP0_SHIFT (3U) #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) #define FTM_COMBINE_DTEN0_MASK (0x10U) #define FTM_COMBINE_DTEN0_SHIFT (4U) #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) #define FTM_COMBINE_SYNCEN0_MASK (0x20U) #define FTM_COMBINE_SYNCEN0_SHIFT (5U) #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) #define FTM_COMBINE_FAULTEN0_MASK (0x40U) #define FTM_COMBINE_FAULTEN0_SHIFT (6U) #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) #define FTM_COMBINE_COMBINE1_MASK (0x100U) #define FTM_COMBINE_COMBINE1_SHIFT (8U) #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) #define FTM_COMBINE_COMP1_MASK (0x200U) #define FTM_COMBINE_COMP1_SHIFT (9U) #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) #define FTM_COMBINE_DECAPEN1_MASK (0x400U) #define FTM_COMBINE_DECAPEN1_SHIFT (10U) #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) #define FTM_COMBINE_DECAP1_MASK (0x800U) #define FTM_COMBINE_DECAP1_SHIFT (11U) #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) #define FTM_COMBINE_DTEN1_MASK (0x1000U) #define FTM_COMBINE_DTEN1_SHIFT (12U) #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) #define FTM_COMBINE_SYNCEN1_SHIFT (13U) #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) #define FTM_COMBINE_FAULTEN1_SHIFT (14U) #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) #define FTM_COMBINE_COMBINE2_MASK (0x10000U) #define FTM_COMBINE_COMBINE2_SHIFT (16U) #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) #define FTM_COMBINE_COMP2_MASK (0x20000U) #define FTM_COMBINE_COMP2_SHIFT (17U) #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) #define FTM_COMBINE_DECAPEN2_SHIFT (18U) #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) #define FTM_COMBINE_DECAP2_MASK (0x80000U) #define FTM_COMBINE_DECAP2_SHIFT (19U) #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) #define FTM_COMBINE_DTEN2_MASK (0x100000U) #define FTM_COMBINE_DTEN2_SHIFT (20U) #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) #define FTM_COMBINE_SYNCEN2_SHIFT (21U) #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) #define FTM_COMBINE_FAULTEN2_SHIFT (22U) #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) #define FTM_COMBINE_COMBINE3_SHIFT (24U) #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) #define FTM_COMBINE_COMP3_MASK (0x2000000U) #define FTM_COMBINE_COMP3_SHIFT (25U) #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) #define FTM_COMBINE_DECAPEN3_SHIFT (26U) #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) #define FTM_COMBINE_DECAP3_MASK (0x8000000U) #define FTM_COMBINE_DECAP3_SHIFT (27U) #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) #define FTM_COMBINE_DTEN3_MASK (0x10000000U) #define FTM_COMBINE_DTEN3_SHIFT (28U) #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) #define FTM_COMBINE_SYNCEN3_SHIFT (29U) #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) #define FTM_COMBINE_FAULTEN3_SHIFT (30U) #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) /*! @name DEADTIME - Deadtime Insertion Control */ #define FTM_DEADTIME_DTVAL_MASK (0x3FU) #define FTM_DEADTIME_DTVAL_SHIFT (0U) #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) #define FTM_DEADTIME_DTPS_MASK (0xC0U) #define FTM_DEADTIME_DTPS_SHIFT (6U) #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) /*! @name EXTTRIG - FTM External Trigger */ #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) #define FTM_EXTTRIG_TRIGF_MASK (0x80U) #define FTM_EXTTRIG_TRIGF_SHIFT (7U) #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) /*! @name POL - Channels Polarity */ #define FTM_POL_POL0_MASK (0x1U) #define FTM_POL_POL0_SHIFT (0U) #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) #define FTM_POL_POL1_MASK (0x2U) #define FTM_POL_POL1_SHIFT (1U) #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) #define FTM_POL_POL2_MASK (0x4U) #define FTM_POL_POL2_SHIFT (2U) #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) #define FTM_POL_POL3_MASK (0x8U) #define FTM_POL_POL3_SHIFT (3U) #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) #define FTM_POL_POL4_MASK (0x10U) #define FTM_POL_POL4_SHIFT (4U) #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) #define FTM_POL_POL5_MASK (0x20U) #define FTM_POL_POL5_SHIFT (5U) #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) #define FTM_POL_POL6_MASK (0x40U) #define FTM_POL_POL6_SHIFT (6U) #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) #define FTM_POL_POL7_MASK (0x80U) #define FTM_POL_POL7_SHIFT (7U) #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) /*! @name FMS - Fault Mode Status */ #define FTM_FMS_FAULTF0_MASK (0x1U) #define FTM_FMS_FAULTF0_SHIFT (0U) #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) #define FTM_FMS_FAULTF1_MASK (0x2U) #define FTM_FMS_FAULTF1_SHIFT (1U) #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) #define FTM_FMS_FAULTF2_MASK (0x4U) #define FTM_FMS_FAULTF2_SHIFT (2U) #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) #define FTM_FMS_FAULTF3_MASK (0x8U) #define FTM_FMS_FAULTF3_SHIFT (3U) #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) #define FTM_FMS_FAULTIN_MASK (0x20U) #define FTM_FMS_FAULTIN_SHIFT (5U) #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) #define FTM_FMS_WPEN_MASK (0x40U) #define FTM_FMS_WPEN_SHIFT (6U) #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) #define FTM_FMS_FAULTF_MASK (0x80U) #define FTM_FMS_FAULTF_SHIFT (7U) #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) /*! @name FILTER - Input Capture Filter Control */ #define FTM_FILTER_CH0FVAL_MASK (0xFU) #define FTM_FILTER_CH0FVAL_SHIFT (0U) #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) #define FTM_FILTER_CH1FVAL_MASK (0xF0U) #define FTM_FILTER_CH1FVAL_SHIFT (4U) #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) #define FTM_FILTER_CH2FVAL_MASK (0xF00U) #define FTM_FILTER_CH2FVAL_SHIFT (8U) #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) #define FTM_FILTER_CH3FVAL_MASK (0xF000U) #define FTM_FILTER_CH3FVAL_SHIFT (12U) #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) /*! @name FLTCTRL - Fault Control */ #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) #define FTM_FLTCTRL_FFVAL_SHIFT (8U) #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) /*! @name QDCTRL - Quadrature Decoder Control And Status */ #define FTM_QDCTRL_QUADEN_MASK (0x1U) #define FTM_QDCTRL_QUADEN_SHIFT (0U) #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) #define FTM_QDCTRL_TOFDIR_MASK (0x2U) #define FTM_QDCTRL_TOFDIR_SHIFT (1U) #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) #define FTM_QDCTRL_QUADIR_MASK (0x4U) #define FTM_QDCTRL_QUADIR_SHIFT (2U) #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) #define FTM_QDCTRL_QUADMODE_MASK (0x8U) #define FTM_QDCTRL_QUADMODE_SHIFT (3U) #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) #define FTM_QDCTRL_PHBPOL_MASK (0x10U) #define FTM_QDCTRL_PHBPOL_SHIFT (4U) #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) #define FTM_QDCTRL_PHAPOL_MASK (0x20U) #define FTM_QDCTRL_PHAPOL_SHIFT (5U) #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) /*! @name CONF - Configuration */ #define FTM_CONF_NUMTOF_MASK (0x1FU) #define FTM_CONF_NUMTOF_SHIFT (0U) #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) #define FTM_CONF_BDMMODE_MASK (0xC0U) #define FTM_CONF_BDMMODE_SHIFT (6U) #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) #define FTM_CONF_GTBEEN_MASK (0x200U) #define FTM_CONF_GTBEEN_SHIFT (9U) #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) #define FTM_CONF_GTBEOUT_MASK (0x400U) #define FTM_CONF_GTBEOUT_SHIFT (10U) #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) /*! @name FLTPOL - FTM Fault Input Polarity */ #define FTM_FLTPOL_FLT0POL_MASK (0x1U) #define FTM_FLTPOL_FLT0POL_SHIFT (0U) #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) #define FTM_FLTPOL_FLT1POL_MASK (0x2U) #define FTM_FLTPOL_FLT1POL_SHIFT (1U) #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) #define FTM_FLTPOL_FLT2POL_MASK (0x4U) #define FTM_FLTPOL_FLT2POL_SHIFT (2U) #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) #define FTM_FLTPOL_FLT3POL_MASK (0x8U) #define FTM_FLTPOL_FLT3POL_SHIFT (3U) #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) /*! @name SYNCONF - Synchronization Configuration */ #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) #define FTM_SYNCONF_CNTINC_MASK (0x4U) #define FTM_SYNCONF_CNTINC_SHIFT (2U) #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) #define FTM_SYNCONF_INVC_MASK (0x10U) #define FTM_SYNCONF_INVC_SHIFT (4U) #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) #define FTM_SYNCONF_SWOC_MASK (0x20U) #define FTM_SYNCONF_SWOC_SHIFT (5U) #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) #define FTM_SYNCONF_SWOM_MASK (0x400U) #define FTM_SYNCONF_SWOM_SHIFT (10U) #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) #define FTM_SYNCONF_SWINVC_MASK (0x800U) #define FTM_SYNCONF_SWINVC_SHIFT (11U) #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) #define FTM_SYNCONF_SWSOC_MASK (0x1000U) #define FTM_SYNCONF_SWSOC_SHIFT (12U) #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) #define FTM_SYNCONF_HWOM_MASK (0x40000U) #define FTM_SYNCONF_HWOM_SHIFT (18U) #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) #define FTM_SYNCONF_HWINVC_MASK (0x80000U) #define FTM_SYNCONF_HWINVC_SHIFT (19U) #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) #define FTM_SYNCONF_HWSOC_MASK (0x100000U) #define FTM_SYNCONF_HWSOC_SHIFT (20U) #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) /*! @name INVCTRL - FTM Inverting Control */ #define FTM_INVCTRL_INV0EN_MASK (0x1U) #define FTM_INVCTRL_INV0EN_SHIFT (0U) #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) #define FTM_INVCTRL_INV1EN_MASK (0x2U) #define FTM_INVCTRL_INV1EN_SHIFT (1U) #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) #define FTM_INVCTRL_INV2EN_MASK (0x4U) #define FTM_INVCTRL_INV2EN_SHIFT (2U) #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) #define FTM_INVCTRL_INV3EN_MASK (0x8U) #define FTM_INVCTRL_INV3EN_SHIFT (3U) #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) /*! @name SWOCTRL - FTM Software Output Control */ #define FTM_SWOCTRL_CH0OC_MASK (0x1U) #define FTM_SWOCTRL_CH0OC_SHIFT (0U) #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) #define FTM_SWOCTRL_CH1OC_MASK (0x2U) #define FTM_SWOCTRL_CH1OC_SHIFT (1U) #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) #define FTM_SWOCTRL_CH2OC_MASK (0x4U) #define FTM_SWOCTRL_CH2OC_SHIFT (2U) #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) #define FTM_SWOCTRL_CH3OC_MASK (0x8U) #define FTM_SWOCTRL_CH3OC_SHIFT (3U) #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) #define FTM_SWOCTRL_CH4OC_MASK (0x10U) #define FTM_SWOCTRL_CH4OC_SHIFT (4U) #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) #define FTM_SWOCTRL_CH5OC_MASK (0x20U) #define FTM_SWOCTRL_CH5OC_SHIFT (5U) #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) #define FTM_SWOCTRL_CH6OC_MASK (0x40U) #define FTM_SWOCTRL_CH6OC_SHIFT (6U) #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) #define FTM_SWOCTRL_CH7OC_MASK (0x80U) #define FTM_SWOCTRL_CH7OC_SHIFT (7U) #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) /*! @name PWMLOAD - FTM PWM Load */ #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) #define FTM_PWMLOAD_LDOK_MASK (0x200U) #define FTM_PWMLOAD_LDOK_SHIFT (9U) #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) /*! * @} */ /* end of group FTM_Register_Masks */ /* FTM - Peripheral instance base addresses */ /** Peripheral FTM0 base address */ #define FTM0_BASE (0x40038000u) /** Peripheral FTM0 base pointer */ #define FTM0 ((FTM_Type *)FTM0_BASE) /** Peripheral FTM1 base address */ #define FTM1_BASE (0x40039000u) /** Peripheral FTM1 base pointer */ #define FTM1 ((FTM_Type *)FTM1_BASE) /** Peripheral FTM2 base address */ #define FTM2_BASE (0x4003A000u) /** Peripheral FTM2 base pointer */ #define FTM2 ((FTM_Type *)FTM2_BASE) /** Peripheral FTM3 base address */ #define FTM3_BASE (0x400B9000u) /** Peripheral FTM3 base pointer */ #define FTM3 ((FTM_Type *)FTM3_BASE) /** Array initializer of FTM peripheral base addresses */ #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } /** Array initializer of FTM peripheral base pointers */ #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } /** Interrupt vectors for the FTM peripheral type */ #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } /*! * @} */ /* end of group FTM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define GPIO_PDOR_PDO_SHIFT (0U) #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) /*! @name PSOR - Port Set Output Register */ #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define GPIO_PSOR_PTSO_SHIFT (0U) #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) /*! @name PCOR - Port Clear Output Register */ #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define GPIO_PCOR_PTCO_SHIFT (0U) #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) /*! @name PTOR - Port Toggle Output Register */ #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define GPIO_PTOR_PTTO_SHIFT (0U) #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) /*! @name PDIR - Port Data Input Register */ #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define GPIO_PDIR_PDI_SHIFT (0U) #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) /*! @name PDDR - Port Data Direction Register */ #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define GPIO_PDDR_PDD_SHIFT (0U) #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIOA base address */ #define GPIOA_BASE (0x400FF000u) /** Peripheral GPIOA base pointer */ #define GPIOA ((GPIO_Type *)GPIOA_BASE) /** Peripheral GPIOB base address */ #define GPIOB_BASE (0x400FF040u) /** Peripheral GPIOB base pointer */ #define GPIOB ((GPIO_Type *)GPIOB_BASE) /** Peripheral GPIOC base address */ #define GPIOC_BASE (0x400FF080u) /** Peripheral GPIOC base pointer */ #define GPIOC ((GPIO_Type *)GPIOC_BASE) /** Peripheral GPIOD base address */ #define GPIOD_BASE (0x400FF0C0u) /** Peripheral GPIOD base pointer */ #define GPIOD ((GPIO_Type *)GPIOD_BASE) /** Peripheral GPIOE base address */ #define GPIOE_BASE (0x400FF100u) /** Peripheral GPIOE base pointer */ #define GPIOE ((GPIO_Type *)GPIOE_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer * @{ */ /** I2C - Register Layout Typedef */ typedef struct { __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ } I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /*! @name A1 - I2C Address Register 1 */ #define I2C_A1_AD_MASK (0xFEU) #define I2C_A1_AD_SHIFT (1U) #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) /*! @name F - I2C Frequency Divider register */ #define I2C_F_ICR_MASK (0x3FU) #define I2C_F_ICR_SHIFT (0U) #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) #define I2C_F_MULT_MASK (0xC0U) #define I2C_F_MULT_SHIFT (6U) #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) /*! @name C1 - I2C Control Register 1 */ #define I2C_C1_DMAEN_MASK (0x1U) #define I2C_C1_DMAEN_SHIFT (0U) #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) #define I2C_C1_WUEN_MASK (0x2U) #define I2C_C1_WUEN_SHIFT (1U) #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) #define I2C_C1_RSTA_MASK (0x4U) #define I2C_C1_RSTA_SHIFT (2U) #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) #define I2C_C1_TXAK_MASK (0x8U) #define I2C_C1_TXAK_SHIFT (3U) #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) #define I2C_C1_TX_MASK (0x10U) #define I2C_C1_TX_SHIFT (4U) #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) #define I2C_C1_MST_MASK (0x20U) #define I2C_C1_MST_SHIFT (5U) #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) #define I2C_C1_IICIE_MASK (0x40U) #define I2C_C1_IICIE_SHIFT (6U) #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) #define I2C_C1_IICEN_MASK (0x80U) #define I2C_C1_IICEN_SHIFT (7U) #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) /*! @name S - I2C Status register */ #define I2C_S_RXAK_MASK (0x1U) #define I2C_S_RXAK_SHIFT (0U) #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) #define I2C_S_IICIF_MASK (0x2U) #define I2C_S_IICIF_SHIFT (1U) #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) #define I2C_S_SRW_MASK (0x4U) #define I2C_S_SRW_SHIFT (2U) #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) #define I2C_S_RAM_MASK (0x8U) #define I2C_S_RAM_SHIFT (3U) #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) #define I2C_S_ARBL_MASK (0x10U) #define I2C_S_ARBL_SHIFT (4U) #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) #define I2C_S_BUSY_MASK (0x20U) #define I2C_S_BUSY_SHIFT (5U) #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) #define I2C_S_IAAS_MASK (0x40U) #define I2C_S_IAAS_SHIFT (6U) #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) #define I2C_S_TCF_MASK (0x80U) #define I2C_S_TCF_SHIFT (7U) #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) /*! @name D - I2C Data I/O register */ #define I2C_D_DATA_MASK (0xFFU) #define I2C_D_DATA_SHIFT (0U) #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) /*! @name C2 - I2C Control Register 2 */ #define I2C_C2_AD_MASK (0x7U) #define I2C_C2_AD_SHIFT (0U) #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) #define I2C_C2_RMEN_MASK (0x8U) #define I2C_C2_RMEN_SHIFT (3U) #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) #define I2C_C2_SBRC_MASK (0x10U) #define I2C_C2_SBRC_SHIFT (4U) #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) #define I2C_C2_HDRS_MASK (0x20U) #define I2C_C2_HDRS_SHIFT (5U) #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) #define I2C_C2_ADEXT_MASK (0x40U) #define I2C_C2_ADEXT_SHIFT (6U) #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) #define I2C_C2_GCAEN_MASK (0x80U) #define I2C_C2_GCAEN_SHIFT (7U) #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) /*! @name FLT - I2C Programmable Input Glitch Filter register */ #define I2C_FLT_FLT_MASK (0xFU) #define I2C_FLT_FLT_SHIFT (0U) #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) #define I2C_FLT_STARTF_MASK (0x10U) #define I2C_FLT_STARTF_SHIFT (4U) #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) #define I2C_FLT_SSIE_MASK (0x20U) #define I2C_FLT_SSIE_SHIFT (5U) #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) #define I2C_FLT_STOPF_MASK (0x40U) #define I2C_FLT_STOPF_SHIFT (6U) #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) #define I2C_FLT_SHEN_MASK (0x80U) #define I2C_FLT_SHEN_SHIFT (7U) #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) /*! @name RA - I2C Range Address register */ #define I2C_RA_RAD_MASK (0xFEU) #define I2C_RA_RAD_SHIFT (1U) #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) /*! @name SMB - I2C SMBus Control and Status register */ #define I2C_SMB_SHTF2IE_MASK (0x1U) #define I2C_SMB_SHTF2IE_SHIFT (0U) #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) #define I2C_SMB_SHTF2_MASK (0x2U) #define I2C_SMB_SHTF2_SHIFT (1U) #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) #define I2C_SMB_SHTF1_MASK (0x4U) #define I2C_SMB_SHTF1_SHIFT (2U) #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) #define I2C_SMB_SLTF_MASK (0x8U) #define I2C_SMB_SLTF_SHIFT (3U) #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) #define I2C_SMB_TCKSEL_MASK (0x10U) #define I2C_SMB_TCKSEL_SHIFT (4U) #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) #define I2C_SMB_SIICAEN_MASK (0x20U) #define I2C_SMB_SIICAEN_SHIFT (5U) #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) #define I2C_SMB_ALERTEN_MASK (0x40U) #define I2C_SMB_ALERTEN_SHIFT (6U) #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) #define I2C_SMB_FACK_MASK (0x80U) #define I2C_SMB_FACK_SHIFT (7U) #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) /*! @name A2 - I2C Address Register 2 */ #define I2C_A2_SAD_MASK (0xFEU) #define I2C_A2_SAD_SHIFT (1U) #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) /*! @name SLTH - I2C SCL Low Timeout Register High */ #define I2C_SLTH_SSLT_MASK (0xFFU) #define I2C_SLTH_SSLT_SHIFT (0U) #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) /*! @name SLTL - I2C SCL Low Timeout Register Low */ #define I2C_SLTL_SSLT_MASK (0xFFU) #define I2C_SLTL_SSLT_SHIFT (0U) #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) /*! * @} */ /* end of group I2C_Register_Masks */ /* I2C - Peripheral instance base addresses */ /** Peripheral I2C0 base address */ #define I2C0_BASE (0x40066000u) /** Peripheral I2C0 base pointer */ #define I2C0 ((I2C_Type *)I2C0_BASE) /** Peripheral I2C1 base address */ #define I2C1_BASE (0x40067000u) /** Peripheral I2C1 base pointer */ #define I2C1 ((I2C_Type *)I2C1_BASE) /** Peripheral I2C2 base address */ #define I2C2_BASE (0x400E6000u) /** Peripheral I2C2 base pointer */ #define I2C2 ((I2C_Type *)I2C2_BASE) /** Array initializer of I2C peripheral base addresses */ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 } /** Interrupt vectors for the I2C peripheral type */ #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn } /*! * @} */ /* end of group I2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ uint8_t RESERVED_0[8]; __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[24]; __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_2[24]; __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_3[28]; __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ uint8_t RESERVED_4[8]; __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_5[24]; __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_6[24]; __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ uint8_t RESERVED_7[28]; __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name TCSR - SAI Transmit Control Register */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @name TCR1 - SAI Transmit Configuration 1 Register */ #define I2S_TCR1_TFW_MASK (0x7U) #define I2S_TCR1_TFW_SHIFT (0U) #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @name TCR2 - SAI Transmit Configuration 2 Register */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @name TCR3 - SAI Transmit Configuration 3 Register */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0x30000U) #define I2S_TCR3_TCE_SHIFT (16U) #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /*! @name TCR4 - SAI Transmit Configuration 4 Register */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) /*! @name TCR5 - SAI Transmit Configuration 5 Register */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @name TDR - SAI Transmit Data Register */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /* The count of I2S_TDR */ #define I2S_TDR_COUNT (2U) /*! @name TFR - SAI Transmit FIFO Register */ #define I2S_TFR_RFP_MASK (0xFU) #define I2S_TFR_RFP_SHIFT (0U) #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0xF0000U) #define I2S_TFR_WFP_SHIFT (16U) #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) /* The count of I2S_TFR */ #define I2S_TFR_COUNT (2U) /*! @name TMR - SAI Transmit Mask Register */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @name RCSR - SAI Receive Control Register */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @name RCR1 - SAI Receive Configuration 1 Register */ #define I2S_RCR1_RFW_MASK (0x7U) #define I2S_RCR1_RFW_SHIFT (0U) #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @name RCR2 - SAI Receive Configuration 2 Register */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @name RCR3 - SAI Receive Configuration 3 Register */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0x30000U) #define I2S_RCR3_RCE_SHIFT (16U) #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /*! @name RCR4 - SAI Receive Configuration 4 Register */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) /*! @name RCR5 - SAI Receive Configuration 5 Register */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @name RDR - SAI Receive Data Register */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /* The count of I2S_RDR */ #define I2S_RDR_COUNT (2U) /*! @name RFR - SAI Receive FIFO Register */ #define I2S_RFR_RFP_MASK (0xFU) #define I2S_RFR_RFP_SHIFT (0U) #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_WFP_MASK (0xF0000U) #define I2S_RFR_WFP_SHIFT (16U) #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /* The count of I2S_RFR */ #define I2S_RFR_COUNT (2U) /*! @name RMR - SAI Receive Mask Register */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @name MCR - SAI MCLK Control Register */ #define I2S_MCR_MICS_MASK (0x3000000U) #define I2S_MCR_MICS_SHIFT (24U) #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) #define I2S_MCR_DUF_MASK (0x80000000U) #define I2S_MCR_DUF_SHIFT (31U) #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) /*! @name MDR - SAI MCLK Divide Register */ #define I2S_MDR_DIVIDE_MASK (0xFFFU) #define I2S_MDR_DIVIDE_SHIFT (0U) #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) #define I2S_MDR_FRACT_MASK (0xFF000U) #define I2S_MDR_FRACT_SHIFT (12U) #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral I2S0 base address */ #define I2S0_BASE (0x4002F000u) /** Peripheral I2S0 base pointer */ #define I2S0 ((I2S_Type *)I2S0_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { I2S0_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { I2S0 } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { I2S0_Rx_IRQn } #define I2S_TX_IRQS { I2S0_Tx_IRQn } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LLWU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer * @{ */ /** LLWU - Register Layout Typedef */ typedef struct { __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */ } LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Masks LLWU Register Masks * @{ */ /*! @name PE1 - LLWU Pin Enable 1 register */ #define LLWU_PE1_WUPE0_MASK (0x3U) #define LLWU_PE1_WUPE0_SHIFT (0U) #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) #define LLWU_PE1_WUPE1_MASK (0xCU) #define LLWU_PE1_WUPE1_SHIFT (2U) #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) #define LLWU_PE1_WUPE2_MASK (0x30U) #define LLWU_PE1_WUPE2_SHIFT (4U) #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) #define LLWU_PE1_WUPE3_MASK (0xC0U) #define LLWU_PE1_WUPE3_SHIFT (6U) #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) /*! @name PE2 - LLWU Pin Enable 2 register */ #define LLWU_PE2_WUPE4_MASK (0x3U) #define LLWU_PE2_WUPE4_SHIFT (0U) #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) #define LLWU_PE2_WUPE5_MASK (0xCU) #define LLWU_PE2_WUPE5_SHIFT (2U) #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) #define LLWU_PE2_WUPE6_MASK (0x30U) #define LLWU_PE2_WUPE6_SHIFT (4U) #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) #define LLWU_PE2_WUPE7_MASK (0xC0U) #define LLWU_PE2_WUPE7_SHIFT (6U) #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) /*! @name PE3 - LLWU Pin Enable 3 register */ #define LLWU_PE3_WUPE8_MASK (0x3U) #define LLWU_PE3_WUPE8_SHIFT (0U) #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) #define LLWU_PE3_WUPE9_MASK (0xCU) #define LLWU_PE3_WUPE9_SHIFT (2U) #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) #define LLWU_PE3_WUPE10_MASK (0x30U) #define LLWU_PE3_WUPE10_SHIFT (4U) #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) #define LLWU_PE3_WUPE11_MASK (0xC0U) #define LLWU_PE3_WUPE11_SHIFT (6U) #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) /*! @name PE4 - LLWU Pin Enable 4 register */ #define LLWU_PE4_WUPE12_MASK (0x3U) #define LLWU_PE4_WUPE12_SHIFT (0U) #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) #define LLWU_PE4_WUPE13_MASK (0xCU) #define LLWU_PE4_WUPE13_SHIFT (2U) #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) #define LLWU_PE4_WUPE14_MASK (0x30U) #define LLWU_PE4_WUPE14_SHIFT (4U) #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) #define LLWU_PE4_WUPE15_MASK (0xC0U) #define LLWU_PE4_WUPE15_SHIFT (6U) #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) /*! @name ME - LLWU Module Enable register */ #define LLWU_ME_WUME0_MASK (0x1U) #define LLWU_ME_WUME0_SHIFT (0U) #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) #define LLWU_ME_WUME1_MASK (0x2U) #define LLWU_ME_WUME1_SHIFT (1U) #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) #define LLWU_ME_WUME2_MASK (0x4U) #define LLWU_ME_WUME2_SHIFT (2U) #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) #define LLWU_ME_WUME3_MASK (0x8U) #define LLWU_ME_WUME3_SHIFT (3U) #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) #define LLWU_ME_WUME4_MASK (0x10U) #define LLWU_ME_WUME4_SHIFT (4U) #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) #define LLWU_ME_WUME5_MASK (0x20U) #define LLWU_ME_WUME5_SHIFT (5U) #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) #define LLWU_ME_WUME6_MASK (0x40U) #define LLWU_ME_WUME6_SHIFT (6U) #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) #define LLWU_ME_WUME7_MASK (0x80U) #define LLWU_ME_WUME7_SHIFT (7U) #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) /*! @name F1 - LLWU Flag 1 register */ #define LLWU_F1_WUF0_MASK (0x1U) #define LLWU_F1_WUF0_SHIFT (0U) #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) #define LLWU_F1_WUF1_MASK (0x2U) #define LLWU_F1_WUF1_SHIFT (1U) #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) #define LLWU_F1_WUF2_MASK (0x4U) #define LLWU_F1_WUF2_SHIFT (2U) #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) #define LLWU_F1_WUF3_MASK (0x8U) #define LLWU_F1_WUF3_SHIFT (3U) #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) #define LLWU_F1_WUF4_MASK (0x10U) #define LLWU_F1_WUF4_SHIFT (4U) #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) #define LLWU_F1_WUF5_MASK (0x20U) #define LLWU_F1_WUF5_SHIFT (5U) #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) #define LLWU_F1_WUF6_MASK (0x40U) #define LLWU_F1_WUF6_SHIFT (6U) #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) #define LLWU_F1_WUF7_MASK (0x80U) #define LLWU_F1_WUF7_SHIFT (7U) #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) /*! @name F2 - LLWU Flag 2 register */ #define LLWU_F2_WUF8_MASK (0x1U) #define LLWU_F2_WUF8_SHIFT (0U) #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) #define LLWU_F2_WUF9_MASK (0x2U) #define LLWU_F2_WUF9_SHIFT (1U) #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) #define LLWU_F2_WUF10_MASK (0x4U) #define LLWU_F2_WUF10_SHIFT (2U) #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) #define LLWU_F2_WUF11_MASK (0x8U) #define LLWU_F2_WUF11_SHIFT (3U) #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) #define LLWU_F2_WUF12_MASK (0x10U) #define LLWU_F2_WUF12_SHIFT (4U) #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) #define LLWU_F2_WUF13_MASK (0x20U) #define LLWU_F2_WUF13_SHIFT (5U) #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) #define LLWU_F2_WUF14_MASK (0x40U) #define LLWU_F2_WUF14_SHIFT (6U) #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) #define LLWU_F2_WUF15_MASK (0x80U) #define LLWU_F2_WUF15_SHIFT (7U) #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) /*! @name F3 - LLWU Flag 3 register */ #define LLWU_F3_MWUF0_MASK (0x1U) #define LLWU_F3_MWUF0_SHIFT (0U) #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) #define LLWU_F3_MWUF1_MASK (0x2U) #define LLWU_F3_MWUF1_SHIFT (1U) #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) #define LLWU_F3_MWUF2_MASK (0x4U) #define LLWU_F3_MWUF2_SHIFT (2U) #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) #define LLWU_F3_MWUF3_MASK (0x8U) #define LLWU_F3_MWUF3_SHIFT (3U) #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) #define LLWU_F3_MWUF4_MASK (0x10U) #define LLWU_F3_MWUF4_SHIFT (4U) #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) #define LLWU_F3_MWUF5_MASK (0x20U) #define LLWU_F3_MWUF5_SHIFT (5U) #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) #define LLWU_F3_MWUF6_MASK (0x40U) #define LLWU_F3_MWUF6_SHIFT (6U) #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) #define LLWU_F3_MWUF7_MASK (0x80U) #define LLWU_F3_MWUF7_SHIFT (7U) #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) /*! @name FILT1 - LLWU Pin Filter 1 register */ #define LLWU_FILT1_FILTSEL_MASK (0xFU) #define LLWU_FILT1_FILTSEL_SHIFT (0U) #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) #define LLWU_FILT1_FILTE_MASK (0x60U) #define LLWU_FILT1_FILTE_SHIFT (5U) #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) #define LLWU_FILT1_FILTF_MASK (0x80U) #define LLWU_FILT1_FILTF_SHIFT (7U) #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) /*! @name FILT2 - LLWU Pin Filter 2 register */ #define LLWU_FILT2_FILTSEL_MASK (0xFU) #define LLWU_FILT2_FILTSEL_SHIFT (0U) #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) #define LLWU_FILT2_FILTE_MASK (0x60U) #define LLWU_FILT2_FILTE_SHIFT (5U) #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) #define LLWU_FILT2_FILTF_MASK (0x80U) #define LLWU_FILT2_FILTF_SHIFT (7U) #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) /*! @name RST - LLWU Reset Enable register */ #define LLWU_RST_RSTFILT_MASK (0x1U) #define LLWU_RST_RSTFILT_SHIFT (0U) #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) #define LLWU_RST_LLRSTE_MASK (0x2U) #define LLWU_RST_LLRSTE_SHIFT (1U) #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) /*! * @} */ /* end of group LLWU_Register_Masks */ /* LLWU - Peripheral instance base addresses */ /** Peripheral LLWU base address */ #define LLWU_BASE (0x4007C000u) /** Peripheral LLWU base pointer */ #define LLWU ((LLWU_Type *)LLWU_BASE) /** Array initializer of LLWU peripheral base addresses */ #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } /** Interrupt vectors for the LLWU peripheral type */ #define LLWU_IRQS { LLWU_IRQn } /*! * @} */ /* end of group LLWU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ } LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /*! @name CSR - Low Power Timer Control Status Register */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) /*! @name PSR - Low Power Timer Prescale Register */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @name CMR - Low Power Timer Compare Register */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) /*! @name CNR - Low Power Timer Counter Register */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x40040000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } /** Interrupt vectors for the LPTMR peripheral type */ #define LPTMR_IRQS { LPTMR0_IRQn } /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer * @{ */ /** MCG - Register Layout Typedef */ typedef struct { __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ uint8_t RESERVED_0[1]; __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ uint8_t RESERVED_1[1]; __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ } MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Register_Masks MCG Register Masks * @{ */ /*! @name C1 - MCG Control 1 Register */ #define MCG_C1_IREFSTEN_MASK (0x1U) #define MCG_C1_IREFSTEN_SHIFT (0U) #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) #define MCG_C1_IRCLKEN_MASK (0x2U) #define MCG_C1_IRCLKEN_SHIFT (1U) #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) #define MCG_C1_IREFS_MASK (0x4U) #define MCG_C1_IREFS_SHIFT (2U) #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) #define MCG_C1_FRDIV_MASK (0x38U) #define MCG_C1_FRDIV_SHIFT (3U) #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) #define MCG_C1_CLKS_MASK (0xC0U) #define MCG_C1_CLKS_SHIFT (6U) #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) /*! @name C2 - MCG Control 2 Register */ #define MCG_C2_IRCS_MASK (0x1U) #define MCG_C2_IRCS_SHIFT (0U) #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) #define MCG_C2_LP_MASK (0x2U) #define MCG_C2_LP_SHIFT (1U) #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) #define MCG_C2_EREFS_MASK (0x4U) #define MCG_C2_EREFS_SHIFT (2U) #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) #define MCG_C2_HGO_MASK (0x8U) #define MCG_C2_HGO_SHIFT (3U) #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) #define MCG_C2_RANGE_MASK (0x30U) #define MCG_C2_RANGE_SHIFT (4U) #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) #define MCG_C2_FCFTRIM_MASK (0x40U) #define MCG_C2_FCFTRIM_SHIFT (6U) #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) #define MCG_C2_LOCRE0_MASK (0x80U) #define MCG_C2_LOCRE0_SHIFT (7U) #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) /*! @name C3 - MCG Control 3 Register */ #define MCG_C3_SCTRIM_MASK (0xFFU) #define MCG_C3_SCTRIM_SHIFT (0U) #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) /*! @name C4 - MCG Control 4 Register */ #define MCG_C4_SCFTRIM_MASK (0x1U) #define MCG_C4_SCFTRIM_SHIFT (0U) #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) #define MCG_C4_FCTRIM_MASK (0x1EU) #define MCG_C4_FCTRIM_SHIFT (1U) #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) #define MCG_C4_DRST_DRS_MASK (0x60U) #define MCG_C4_DRST_DRS_SHIFT (5U) #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) #define MCG_C4_DMX32_MASK (0x80U) #define MCG_C4_DMX32_SHIFT (7U) #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) /*! @name C5 - MCG Control 5 Register */ #define MCG_C5_PRDIV0_MASK (0x1FU) #define MCG_C5_PRDIV0_SHIFT (0U) #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) #define MCG_C5_PLLSTEN0_MASK (0x20U) #define MCG_C5_PLLSTEN0_SHIFT (5U) #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) #define MCG_C5_PLLCLKEN0_MASK (0x40U) #define MCG_C5_PLLCLKEN0_SHIFT (6U) #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) /*! @name C6 - MCG Control 6 Register */ #define MCG_C6_VDIV0_MASK (0x1FU) #define MCG_C6_VDIV0_SHIFT (0U) #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) #define MCG_C6_CME0_MASK (0x20U) #define MCG_C6_CME0_SHIFT (5U) #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) #define MCG_C6_PLLS_MASK (0x40U) #define MCG_C6_PLLS_SHIFT (6U) #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) #define MCG_C6_LOLIE0_MASK (0x80U) #define MCG_C6_LOLIE0_SHIFT (7U) #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) /*! @name S - MCG Status Register */ #define MCG_S_IRCST_MASK (0x1U) #define MCG_S_IRCST_SHIFT (0U) #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) #define MCG_S_OSCINIT0_MASK (0x2U) #define MCG_S_OSCINIT0_SHIFT (1U) #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) #define MCG_S_CLKST_MASK (0xCU) #define MCG_S_CLKST_SHIFT (2U) #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) #define MCG_S_IREFST_MASK (0x10U) #define MCG_S_IREFST_SHIFT (4U) #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) #define MCG_S_PLLST_MASK (0x20U) #define MCG_S_PLLST_SHIFT (5U) #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) #define MCG_S_LOCK0_MASK (0x40U) #define MCG_S_LOCK0_SHIFT (6U) #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) #define MCG_S_LOLS0_MASK (0x80U) #define MCG_S_LOLS0_SHIFT (7U) #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) /*! @name SC - MCG Status and Control Register */ #define MCG_SC_LOCS0_MASK (0x1U) #define MCG_SC_LOCS0_SHIFT (0U) #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) #define MCG_SC_FCRDIV_MASK (0xEU) #define MCG_SC_FCRDIV_SHIFT (1U) #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) #define MCG_SC_FLTPRSRV_MASK (0x10U) #define MCG_SC_FLTPRSRV_SHIFT (4U) #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) #define MCG_SC_ATMF_MASK (0x20U) #define MCG_SC_ATMF_SHIFT (5U) #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) #define MCG_SC_ATMS_MASK (0x40U) #define MCG_SC_ATMS_SHIFT (6U) #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) #define MCG_SC_ATME_MASK (0x80U) #define MCG_SC_ATME_SHIFT (7U) #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ #define MCG_ATCVH_ATCVH_MASK (0xFFU) #define MCG_ATCVH_ATCVH_SHIFT (0U) #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ #define MCG_ATCVL_ATCVL_MASK (0xFFU) #define MCG_ATCVL_ATCVL_SHIFT (0U) #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) /*! @name C7 - MCG Control 7 Register */ #define MCG_C7_OSCSEL_MASK (0x3U) #define MCG_C7_OSCSEL_SHIFT (0U) #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) /*! @name C8 - MCG Control 8 Register */ #define MCG_C8_LOCS1_MASK (0x1U) #define MCG_C8_LOCS1_SHIFT (0U) #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) #define MCG_C8_CME1_MASK (0x20U) #define MCG_C8_CME1_SHIFT (5U) #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) #define MCG_C8_LOLRE_MASK (0x40U) #define MCG_C8_LOLRE_SHIFT (6U) #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) #define MCG_C8_LOCRE1_MASK (0x80U) #define MCG_C8_LOCRE1_SHIFT (7U) #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) /*! * @} */ /* end of group MCG_Register_Masks */ /* MCG - Peripheral instance base addresses */ /** Peripheral MCG base address */ #define MCG_BASE (0x40064000u) /** Peripheral MCG base pointer */ #define MCG ((MCG_Type *)MCG_BASE) /** Array initializer of MCG peripheral base addresses */ #define MCG_BASE_ADDRS { MCG_BASE } /** Array initializer of MCG peripheral base pointers */ #define MCG_BASE_PTRS { MCG } /*! * @} */ /* end of group MCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer * @{ */ /** MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ __IO uint32_t CR; /**< Control Register, offset: 0xC */ __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */ __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */ __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */ uint8_t RESERVED_1[16]; __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ } MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ #define MCM_PLASC_ASC_MASK (0xFFU) #define MCM_PLASC_ASC_SHIFT (0U) #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ #define MCM_PLAMC_AMC_MASK (0xFFU) #define MCM_PLAMC_AMC_SHIFT (0U) #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) /*! @name CR - Control Register */ #define MCM_CR_SRAMUAP_MASK (0x3000000U) #define MCM_CR_SRAMUAP_SHIFT (24U) #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) #define MCM_CR_SRAMUWP_MASK (0x4000000U) #define MCM_CR_SRAMUWP_SHIFT (26U) #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) #define MCM_CR_SRAMLAP_MASK (0x30000000U) #define MCM_CR_SRAMLAP_SHIFT (28U) #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) #define MCM_CR_SRAMLWP_MASK (0x40000000U) #define MCM_CR_SRAMLWP_SHIFT (30U) #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) /*! @name ISCR - Interrupt Status Register */ #define MCM_ISCR_IRQ_MASK (0x2U) #define MCM_ISCR_IRQ_SHIFT (1U) #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK) #define MCM_ISCR_NMI_MASK (0x4U) #define MCM_ISCR_NMI_SHIFT (2U) #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK) #define MCM_ISCR_DHREQ_MASK (0x8U) #define MCM_ISCR_DHREQ_SHIFT (3U) #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK) #define MCM_ISCR_FIOC_MASK (0x100U) #define MCM_ISCR_FIOC_SHIFT (8U) #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) #define MCM_ISCR_FDZC_MASK (0x200U) #define MCM_ISCR_FDZC_SHIFT (9U) #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) #define MCM_ISCR_FOFC_MASK (0x400U) #define MCM_ISCR_FOFC_SHIFT (10U) #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) #define MCM_ISCR_FUFC_MASK (0x800U) #define MCM_ISCR_FUFC_SHIFT (11U) #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) #define MCM_ISCR_FIXC_MASK (0x1000U) #define MCM_ISCR_FIXC_SHIFT (12U) #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) #define MCM_ISCR_FIDC_MASK (0x8000U) #define MCM_ISCR_FIDC_SHIFT (15U) #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) #define MCM_ISCR_FIOCE_MASK (0x1000000U) #define MCM_ISCR_FIOCE_SHIFT (24U) #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) #define MCM_ISCR_FDZCE_MASK (0x2000000U) #define MCM_ISCR_FDZCE_SHIFT (25U) #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) #define MCM_ISCR_FOFCE_MASK (0x4000000U) #define MCM_ISCR_FOFCE_SHIFT (26U) #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) #define MCM_ISCR_FUFCE_MASK (0x8000000U) #define MCM_ISCR_FUFCE_SHIFT (27U) #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) #define MCM_ISCR_FIXCE_MASK (0x10000000U) #define MCM_ISCR_FIXCE_SHIFT (28U) #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) #define MCM_ISCR_FIDCE_MASK (0x80000000U) #define MCM_ISCR_FIDCE_SHIFT (31U) #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) /*! @name ETBCC - ETB Counter Control register */ #define MCM_ETBCC_CNTEN_MASK (0x1U) #define MCM_ETBCC_CNTEN_SHIFT (0U) #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK) #define MCM_ETBCC_RSPT_MASK (0x6U) #define MCM_ETBCC_RSPT_SHIFT (1U) #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK) #define MCM_ETBCC_RLRQ_MASK (0x8U) #define MCM_ETBCC_RLRQ_SHIFT (3U) #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK) #define MCM_ETBCC_ETDIS_MASK (0x10U) #define MCM_ETBCC_ETDIS_SHIFT (4U) #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK) #define MCM_ETBCC_ITDIS_MASK (0x20U) #define MCM_ETBCC_ITDIS_SHIFT (5U) #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK) /*! @name ETBRL - ETB Reload register */ #define MCM_ETBRL_RELOAD_MASK (0x7FFU) #define MCM_ETBRL_RELOAD_SHIFT (0U) #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK) /*! @name ETBCNT - ETB Counter Value register */ #define MCM_ETBCNT_COUNTER_MASK (0x7FFU) #define MCM_ETBCNT_COUNTER_SHIFT (0U) #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK) /*! @name PID - Process ID register */ #define MCM_PID_PID_MASK (0xFFU) #define MCM_PID_PID_SHIFT (0U) #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) /*! * @} */ /* end of group MCM_Register_Masks */ /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xE0080000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) /** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } /** Interrupt vectors for the MCM peripheral type */ #define MCM_IRQS { MCM_IRQn } /*! * @} */ /* end of group MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NV Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer * @{ */ /** NV - Register Layout Typedef */ typedef struct { __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ } NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Masks NV Register Masks * @{ */ /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ #define NV_BACKKEY3_KEY_MASK (0xFFU) #define NV_BACKKEY3_KEY_SHIFT (0U) #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ #define NV_BACKKEY2_KEY_MASK (0xFFU) #define NV_BACKKEY2_KEY_SHIFT (0U) #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ #define NV_BACKKEY1_KEY_MASK (0xFFU) #define NV_BACKKEY1_KEY_SHIFT (0U) #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ #define NV_BACKKEY0_KEY_MASK (0xFFU) #define NV_BACKKEY0_KEY_SHIFT (0U) #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ #define NV_BACKKEY7_KEY_MASK (0xFFU) #define NV_BACKKEY7_KEY_SHIFT (0U) #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ #define NV_BACKKEY6_KEY_MASK (0xFFU) #define NV_BACKKEY6_KEY_SHIFT (0U) #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ #define NV_BACKKEY5_KEY_MASK (0xFFU) #define NV_BACKKEY5_KEY_SHIFT (0U) #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ #define NV_BACKKEY4_KEY_MASK (0xFFU) #define NV_BACKKEY4_KEY_SHIFT (0U) #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ #define NV_FPROT3_PROT_MASK (0xFFU) #define NV_FPROT3_PROT_SHIFT (0U) #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ #define NV_FPROT2_PROT_MASK (0xFFU) #define NV_FPROT2_PROT_SHIFT (0U) #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ #define NV_FPROT1_PROT_MASK (0xFFU) #define NV_FPROT1_PROT_SHIFT (0U) #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ #define NV_FPROT0_PROT_MASK (0xFFU) #define NV_FPROT0_PROT_SHIFT (0U) #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) /*! @name FSEC - Non-volatile Flash Security Register */ #define NV_FSEC_SEC_MASK (0x3U) #define NV_FSEC_SEC_SHIFT (0U) #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) #define NV_FSEC_FSLACC_MASK (0xCU) #define NV_FSEC_FSLACC_SHIFT (2U) #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) #define NV_FSEC_MEEN_MASK (0x30U) #define NV_FSEC_MEEN_SHIFT (4U) #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) #define NV_FSEC_KEYEN_MASK (0xC0U) #define NV_FSEC_KEYEN_SHIFT (6U) #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) /*! @name FOPT - Non-volatile Flash Option Register */ #define NV_FOPT_LPBOOT_MASK (0x1U) #define NV_FOPT_LPBOOT_SHIFT (0U) #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) #define NV_FOPT_EZPORT_DIS_MASK (0x2U) #define NV_FOPT_EZPORT_DIS_SHIFT (1U) #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) /*! @name FEPROT - Non-volatile EERAM Protection Register */ #define NV_FEPROT_EPROT_MASK (0xFFU) #define NV_FEPROT_EPROT_SHIFT (0U) #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) /*! @name FDPROT - Non-volatile D-Flash Protection Register */ #define NV_FDPROT_DPROT_MASK (0xFFU) #define NV_FDPROT_DPROT_SHIFT (0U) #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) /*! * @} */ /* end of group NV_Register_Masks */ /* NV - Peripheral instance base addresses */ /** Peripheral FTFE_FlashConfig base address */ #define FTFE_FlashConfig_BASE (0x400u) /** Peripheral FTFE_FlashConfig base pointer */ #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE) /** Array initializer of NV peripheral base addresses */ #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE } /** Array initializer of NV peripheral base pointers */ #define NV_BASE_PTRS { FTFE_FlashConfig } /*! * @} */ /* end of group NV_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OSC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer * @{ */ /** OSC - Register Layout Typedef */ typedef struct { __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ } OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Masks OSC Register Masks * @{ */ /*! @name CR - OSC Control Register */ #define OSC_CR_SC16P_MASK (0x1U) #define OSC_CR_SC16P_SHIFT (0U) #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) #define OSC_CR_SC8P_MASK (0x2U) #define OSC_CR_SC8P_SHIFT (1U) #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) #define OSC_CR_SC4P_MASK (0x4U) #define OSC_CR_SC4P_SHIFT (2U) #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) #define OSC_CR_SC2P_MASK (0x8U) #define OSC_CR_SC2P_SHIFT (3U) #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) #define OSC_CR_EREFSTEN_MASK (0x20U) #define OSC_CR_EREFSTEN_SHIFT (5U) #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) #define OSC_CR_ERCLKEN_MASK (0x80U) #define OSC_CR_ERCLKEN_SHIFT (7U) #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) /*! * @} */ /* end of group OSC_Register_Masks */ /* OSC - Peripheral instance base addresses */ /** Peripheral OSC base address */ #define OSC_BASE (0x40065000u) /** Peripheral OSC base pointer */ #define OSC ((OSC_Type *)OSC_BASE) /** Array initializer of OSC peripheral base addresses */ #define OSC_BASE_ADDRS { OSC_BASE } /** Array initializer of OSC peripheral base pointers */ #define OSC_BASE_PTRS { OSC } /*! * @} */ /* end of group OSC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer * @{ */ /** PDB - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ __I uint32_t CNT; /**< Counter register, offset: 0x8 */ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ uint8_t RESERVED_0[24]; } CH[2]; uint8_t RESERVED_0[240]; struct { /* offset: 0x150, array step: 0x8 */ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ } DAC[2]; uint8_t RESERVED_1[48]; __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ } PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Register_Masks PDB Register Masks * @{ */ /*! @name SC - Status and Control register */ #define PDB_SC_LDOK_MASK (0x1U) #define PDB_SC_LDOK_SHIFT (0U) #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) #define PDB_SC_CONT_MASK (0x2U) #define PDB_SC_CONT_SHIFT (1U) #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) #define PDB_SC_MULT_MASK (0xCU) #define PDB_SC_MULT_SHIFT (2U) #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) #define PDB_SC_PDBIE_MASK (0x20U) #define PDB_SC_PDBIE_SHIFT (5U) #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) #define PDB_SC_PDBIF_MASK (0x40U) #define PDB_SC_PDBIF_SHIFT (6U) #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) #define PDB_SC_PDBEN_MASK (0x80U) #define PDB_SC_PDBEN_SHIFT (7U) #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) #define PDB_SC_TRGSEL_MASK (0xF00U) #define PDB_SC_TRGSEL_SHIFT (8U) #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) #define PDB_SC_PRESCALER_MASK (0x7000U) #define PDB_SC_PRESCALER_SHIFT (12U) #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) #define PDB_SC_DMAEN_MASK (0x8000U) #define PDB_SC_DMAEN_SHIFT (15U) #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) #define PDB_SC_SWTRIG_MASK (0x10000U) #define PDB_SC_SWTRIG_SHIFT (16U) #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) #define PDB_SC_PDBEIE_MASK (0x20000U) #define PDB_SC_PDBEIE_SHIFT (17U) #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) #define PDB_SC_LDMOD_MASK (0xC0000U) #define PDB_SC_LDMOD_SHIFT (18U) #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) /*! @name MOD - Modulus register */ #define PDB_MOD_MOD_MASK (0xFFFFU) #define PDB_MOD_MOD_SHIFT (0U) #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) /*! @name CNT - Counter register */ #define PDB_CNT_CNT_MASK (0xFFFFU) #define PDB_CNT_CNT_SHIFT (0U) #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) /*! @name IDLY - Interrupt Delay register */ #define PDB_IDLY_IDLY_MASK (0xFFFFU) #define PDB_IDLY_IDLY_SHIFT (0U) #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) /*! @name C1 - Channel n Control register 1 */ #define PDB_C1_EN_MASK (0xFFU) #define PDB_C1_EN_SHIFT (0U) #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) #define PDB_C1_TOS_MASK (0xFF00U) #define PDB_C1_TOS_SHIFT (8U) #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) #define PDB_C1_BB_MASK (0xFF0000U) #define PDB_C1_BB_SHIFT (16U) #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) /* The count of PDB_C1 */ #define PDB_C1_COUNT (2U) /*! @name S - Channel n Status register */ #define PDB_S_ERR_MASK (0xFFU) #define PDB_S_ERR_SHIFT (0U) #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) #define PDB_S_CF_MASK (0xFF0000U) #define PDB_S_CF_SHIFT (16U) #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) /* The count of PDB_S */ #define PDB_S_COUNT (2U) /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ #define PDB_DLY_DLY_MASK (0xFFFFU) #define PDB_DLY_DLY_SHIFT (0U) #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) /* The count of PDB_DLY */ #define PDB_DLY_COUNT (2U) /* The count of PDB_DLY */ #define PDB_DLY_COUNT2 (2U) /*! @name INTC - DAC Interval Trigger n Control register */ #define PDB_INTC_TOE_MASK (0x1U) #define PDB_INTC_TOE_SHIFT (0U) #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) #define PDB_INTC_EXT_MASK (0x2U) #define PDB_INTC_EXT_SHIFT (1U) #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) /* The count of PDB_INTC */ #define PDB_INTC_COUNT (2U) /*! @name INT - DAC Interval n register */ #define PDB_INT_INT_MASK (0xFFFFU) #define PDB_INT_INT_SHIFT (0U) #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) /* The count of PDB_INT */ #define PDB_INT_COUNT (2U) /*! @name POEN - Pulse-Out n Enable register */ #define PDB_POEN_POEN_MASK (0xFFU) #define PDB_POEN_POEN_SHIFT (0U) #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) /*! @name PODLY - Pulse-Out n Delay register */ #define PDB_PODLY_DLY2_MASK (0xFFFFU) #define PDB_PODLY_DLY2_SHIFT (0U) #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) #define PDB_PODLY_DLY1_SHIFT (16U) #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) /* The count of PDB_PODLY */ #define PDB_PODLY_COUNT (3U) /*! * @} */ /* end of group PDB_Register_Masks */ /* PDB - Peripheral instance base addresses */ /** Peripheral PDB0 base address */ #define PDB0_BASE (0x40036000u) /** Peripheral PDB0 base pointer */ #define PDB0 ((PDB_Type *)PDB0_BASE) /** Array initializer of PDB peripheral base addresses */ #define PDB_BASE_ADDRS { PDB0_BASE } /** Array initializer of PDB peripheral base pointers */ #define PDB_BASE_PTRS { PDB0 } /** Interrupt vectors for the PDB peripheral type */ #define PDB_IRQS { PDB0_IRQn } /*! * @} */ /* end of group PDB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer * @{ */ /** PIT - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ uint8_t RESERVED_0[252]; struct { /* offset: 0x100, array step: 0x10 */ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ } CHANNEL[4]; } PIT_Type; /* ---------------------------------------------------------------------------- -- PIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Masks PIT Register Masks * @{ */ /*! @name MCR - PIT Module Control Register */ #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) /*! @name LDVAL - Timer Load Value Register */ #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) /* The count of PIT_LDVAL */ #define PIT_LDVAL_COUNT (4U) /*! @name CVAL - Current Timer Value Register */ #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) /* The count of PIT_CVAL */ #define PIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) #define PIT_TCTRL_TIE_MASK (0x2U) #define PIT_TCTRL_TIE_SHIFT (1U) #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) /* The count of PIT_TCTRL */ #define PIT_TCTRL_COUNT (4U) /*! @name TFLG - Timer Flag Register */ #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) /* The count of PIT_TFLG */ #define PIT_TFLG_COUNT (4U) /*! * @} */ /* end of group PIT_Register_Masks */ /* PIT - Peripheral instance base addresses */ /** Peripheral PIT base address */ #define PIT_BASE (0x40037000u) /** Peripheral PIT base pointer */ #define PIT ((PIT_Type *)PIT_BASE) /** Array initializer of PIT peripheral base addresses */ #define PIT_BASE_ADDRS { PIT_BASE } /** Array initializer of PIT peripheral base pointers */ #define PIT_BASE_PTRS { PIT } /** Interrupt vectors for the PIT peripheral type */ #define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } } /*! * @} */ /* end of group PIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer * @{ */ /** PMC - Register Layout Typedef */ typedef struct { __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ } PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Masks PMC Register Masks * @{ */ /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ #define PMC_LVDSC1_LVDV_MASK (0x3U) #define PMC_LVDSC1_LVDV_SHIFT (0U) #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) #define PMC_LVDSC1_LVDRE_MASK (0x10U) #define PMC_LVDSC1_LVDRE_SHIFT (4U) #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) #define PMC_LVDSC1_LVDIE_MASK (0x20U) #define PMC_LVDSC1_LVDIE_SHIFT (5U) #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) #define PMC_LVDSC1_LVDACK_MASK (0x40U) #define PMC_LVDSC1_LVDACK_SHIFT (6U) #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) #define PMC_LVDSC1_LVDF_MASK (0x80U) #define PMC_LVDSC1_LVDF_SHIFT (7U) #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ #define PMC_LVDSC2_LVWV_MASK (0x3U) #define PMC_LVDSC2_LVWV_SHIFT (0U) #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) #define PMC_LVDSC2_LVWIE_MASK (0x20U) #define PMC_LVDSC2_LVWIE_SHIFT (5U) #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) #define PMC_LVDSC2_LVWACK_MASK (0x40U) #define PMC_LVDSC2_LVWACK_SHIFT (6U) #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) #define PMC_LVDSC2_LVWF_MASK (0x80U) #define PMC_LVDSC2_LVWF_SHIFT (7U) #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) /*! @name REGSC - Regulator Status And Control register */ #define PMC_REGSC_BGBE_MASK (0x1U) #define PMC_REGSC_BGBE_SHIFT (0U) #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) #define PMC_REGSC_REGONS_MASK (0x4U) #define PMC_REGSC_REGONS_SHIFT (2U) #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) #define PMC_REGSC_ACKISO_MASK (0x8U) #define PMC_REGSC_ACKISO_SHIFT (3U) #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) #define PMC_REGSC_BGEN_MASK (0x10U) #define PMC_REGSC_BGEN_SHIFT (4U) #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) /*! * @} */ /* end of group PMC_Register_Masks */ /* PMC - Peripheral instance base addresses */ /** Peripheral PMC base address */ #define PMC_BASE (0x4007D000u) /** Peripheral PMC base pointer */ #define PMC ((PMC_Type *)PMC_BASE) /** Array initializer of PMC peripheral base addresses */ #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } /** Interrupt vectors for the PMC peripheral type */ #define PMC_IRQS { LVD_LVW_IRQn } /*! * @} */ /* end of group PMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Register Layout Typedef */ typedef struct { __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ uint8_t RESERVED_0[24]; __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ uint8_t RESERVED_1[28]; __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ } PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /*! @name PCR - Pin Control Register n */ #define PORT_PCR_PS_MASK (0x1U) #define PORT_PCR_PS_SHIFT (0U) #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) #define PORT_PCR_PE_MASK (0x2U) #define PORT_PCR_PE_SHIFT (1U) #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) #define PORT_PCR_SRE_MASK (0x4U) #define PORT_PCR_SRE_SHIFT (2U) #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) #define PORT_PCR_PFE_MASK (0x10U) #define PORT_PCR_PFE_SHIFT (4U) #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) #define PORT_PCR_ODE_MASK (0x20U) #define PORT_PCR_ODE_SHIFT (5U) #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) #define PORT_PCR_DSE_MASK (0x40U) #define PORT_PCR_DSE_SHIFT (6U) #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) #define PORT_PCR_MUX_MASK (0x700U) #define PORT_PCR_MUX_SHIFT (8U) #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) #define PORT_PCR_LK_MASK (0x8000U) #define PORT_PCR_LK_SHIFT (15U) #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) #define PORT_PCR_IRQC_MASK (0xF0000U) #define PORT_PCR_IRQC_SHIFT (16U) #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK (0x1000000U) #define PORT_PCR_ISF_SHIFT (24U) #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) /* The count of PORT_PCR */ #define PORT_PCR_COUNT (32U) /*! @name GPCLR - Global Pin Control Low Register */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCLR_GPWE_SHIFT (16U) #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) /*! @name GPCHR - Global Pin Control High Register */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCHR_GPWE_SHIFT (16U) #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) /*! @name ISFR - Interrupt Status Flag Register */ #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) #define PORT_ISFR_ISF_SHIFT (0U) #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) /*! @name DFER - Digital Filter Enable Register */ #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) #define PORT_DFER_DFE_SHIFT (0U) #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) /*! @name DFCR - Digital Filter Clock Register */ #define PORT_DFCR_CS_MASK (0x1U) #define PORT_DFCR_CS_SHIFT (0U) #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) /*! @name DFWR - Digital Filter Width Register */ #define PORT_DFWR_FILT_MASK (0x1FU) #define PORT_DFWR_FILT_SHIFT (0U) #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) /*! * @} */ /* end of group PORT_Register_Masks */ /* PORT - Peripheral instance base addresses */ /** Peripheral PORTA base address */ #define PORTA_BASE (0x40049000u) /** Peripheral PORTA base pointer */ #define PORTA ((PORT_Type *)PORTA_BASE) /** Peripheral PORTB base address */ #define PORTB_BASE (0x4004A000u) /** Peripheral PORTB base pointer */ #define PORTB ((PORT_Type *)PORTB_BASE) /** Peripheral PORTC base address */ #define PORTC_BASE (0x4004B000u) /** Peripheral PORTC base pointer */ #define PORTC ((PORT_Type *)PORTC_BASE) /** Peripheral PORTD base address */ #define PORTD_BASE (0x4004C000u) /** Peripheral PORTD base pointer */ #define PORTD ((PORT_Type *)PORTD_BASE) /** Peripheral PORTE base address */ #define PORTE_BASE (0x4004D000u) /** Peripheral PORTE base pointer */ #define PORTE ((PORT_Type *)PORTE_BASE) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } /** Interrupt vectors for the PORT peripheral type */ #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer * @{ */ /** RCM - Register Layout Typedef */ typedef struct { __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ uint8_t RESERVED_0[2]; __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ uint8_t RESERVED_1[1]; __I uint8_t MR; /**< Mode Register, offset: 0x7 */ } RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Masks RCM Register Masks * @{ */ /*! @name SRS0 - System Reset Status Register 0 */ #define RCM_SRS0_WAKEUP_MASK (0x1U) #define RCM_SRS0_WAKEUP_SHIFT (0U) #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) #define RCM_SRS0_LVD_MASK (0x2U) #define RCM_SRS0_LVD_SHIFT (1U) #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) #define RCM_SRS0_LOC_MASK (0x4U) #define RCM_SRS0_LOC_SHIFT (2U) #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) #define RCM_SRS0_LOL_MASK (0x8U) #define RCM_SRS0_LOL_SHIFT (3U) #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) #define RCM_SRS0_WDOG_MASK (0x20U) #define RCM_SRS0_WDOG_SHIFT (5U) #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) #define RCM_SRS0_PIN_MASK (0x40U) #define RCM_SRS0_PIN_SHIFT (6U) #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) #define RCM_SRS0_POR_MASK (0x80U) #define RCM_SRS0_POR_SHIFT (7U) #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) /*! @name SRS1 - System Reset Status Register 1 */ #define RCM_SRS1_JTAG_MASK (0x1U) #define RCM_SRS1_JTAG_SHIFT (0U) #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) #define RCM_SRS1_LOCKUP_MASK (0x2U) #define RCM_SRS1_LOCKUP_SHIFT (1U) #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) #define RCM_SRS1_SW_MASK (0x4U) #define RCM_SRS1_SW_SHIFT (2U) #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) #define RCM_SRS1_MDM_AP_MASK (0x8U) #define RCM_SRS1_MDM_AP_SHIFT (3U) #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) #define RCM_SRS1_EZPT_MASK (0x10U) #define RCM_SRS1_EZPT_SHIFT (4U) #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) #define RCM_SRS1_SACKERR_MASK (0x20U) #define RCM_SRS1_SACKERR_SHIFT (5U) #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) /*! @name RPFC - Reset Pin Filter Control register */ #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) #define RCM_RPFC_RSTFLTSS_MASK (0x4U) #define RCM_RPFC_RSTFLTSS_SHIFT (2U) #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) /*! @name RPFW - Reset Pin Filter Width register */ #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) /*! @name MR - Mode Register */ #define RCM_MR_EZP_MS_MASK (0x2U) #define RCM_MR_EZP_MS_SHIFT (1U) #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) /*! * @} */ /* end of group RCM_Register_Masks */ /* RCM - Peripheral instance base addresses */ /** Peripheral RCM base address */ #define RCM_BASE (0x4007F000u) /** Peripheral RCM base pointer */ #define RCM ((RCM_Type *)RCM_BASE) /** Array initializer of RCM peripheral base addresses */ #define RCM_BASE_ADDRS { RCM_BASE } /** Array initializer of RCM peripheral base pointers */ #define RCM_BASE_PTRS { RCM } /*! * @} */ /* end of group RCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RFSYS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer * @{ */ /** RFSYS - Register Layout Typedef */ typedef struct { __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ } RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Register_Masks RFSYS Register Masks * @{ */ /*! @name REG - Register file register */ #define RFSYS_REG_LL_MASK (0xFFU) #define RFSYS_REG_LL_SHIFT (0U) #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) #define RFSYS_REG_LH_MASK (0xFF00U) #define RFSYS_REG_LH_SHIFT (8U) #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) #define RFSYS_REG_HL_MASK (0xFF0000U) #define RFSYS_REG_HL_SHIFT (16U) #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) #define RFSYS_REG_HH_MASK (0xFF000000U) #define RFSYS_REG_HH_SHIFT (24U) #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) /* The count of RFSYS_REG */ #define RFSYS_REG_COUNT (8U) /*! * @} */ /* end of group RFSYS_Register_Masks */ /* RFSYS - Peripheral instance base addresses */ /** Peripheral RFSYS base address */ #define RFSYS_BASE (0x40041000u) /** Peripheral RFSYS base pointer */ #define RFSYS ((RFSYS_Type *)RFSYS_BASE) /** Array initializer of RFSYS peripheral base addresses */ #define RFSYS_BASE_ADDRS { RFSYS_BASE } /** Array initializer of RFSYS peripheral base pointers */ #define RFSYS_BASE_PTRS { RFSYS } /*! * @} */ /* end of group RFSYS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RFVBAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer * @{ */ /** RFVBAT - Register Layout Typedef */ typedef struct { __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ } RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks * @{ */ /*! @name REG - VBAT register file register */ #define RFVBAT_REG_LL_MASK (0xFFU) #define RFVBAT_REG_LL_SHIFT (0U) #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) #define RFVBAT_REG_LH_MASK (0xFF00U) #define RFVBAT_REG_LH_SHIFT (8U) #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) #define RFVBAT_REG_HL_MASK (0xFF0000U) #define RFVBAT_REG_HL_SHIFT (16U) #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) #define RFVBAT_REG_HH_MASK (0xFF000000U) #define RFVBAT_REG_HH_SHIFT (24U) #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) /* The count of RFVBAT_REG */ #define RFVBAT_REG_COUNT (8U) /*! * @} */ /* end of group RFVBAT_Register_Masks */ /* RFVBAT - Peripheral instance base addresses */ /** Peripheral RFVBAT base address */ #define RFVBAT_BASE (0x4003E000u) /** Peripheral RFVBAT base pointer */ #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) /** Array initializer of RFVBAT peripheral base addresses */ #define RFVBAT_BASE_ADDRS { RFVBAT_BASE } /** Array initializer of RFVBAT peripheral base pointers */ #define RFVBAT_BASE_PTRS { RFVBAT } /*! * @} */ /* end of group RFVBAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RNG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer * @{ */ /** RNG - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ } RNG_Type; /* ---------------------------------------------------------------------------- -- RNG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RNG_Register_Masks RNG Register Masks * @{ */ /*! @name CR - RNGA Control Register */ #define RNG_CR_GO_MASK (0x1U) #define RNG_CR_GO_SHIFT (0U) #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) #define RNG_CR_HA_MASK (0x2U) #define RNG_CR_HA_SHIFT (1U) #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) #define RNG_CR_INTM_MASK (0x4U) #define RNG_CR_INTM_SHIFT (2U) #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) #define RNG_CR_CLRI_MASK (0x8U) #define RNG_CR_CLRI_SHIFT (3U) #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) #define RNG_CR_SLP_MASK (0x10U) #define RNG_CR_SLP_SHIFT (4U) #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) /*! @name SR - RNGA Status Register */ #define RNG_SR_SECV_MASK (0x1U) #define RNG_SR_SECV_SHIFT (0U) #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) #define RNG_SR_LRS_MASK (0x2U) #define RNG_SR_LRS_SHIFT (1U) #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) #define RNG_SR_ORU_MASK (0x4U) #define RNG_SR_ORU_SHIFT (2U) #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) #define RNG_SR_ERRI_MASK (0x8U) #define RNG_SR_ERRI_SHIFT (3U) #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) #define RNG_SR_SLP_MASK (0x10U) #define RNG_SR_SLP_SHIFT (4U) #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) #define RNG_SR_OREG_LVL_MASK (0xFF00U) #define RNG_SR_OREG_LVL_SHIFT (8U) #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) #define RNG_SR_OREG_SIZE_MASK (0xFF0000U) #define RNG_SR_OREG_SIZE_SHIFT (16U) #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) /*! @name ER - RNGA Entropy Register */ #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) #define RNG_ER_EXT_ENT_SHIFT (0U) #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) /*! @name OR - RNGA Output Register */ #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) #define RNG_OR_RANDOUT_SHIFT (0U) #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) /*! * @} */ /* end of group RNG_Register_Masks */ /* RNG - Peripheral instance base addresses */ /** Peripheral RNG base address */ #define RNG_BASE (0x40029000u) /** Peripheral RNG base pointer */ #define RNG ((RNG_Type *)RNG_BASE) /** Array initializer of RNG peripheral base addresses */ #define RNG_BASE_ADDRS { RNG_BASE } /** Array initializer of RNG peripheral base pointers */ #define RNG_BASE_PTRS { RNG } /** Interrupt vectors for the RNG peripheral type */ #define RNG_IRQS { RNG_IRQn } /*! * @} */ /* end of group RNG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer * @{ */ /** RTC - Register Layout Typedef */ typedef struct { __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ uint8_t RESERVED_0[2016]; __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ } RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /*! @name TSR - RTC Time Seconds Register */ #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) #define RTC_TSR_TSR_SHIFT (0U) #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) /*! @name TPR - RTC Time Prescaler Register */ #define RTC_TPR_TPR_MASK (0xFFFFU) #define RTC_TPR_TPR_SHIFT (0U) #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) /*! @name TAR - RTC Time Alarm Register */ #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) #define RTC_TAR_TAR_SHIFT (0U) #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) /*! @name TCR - RTC Time Compensation Register */ #define RTC_TCR_TCR_MASK (0xFFU) #define RTC_TCR_TCR_SHIFT (0U) #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) #define RTC_TCR_CIR_MASK (0xFF00U) #define RTC_TCR_CIR_SHIFT (8U) #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) #define RTC_TCR_TCV_MASK (0xFF0000U) #define RTC_TCR_TCV_SHIFT (16U) #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) #define RTC_TCR_CIC_MASK (0xFF000000U) #define RTC_TCR_CIC_SHIFT (24U) #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) /*! @name CR - RTC Control Register */ #define RTC_CR_SWR_MASK (0x1U) #define RTC_CR_SWR_SHIFT (0U) #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) #define RTC_CR_WPE_MASK (0x2U) #define RTC_CR_WPE_SHIFT (1U) #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) #define RTC_CR_SUP_MASK (0x4U) #define RTC_CR_SUP_SHIFT (2U) #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) #define RTC_CR_UM_MASK (0x8U) #define RTC_CR_UM_SHIFT (3U) #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) #define RTC_CR_WPS_MASK (0x10U) #define RTC_CR_WPS_SHIFT (4U) #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) #define RTC_CR_OSCE_MASK (0x100U) #define RTC_CR_OSCE_SHIFT (8U) #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) #define RTC_CR_CLKO_MASK (0x200U) #define RTC_CR_CLKO_SHIFT (9U) #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) #define RTC_CR_SC16P_MASK (0x400U) #define RTC_CR_SC16P_SHIFT (10U) #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) #define RTC_CR_SC8P_MASK (0x800U) #define RTC_CR_SC8P_SHIFT (11U) #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) #define RTC_CR_SC4P_MASK (0x1000U) #define RTC_CR_SC4P_SHIFT (12U) #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) #define RTC_CR_SC2P_MASK (0x2000U) #define RTC_CR_SC2P_SHIFT (13U) #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) /*! @name SR - RTC Status Register */ #define RTC_SR_TIF_MASK (0x1U) #define RTC_SR_TIF_SHIFT (0U) #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) #define RTC_SR_TOF_MASK (0x2U) #define RTC_SR_TOF_SHIFT (1U) #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) #define RTC_SR_TAF_MASK (0x4U) #define RTC_SR_TAF_SHIFT (2U) #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) #define RTC_SR_TCE_MASK (0x10U) #define RTC_SR_TCE_SHIFT (4U) #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) /*! @name LR - RTC Lock Register */ #define RTC_LR_TCL_MASK (0x8U) #define RTC_LR_TCL_SHIFT (3U) #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) #define RTC_LR_CRL_MASK (0x10U) #define RTC_LR_CRL_SHIFT (4U) #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) #define RTC_LR_SRL_MASK (0x20U) #define RTC_LR_SRL_SHIFT (5U) #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) #define RTC_LR_LRL_MASK (0x40U) #define RTC_LR_LRL_SHIFT (6U) #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) /*! @name IER - RTC Interrupt Enable Register */ #define RTC_IER_TIIE_MASK (0x1U) #define RTC_IER_TIIE_SHIFT (0U) #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) #define RTC_IER_TOIE_MASK (0x2U) #define RTC_IER_TOIE_SHIFT (1U) #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) #define RTC_IER_TAIE_MASK (0x4U) #define RTC_IER_TAIE_SHIFT (2U) #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) #define RTC_IER_TSIE_MASK (0x10U) #define RTC_IER_TSIE_SHIFT (4U) #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) #define RTC_IER_WPON_MASK (0x80U) #define RTC_IER_WPON_SHIFT (7U) #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) /*! @name WAR - RTC Write Access Register */ #define RTC_WAR_TSRW_MASK (0x1U) #define RTC_WAR_TSRW_SHIFT (0U) #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) #define RTC_WAR_TPRW_MASK (0x2U) #define RTC_WAR_TPRW_SHIFT (1U) #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) #define RTC_WAR_TARW_MASK (0x4U) #define RTC_WAR_TARW_SHIFT (2U) #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) #define RTC_WAR_TCRW_MASK (0x8U) #define RTC_WAR_TCRW_SHIFT (3U) #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) #define RTC_WAR_CRW_MASK (0x10U) #define RTC_WAR_CRW_SHIFT (4U) #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) #define RTC_WAR_SRW_MASK (0x20U) #define RTC_WAR_SRW_SHIFT (5U) #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) #define RTC_WAR_LRW_MASK (0x40U) #define RTC_WAR_LRW_SHIFT (6U) #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) #define RTC_WAR_IERW_MASK (0x80U) #define RTC_WAR_IERW_SHIFT (7U) #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) /*! @name RAR - RTC Read Access Register */ #define RTC_RAR_TSRR_MASK (0x1U) #define RTC_RAR_TSRR_SHIFT (0U) #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) #define RTC_RAR_TPRR_MASK (0x2U) #define RTC_RAR_TPRR_SHIFT (1U) #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) #define RTC_RAR_TARR_MASK (0x4U) #define RTC_RAR_TARR_SHIFT (2U) #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) #define RTC_RAR_TCRR_MASK (0x8U) #define RTC_RAR_TCRR_SHIFT (3U) #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) #define RTC_RAR_CRR_MASK (0x10U) #define RTC_RAR_CRR_SHIFT (4U) #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) #define RTC_RAR_SRR_MASK (0x20U) #define RTC_RAR_SRR_SHIFT (5U) #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) #define RTC_RAR_LRR_MASK (0x40U) #define RTC_RAR_LRR_SHIFT (6U) #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) #define RTC_RAR_IERR_MASK (0x80U) #define RTC_RAR_IERR_SHIFT (7U) #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) /*! * @} */ /* end of group RTC_Register_Masks */ /* RTC - Peripheral instance base addresses */ /** Peripheral RTC base address */ #define RTC_BASE (0x4003D000u) /** Peripheral RTC base pointer */ #define RTC ((RTC_Type *)RTC_BASE) /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } /** Interrupt vectors for the RTC peripheral type */ #define RTC_IRQS { RTC_IRQn } #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } /*! * @} */ /* end of group RTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer * @{ */ /** SDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */ __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */ __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */ __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */ __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */ __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */ __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */ __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */ __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */ __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */ __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */ __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */ __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */ uint8_t RESERVED_0[8]; __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */ __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */ __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */ uint8_t RESERVED_1[100]; __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */ __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */ uint8_t RESERVED_2[52]; __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */ } SDHC_Type; /* ---------------------------------------------------------------------------- -- SDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDHC_Register_Masks SDHC Register Masks * @{ */ /*! @name DSADDR - DMA System Address register */ #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU) #define SDHC_DSADDR_DSADDR_SHIFT (2U) #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK) /*! @name BLKATTR - Block Attributes register */ #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU) #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U) #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK) #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U) #define SDHC_BLKATTR_BLKCNT_SHIFT (16U) #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK) /*! @name CMDARG - Command Argument register */ #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU) #define SDHC_CMDARG_CMDARG_SHIFT (0U) #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK) /*! @name XFERTYP - Transfer Type register */ #define SDHC_XFERTYP_DMAEN_MASK (0x1U) #define SDHC_XFERTYP_DMAEN_SHIFT (0U) #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK) #define SDHC_XFERTYP_BCEN_MASK (0x2U) #define SDHC_XFERTYP_BCEN_SHIFT (1U) #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK) #define SDHC_XFERTYP_AC12EN_MASK (0x4U) #define SDHC_XFERTYP_AC12EN_SHIFT (2U) #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK) #define SDHC_XFERTYP_DTDSEL_MASK (0x10U) #define SDHC_XFERTYP_DTDSEL_SHIFT (4U) #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK) #define SDHC_XFERTYP_MSBSEL_MASK (0x20U) #define SDHC_XFERTYP_MSBSEL_SHIFT (5U) #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK) #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U) #define SDHC_XFERTYP_RSPTYP_SHIFT (16U) #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK) #define SDHC_XFERTYP_CCCEN_MASK (0x80000U) #define SDHC_XFERTYP_CCCEN_SHIFT (19U) #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK) #define SDHC_XFERTYP_CICEN_MASK (0x100000U) #define SDHC_XFERTYP_CICEN_SHIFT (20U) #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK) #define SDHC_XFERTYP_DPSEL_MASK (0x200000U) #define SDHC_XFERTYP_DPSEL_SHIFT (21U) #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK) #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U) #define SDHC_XFERTYP_CMDTYP_SHIFT (22U) #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK) #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U) #define SDHC_XFERTYP_CMDINX_SHIFT (24U) #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK) /*! @name CMDRSP - Command Response 0..Command Response 3 */ #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK) #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK) #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK) #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU) #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U) #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK) /* The count of SDHC_CMDRSP */ #define SDHC_CMDRSP_COUNT (4U) /*! @name DATPORT - Buffer Data Port register */ #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU) #define SDHC_DATPORT_DATCONT_SHIFT (0U) #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK) /*! @name PRSSTAT - Present State register */ #define SDHC_PRSSTAT_CIHB_MASK (0x1U) #define SDHC_PRSSTAT_CIHB_SHIFT (0U) #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK) #define SDHC_PRSSTAT_CDIHB_MASK (0x2U) #define SDHC_PRSSTAT_CDIHB_SHIFT (1U) #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK) #define SDHC_PRSSTAT_DLA_MASK (0x4U) #define SDHC_PRSSTAT_DLA_SHIFT (2U) #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK) #define SDHC_PRSSTAT_SDSTB_MASK (0x8U) #define SDHC_PRSSTAT_SDSTB_SHIFT (3U) #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK) #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U) #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U) #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK) #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U) #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U) #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK) #define SDHC_PRSSTAT_PEROFF_MASK (0x40U) #define SDHC_PRSSTAT_PEROFF_SHIFT (6U) #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK) #define SDHC_PRSSTAT_SDOFF_MASK (0x80U) #define SDHC_PRSSTAT_SDOFF_SHIFT (7U) #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK) #define SDHC_PRSSTAT_WTA_MASK (0x100U) #define SDHC_PRSSTAT_WTA_SHIFT (8U) #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK) #define SDHC_PRSSTAT_RTA_MASK (0x200U) #define SDHC_PRSSTAT_RTA_SHIFT (9U) #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK) #define SDHC_PRSSTAT_BWEN_MASK (0x400U) #define SDHC_PRSSTAT_BWEN_SHIFT (10U) #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK) #define SDHC_PRSSTAT_BREN_MASK (0x800U) #define SDHC_PRSSTAT_BREN_SHIFT (11U) #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK) #define SDHC_PRSSTAT_CINS_MASK (0x10000U) #define SDHC_PRSSTAT_CINS_SHIFT (16U) #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK) #define SDHC_PRSSTAT_CLSL_MASK (0x800000U) #define SDHC_PRSSTAT_CLSL_SHIFT (23U) #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK) #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U) #define SDHC_PRSSTAT_DLSL_SHIFT (24U) #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK) /*! @name PROCTL - Protocol Control register */ #define SDHC_PROCTL_LCTL_MASK (0x1U) #define SDHC_PROCTL_LCTL_SHIFT (0U) #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK) #define SDHC_PROCTL_DTW_MASK (0x6U) #define SDHC_PROCTL_DTW_SHIFT (1U) #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK) #define SDHC_PROCTL_D3CD_MASK (0x8U) #define SDHC_PROCTL_D3CD_SHIFT (3U) #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK) #define SDHC_PROCTL_EMODE_MASK (0x30U) #define SDHC_PROCTL_EMODE_SHIFT (4U) #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK) #define SDHC_PROCTL_CDTL_MASK (0x40U) #define SDHC_PROCTL_CDTL_SHIFT (6U) #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK) #define SDHC_PROCTL_CDSS_MASK (0x80U) #define SDHC_PROCTL_CDSS_SHIFT (7U) #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK) #define SDHC_PROCTL_DMAS_MASK (0x300U) #define SDHC_PROCTL_DMAS_SHIFT (8U) #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK) #define SDHC_PROCTL_SABGREQ_MASK (0x10000U) #define SDHC_PROCTL_SABGREQ_SHIFT (16U) #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK) #define SDHC_PROCTL_CREQ_MASK (0x20000U) #define SDHC_PROCTL_CREQ_SHIFT (17U) #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK) #define SDHC_PROCTL_RWCTL_MASK (0x40000U) #define SDHC_PROCTL_RWCTL_SHIFT (18U) #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK) #define SDHC_PROCTL_IABG_MASK (0x80000U) #define SDHC_PROCTL_IABG_SHIFT (19U) #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK) #define SDHC_PROCTL_WECINT_MASK (0x1000000U) #define SDHC_PROCTL_WECINT_SHIFT (24U) #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK) #define SDHC_PROCTL_WECINS_MASK (0x2000000U) #define SDHC_PROCTL_WECINS_SHIFT (25U) #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK) #define SDHC_PROCTL_WECRM_MASK (0x4000000U) #define SDHC_PROCTL_WECRM_SHIFT (26U) #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK) /*! @name SYSCTL - System Control register */ #define SDHC_SYSCTL_IPGEN_MASK (0x1U) #define SDHC_SYSCTL_IPGEN_SHIFT (0U) #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK) #define SDHC_SYSCTL_HCKEN_MASK (0x2U) #define SDHC_SYSCTL_HCKEN_SHIFT (1U) #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK) #define SDHC_SYSCTL_PEREN_MASK (0x4U) #define SDHC_SYSCTL_PEREN_SHIFT (2U) #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK) #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U) #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U) #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK) #define SDHC_SYSCTL_DVS_MASK (0xF0U) #define SDHC_SYSCTL_DVS_SHIFT (4U) #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK) #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U) #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U) #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK) #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U) #define SDHC_SYSCTL_DTOCV_SHIFT (16U) #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK) #define SDHC_SYSCTL_RSTA_MASK (0x1000000U) #define SDHC_SYSCTL_RSTA_SHIFT (24U) #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK) #define SDHC_SYSCTL_RSTC_MASK (0x2000000U) #define SDHC_SYSCTL_RSTC_SHIFT (25U) #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK) #define SDHC_SYSCTL_RSTD_MASK (0x4000000U) #define SDHC_SYSCTL_RSTD_SHIFT (26U) #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK) #define SDHC_SYSCTL_INITA_MASK (0x8000000U) #define SDHC_SYSCTL_INITA_SHIFT (27U) #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK) /*! @name IRQSTAT - Interrupt Status register */ #define SDHC_IRQSTAT_CC_MASK (0x1U) #define SDHC_IRQSTAT_CC_SHIFT (0U) #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK) #define SDHC_IRQSTAT_TC_MASK (0x2U) #define SDHC_IRQSTAT_TC_SHIFT (1U) #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK) #define SDHC_IRQSTAT_BGE_MASK (0x4U) #define SDHC_IRQSTAT_BGE_SHIFT (2U) #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK) #define SDHC_IRQSTAT_DINT_MASK (0x8U) #define SDHC_IRQSTAT_DINT_SHIFT (3U) #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK) #define SDHC_IRQSTAT_BWR_MASK (0x10U) #define SDHC_IRQSTAT_BWR_SHIFT (4U) #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK) #define SDHC_IRQSTAT_BRR_MASK (0x20U) #define SDHC_IRQSTAT_BRR_SHIFT (5U) #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK) #define SDHC_IRQSTAT_CINS_MASK (0x40U) #define SDHC_IRQSTAT_CINS_SHIFT (6U) #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK) #define SDHC_IRQSTAT_CRM_MASK (0x80U) #define SDHC_IRQSTAT_CRM_SHIFT (7U) #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK) #define SDHC_IRQSTAT_CINT_MASK (0x100U) #define SDHC_IRQSTAT_CINT_SHIFT (8U) #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK) #define SDHC_IRQSTAT_CTOE_MASK (0x10000U) #define SDHC_IRQSTAT_CTOE_SHIFT (16U) #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK) #define SDHC_IRQSTAT_CCE_MASK (0x20000U) #define SDHC_IRQSTAT_CCE_SHIFT (17U) #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK) #define SDHC_IRQSTAT_CEBE_MASK (0x40000U) #define SDHC_IRQSTAT_CEBE_SHIFT (18U) #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK) #define SDHC_IRQSTAT_CIE_MASK (0x80000U) #define SDHC_IRQSTAT_CIE_SHIFT (19U) #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK) #define SDHC_IRQSTAT_DTOE_MASK (0x100000U) #define SDHC_IRQSTAT_DTOE_SHIFT (20U) #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK) #define SDHC_IRQSTAT_DCE_MASK (0x200000U) #define SDHC_IRQSTAT_DCE_SHIFT (21U) #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK) #define SDHC_IRQSTAT_DEBE_MASK (0x400000U) #define SDHC_IRQSTAT_DEBE_SHIFT (22U) #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK) #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U) #define SDHC_IRQSTAT_AC12E_SHIFT (24U) #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK) #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U) #define SDHC_IRQSTAT_DMAE_SHIFT (28U) #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK) /*! @name IRQSTATEN - Interrupt Status Enable register */ #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U) #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U) #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK) #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U) #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U) #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK) #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U) #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U) #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK) #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U) #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U) #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK) #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U) #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U) #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK) #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U) #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U) #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK) #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U) #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U) #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK) #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U) #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U) #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK) #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U) #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U) #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK) #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U) #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U) #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK) #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U) #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U) #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK) #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U) #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U) #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK) #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U) #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U) #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK) #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U) #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U) #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK) #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U) #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U) #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK) #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U) #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U) #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK) #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U) #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U) #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK) #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U) #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U) #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK) /*! @name IRQSIGEN - Interrupt Signal Enable register */ #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U) #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U) #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK) #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U) #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U) #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK) #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U) #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U) #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK) #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U) #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U) #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK) #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U) #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U) #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK) #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U) #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U) #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK) #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U) #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U) #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK) #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U) #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U) #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK) #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U) #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U) #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK) #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U) #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U) #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK) #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U) #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U) #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK) #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U) #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U) #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK) #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U) #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U) #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK) #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U) #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U) #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK) #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U) #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U) #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK) #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U) #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U) #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK) #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U) #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U) #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK) #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U) #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U) #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK) /*! @name AC12ERR - Auto CMD12 Error Status Register */ #define SDHC_AC12ERR_AC12NE_MASK (0x1U) #define SDHC_AC12ERR_AC12NE_SHIFT (0U) #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK) #define SDHC_AC12ERR_AC12TOE_MASK (0x2U) #define SDHC_AC12ERR_AC12TOE_SHIFT (1U) #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK) #define SDHC_AC12ERR_AC12EBE_MASK (0x4U) #define SDHC_AC12ERR_AC12EBE_SHIFT (2U) #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK) #define SDHC_AC12ERR_AC12CE_MASK (0x8U) #define SDHC_AC12ERR_AC12CE_SHIFT (3U) #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK) #define SDHC_AC12ERR_AC12IE_MASK (0x10U) #define SDHC_AC12ERR_AC12IE_SHIFT (4U) #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK) #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U) #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U) #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK) /*! @name HTCAPBLT - Host Controller Capabilities */ #define SDHC_HTCAPBLT_MBL_MASK (0x70000U) #define SDHC_HTCAPBLT_MBL_SHIFT (16U) #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK) #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U) #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U) #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK) #define SDHC_HTCAPBLT_HSS_MASK (0x200000U) #define SDHC_HTCAPBLT_HSS_SHIFT (21U) #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK) #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U) #define SDHC_HTCAPBLT_DMAS_SHIFT (22U) #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK) #define SDHC_HTCAPBLT_SRS_MASK (0x800000U) #define SDHC_HTCAPBLT_SRS_SHIFT (23U) #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK) #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U) #define SDHC_HTCAPBLT_VS33_SHIFT (24U) #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK) /*! @name WML - Watermark Level Register */ #define SDHC_WML_RDWML_MASK (0xFFU) #define SDHC_WML_RDWML_SHIFT (0U) #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK) #define SDHC_WML_WRWML_MASK (0xFF0000U) #define SDHC_WML_WRWML_SHIFT (16U) #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK) /*! @name FEVT - Force Event register */ #define SDHC_FEVT_AC12NE_MASK (0x1U) #define SDHC_FEVT_AC12NE_SHIFT (0U) #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK) #define SDHC_FEVT_AC12TOE_MASK (0x2U) #define SDHC_FEVT_AC12TOE_SHIFT (1U) #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK) #define SDHC_FEVT_AC12CE_MASK (0x4U) #define SDHC_FEVT_AC12CE_SHIFT (2U) #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK) #define SDHC_FEVT_AC12EBE_MASK (0x8U) #define SDHC_FEVT_AC12EBE_SHIFT (3U) #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK) #define SDHC_FEVT_AC12IE_MASK (0x10U) #define SDHC_FEVT_AC12IE_SHIFT (4U) #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK) #define SDHC_FEVT_CNIBAC12E_MASK (0x80U) #define SDHC_FEVT_CNIBAC12E_SHIFT (7U) #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK) #define SDHC_FEVT_CTOE_MASK (0x10000U) #define SDHC_FEVT_CTOE_SHIFT (16U) #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK) #define SDHC_FEVT_CCE_MASK (0x20000U) #define SDHC_FEVT_CCE_SHIFT (17U) #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK) #define SDHC_FEVT_CEBE_MASK (0x40000U) #define SDHC_FEVT_CEBE_SHIFT (18U) #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK) #define SDHC_FEVT_CIE_MASK (0x80000U) #define SDHC_FEVT_CIE_SHIFT (19U) #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK) #define SDHC_FEVT_DTOE_MASK (0x100000U) #define SDHC_FEVT_DTOE_SHIFT (20U) #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK) #define SDHC_FEVT_DCE_MASK (0x200000U) #define SDHC_FEVT_DCE_SHIFT (21U) #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK) #define SDHC_FEVT_DEBE_MASK (0x400000U) #define SDHC_FEVT_DEBE_SHIFT (22U) #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK) #define SDHC_FEVT_AC12E_MASK (0x1000000U) #define SDHC_FEVT_AC12E_SHIFT (24U) #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK) #define SDHC_FEVT_DMAE_MASK (0x10000000U) #define SDHC_FEVT_DMAE_SHIFT (28U) #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK) #define SDHC_FEVT_CINT_MASK (0x80000000U) #define SDHC_FEVT_CINT_SHIFT (31U) #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK) /*! @name ADMAES - ADMA Error Status register */ #define SDHC_ADMAES_ADMAES_MASK (0x3U) #define SDHC_ADMAES_ADMAES_SHIFT (0U) #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK) #define SDHC_ADMAES_ADMALME_MASK (0x4U) #define SDHC_ADMAES_ADMALME_SHIFT (2U) #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK) #define SDHC_ADMAES_ADMADCE_MASK (0x8U) #define SDHC_ADMAES_ADMADCE_SHIFT (3U) #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK) /*! @name ADSADDR - ADMA System Addressregister */ #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU) #define SDHC_ADSADDR_ADSADDR_SHIFT (2U) #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK) /*! @name VENDOR - Vendor Specific register */ #define SDHC_VENDOR_EXTDMAEN_MASK (0x1U) #define SDHC_VENDOR_EXTDMAEN_SHIFT (0U) #define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK) #define SDHC_VENDOR_EXBLKNU_MASK (0x2U) #define SDHC_VENDOR_EXBLKNU_SHIFT (1U) #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK) #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U) #define SDHC_VENDOR_INTSTVAL_SHIFT (16U) #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK) /*! @name MMCBOOT - MMC Boot register */ #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU) #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U) #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK) #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U) #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U) #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK) #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U) #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U) #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK) #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U) #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U) #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK) #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U) #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U) #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK) #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U) #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U) #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) /*! @name HOSTVER - Host Controller Version */ #define SDHC_HOSTVER_SVN_MASK (0xFFU) #define SDHC_HOSTVER_SVN_SHIFT (0U) #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK) #define SDHC_HOSTVER_VVN_MASK (0xFF00U) #define SDHC_HOSTVER_VVN_SHIFT (8U) #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK) /*! * @} */ /* end of group SDHC_Register_Masks */ /* SDHC - Peripheral instance base addresses */ /** Peripheral SDHC base address */ #define SDHC_BASE (0x400B1000u) /** Peripheral SDHC base pointer */ #define SDHC ((SDHC_Type *)SDHC_BASE) /** Array initializer of SDHC peripheral base addresses */ #define SDHC_BASE_ADDRS { SDHC_BASE } /** Array initializer of SDHC peripheral base pointers */ #define SDHC_BASE_PTRS { SDHC } /** Interrupt vectors for the SDHC peripheral type */ #define SDHC_IRQS { SDHC_IRQn } /*! * @} */ /* end of group SDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer * @{ */ /** SIM - Register Layout Typedef */ typedef struct { __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ uint8_t RESERVED_0[4092]; __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ uint8_t RESERVED_1[4]; __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ uint8_t RESERVED_2[4]; __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ uint8_t RESERVED_3[8]; __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ } SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /*! @name SOPT1 - System Options Register 1 */ #define SIM_SOPT1_RAMSIZE_MASK (0xF000U) #define SIM_SOPT1_RAMSIZE_SHIFT (12U) #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) #define SIM_SOPT1_USBVSTBY_SHIFT (29U) #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) #define SIM_SOPT1_USBSSTBY_SHIFT (30U) #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) #define SIM_SOPT1_USBREGEN_SHIFT (31U) #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) /*! @name SOPT1CFG - SOPT1 Configuration Register */ #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) #define SIM_SOPT1CFG_URWE_SHIFT (24U) #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) #define SIM_SOPT1CFG_USSWE_SHIFT (26U) #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) /*! @name SOPT2 - System Options Register 2 */ #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) #define SIM_SOPT2_FBSL_MASK (0x300U) #define SIM_SOPT2_FBSL_SHIFT (8U) #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) #define SIM_SOPT2_PTD7PAD_MASK (0x800U) #define SIM_SOPT2_PTD7PAD_SHIFT (11U) #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) #define SIM_SOPT2_USBSRC_MASK (0x40000U) #define SIM_SOPT2_USBSRC_SHIFT (18U) #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) #define SIM_SOPT2_RMIISRC_MASK (0x80000U) #define SIM_SOPT2_RMIISRC_SHIFT (19U) #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK) #define SIM_SOPT2_TIMESRC_MASK (0x300000U) #define SIM_SOPT2_TIMESRC_SHIFT (20U) #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK) #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U) #define SIM_SOPT2_SDHCSRC_SHIFT (28U) #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK) /*! @name SOPT4 - System Options Register 4 */ #define SIM_SOPT4_FTM0FLT0_MASK (0x1U) #define SIM_SOPT4_FTM0FLT0_SHIFT (0U) #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) #define SIM_SOPT4_FTM0FLT1_MASK (0x2U) #define SIM_SOPT4_FTM0FLT1_SHIFT (1U) #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) #define SIM_SOPT4_FTM0FLT2_MASK (0x4U) #define SIM_SOPT4_FTM0FLT2_SHIFT (2U) #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK) #define SIM_SOPT4_FTM1FLT0_MASK (0x10U) #define SIM_SOPT4_FTM1FLT0_SHIFT (4U) #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) #define SIM_SOPT4_FTM2FLT0_MASK (0x100U) #define SIM_SOPT4_FTM2FLT0_SHIFT (8U) #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) #define SIM_SOPT4_FTM3FLT0_SHIFT (12U) #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) /*! @name SOPT5 - System Options Register 5 */ #define SIM_SOPT5_UART0TXSRC_MASK (0x3U) #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) #define SIM_SOPT5_UART0RXSRC_MASK (0xCU) #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) #define SIM_SOPT5_UART1TXSRC_MASK (0x30U) #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) /*! @name SOPT7 - System Options Register 7 */ #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U) #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U) #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) /*! @name SDID - System Device Identification Register */ #define SIM_SDID_PINID_MASK (0xFU) #define SIM_SDID_PINID_SHIFT (0U) #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) #define SIM_SDID_FAMID_MASK (0x70U) #define SIM_SDID_FAMID_SHIFT (4U) #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) #define SIM_SDID_DIEID_MASK (0xF80U) #define SIM_SDID_DIEID_SHIFT (7U) #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) #define SIM_SDID_REVID_MASK (0xF000U) #define SIM_SDID_REVID_SHIFT (12U) #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) #define SIM_SDID_SERIESID_MASK (0xF00000U) #define SIM_SDID_SERIESID_SHIFT (20U) #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) #define SIM_SDID_SUBFAMID_MASK (0xF000000U) #define SIM_SDID_SUBFAMID_SHIFT (24U) #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) #define SIM_SDID_FAMILYID_MASK (0xF0000000U) #define SIM_SDID_FAMILYID_SHIFT (28U) #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) /*! @name SCGC1 - System Clock Gating Control Register 1 */ #define SIM_SCGC1_I2C2_MASK (0x40U) #define SIM_SCGC1_I2C2_SHIFT (6U) #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK) #define SIM_SCGC1_UART4_MASK (0x400U) #define SIM_SCGC1_UART4_SHIFT (10U) #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK) #define SIM_SCGC1_UART5_MASK (0x800U) #define SIM_SCGC1_UART5_SHIFT (11U) #define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK) /*! @name SCGC2 - System Clock Gating Control Register 2 */ #define SIM_SCGC2_ENET_MASK (0x1U) #define SIM_SCGC2_ENET_SHIFT (0U) #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK) #define SIM_SCGC2_DAC0_MASK (0x1000U) #define SIM_SCGC2_DAC0_SHIFT (12U) #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK) #define SIM_SCGC2_DAC1_MASK (0x2000U) #define SIM_SCGC2_DAC1_SHIFT (13U) #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK) /*! @name SCGC3 - System Clock Gating Control Register 3 */ #define SIM_SCGC3_RNGA_MASK (0x1U) #define SIM_SCGC3_RNGA_SHIFT (0U) #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK) #define SIM_SCGC3_SPI2_MASK (0x1000U) #define SIM_SCGC3_SPI2_SHIFT (12U) #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK) #define SIM_SCGC3_SDHC_MASK (0x20000U) #define SIM_SCGC3_SDHC_SHIFT (17U) #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK) #define SIM_SCGC3_FTM2_MASK (0x1000000U) #define SIM_SCGC3_FTM2_SHIFT (24U) #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK) #define SIM_SCGC3_FTM3_MASK (0x2000000U) #define SIM_SCGC3_FTM3_SHIFT (25U) #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK) #define SIM_SCGC3_ADC1_MASK (0x8000000U) #define SIM_SCGC3_ADC1_SHIFT (27U) #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK) /*! @name SCGC4 - System Clock Gating Control Register 4 */ #define SIM_SCGC4_EWM_MASK (0x2U) #define SIM_SCGC4_EWM_SHIFT (1U) #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) #define SIM_SCGC4_CMT_MASK (0x4U) #define SIM_SCGC4_CMT_SHIFT (2U) #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) #define SIM_SCGC4_I2C0_MASK (0x40U) #define SIM_SCGC4_I2C0_SHIFT (6U) #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) #define SIM_SCGC4_I2C1_MASK (0x80U) #define SIM_SCGC4_I2C1_SHIFT (7U) #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) #define SIM_SCGC4_UART0_MASK (0x400U) #define SIM_SCGC4_UART0_SHIFT (10U) #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) #define SIM_SCGC4_UART1_MASK (0x800U) #define SIM_SCGC4_UART1_SHIFT (11U) #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) #define SIM_SCGC4_UART2_MASK (0x1000U) #define SIM_SCGC4_UART2_SHIFT (12U) #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) #define SIM_SCGC4_UART3_MASK (0x2000U) #define SIM_SCGC4_UART3_SHIFT (13U) #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) #define SIM_SCGC4_USBOTG_MASK (0x40000U) #define SIM_SCGC4_USBOTG_SHIFT (18U) #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) #define SIM_SCGC4_CMP_MASK (0x80000U) #define SIM_SCGC4_CMP_SHIFT (19U) #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) #define SIM_SCGC4_VREF_MASK (0x100000U) #define SIM_SCGC4_VREF_SHIFT (20U) #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) /*! @name SCGC5 - System Clock Gating Control Register 5 */ #define SIM_SCGC5_LPTMR_MASK (0x1U) #define SIM_SCGC5_LPTMR_SHIFT (0U) #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) #define SIM_SCGC5_PORTA_MASK (0x200U) #define SIM_SCGC5_PORTA_SHIFT (9U) #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) #define SIM_SCGC5_PORTB_MASK (0x400U) #define SIM_SCGC5_PORTB_SHIFT (10U) #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) #define SIM_SCGC5_PORTC_MASK (0x800U) #define SIM_SCGC5_PORTC_SHIFT (11U) #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) #define SIM_SCGC5_PORTD_MASK (0x1000U) #define SIM_SCGC5_PORTD_SHIFT (12U) #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) #define SIM_SCGC5_PORTE_MASK (0x2000U) #define SIM_SCGC5_PORTE_SHIFT (13U) #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) /*! @name SCGC6 - System Clock Gating Control Register 6 */ #define SIM_SCGC6_FTF_MASK (0x1U) #define SIM_SCGC6_FTF_SHIFT (0U) #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) #define SIM_SCGC6_DMAMUX_MASK (0x2U) #define SIM_SCGC6_DMAMUX_SHIFT (1U) #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) #define SIM_SCGC6_FLEXCAN0_MASK (0x10U) #define SIM_SCGC6_FLEXCAN0_SHIFT (4U) #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK) #define SIM_SCGC6_RNGA_MASK (0x200U) #define SIM_SCGC6_RNGA_SHIFT (9U) #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) #define SIM_SCGC6_SPI0_MASK (0x1000U) #define SIM_SCGC6_SPI0_SHIFT (12U) #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) #define SIM_SCGC6_SPI1_MASK (0x2000U) #define SIM_SCGC6_SPI1_SHIFT (13U) #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) #define SIM_SCGC6_I2S_MASK (0x8000U) #define SIM_SCGC6_I2S_SHIFT (15U) #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) #define SIM_SCGC6_CRC_MASK (0x40000U) #define SIM_SCGC6_CRC_SHIFT (18U) #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) #define SIM_SCGC6_USBDCD_MASK (0x200000U) #define SIM_SCGC6_USBDCD_SHIFT (21U) #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) #define SIM_SCGC6_PDB_MASK (0x400000U) #define SIM_SCGC6_PDB_SHIFT (22U) #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) #define SIM_SCGC6_PIT_MASK (0x800000U) #define SIM_SCGC6_PIT_SHIFT (23U) #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) #define SIM_SCGC6_FTM0_MASK (0x1000000U) #define SIM_SCGC6_FTM0_SHIFT (24U) #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) #define SIM_SCGC6_FTM1_MASK (0x2000000U) #define SIM_SCGC6_FTM1_SHIFT (25U) #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) #define SIM_SCGC6_FTM2_MASK (0x4000000U) #define SIM_SCGC6_FTM2_SHIFT (26U) #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) #define SIM_SCGC6_ADC0_MASK (0x8000000U) #define SIM_SCGC6_ADC0_SHIFT (27U) #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) #define SIM_SCGC6_RTC_MASK (0x20000000U) #define SIM_SCGC6_RTC_SHIFT (29U) #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) #define SIM_SCGC6_DAC0_MASK (0x80000000U) #define SIM_SCGC6_DAC0_SHIFT (31U) #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) /*! @name SCGC7 - System Clock Gating Control Register 7 */ #define SIM_SCGC7_FLEXBUS_MASK (0x1U) #define SIM_SCGC7_FLEXBUS_SHIFT (0U) #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) #define SIM_SCGC7_DMA_MASK (0x2U) #define SIM_SCGC7_DMA_SHIFT (1U) #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) #define SIM_SCGC7_MPU_MASK (0x4U) #define SIM_SCGC7_MPU_SHIFT (2U) #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) /*! @name CLKDIV1 - System Clock Divider Register 1 */ #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) /*! @name CLKDIV2 - System Clock Divider Register 2 */ #define SIM_CLKDIV2_USBFRAC_MASK (0x1U) #define SIM_CLKDIV2_USBFRAC_SHIFT (0U) #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) #define SIM_CLKDIV2_USBDIV_MASK (0xEU) #define SIM_CLKDIV2_USBDIV_SHIFT (1U) #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) /*! @name FCFG1 - Flash Configuration Register 1 */ #define SIM_FCFG1_FLASHDIS_MASK (0x1U) #define SIM_FCFG1_FLASHDIS_SHIFT (0U) #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) #define SIM_FCFG1_DEPART_MASK (0xF00U) #define SIM_FCFG1_DEPART_SHIFT (8U) #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) #define SIM_FCFG1_EESIZE_MASK (0xF0000U) #define SIM_FCFG1_EESIZE_SHIFT (16U) #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) #define SIM_FCFG1_PFSIZE_SHIFT (24U) #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) #define SIM_FCFG1_NVMSIZE_SHIFT (28U) #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) /*! @name FCFG2 - Flash Configuration Register 2 */ #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) #define SIM_FCFG2_MAXADDR1_SHIFT (16U) #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) #define SIM_FCFG2_PFLSH_MASK (0x800000U) #define SIM_FCFG2_PFLSH_SHIFT (23U) #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) #define SIM_FCFG2_MAXADDR0_SHIFT (24U) #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) /*! @name UIDH - Unique Identification Register High */ #define SIM_UIDH_UID_MASK (0xFFFFFFFFU) #define SIM_UIDH_UID_SHIFT (0U) #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) /*! @name UIDMH - Unique Identification Register Mid-High */ #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) #define SIM_UIDMH_UID_SHIFT (0U) #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) /*! @name UIDML - Unique Identification Register Mid Low */ #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) #define SIM_UIDML_UID_SHIFT (0U) #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) /*! @name UIDL - Unique Identification Register Low */ #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) #define SIM_UIDL_UID_SHIFT (0U) #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) /*! * @} */ /* end of group SIM_Register_Masks */ /* SIM - Peripheral instance base addresses */ /** Peripheral SIM base address */ #define SIM_BASE (0x40047000u) /** Peripheral SIM base pointer */ #define SIM ((SIM_Type *)SIM_BASE) /** Array initializer of SIM peripheral base addresses */ #define SIM_BASE_ADDRS { SIM_BASE } /** Array initializer of SIM peripheral base pointers */ #define SIM_BASE_PTRS { SIM } /*! * @} */ /* end of group SIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer * @{ */ /** SMC - Register Layout Typedef */ typedef struct { __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ } SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /*! @name PMPROT - Power Mode Protection register */ #define SMC_PMPROT_AVLLS_MASK (0x2U) #define SMC_PMPROT_AVLLS_SHIFT (1U) #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) #define SMC_PMPROT_ALLS_MASK (0x8U) #define SMC_PMPROT_ALLS_SHIFT (3U) #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) #define SMC_PMPROT_AVLP_MASK (0x20U) #define SMC_PMPROT_AVLP_SHIFT (5U) #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) /*! @name PMCTRL - Power Mode Control register */ #define SMC_PMCTRL_STOPM_MASK (0x7U) #define SMC_PMCTRL_STOPM_SHIFT (0U) #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_STOPA_MASK (0x8U) #define SMC_PMCTRL_STOPA_SHIFT (3U) #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) #define SMC_PMCTRL_RUNM_MASK (0x60U) #define SMC_PMCTRL_RUNM_SHIFT (5U) #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) #define SMC_PMCTRL_LPWUI_MASK (0x80U) #define SMC_PMCTRL_LPWUI_SHIFT (7U) #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) /*! @name VLLSCTRL - VLLS Control register */ #define SMC_VLLSCTRL_VLLSM_MASK (0x7U) #define SMC_VLLSCTRL_VLLSM_SHIFT (0U) #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) #define SMC_VLLSCTRL_PORPO_MASK (0x20U) #define SMC_VLLSCTRL_PORPO_SHIFT (5U) #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) /*! @name PMSTAT - Power Mode Status register */ #define SMC_PMSTAT_PMSTAT_MASK (0x7FU) #define SMC_PMSTAT_PMSTAT_SHIFT (0U) #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) /*! * @} */ /* end of group SMC_Register_Masks */ /* SMC - Peripheral instance base addresses */ /** Peripheral SMC base address */ #define SMC_BASE (0x4007E000u) /** Peripheral SMC base pointer */ #define SMC ((SMC_Type *)SMC_BASE) /** Array initializer of SMC peripheral base addresses */ #define SMC_BASE_ADDRS { SMC_BASE } /** Array initializer of SMC peripheral base pointers */ #define SMC_BASE_PTRS { SMC } /*! * @} */ /* end of group SMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer * @{ */ /** SPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ union { /* offset: 0xC */ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ }; uint8_t RESERVED_1[24]; __IO uint32_t SR; /**< Status Register, offset: 0x2C */ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ union { /* offset: 0x34 */ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ }; __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ uint8_t RESERVED_2[48]; __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ } SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Masks SPI Register Masks * @{ */ /*! @name MCR - Module Configuration Register */ #define SPI_MCR_HALT_MASK (0x1U) #define SPI_MCR_HALT_SHIFT (0U) #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) #define SPI_MCR_SMPL_PT_MASK (0x300U) #define SPI_MCR_SMPL_PT_SHIFT (8U) #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) #define SPI_MCR_CLR_RXF_MASK (0x400U) #define SPI_MCR_CLR_RXF_SHIFT (10U) #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) #define SPI_MCR_CLR_TXF_MASK (0x800U) #define SPI_MCR_CLR_TXF_SHIFT (11U) #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) #define SPI_MCR_DIS_RXF_MASK (0x1000U) #define SPI_MCR_DIS_RXF_SHIFT (12U) #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) #define SPI_MCR_DIS_TXF_MASK (0x2000U) #define SPI_MCR_DIS_TXF_SHIFT (13U) #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) #define SPI_MCR_MDIS_MASK (0x4000U) #define SPI_MCR_MDIS_SHIFT (14U) #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) #define SPI_MCR_DOZE_MASK (0x8000U) #define SPI_MCR_DOZE_SHIFT (15U) #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) #define SPI_MCR_PCSIS_MASK (0x3F0000U) #define SPI_MCR_PCSIS_SHIFT (16U) #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) #define SPI_MCR_ROOE_MASK (0x1000000U) #define SPI_MCR_ROOE_SHIFT (24U) #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) #define SPI_MCR_PCSSE_MASK (0x2000000U) #define SPI_MCR_PCSSE_SHIFT (25U) #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) #define SPI_MCR_MTFE_MASK (0x4000000U) #define SPI_MCR_MTFE_SHIFT (26U) #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) #define SPI_MCR_FRZ_MASK (0x8000000U) #define SPI_MCR_FRZ_SHIFT (27U) #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) #define SPI_MCR_DCONF_MASK (0x30000000U) #define SPI_MCR_DCONF_SHIFT (28U) #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) #define SPI_MCR_CONT_SCKE_SHIFT (30U) #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) #define SPI_MCR_MSTR_MASK (0x80000000U) #define SPI_MCR_MSTR_SHIFT (31U) #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) /*! @name TCR - Transfer Count Register */ #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) #define SPI_TCR_SPI_TCNT_SHIFT (16U) #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ #define SPI_CTAR_BR_MASK (0xFU) #define SPI_CTAR_BR_SHIFT (0U) #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) #define SPI_CTAR_DT_MASK (0xF0U) #define SPI_CTAR_DT_SHIFT (4U) #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) #define SPI_CTAR_ASC_MASK (0xF00U) #define SPI_CTAR_ASC_SHIFT (8U) #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) #define SPI_CTAR_CSSCK_MASK (0xF000U) #define SPI_CTAR_CSSCK_SHIFT (12U) #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) #define SPI_CTAR_PBR_MASK (0x30000U) #define SPI_CTAR_PBR_SHIFT (16U) #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) #define SPI_CTAR_PDT_MASK (0xC0000U) #define SPI_CTAR_PDT_SHIFT (18U) #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) #define SPI_CTAR_PASC_MASK (0x300000U) #define SPI_CTAR_PASC_SHIFT (20U) #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) #define SPI_CTAR_PCSSCK_MASK (0xC00000U) #define SPI_CTAR_PCSSCK_SHIFT (22U) #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) #define SPI_CTAR_LSBFE_MASK (0x1000000U) #define SPI_CTAR_LSBFE_SHIFT (24U) #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) #define SPI_CTAR_CPHA_MASK (0x2000000U) #define SPI_CTAR_CPHA_SHIFT (25U) #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) #define SPI_CTAR_CPOL_MASK (0x4000000U) #define SPI_CTAR_CPOL_SHIFT (26U) #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) #define SPI_CTAR_FMSZ_MASK (0x78000000U) #define SPI_CTAR_FMSZ_SHIFT (27U) #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) #define SPI_CTAR_DBR_MASK (0x80000000U) #define SPI_CTAR_DBR_SHIFT (31U) #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) /* The count of SPI_CTAR */ #define SPI_CTAR_COUNT (2U) /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) /* The count of SPI_CTAR_SLAVE */ #define SPI_CTAR_SLAVE_COUNT (1U) /*! @name SR - Status Register */ #define SPI_SR_POPNXTPTR_MASK (0xFU) #define SPI_SR_POPNXTPTR_SHIFT (0U) #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) #define SPI_SR_RXCTR_MASK (0xF0U) #define SPI_SR_RXCTR_SHIFT (4U) #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) #define SPI_SR_TXNXTPTR_MASK (0xF00U) #define SPI_SR_TXNXTPTR_SHIFT (8U) #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) #define SPI_SR_TXCTR_MASK (0xF000U) #define SPI_SR_TXCTR_SHIFT (12U) #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) #define SPI_SR_RFDF_MASK (0x20000U) #define SPI_SR_RFDF_SHIFT (17U) #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) #define SPI_SR_RFOF_MASK (0x80000U) #define SPI_SR_RFOF_SHIFT (19U) #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) #define SPI_SR_TFFF_MASK (0x2000000U) #define SPI_SR_TFFF_SHIFT (25U) #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) #define SPI_SR_TFUF_MASK (0x8000000U) #define SPI_SR_TFUF_SHIFT (27U) #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) #define SPI_SR_EOQF_MASK (0x10000000U) #define SPI_SR_EOQF_SHIFT (28U) #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) #define SPI_SR_TXRXS_MASK (0x40000000U) #define SPI_SR_TXRXS_SHIFT (30U) #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) #define SPI_SR_TCF_MASK (0x80000000U) #define SPI_SR_TCF_SHIFT (31U) #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) #define SPI_RSER_RFDF_DIRS_SHIFT (16U) #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) #define SPI_RSER_RFDF_RE_MASK (0x20000U) #define SPI_RSER_RFDF_RE_SHIFT (17U) #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) #define SPI_RSER_RFOF_RE_MASK (0x80000U) #define SPI_RSER_RFOF_RE_SHIFT (19U) #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) #define SPI_RSER_TFFF_DIRS_SHIFT (24U) #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) #define SPI_RSER_TFFF_RE_MASK (0x2000000U) #define SPI_RSER_TFFF_RE_SHIFT (25U) #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) #define SPI_RSER_TFUF_RE_MASK (0x8000000U) #define SPI_RSER_TFUF_RE_SHIFT (27U) #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) #define SPI_RSER_EOQF_RE_MASK (0x10000000U) #define SPI_RSER_EOQF_RE_SHIFT (28U) #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) #define SPI_RSER_TCF_RE_MASK (0x80000000U) #define SPI_RSER_TCF_RE_SHIFT (31U) #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) #define SPI_PUSHR_TXDATA_SHIFT (0U) #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) #define SPI_PUSHR_PCS_MASK (0x3F0000U) #define SPI_PUSHR_PCS_SHIFT (16U) #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) #define SPI_PUSHR_CTCNT_MASK (0x4000000U) #define SPI_PUSHR_CTCNT_SHIFT (26U) #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) #define SPI_PUSHR_EOQ_MASK (0x8000000U) #define SPI_PUSHR_EOQ_SHIFT (27U) #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) #define SPI_PUSHR_CTAS_MASK (0x70000000U) #define SPI_PUSHR_CTAS_SHIFT (28U) #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) #define SPI_PUSHR_CONT_MASK (0x80000000U) #define SPI_PUSHR_CONT_SHIFT (31U) #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) /*! @name POPR - POP RX FIFO Register */ #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) #define SPI_POPR_RXDATA_SHIFT (0U) #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) /*! @name TXFR0 - Transmit FIFO Registers */ #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) #define SPI_TXFR0_TXDATA_SHIFT (0U) #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) /*! @name TXFR1 - Transmit FIFO Registers */ #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) #define SPI_TXFR1_TXDATA_SHIFT (0U) #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) /*! @name TXFR2 - Transmit FIFO Registers */ #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) #define SPI_TXFR2_TXDATA_SHIFT (0U) #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) /*! @name TXFR3 - Transmit FIFO Registers */ #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) #define SPI_TXFR3_TXDATA_SHIFT (0U) #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) /*! @name RXFR0 - Receive FIFO Registers */ #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR0_RXDATA_SHIFT (0U) #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) /*! @name RXFR1 - Receive FIFO Registers */ #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR1_RXDATA_SHIFT (0U) #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) /*! @name RXFR2 - Receive FIFO Registers */ #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR2_RXDATA_SHIFT (0U) #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) /*! @name RXFR3 - Receive FIFO Registers */ #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) #define SPI_RXFR3_RXDATA_SHIFT (0U) #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) /*! * @} */ /* end of group SPI_Register_Masks */ /* SPI - Peripheral instance base addresses */ /** Peripheral SPI0 base address */ #define SPI0_BASE (0x4002C000u) /** Peripheral SPI0 base pointer */ #define SPI0 ((SPI_Type *)SPI0_BASE) /** Peripheral SPI1 base address */ #define SPI1_BASE (0x4002D000u) /** Peripheral SPI1 base pointer */ #define SPI1 ((SPI_Type *)SPI1_BASE) /** Peripheral SPI2 base address */ #define SPI2_BASE (0x400AC000u) /** Peripheral SPI2 base pointer */ #define SPI2 ((SPI_Type *)SPI2_BASE) /** Array initializer of SPI peripheral base addresses */ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE } /** Array initializer of SPI peripheral base pointers */ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 } /** Interrupt vectors for the SPI peripheral type */ #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn } /*! * @} */ /* end of group SPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYSMPU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer * @{ */ /** SYSMPU - Register Layout Typedef */ typedef struct { __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ uint8_t RESERVED_0[12]; struct { /* offset: 0x10, array step: 0x8 */ __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ } SP[5]; uint8_t RESERVED_1[968]; __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[832]; __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ } SYSMPU_Type; /* ---------------------------------------------------------------------------- -- SYSMPU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks * @{ */ /*! @name CESR - Control/Error Status Register */ #define SYSMPU_CESR_VLD_MASK (0x1U) #define SYSMPU_CESR_VLD_SHIFT (0U) #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK) #define SYSMPU_CESR_NRGD_MASK (0xF00U) #define SYSMPU_CESR_NRGD_SHIFT (8U) #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) #define SYSMPU_CESR_NSP_MASK (0xF000U) #define SYSMPU_CESR_NSP_SHIFT (12U) #define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) #define SYSMPU_CESR_HRL_MASK (0xF0000U) #define SYSMPU_CESR_HRL_SHIFT (16U) #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) #define SYSMPU_CESR_SPERR_MASK (0xF8000000U) #define SYSMPU_CESR_SPERR_SHIFT (27U) #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) /*! @name EAR - Error Address Register, slave port n */ #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU) #define SYSMPU_EAR_EADDR_SHIFT (0U) #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK) /* The count of SYSMPU_EAR */ #define SYSMPU_EAR_COUNT (5U) /*! @name EDR - Error Detail Register, slave port n */ #define SYSMPU_EDR_ERW_MASK (0x1U) #define SYSMPU_EDR_ERW_SHIFT (0U) #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK) #define SYSMPU_EDR_EATTR_MASK (0xEU) #define SYSMPU_EDR_EATTR_SHIFT (1U) #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) #define SYSMPU_EDR_EMN_MASK (0xF0U) #define SYSMPU_EDR_EMN_SHIFT (4U) #define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) #define SYSMPU_EDR_EPID_MASK (0xFF00U) #define SYSMPU_EDR_EPID_SHIFT (8U) #define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) #define SYSMPU_EDR_EACD_SHIFT (16U) #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) /* The count of SYSMPU_EDR */ #define SYSMPU_EDR_COUNT (5U) /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ #define SYSMPU_WORD_VLD_MASK (0x1U) #define SYSMPU_WORD_VLD_SHIFT (0U) #define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) #define SYSMPU_WORD_M0UM_MASK (0x7U) #define SYSMPU_WORD_M0UM_SHIFT (0U) #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) #define SYSMPU_WORD_M0SM_MASK (0x18U) #define SYSMPU_WORD_M0SM_SHIFT (3U) #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) #define SYSMPU_WORD_M0PE_MASK (0x20U) #define SYSMPU_WORD_M0PE_SHIFT (5U) #define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) #define SYSMPU_WORD_ENDADDR_SHIFT (5U) #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) #define SYSMPU_WORD_SRTADDR_SHIFT (5U) #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) #define SYSMPU_WORD_M1UM_MASK (0x1C0U) #define SYSMPU_WORD_M1UM_SHIFT (6U) #define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) #define SYSMPU_WORD_M1SM_MASK (0x600U) #define SYSMPU_WORD_M1SM_SHIFT (9U) #define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) #define SYSMPU_WORD_M1PE_MASK (0x800U) #define SYSMPU_WORD_M1PE_SHIFT (11U) #define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK) #define SYSMPU_WORD_M2UM_MASK (0x7000U) #define SYSMPU_WORD_M2UM_SHIFT (12U) #define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) #define SYSMPU_WORD_M2SM_MASK (0x18000U) #define SYSMPU_WORD_M2SM_SHIFT (15U) #define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) #define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) #define SYSMPU_WORD_PIDMASK_SHIFT (16U) #define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) #define SYSMPU_WORD_M2PE_MASK (0x20000U) #define SYSMPU_WORD_M2PE_SHIFT (17U) #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK) #define SYSMPU_WORD_M3UM_MASK (0x1C0000U) #define SYSMPU_WORD_M3UM_SHIFT (18U) #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) #define SYSMPU_WORD_M3SM_MASK (0x600000U) #define SYSMPU_WORD_M3SM_SHIFT (21U) #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) #define SYSMPU_WORD_M3PE_MASK (0x800000U) #define SYSMPU_WORD_M3PE_SHIFT (23U) #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK) #define SYSMPU_WORD_PID_MASK (0xFF000000U) #define SYSMPU_WORD_PID_SHIFT (24U) #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) #define SYSMPU_WORD_M4WE_MASK (0x1000000U) #define SYSMPU_WORD_M4WE_SHIFT (24U) #define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) #define SYSMPU_WORD_M4RE_MASK (0x2000000U) #define SYSMPU_WORD_M4RE_SHIFT (25U) #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK) #define SYSMPU_WORD_M5WE_MASK (0x4000000U) #define SYSMPU_WORD_M5WE_SHIFT (26U) #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK) #define SYSMPU_WORD_M5RE_MASK (0x8000000U) #define SYSMPU_WORD_M5RE_SHIFT (27U) #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK) #define SYSMPU_WORD_M6WE_MASK (0x10000000U) #define SYSMPU_WORD_M6WE_SHIFT (28U) #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK) #define SYSMPU_WORD_M6RE_MASK (0x20000000U) #define SYSMPU_WORD_M6RE_SHIFT (29U) #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK) #define SYSMPU_WORD_M7WE_MASK (0x40000000U) #define SYSMPU_WORD_M7WE_SHIFT (30U) #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK) #define SYSMPU_WORD_M7RE_MASK (0x80000000U) #define SYSMPU_WORD_M7RE_SHIFT (31U) #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK) /* The count of SYSMPU_WORD */ #define SYSMPU_WORD_COUNT (12U) /* The count of SYSMPU_WORD */ #define SYSMPU_WORD_COUNT2 (4U) /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ #define SYSMPU_RGDAAC_M0UM_MASK (0x7U) #define SYSMPU_RGDAAC_M0UM_SHIFT (0U) #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) #define SYSMPU_RGDAAC_M0SM_MASK (0x18U) #define SYSMPU_RGDAAC_M0SM_SHIFT (3U) #define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) #define SYSMPU_RGDAAC_M0PE_MASK (0x20U) #define SYSMPU_RGDAAC_M0PE_SHIFT (5U) #define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK) #define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) #define SYSMPU_RGDAAC_M1UM_SHIFT (6U) #define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) #define SYSMPU_RGDAAC_M1SM_MASK (0x600U) #define SYSMPU_RGDAAC_M1SM_SHIFT (9U) #define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) #define SYSMPU_RGDAAC_M1PE_MASK (0x800U) #define SYSMPU_RGDAAC_M1PE_SHIFT (11U) #define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK) #define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) #define SYSMPU_RGDAAC_M2UM_SHIFT (12U) #define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) #define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) #define SYSMPU_RGDAAC_M2SM_SHIFT (15U) #define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) #define SYSMPU_RGDAAC_M2PE_MASK (0x20000U) #define SYSMPU_RGDAAC_M2PE_SHIFT (17U) #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK) #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) #define SYSMPU_RGDAAC_M3UM_SHIFT (18U) #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) #define SYSMPU_RGDAAC_M3SM_SHIFT (21U) #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U) #define SYSMPU_RGDAAC_M3PE_SHIFT (23U) #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK) #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U) #define SYSMPU_RGDAAC_M4WE_SHIFT (24U) #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK) #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U) #define SYSMPU_RGDAAC_M4RE_SHIFT (25U) #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK) #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U) #define SYSMPU_RGDAAC_M5WE_SHIFT (26U) #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK) #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U) #define SYSMPU_RGDAAC_M5RE_SHIFT (27U) #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK) #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U) #define SYSMPU_RGDAAC_M6WE_SHIFT (28U) #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK) #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U) #define SYSMPU_RGDAAC_M6RE_SHIFT (29U) #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK) #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U) #define SYSMPU_RGDAAC_M7WE_SHIFT (30U) #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK) #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U) #define SYSMPU_RGDAAC_M7RE_SHIFT (31U) #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK) /* The count of SYSMPU_RGDAAC */ #define SYSMPU_RGDAAC_COUNT (12U) /*! * @} */ /* end of group SYSMPU_Register_Masks */ /* SYSMPU - Peripheral instance base addresses */ /** Peripheral SYSMPU base address */ #define SYSMPU_BASE (0x4000D000u) /** Peripheral SYSMPU base pointer */ #define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE) /** Array initializer of SYSMPU peripheral base addresses */ #define SYSMPU_BASE_ADDRS { SYSMPU_BASE } /** Array initializer of SYSMPU peripheral base pointers */ #define SYSMPU_BASE_PTRS { SYSMPU } /*! * @} */ /* end of group SYSMPU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- UART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer * @{ */ /** UART - Register Layout Typedef */ typedef struct { __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ uint8_t RESERVED_0[1]; __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ uint8_t RESERVED_1[1]; __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ union { /* offset: 0x1B */ __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ }; __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ } UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /*! @name BDH - UART Baud Rate Registers: High */ #define UART_BDH_SBR_MASK (0x1FU) #define UART_BDH_SBR_SHIFT (0U) #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) #define UART_BDH_SBNS_MASK (0x20U) #define UART_BDH_SBNS_SHIFT (5U) #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) #define UART_BDH_RXEDGIE_MASK (0x40U) #define UART_BDH_RXEDGIE_SHIFT (6U) #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) #define UART_BDH_LBKDIE_MASK (0x80U) #define UART_BDH_LBKDIE_SHIFT (7U) #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) /*! @name BDL - UART Baud Rate Registers: Low */ #define UART_BDL_SBR_MASK (0xFFU) #define UART_BDL_SBR_SHIFT (0U) #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) /*! @name C1 - UART Control Register 1 */ #define UART_C1_PT_MASK (0x1U) #define UART_C1_PT_SHIFT (0U) #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) #define UART_C1_PE_MASK (0x2U) #define UART_C1_PE_SHIFT (1U) #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) #define UART_C1_ILT_MASK (0x4U) #define UART_C1_ILT_SHIFT (2U) #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) #define UART_C1_WAKE_MASK (0x8U) #define UART_C1_WAKE_SHIFT (3U) #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) #define UART_C1_M_MASK (0x10U) #define UART_C1_M_SHIFT (4U) #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) #define UART_C1_RSRC_MASK (0x20U) #define UART_C1_RSRC_SHIFT (5U) #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) #define UART_C1_UARTSWAI_MASK (0x40U) #define UART_C1_UARTSWAI_SHIFT (6U) #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) #define UART_C1_LOOPS_MASK (0x80U) #define UART_C1_LOOPS_SHIFT (7U) #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) /*! @name C2 - UART Control Register 2 */ #define UART_C2_SBK_MASK (0x1U) #define UART_C2_SBK_SHIFT (0U) #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) #define UART_C2_RWU_MASK (0x2U) #define UART_C2_RWU_SHIFT (1U) #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) #define UART_C2_RE_MASK (0x4U) #define UART_C2_RE_SHIFT (2U) #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) #define UART_C2_TE_MASK (0x8U) #define UART_C2_TE_SHIFT (3U) #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) #define UART_C2_ILIE_MASK (0x10U) #define UART_C2_ILIE_SHIFT (4U) #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) #define UART_C2_RIE_MASK (0x20U) #define UART_C2_RIE_SHIFT (5U) #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) #define UART_C2_TCIE_MASK (0x40U) #define UART_C2_TCIE_SHIFT (6U) #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) #define UART_C2_TIE_MASK (0x80U) #define UART_C2_TIE_SHIFT (7U) #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) /*! @name S1 - UART Status Register 1 */ #define UART_S1_PF_MASK (0x1U) #define UART_S1_PF_SHIFT (0U) #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) #define UART_S1_FE_MASK (0x2U) #define UART_S1_FE_SHIFT (1U) #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) #define UART_S1_NF_MASK (0x4U) #define UART_S1_NF_SHIFT (2U) #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) #define UART_S1_OR_MASK (0x8U) #define UART_S1_OR_SHIFT (3U) #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) #define UART_S1_IDLE_MASK (0x10U) #define UART_S1_IDLE_SHIFT (4U) #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) #define UART_S1_RDRF_MASK (0x20U) #define UART_S1_RDRF_SHIFT (5U) #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) #define UART_S1_TC_MASK (0x40U) #define UART_S1_TC_SHIFT (6U) #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) #define UART_S1_TDRE_MASK (0x80U) #define UART_S1_TDRE_SHIFT (7U) #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) /*! @name S2 - UART Status Register 2 */ #define UART_S2_RAF_MASK (0x1U) #define UART_S2_RAF_SHIFT (0U) #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) #define UART_S2_LBKDE_MASK (0x2U) #define UART_S2_LBKDE_SHIFT (1U) #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) #define UART_S2_BRK13_MASK (0x4U) #define UART_S2_BRK13_SHIFT (2U) #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) #define UART_S2_RWUID_MASK (0x8U) #define UART_S2_RWUID_SHIFT (3U) #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) #define UART_S2_RXINV_MASK (0x10U) #define UART_S2_RXINV_SHIFT (4U) #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) #define UART_S2_MSBF_MASK (0x20U) #define UART_S2_MSBF_SHIFT (5U) #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) #define UART_S2_RXEDGIF_MASK (0x40U) #define UART_S2_RXEDGIF_SHIFT (6U) #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) #define UART_S2_LBKDIF_MASK (0x80U) #define UART_S2_LBKDIF_SHIFT (7U) #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) /*! @name C3 - UART Control Register 3 */ #define UART_C3_PEIE_MASK (0x1U) #define UART_C3_PEIE_SHIFT (0U) #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) #define UART_C3_FEIE_MASK (0x2U) #define UART_C3_FEIE_SHIFT (1U) #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) #define UART_C3_NEIE_MASK (0x4U) #define UART_C3_NEIE_SHIFT (2U) #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) #define UART_C3_ORIE_MASK (0x8U) #define UART_C3_ORIE_SHIFT (3U) #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) #define UART_C3_TXINV_MASK (0x10U) #define UART_C3_TXINV_SHIFT (4U) #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) #define UART_C3_TXDIR_MASK (0x20U) #define UART_C3_TXDIR_SHIFT (5U) #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) #define UART_C3_T8_MASK (0x40U) #define UART_C3_T8_SHIFT (6U) #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) #define UART_C3_R8_MASK (0x80U) #define UART_C3_R8_SHIFT (7U) #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) /*! @name D - UART Data Register */ #define UART_D_RT_MASK (0xFFU) #define UART_D_RT_SHIFT (0U) #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) /*! @name MA1 - UART Match Address Registers 1 */ #define UART_MA1_MA_MASK (0xFFU) #define UART_MA1_MA_SHIFT (0U) #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) /*! @name MA2 - UART Match Address Registers 2 */ #define UART_MA2_MA_MASK (0xFFU) #define UART_MA2_MA_SHIFT (0U) #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) /*! @name C4 - UART Control Register 4 */ #define UART_C4_BRFA_MASK (0x1FU) #define UART_C4_BRFA_SHIFT (0U) #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) #define UART_C4_M10_MASK (0x20U) #define UART_C4_M10_SHIFT (5U) #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) #define UART_C4_MAEN2_MASK (0x40U) #define UART_C4_MAEN2_SHIFT (6U) #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) #define UART_C4_MAEN1_MASK (0x80U) #define UART_C4_MAEN1_SHIFT (7U) #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) /*! @name C5 - UART Control Register 5 */ #define UART_C5_LBKDDMAS_MASK (0x8U) #define UART_C5_LBKDDMAS_SHIFT (3U) #define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK) #define UART_C5_ILDMAS_MASK (0x10U) #define UART_C5_ILDMAS_SHIFT (4U) #define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK) #define UART_C5_RDMAS_MASK (0x20U) #define UART_C5_RDMAS_SHIFT (5U) #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) #define UART_C5_TCDMAS_MASK (0x40U) #define UART_C5_TCDMAS_SHIFT (6U) #define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK) #define UART_C5_TDMAS_MASK (0x80U) #define UART_C5_TDMAS_SHIFT (7U) #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) /*! @name ED - UART Extended Data Register */ #define UART_ED_PARITYE_MASK (0x40U) #define UART_ED_PARITYE_SHIFT (6U) #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) #define UART_ED_NOISY_MASK (0x80U) #define UART_ED_NOISY_SHIFT (7U) #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) /*! @name MODEM - UART Modem Register */ #define UART_MODEM_TXCTSE_MASK (0x1U) #define UART_MODEM_TXCTSE_SHIFT (0U) #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) #define UART_MODEM_TXRTSE_MASK (0x2U) #define UART_MODEM_TXRTSE_SHIFT (1U) #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) #define UART_MODEM_TXRTSPOL_MASK (0x4U) #define UART_MODEM_TXRTSPOL_SHIFT (2U) #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) #define UART_MODEM_RXRTSE_MASK (0x8U) #define UART_MODEM_RXRTSE_SHIFT (3U) #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) /*! @name IR - UART Infrared Register */ #define UART_IR_TNP_MASK (0x3U) #define UART_IR_TNP_SHIFT (0U) #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) #define UART_IR_IREN_MASK (0x4U) #define UART_IR_IREN_SHIFT (2U) #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) /*! @name PFIFO - UART FIFO Parameters */ #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) #define UART_PFIFO_RXFE_MASK (0x8U) #define UART_PFIFO_RXFE_SHIFT (3U) #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) #define UART_PFIFO_TXFE_MASK (0x80U) #define UART_PFIFO_TXFE_SHIFT (7U) #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) /*! @name CFIFO - UART FIFO Control Register */ #define UART_CFIFO_RXUFE_MASK (0x1U) #define UART_CFIFO_RXUFE_SHIFT (0U) #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) #define UART_CFIFO_TXOFE_MASK (0x2U) #define UART_CFIFO_TXOFE_SHIFT (1U) #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) #define UART_CFIFO_RXOFE_MASK (0x4U) #define UART_CFIFO_RXOFE_SHIFT (2U) #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) #define UART_CFIFO_RXFLUSH_MASK (0x40U) #define UART_CFIFO_RXFLUSH_SHIFT (6U) #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) #define UART_CFIFO_TXFLUSH_MASK (0x80U) #define UART_CFIFO_TXFLUSH_SHIFT (7U) #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) /*! @name SFIFO - UART FIFO Status Register */ #define UART_SFIFO_RXUF_MASK (0x1U) #define UART_SFIFO_RXUF_SHIFT (0U) #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) #define UART_SFIFO_TXOF_MASK (0x2U) #define UART_SFIFO_TXOF_SHIFT (1U) #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) #define UART_SFIFO_RXOF_MASK (0x4U) #define UART_SFIFO_RXOF_SHIFT (2U) #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) #define UART_SFIFO_RXEMPT_MASK (0x40U) #define UART_SFIFO_RXEMPT_SHIFT (6U) #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) #define UART_SFIFO_TXEMPT_MASK (0x80U) #define UART_SFIFO_TXEMPT_SHIFT (7U) #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) /*! @name TWFIFO - UART FIFO Transmit Watermark */ #define UART_TWFIFO_TXWATER_MASK (0xFFU) #define UART_TWFIFO_TXWATER_SHIFT (0U) #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) /*! @name TCFIFO - UART FIFO Transmit Count */ #define UART_TCFIFO_TXCOUNT_MASK (0xFFU) #define UART_TCFIFO_TXCOUNT_SHIFT (0U) #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) /*! @name RWFIFO - UART FIFO Receive Watermark */ #define UART_RWFIFO_RXWATER_MASK (0xFFU) #define UART_RWFIFO_RXWATER_SHIFT (0U) #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) /*! @name RCFIFO - UART FIFO Receive Count */ #define UART_RCFIFO_RXCOUNT_MASK (0xFFU) #define UART_RCFIFO_RXCOUNT_SHIFT (0U) #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) /*! @name C7816 - UART 7816 Control Register */ #define UART_C7816_ISO_7816E_MASK (0x1U) #define UART_C7816_ISO_7816E_SHIFT (0U) #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) #define UART_C7816_TTYPE_MASK (0x2U) #define UART_C7816_TTYPE_SHIFT (1U) #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) #define UART_C7816_INIT_MASK (0x4U) #define UART_C7816_INIT_SHIFT (2U) #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) #define UART_C7816_ANACK_MASK (0x8U) #define UART_C7816_ANACK_SHIFT (3U) #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) #define UART_C7816_ONACK_MASK (0x10U) #define UART_C7816_ONACK_SHIFT (4U) #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) /*! @name IE7816 - UART 7816 Interrupt Enable Register */ #define UART_IE7816_RXTE_MASK (0x1U) #define UART_IE7816_RXTE_SHIFT (0U) #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) #define UART_IE7816_TXTE_MASK (0x2U) #define UART_IE7816_TXTE_SHIFT (1U) #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) #define UART_IE7816_GTVE_MASK (0x4U) #define UART_IE7816_GTVE_SHIFT (2U) #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) #define UART_IE7816_INITDE_MASK (0x10U) #define UART_IE7816_INITDE_SHIFT (4U) #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) #define UART_IE7816_BWTE_MASK (0x20U) #define UART_IE7816_BWTE_SHIFT (5U) #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) #define UART_IE7816_CWTE_MASK (0x40U) #define UART_IE7816_CWTE_SHIFT (6U) #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) #define UART_IE7816_WTE_MASK (0x80U) #define UART_IE7816_WTE_SHIFT (7U) #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) /*! @name IS7816 - UART 7816 Interrupt Status Register */ #define UART_IS7816_RXT_MASK (0x1U) #define UART_IS7816_RXT_SHIFT (0U) #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) #define UART_IS7816_TXT_MASK (0x2U) #define UART_IS7816_TXT_SHIFT (1U) #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) #define UART_IS7816_GTV_MASK (0x4U) #define UART_IS7816_GTV_SHIFT (2U) #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) #define UART_IS7816_INITD_MASK (0x10U) #define UART_IS7816_INITD_SHIFT (4U) #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) #define UART_IS7816_BWT_MASK (0x20U) #define UART_IS7816_BWT_SHIFT (5U) #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) #define UART_IS7816_CWT_MASK (0x40U) #define UART_IS7816_CWT_SHIFT (6U) #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) #define UART_IS7816_WT_MASK (0x80U) #define UART_IS7816_WT_SHIFT (7U) #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) /*! @name WP7816T0 - UART 7816 Wait Parameter Register */ #define UART_WP7816T0_WI_MASK (0xFFU) #define UART_WP7816T0_WI_SHIFT (0U) #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) /*! @name WP7816T1 - UART 7816 Wait Parameter Register */ #define UART_WP7816T1_BWI_MASK (0xFU) #define UART_WP7816T1_BWI_SHIFT (0U) #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) #define UART_WP7816T1_CWI_MASK (0xF0U) #define UART_WP7816T1_CWI_SHIFT (4U) #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) /*! @name WN7816 - UART 7816 Wait N Register */ #define UART_WN7816_GTN_MASK (0xFFU) #define UART_WN7816_GTN_SHIFT (0U) #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) /*! @name WF7816 - UART 7816 Wait FD Register */ #define UART_WF7816_GTFD_MASK (0xFFU) #define UART_WF7816_GTFD_SHIFT (0U) #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) /*! @name ET7816 - UART 7816 Error Threshold Register */ #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) /*! @name TL7816 - UART 7816 Transmit Length Register */ #define UART_TL7816_TLEN_MASK (0xFFU) #define UART_TL7816_TLEN_SHIFT (0U) #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) /*! * @} */ /* end of group UART_Register_Masks */ /* UART - Peripheral instance base addresses */ /** Peripheral UART0 base address */ #define UART0_BASE (0x4006A000u) /** Peripheral UART0 base pointer */ #define UART0 ((UART_Type *)UART0_BASE) /** Peripheral UART1 base address */ #define UART1_BASE (0x4006B000u) /** Peripheral UART1 base pointer */ #define UART1 ((UART_Type *)UART1_BASE) /** Peripheral UART2 base address */ #define UART2_BASE (0x4006C000u) /** Peripheral UART2 base pointer */ #define UART2 ((UART_Type *)UART2_BASE) /** Peripheral UART3 base address */ #define UART3_BASE (0x4006D000u) /** Peripheral UART3 base pointer */ #define UART3 ((UART_Type *)UART3_BASE) /** Peripheral UART4 base address */ #define UART4_BASE (0x400EA000u) /** Peripheral UART4 base pointer */ #define UART4 ((UART_Type *)UART4_BASE) /** Peripheral UART5 base address */ #define UART5_BASE (0x400EB000u) /** Peripheral UART5 base pointer */ #define UART5 ((UART_Type *)UART5_BASE) /** Array initializer of UART peripheral base addresses */ #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE } /** Array initializer of UART peripheral base pointers */ #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 } /** Interrupt vectors for the UART peripheral type */ #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn } #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn } #define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group UART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ uint8_t RESERVED_0[3]; __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ uint8_t RESERVED_1[3]; __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ uint8_t RESERVED_2[3]; __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ uint8_t RESERVED_3[3]; __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ uint8_t RESERVED_4[3]; __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ uint8_t RESERVED_5[3]; __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ uint8_t RESERVED_6[3]; __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ uint8_t RESERVED_7[99]; __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ uint8_t RESERVED_8[3]; __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ uint8_t RESERVED_9[3]; __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ uint8_t RESERVED_10[3]; __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ uint8_t RESERVED_11[3]; __I uint8_t STAT; /**< Status register, offset: 0x90 */ uint8_t RESERVED_12[3]; __IO uint8_t CTL; /**< Control register, offset: 0x94 */ uint8_t RESERVED_13[3]; __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ uint8_t RESERVED_14[3]; __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ uint8_t RESERVED_15[3]; __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ uint8_t RESERVED_16[3]; __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ uint8_t RESERVED_17[3]; __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ uint8_t RESERVED_18[3]; __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ uint8_t RESERVED_19[3]; __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ uint8_t RESERVED_20[3]; __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ uint8_t RESERVED_21[11]; struct { /* offset: 0xC0, array step: 0x4 */ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_0[3]; } ENDPOINT[16]; __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ uint8_t RESERVED_22[3]; __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ uint8_t RESERVED_23[3]; __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ uint8_t RESERVED_24[3]; __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ uint8_t RESERVED_25[7]; __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ uint8_t RESERVED_26[43]; __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ uint8_t RESERVED_27[3]; __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ uint8_t RESERVED_28[23]; __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name PERID - Peripheral ID register */ #define USB_PERID_ID_MASK (0x3FU) #define USB_PERID_ID_SHIFT (0U) #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) /*! @name IDCOMP - Peripheral ID Complement register */ #define USB_IDCOMP_NID_MASK (0x3FU) #define USB_IDCOMP_NID_SHIFT (0U) #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) /*! @name REV - Peripheral Revision register */ #define USB_REV_REV_MASK (0xFFU) #define USB_REV_REV_SHIFT (0U) #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) /*! @name ADDINFO - Peripheral Additional Info register */ #define USB_ADDINFO_IEHOST_MASK (0x1U) #define USB_ADDINFO_IEHOST_SHIFT (0U) #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) #define USB_ADDINFO_IRQNUM_MASK (0xF8U) #define USB_ADDINFO_IRQNUM_SHIFT (3U) #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) /*! @name OTGISTAT - OTG Interrupt Status register */ #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) #define USB_OTGISTAT_IDCHG_MASK (0x80U) #define USB_OTGISTAT_IDCHG_SHIFT (7U) #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) /*! @name OTGICR - OTG Interrupt Control register */ #define USB_OTGICR_AVBUSEN_MASK (0x1U) #define USB_OTGICR_AVBUSEN_SHIFT (0U) #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) #define USB_OTGICR_BSESSEN_MASK (0x4U) #define USB_OTGICR_BSESSEN_SHIFT (2U) #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) #define USB_OTGICR_SESSVLDEN_MASK (0x8U) #define USB_OTGICR_SESSVLDEN_SHIFT (3U) #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) #define USB_OTGICR_LINESTATEEN_MASK (0x20U) #define USB_OTGICR_LINESTATEEN_SHIFT (5U) #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) #define USB_OTGICR_ONEMSECEN_MASK (0x40U) #define USB_OTGICR_ONEMSECEN_SHIFT (6U) #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) #define USB_OTGICR_IDEN_MASK (0x80U) #define USB_OTGICR_IDEN_SHIFT (7U) #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) /*! @name OTGSTAT - OTG Status register */ #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) #define USB_OTGSTAT_BSESSEND_MASK (0x4U) #define USB_OTGSTAT_BSESSEND_SHIFT (2U) #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) #define USB_OTGSTAT_ID_MASK (0x80U) #define USB_OTGSTAT_ID_SHIFT (7U) #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) /*! @name OTGCTL - OTG Control register */ #define USB_OTGCTL_OTGEN_MASK (0x4U) #define USB_OTGCTL_OTGEN_SHIFT (2U) #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) #define USB_OTGCTL_DMLOW_MASK (0x10U) #define USB_OTGCTL_DMLOW_SHIFT (4U) #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) #define USB_OTGCTL_DPLOW_MASK (0x20U) #define USB_OTGCTL_DPLOW_SHIFT (5U) #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) #define USB_OTGCTL_DPHIGH_MASK (0x80U) #define USB_OTGCTL_DPHIGH_SHIFT (7U) #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) /*! @name ISTAT - Interrupt Status register */ #define USB_ISTAT_USBRST_MASK (0x1U) #define USB_ISTAT_USBRST_SHIFT (0U) #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) #define USB_ISTAT_ERROR_MASK (0x2U) #define USB_ISTAT_ERROR_SHIFT (1U) #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) #define USB_ISTAT_SOFTOK_MASK (0x4U) #define USB_ISTAT_SOFTOK_SHIFT (2U) #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) #define USB_ISTAT_TOKDNE_MASK (0x8U) #define USB_ISTAT_TOKDNE_SHIFT (3U) #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) #define USB_ISTAT_SLEEP_MASK (0x10U) #define USB_ISTAT_SLEEP_SHIFT (4U) #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) #define USB_ISTAT_RESUME_MASK (0x20U) #define USB_ISTAT_RESUME_SHIFT (5U) #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) #define USB_ISTAT_ATTACH_MASK (0x40U) #define USB_ISTAT_ATTACH_SHIFT (6U) #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) #define USB_ISTAT_STALL_MASK (0x80U) #define USB_ISTAT_STALL_SHIFT (7U) #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) /*! @name INTEN - Interrupt Enable register */ #define USB_INTEN_USBRSTEN_MASK (0x1U) #define USB_INTEN_USBRSTEN_SHIFT (0U) #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) #define USB_INTEN_ERROREN_MASK (0x2U) #define USB_INTEN_ERROREN_SHIFT (1U) #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) #define USB_INTEN_SOFTOKEN_MASK (0x4U) #define USB_INTEN_SOFTOKEN_SHIFT (2U) #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) #define USB_INTEN_TOKDNEEN_MASK (0x8U) #define USB_INTEN_TOKDNEEN_SHIFT (3U) #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) #define USB_INTEN_SLEEPEN_MASK (0x10U) #define USB_INTEN_SLEEPEN_SHIFT (4U) #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) #define USB_INTEN_RESUMEEN_MASK (0x20U) #define USB_INTEN_RESUMEEN_SHIFT (5U) #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) #define USB_INTEN_ATTACHEN_MASK (0x40U) #define USB_INTEN_ATTACHEN_SHIFT (6U) #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) #define USB_INTEN_STALLEN_MASK (0x80U) #define USB_INTEN_STALLEN_SHIFT (7U) #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) /*! @name ERRSTAT - Error Interrupt Status register */ #define USB_ERRSTAT_PIDERR_MASK (0x1U) #define USB_ERRSTAT_PIDERR_SHIFT (0U) #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) #define USB_ERRSTAT_CRC16_MASK (0x4U) #define USB_ERRSTAT_CRC16_SHIFT (2U) #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) #define USB_ERRSTAT_DFN8_MASK (0x8U) #define USB_ERRSTAT_DFN8_SHIFT (3U) #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) #define USB_ERRSTAT_BTOERR_MASK (0x10U) #define USB_ERRSTAT_BTOERR_SHIFT (4U) #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) #define USB_ERRSTAT_DMAERR_MASK (0x20U) #define USB_ERRSTAT_DMAERR_SHIFT (5U) #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) #define USB_ERRSTAT_BTSERR_MASK (0x80U) #define USB_ERRSTAT_BTSERR_SHIFT (7U) #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) /*! @name ERREN - Error Interrupt Enable register */ #define USB_ERREN_PIDERREN_MASK (0x1U) #define USB_ERREN_PIDERREN_SHIFT (0U) #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) #define USB_ERREN_CRC5EOFEN_MASK (0x2U) #define USB_ERREN_CRC5EOFEN_SHIFT (1U) #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) #define USB_ERREN_CRC16EN_MASK (0x4U) #define USB_ERREN_CRC16EN_SHIFT (2U) #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) #define USB_ERREN_DFN8EN_MASK (0x8U) #define USB_ERREN_DFN8EN_SHIFT (3U) #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) #define USB_ERREN_BTOERREN_MASK (0x10U) #define USB_ERREN_BTOERREN_SHIFT (4U) #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) #define USB_ERREN_DMAERREN_MASK (0x20U) #define USB_ERREN_DMAERREN_SHIFT (5U) #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) #define USB_ERREN_BTSERREN_MASK (0x80U) #define USB_ERREN_BTSERREN_SHIFT (7U) #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) /*! @name STAT - Status register */ #define USB_STAT_ODD_MASK (0x4U) #define USB_STAT_ODD_SHIFT (2U) #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) #define USB_STAT_TX_MASK (0x8U) #define USB_STAT_TX_SHIFT (3U) #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) #define USB_STAT_ENDP_MASK (0xF0U) #define USB_STAT_ENDP_SHIFT (4U) #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) /*! @name CTL - Control register */ #define USB_CTL_USBENSOFEN_MASK (0x1U) #define USB_CTL_USBENSOFEN_SHIFT (0U) #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) #define USB_CTL_ODDRST_MASK (0x2U) #define USB_CTL_ODDRST_SHIFT (1U) #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) #define USB_CTL_RESUME_MASK (0x4U) #define USB_CTL_RESUME_SHIFT (2U) #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) #define USB_CTL_HOSTMODEEN_MASK (0x8U) #define USB_CTL_HOSTMODEEN_SHIFT (3U) #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) #define USB_CTL_RESET_MASK (0x10U) #define USB_CTL_RESET_SHIFT (4U) #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) #define USB_CTL_SE0_MASK (0x40U) #define USB_CTL_SE0_SHIFT (6U) #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) #define USB_CTL_JSTATE_MASK (0x80U) #define USB_CTL_JSTATE_SHIFT (7U) #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) /*! @name ADDR - Address register */ #define USB_ADDR_ADDR_MASK (0x7FU) #define USB_ADDR_ADDR_SHIFT (0U) #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) #define USB_ADDR_LSEN_MASK (0x80U) #define USB_ADDR_LSEN_SHIFT (7U) #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) /*! @name BDTPAGE1 - BDT Page register 1 */ #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) #define USB_BDTPAGE1_BDTBA_SHIFT (1U) #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) /*! @name FRMNUML - Frame Number register Low */ #define USB_FRMNUML_FRM_MASK (0xFFU) #define USB_FRMNUML_FRM_SHIFT (0U) #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) /*! @name FRMNUMH - Frame Number register High */ #define USB_FRMNUMH_FRM_MASK (0x7U) #define USB_FRMNUMH_FRM_SHIFT (0U) #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) /*! @name TOKEN - Token register */ #define USB_TOKEN_TOKENENDPT_MASK (0xFU) #define USB_TOKEN_TOKENENDPT_SHIFT (0U) #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) #define USB_TOKEN_TOKENPID_MASK (0xF0U) #define USB_TOKEN_TOKENPID_SHIFT (4U) #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) /*! @name SOFTHLD - SOF Threshold register */ #define USB_SOFTHLD_CNT_MASK (0xFFU) #define USB_SOFTHLD_CNT_SHIFT (0U) #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) /*! @name BDTPAGE2 - BDT Page Register 2 */ #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) #define USB_BDTPAGE2_BDTBA_SHIFT (0U) #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) /*! @name BDTPAGE3 - BDT Page Register 3 */ #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) #define USB_BDTPAGE3_BDTBA_SHIFT (0U) #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) /*! @name ENDPT - Endpoint Control register */ #define USB_ENDPT_EPHSHK_MASK (0x1U) #define USB_ENDPT_EPHSHK_SHIFT (0U) #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) #define USB_ENDPT_EPSTALL_MASK (0x2U) #define USB_ENDPT_EPSTALL_SHIFT (1U) #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) #define USB_ENDPT_EPTXEN_MASK (0x4U) #define USB_ENDPT_EPTXEN_SHIFT (2U) #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) #define USB_ENDPT_EPRXEN_MASK (0x8U) #define USB_ENDPT_EPRXEN_SHIFT (3U) #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) #define USB_ENDPT_EPCTLDIS_MASK (0x10U) #define USB_ENDPT_EPCTLDIS_SHIFT (4U) #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) #define USB_ENDPT_RETRYDIS_MASK (0x40U) #define USB_ENDPT_RETRYDIS_SHIFT (6U) #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) /* The count of USB_ENDPT */ #define USB_ENDPT_COUNT (16U) /*! @name USBCTRL - USB Control register */ #define USB_USBCTRL_PDE_MASK (0x40U) #define USB_USBCTRL_PDE_SHIFT (6U) #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) #define USB_USBCTRL_SUSP_MASK (0x80U) #define USB_USBCTRL_SUSP_SHIFT (7U) #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) /*! @name OBSERVE - USB OTG Observe register */ #define USB_OBSERVE_DMPD_MASK (0x10U) #define USB_OBSERVE_DMPD_SHIFT (4U) #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) #define USB_OBSERVE_DPPD_MASK (0x40U) #define USB_OBSERVE_DPPD_SHIFT (6U) #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) #define USB_OBSERVE_DPPU_MASK (0x80U) #define USB_OBSERVE_DPPU_SHIFT (7U) #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) /*! @name CONTROL - USB OTG Control register */ #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) /*! @name USBTRC0 - USB Transceiver Control register 0 */ #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) #define USB_USBTRC0_SYNC_DET_MASK (0x2U) #define USB_USBTRC0_SYNC_DET_SHIFT (1U) #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) #define USB_USBTRC0_USBRESMEN_MASK (0x20U) #define USB_USBTRC0_USBRESMEN_SHIFT (5U) #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) #define USB_USBTRC0_USBRESET_MASK (0x80U) #define USB_USBTRC0_USBRESET_SHIFT (7U) #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) /*! @name USBFRMADJUST - Frame Adjust Register */ #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) #define USB_USBFRMADJUST_ADJ_SHIFT (0U) #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral USB0 base address */ #define USB0_BASE (0x40072000u) /** Peripheral USB0 base pointer */ #define USB0 ((USB_Type *)USB0_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USB0_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USB0 } /** Interrupt vectors for the USB peripheral type */ #define USB_IRQS { USB0_IRQn } /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBDCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer * @{ */ /** USBDCD - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ __I uint32_t STATUS; /**< Status register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ union { /* offset: 0x18 */ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ }; } USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Register_Masks USBDCD Register Masks * @{ */ /*! @name CONTROL - Control register */ #define USBDCD_CONTROL_IACK_MASK (0x1U) #define USBDCD_CONTROL_IACK_SHIFT (0U) #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) #define USBDCD_CONTROL_IF_MASK (0x100U) #define USBDCD_CONTROL_IF_SHIFT (8U) #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) #define USBDCD_CONTROL_IE_MASK (0x10000U) #define USBDCD_CONTROL_IE_SHIFT (16U) #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) #define USBDCD_CONTROL_BC12_MASK (0x20000U) #define USBDCD_CONTROL_BC12_SHIFT (17U) #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) #define USBDCD_CONTROL_START_MASK (0x1000000U) #define USBDCD_CONTROL_START_SHIFT (24U) #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) #define USBDCD_CONTROL_SR_MASK (0x2000000U) #define USBDCD_CONTROL_SR_SHIFT (25U) #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) /*! @name CLOCK - Clock register */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) /*! @name STATUS - Status register */ #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) #define USBDCD_STATUS_ERR_MASK (0x100000U) #define USBDCD_STATUS_ERR_SHIFT (20U) #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) #define USBDCD_STATUS_TO_MASK (0x200000U) #define USBDCD_STATUS_TO_SHIFT (21U) #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBDCD_STATUS_ACTIVE_SHIFT (22U) #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) /*! @name TIMER0 - TIMER0 register */ #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) /*! @name TIMER1 - TIMER1 register */ #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) /*! @name TIMER2_BC11 - TIMER2_BC11 register */ #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @name TIMER2_BC12 - TIMER2_BC12 register */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! * @} */ /* end of group USBDCD_Register_Masks */ /* USBDCD - Peripheral instance base addresses */ /** Peripheral USBDCD base address */ #define USBDCD_BASE (0x40035000u) /** Peripheral USBDCD base pointer */ #define USBDCD ((USBDCD_Type *)USBDCD_BASE) /** Array initializer of USBDCD peripheral base addresses */ #define USBDCD_BASE_ADDRS { USBDCD_BASE } /** Array initializer of USBDCD peripheral base pointers */ #define USBDCD_BASE_PTRS { USBDCD } /** Interrupt vectors for the USBDCD peripheral type */ #define USBDCD_IRQS { USBDCD_IRQn } /*! * @} */ /* end of group USBDCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VREF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer * @{ */ /** VREF - Register Layout Typedef */ typedef struct { __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ } VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Masks VREF Register Masks * @{ */ /*! @name TRM - VREF Trim Register */ #define VREF_TRM_TRIM_MASK (0x3FU) #define VREF_TRM_TRIM_SHIFT (0U) #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) #define VREF_TRM_CHOPEN_MASK (0x40U) #define VREF_TRM_CHOPEN_SHIFT (6U) #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) /*! @name SC - VREF Status and Control Register */ #define VREF_SC_MODE_LV_MASK (0x3U) #define VREF_SC_MODE_LV_SHIFT (0U) #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) #define VREF_SC_VREFST_MASK (0x4U) #define VREF_SC_VREFST_SHIFT (2U) #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) #define VREF_SC_ICOMPEN_MASK (0x20U) #define VREF_SC_ICOMPEN_SHIFT (5U) #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) #define VREF_SC_REGEN_MASK (0x40U) #define VREF_SC_REGEN_SHIFT (6U) #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) #define VREF_SC_VREFEN_MASK (0x80U) #define VREF_SC_VREFEN_SHIFT (7U) #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) /*! * @} */ /* end of group VREF_Register_Masks */ /* VREF - Peripheral instance base addresses */ /** Peripheral VREF base address */ #define VREF_BASE (0x40074000u) /** Peripheral VREF base pointer */ #define VREF ((VREF_Type *)VREF_BASE) /** Array initializer of VREF peripheral base addresses */ #define VREF_BASE_ADDRS { VREF_BASE } /** Array initializer of VREF peripheral base pointers */ #define VREF_BASE_PTRS { VREF } /*! * @} */ /* end of group VREF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name STCTRLH - Watchdog Status and Control Register High */ #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) #define WDOG_STCTRLH_WINEN_MASK (0x8U) #define WDOG_STCTRLH_WINEN_SHIFT (3U) #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) #define WDOG_STCTRLH_DBGEN_MASK (0x20U) #define WDOG_STCTRLH_DBGEN_SHIFT (5U) #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) #define WDOG_STCTRLH_STOPEN_MASK (0x40U) #define WDOG_STCTRLH_STOPEN_SHIFT (6U) #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) #define WDOG_STCTRLH_WAITEN_MASK (0x80U) #define WDOG_STCTRLH_WAITEN_SHIFT (7U) #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) /*! @name STCTRLL - Watchdog Status and Control Register Low */ #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) #define WDOG_STCTRLL_INTFLG_SHIFT (15U) #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) /*! @name TOVALH - Watchdog Time-out Value Register High */ #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) /*! @name TOVALL - Watchdog Time-out Value Register Low */ #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) /*! @name WINH - Watchdog Window Register High */ #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) #define WDOG_WINH_WINHIGH_SHIFT (0U) #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) /*! @name WINL - Watchdog Window Register Low */ #define WDOG_WINL_WINLOW_MASK (0xFFFFU) #define WDOG_WINL_WINLOW_SHIFT (0U) #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) /*! @name REFRESH - Watchdog Refresh register */ #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) /*! @name UNLOCK - Watchdog Unlock register */ #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) /*! @name TMROUTH - Watchdog Timer Output Register High */ #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) /*! @name TMROUTL - Watchdog Timer Output Register Low */ #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) /*! @name RSTCNT - Watchdog Reset Count register */ #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) /*! @name PRESC - Watchdog Prescaler register */ #define WDOG_PRESC_PRESCVAL_MASK (0x700U) #define WDOG_PRESC_PRESCVAL_SHIFT (8U) #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG base address */ #define WDOG_BASE (0x40052000u) /** Peripheral WDOG base pointer */ #define WDOG ((WDOG_Type *)WDOG_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { WDOG_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { WDOG } /** Interrupt vectors for the WDOG peripheral type */ #define WDOG_IRQS { WDOG_EWM_IRQn } /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma pop #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base) #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base) #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) #define MCM_ISR_REG(base) MCM_ISCR_REG(base) #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT #define DSPI0 SPI0 #define DSPI1 SPI1 #define DSPI2 SPI2 #define FLEXCAN0 CAN0 #define PTA_BASE GPIOA_BASE #define PTA GPIOA #define PTB_BASE GPIOB_BASE #define PTB GPIOB #define PTC_BASE GPIOC_BASE #define PTC GPIOC #define PTD_BASE GPIOD_BASE #define PTD GPIOD #define PTE_BASE GPIOE_BASE #define PTE GPIOE #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x) #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x) #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x) #define Watchdog_IRQn WDOG_EWM_IRQn #define Watchdog_IRQHandler WDOG_EWM_IRQHandler #define LPTimer_IRQn LPTMR0_IRQn #define LPTimer_IRQHandler LPTMR0_IRQHandler #define LLW_IRQn LLWU_IRQn #define LLW_IRQHandler LLWU_IRQHandler #define DMAMUX0 DMAMUX #define WDOG0 WDOG #define MCM0 MCM #define RTC0 RTC /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* _MK64F12_H_ */ ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/MK64F12_features.h ================================================ /* ** ################################################################### ** Version: rev. 2.15, 2016-03-21 ** Build: b170918 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** - rev. 2.4 (2014-01-30) ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. ** - rev. 2.5 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** - rev. 2.6 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** Module access macro module_BASES replaced by module_BASE_PTRS. ** - rev. 2.7 (2014-08-28) ** Update of system files - default clock configuration changed. ** Update of startup files - possibility to override DefaultISR added. ** - rev. 2.8 (2014-10-14) ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. ** - rev. 2.9 (2015-01-21) ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances ** - rev. 2.10 (2015-02-19) ** Renamed interrupt vector LLW to LLWU. ** - rev. 2.11 (2015-05-19) ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. ** Added features for PDB and PORT. ** - rev. 2.12 (2015-05-25) ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS ** - rev. 2.13 (2015-05-27) ** Several USB features added. ** - rev. 2.14 (2015-06-08) ** FTM features BUS_CLOCK and FAST_CLOCK removed. ** - rev. 2.15 (2016-03-21) ** Added MK64FN1M0CAJ12 part. ** ** ################################################################### */ #ifndef _MK64F12_FEATURES_H_ #define _MK64F12_FEATURES_H_ /* SOC module features */ #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) /* @brief ACMP availability on the SoC. */ #define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC16 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC16_COUNT (2) /* @brief ADC12 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC12_COUNT (0) /* @brief AFE availability on the SoC. */ #define FSL_FEATURE_SOC_AFE_COUNT (0) /* @brief AIPS availability on the SoC. */ #define FSL_FEATURE_SOC_AIPS_COUNT (2) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (0) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief ASMC availability on the SoC. */ #define FSL_FEATURE_SOC_ASMC_COUNT (0) /* @brief CADC availability on the SoC. */ #define FSL_FEATURE_SOC_CADC_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) /* @brief MMCAU availability on the SoC. */ #define FSL_FEATURE_SOC_MMCAU_COUNT (1) /* @brief CMP availability on the SoC. */ #define FSL_FEATURE_SOC_CMP_COUNT (3) /* @brief CMT availability on the SoC. */ #define FSL_FEATURE_SOC_CMT_COUNT (1) /* @brief CNC availability on the SoC. */ #define FSL_FEATURE_SOC_CNC_COUNT (0) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief DAC availability on the SoC. */ #define FSL_FEATURE_SOC_DAC_COUNT (2) /* @brief DAC32 availability on the SoC. */ #define FSL_FEATURE_SOC_DAC32_COUNT (0) /* @brief DCDC availability on the SoC. */ #define FSL_FEATURE_SOC_DCDC_COUNT (0) /* @brief DDR availability on the SoC. */ #define FSL_FEATURE_SOC_DDR_COUNT (0) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) /* @brief DRY availability on the SoC. */ #define FSL_FEATURE_SOC_DRY_COUNT (0) /* @brief DSPI availability on the SoC. */ #define FSL_FEATURE_SOC_DSPI_COUNT (3) /* @brief EMVSIM availability on the SoC. */ #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) /* @brief ENC availability on the SoC. */ #define FSL_FEATURE_SOC_ENC_COUNT (0) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FB availability on the SoC. */ #define FSL_FEATURE_SOC_FB_COUNT (1) /* @brief FGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_FGPIO_COUNT (0) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) /* @brief FMC availability on the SoC. */ #define FSL_FEATURE_SOC_FMC_COUNT (1) /* @brief FSKDT availability on the SoC. */ #define FSL_FEATURE_SOC_FSKDT_COUNT (0) /* @brief FTFA availability on the SoC. */ #define FSL_FEATURE_SOC_FTFA_COUNT (0) /* @brief FTFE availability on the SoC. */ #define FSL_FEATURE_SOC_FTFE_COUNT (1) /* @brief FTFL availability on the SoC. */ #define FSL_FEATURE_SOC_FTFL_COUNT (0) /* @brief FTM availability on the SoC. */ #define FSL_FEATURE_SOC_FTM_COUNT (4) /* @brief FTMRA availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRA_COUNT (0) /* @brief FTMRE availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRE_COUNT (0) /* @brief FTMRH availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRH_COUNT (0) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (5) /* @brief HSADC availability on the SoC. */ #define FSL_FEATURE_SOC_HSADC_COUNT (0) /* @brief I2C availability on the SoC. */ #define FSL_FEATURE_SOC_I2C_COUNT (3) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (1) /* @brief ICS availability on the SoC. */ #define FSL_FEATURE_SOC_ICS_COUNT (0) /* @brief INTMUX availability on the SoC. */ #define FSL_FEATURE_SOC_INTMUX_COUNT (0) /* @brief IRQ availability on the SoC. */ #define FSL_FEATURE_SOC_IRQ_COUNT (0) /* @brief KBI availability on the SoC. */ #define FSL_FEATURE_SOC_KBI_COUNT (0) /* @brief SLCD availability on the SoC. */ #define FSL_FEATURE_SOC_SLCD_COUNT (0) /* @brief LCDC availability on the SoC. */ #define FSL_FEATURE_SOC_LCDC_COUNT (0) /* @brief LDO availability on the SoC. */ #define FSL_FEATURE_SOC_LDO_COUNT (0) /* @brief LLWU availability on the SoC. */ #define FSL_FEATURE_SOC_LLWU_COUNT (1) /* @brief LMEM availability on the SoC. */ #define FSL_FEATURE_SOC_LMEM_COUNT (0) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (0) /* @brief LPIT availability on the SoC. */ #define FSL_FEATURE_SOC_LPIT_COUNT (0) /* @brief LPSCI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSCI_COUNT (0) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (0) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (1) /* @brief LPTPM availability on the SoC. */ #define FSL_FEATURE_SOC_LPTPM_COUNT (0) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (0) /* @brief LTC availability on the SoC. */ #define FSL_FEATURE_SOC_LTC_COUNT (0) /* @brief MC availability on the SoC. */ #define FSL_FEATURE_SOC_MC_COUNT (0) /* @brief MCG availability on the SoC. */ #define FSL_FEATURE_SOC_MCG_COUNT (1) /* @brief MCGLITE availability on the SoC. */ #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) /* @brief MMAU availability on the SoC. */ #define FSL_FEATURE_SOC_MMAU_COUNT (0) /* @brief MMDVSQ availability on the SoC. */ #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) /* @brief SYSMPU availability on the SoC. */ #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) /* @brief MSCAN availability on the SoC. */ #define FSL_FEATURE_SOC_MSCAN_COUNT (0) /* @brief MSCM availability on the SoC. */ #define FSL_FEATURE_SOC_MSCM_COUNT (0) /* @brief MTB availability on the SoC. */ #define FSL_FEATURE_SOC_MTB_COUNT (0) /* @brief MTBDWT availability on the SoC. */ #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (0) /* @brief NFC availability on the SoC. */ #define FSL_FEATURE_SOC_NFC_COUNT (0) /* @brief OPAMP availability on the SoC. */ #define FSL_FEATURE_SOC_OPAMP_COUNT (0) /* @brief OSC availability on the SoC. */ #define FSL_FEATURE_SOC_OSC_COUNT (1) /* @brief OSC32 availability on the SoC. */ #define FSL_FEATURE_SOC_OSC32_COUNT (0) /* @brief OTFAD availability on the SoC. */ #define FSL_FEATURE_SOC_OTFAD_COUNT (0) /* @brief PDB availability on the SoC. */ #define FSL_FEATURE_SOC_PDB_COUNT (1) /* @brief PCC availability on the SoC. */ #define FSL_FEATURE_SOC_PCC_COUNT (0) /* @brief PGA availability on the SoC. */ #define FSL_FEATURE_SOC_PGA_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (5) /* @brief PWM availability on the SoC. */ #define FSL_FEATURE_SOC_PWM_COUNT (0) /* @brief PWT availability on the SoC. */ #define FSL_FEATURE_SOC_PWT_COUNT (0) /* @brief QuadSPI availability on the SoC. */ #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) /* @brief RCM availability on the SoC. */ #define FSL_FEATURE_SOC_RCM_COUNT (1) /* @brief RFSYS availability on the SoC. */ #define FSL_FEATURE_SOC_RFSYS_COUNT (1) /* @brief RFVBAT availability on the SoC. */ #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) /* @brief RNG availability on the SoC. */ #define FSL_FEATURE_SOC_RNG_COUNT (1) /* @brief RNGB availability on the SoC. */ #define FSL_FEATURE_SOC_RNGB_COUNT (0) /* @brief ROM availability on the SoC. */ #define FSL_FEATURE_SOC_ROM_COUNT (0) /* @brief RSIM availability on the SoC. */ #define FSL_FEATURE_SOC_RSIM_COUNT (0) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (0) /* @brief SCI availability on the SoC. */ #define FSL_FEATURE_SOC_SCI_COUNT (0) /* @brief SDHC availability on the SoC. */ #define FSL_FEATURE_SOC_SDHC_COUNT (1) /* @brief SDRAM availability on the SoC. */ #define FSL_FEATURE_SOC_SDRAM_COUNT (0) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (1) /* @brief SPI availability on the SoC. */ #define FSL_FEATURE_SOC_SPI_COUNT (0) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (0) /* @brief TPM availability on the SoC. */ #define FSL_FEATURE_SOC_TPM_COUNT (0) /* @brief TRGMUX availability on the SoC. */ #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) /* @brief TRIAMP availability on the SoC. */ #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (0) /* @brief TSI availability on the SoC. */ #define FSL_FEATURE_SOC_TSI_COUNT (0) /* @brief TSTMR availability on the SoC. */ #define FSL_FEATURE_SOC_TSTMR_COUNT (0) /* @brief UART availability on the SoC. */ #define FSL_FEATURE_SOC_UART_COUNT (6) /* @brief USB availability on the SoC. */ #define FSL_FEATURE_SOC_USB_COUNT (1) /* @brief USBDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBDCD_COUNT (1) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (0) /* @brief USBHSDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (0) /* @brief VREF availability on the SoC. */ #define FSL_FEATURE_SOC_VREF_COUNT (1) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (1) /* @brief XBAR availability on the SoC. */ #define FSL_FEATURE_SOC_XBAR_COUNT (0) /* @brief XBARA availability on the SoC. */ #define FSL_FEATURE_SOC_XBARA_COUNT (0) /* @brief XBARB availability on the SoC. */ #define FSL_FEATURE_SOC_XBARB_COUNT (0) /* @brief XCVR availability on the SoC. */ #define FSL_FEATURE_SOC_XCVR_COUNT (0) /* @brief XRDC availability on the SoC. */ #define FSL_FEATURE_SOC_XRDC_COUNT (0) /* @brief ZLL availability on the SoC. */ #define FSL_FEATURE_SOC_ZLL_COUNT (0) #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) /* @brief ACMP availability on the SoC. */ #define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC16 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC16_COUNT (2) /* @brief ADC12 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC12_COUNT (0) /* @brief AFE availability on the SoC. */ #define FSL_FEATURE_SOC_AFE_COUNT (0) /* @brief AIPS availability on the SoC. */ #define FSL_FEATURE_SOC_AIPS_COUNT (2) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (0) /* @brief AXBS availability on the SoC. */ #define FSL_FEATURE_SOC_AXBS_COUNT (1) /* @brief ASMC availability on the SoC. */ #define FSL_FEATURE_SOC_ASMC_COUNT (0) /* @brief CADC availability on the SoC. */ #define FSL_FEATURE_SOC_CADC_COUNT (0) /* @brief FLEXCAN availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) /* @brief MMCAU availability on the SoC. */ #define FSL_FEATURE_SOC_MMCAU_COUNT (1) /* @brief CMP availability on the SoC. */ #define FSL_FEATURE_SOC_CMP_COUNT (3) /* @brief CMT availability on the SoC. */ #define FSL_FEATURE_SOC_CMT_COUNT (1) /* @brief CNC availability on the SoC. */ #define FSL_FEATURE_SOC_CNC_COUNT (0) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief DAC availability on the SoC. */ #define FSL_FEATURE_SOC_DAC_COUNT (1) /* @brief DAC32 availability on the SoC. */ #define FSL_FEATURE_SOC_DAC32_COUNT (0) /* @brief DCDC availability on the SoC. */ #define FSL_FEATURE_SOC_DCDC_COUNT (0) /* @brief DDR availability on the SoC. */ #define FSL_FEATURE_SOC_DDR_COUNT (0) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (0) /* @brief EDMA availability on the SoC. */ #define FSL_FEATURE_SOC_EDMA_COUNT (1) /* @brief DMAMUX availability on the SoC. */ #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) /* @brief DRY availability on the SoC. */ #define FSL_FEATURE_SOC_DRY_COUNT (0) /* @brief DSPI availability on the SoC. */ #define FSL_FEATURE_SOC_DSPI_COUNT (3) /* @brief EMVSIM availability on the SoC. */ #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) /* @brief ENC availability on the SoC. */ #define FSL_FEATURE_SOC_ENC_COUNT (0) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_ENET_COUNT (1) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FB availability on the SoC. */ #define FSL_FEATURE_SOC_FB_COUNT (1) /* @brief FGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_FGPIO_COUNT (0) /* @brief FLEXIO availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) /* @brief FMC availability on the SoC. */ #define FSL_FEATURE_SOC_FMC_COUNT (1) /* @brief FSKDT availability on the SoC. */ #define FSL_FEATURE_SOC_FSKDT_COUNT (0) /* @brief FTFA availability on the SoC. */ #define FSL_FEATURE_SOC_FTFA_COUNT (0) /* @brief FTFE availability on the SoC. */ #define FSL_FEATURE_SOC_FTFE_COUNT (1) /* @brief FTFL availability on the SoC. */ #define FSL_FEATURE_SOC_FTFL_COUNT (0) /* @brief FTM availability on the SoC. */ #define FSL_FEATURE_SOC_FTM_COUNT (4) /* @brief FTMRA availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRA_COUNT (0) /* @brief FTMRE availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRE_COUNT (0) /* @brief FTMRH availability on the SoC. */ #define FSL_FEATURE_SOC_FTMRH_COUNT (0) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (5) /* @brief HSADC availability on the SoC. */ #define FSL_FEATURE_SOC_HSADC_COUNT (0) /* @brief I2C availability on the SoC. */ #define FSL_FEATURE_SOC_I2C_COUNT (3) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (1) /* @brief ICS availability on the SoC. */ #define FSL_FEATURE_SOC_ICS_COUNT (0) /* @brief INTMUX availability on the SoC. */ #define FSL_FEATURE_SOC_INTMUX_COUNT (0) /* @brief IRQ availability on the SoC. */ #define FSL_FEATURE_SOC_IRQ_COUNT (0) /* @brief KBI availability on the SoC. */ #define FSL_FEATURE_SOC_KBI_COUNT (0) /* @brief SLCD availability on the SoC. */ #define FSL_FEATURE_SOC_SLCD_COUNT (0) /* @brief LCDC availability on the SoC. */ #define FSL_FEATURE_SOC_LCDC_COUNT (0) /* @brief LDO availability on the SoC. */ #define FSL_FEATURE_SOC_LDO_COUNT (0) /* @brief LLWU availability on the SoC. */ #define FSL_FEATURE_SOC_LLWU_COUNT (1) /* @brief LMEM availability on the SoC. */ #define FSL_FEATURE_SOC_LMEM_COUNT (0) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (0) /* @brief LPIT availability on the SoC. */ #define FSL_FEATURE_SOC_LPIT_COUNT (0) /* @brief LPSCI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSCI_COUNT (0) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (0) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (1) /* @brief LPTPM availability on the SoC. */ #define FSL_FEATURE_SOC_LPTPM_COUNT (0) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (0) /* @brief LTC availability on the SoC. */ #define FSL_FEATURE_SOC_LTC_COUNT (0) /* @brief MC availability on the SoC. */ #define FSL_FEATURE_SOC_MC_COUNT (0) /* @brief MCG availability on the SoC. */ #define FSL_FEATURE_SOC_MCG_COUNT (1) /* @brief MCGLITE availability on the SoC. */ #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) /* @brief MMAU availability on the SoC. */ #define FSL_FEATURE_SOC_MMAU_COUNT (0) /* @brief MMDVSQ availability on the SoC. */ #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) /* @brief SYSMPU availability on the SoC. */ #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) /* @brief MSCAN availability on the SoC. */ #define FSL_FEATURE_SOC_MSCAN_COUNT (0) /* @brief MSCM availability on the SoC. */ #define FSL_FEATURE_SOC_MSCM_COUNT (0) /* @brief MTB availability on the SoC. */ #define FSL_FEATURE_SOC_MTB_COUNT (0) /* @brief MTBDWT availability on the SoC. */ #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) /* @brief MU availability on the SoC. */ #define FSL_FEATURE_SOC_MU_COUNT (0) /* @brief NFC availability on the SoC. */ #define FSL_FEATURE_SOC_NFC_COUNT (0) /* @brief OPAMP availability on the SoC. */ #define FSL_FEATURE_SOC_OPAMP_COUNT (0) /* @brief OSC availability on the SoC. */ #define FSL_FEATURE_SOC_OSC_COUNT (1) /* @brief OSC32 availability on the SoC. */ #define FSL_FEATURE_SOC_OSC32_COUNT (0) /* @brief OTFAD availability on the SoC. */ #define FSL_FEATURE_SOC_OTFAD_COUNT (0) /* @brief PDB availability on the SoC. */ #define FSL_FEATURE_SOC_PDB_COUNT (1) /* @brief PCC availability on the SoC. */ #define FSL_FEATURE_SOC_PCC_COUNT (0) /* @brief PGA availability on the SoC. */ #define FSL_FEATURE_SOC_PGA_COUNT (0) /* @brief PIT availability on the SoC. */ #define FSL_FEATURE_SOC_PIT_COUNT (1) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (5) /* @brief PWM availability on the SoC. */ #define FSL_FEATURE_SOC_PWM_COUNT (0) /* @brief PWT availability on the SoC. */ #define FSL_FEATURE_SOC_PWT_COUNT (0) /* @brief QuadSPI availability on the SoC. */ #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) /* @brief RCM availability on the SoC. */ #define FSL_FEATURE_SOC_RCM_COUNT (1) /* @brief RFSYS availability on the SoC. */ #define FSL_FEATURE_SOC_RFSYS_COUNT (1) /* @brief RFVBAT availability on the SoC. */ #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) /* @brief RNG availability on the SoC. */ #define FSL_FEATURE_SOC_RNG_COUNT (1) /* @brief RNGB availability on the SoC. */ #define FSL_FEATURE_SOC_RNGB_COUNT (0) /* @brief ROM availability on the SoC. */ #define FSL_FEATURE_SOC_ROM_COUNT (0) /* @brief RSIM availability on the SoC. */ #define FSL_FEATURE_SOC_RSIM_COUNT (0) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (0) /* @brief SCI availability on the SoC. */ #define FSL_FEATURE_SOC_SCI_COUNT (0) /* @brief SDHC availability on the SoC. */ #define FSL_FEATURE_SOC_SDHC_COUNT (1) /* @brief SDRAM availability on the SoC. */ #define FSL_FEATURE_SOC_SDRAM_COUNT (0) /* @brief SEMA42 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (1) /* @brief SPI availability on the SoC. */ #define FSL_FEATURE_SOC_SPI_COUNT (0) /* @brief TMR availability on the SoC. */ #define FSL_FEATURE_SOC_TMR_COUNT (0) /* @brief TPM availability on the SoC. */ #define FSL_FEATURE_SOC_TPM_COUNT (0) /* @brief TRGMUX availability on the SoC. */ #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) /* @brief TRIAMP availability on the SoC. */ #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) /* @brief TRNG availability on the SoC. */ #define FSL_FEATURE_SOC_TRNG_COUNT (0) /* @brief TSI availability on the SoC. */ #define FSL_FEATURE_SOC_TSI_COUNT (0) /* @brief TSTMR availability on the SoC. */ #define FSL_FEATURE_SOC_TSTMR_COUNT (0) /* @brief UART availability on the SoC. */ #define FSL_FEATURE_SOC_UART_COUNT (5) /* @brief USB availability on the SoC. */ #define FSL_FEATURE_SOC_USB_COUNT (1) /* @brief USBDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBDCD_COUNT (1) /* @brief USBHS availability on the SoC. */ #define FSL_FEATURE_SOC_USBHS_COUNT (0) /* @brief USBHSDCD availability on the SoC. */ #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (0) /* @brief VREF availability on the SoC. */ #define FSL_FEATURE_SOC_VREF_COUNT (1) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (1) /* @brief XBAR availability on the SoC. */ #define FSL_FEATURE_SOC_XBAR_COUNT (0) /* @brief XBARA availability on the SoC. */ #define FSL_FEATURE_SOC_XBARA_COUNT (0) /* @brief XBARB availability on the SoC. */ #define FSL_FEATURE_SOC_XBARB_COUNT (0) /* @brief XCVR availability on the SoC. */ #define FSL_FEATURE_SOC_XCVR_COUNT (0) /* @brief XRDC availability on the SoC. */ #define FSL_FEATURE_SOC_XRDC_COUNT (0) /* @brief ZLL availability on the SoC. */ #define FSL_FEATURE_SOC_ZLL_COUNT (0) #endif /* ADC16 module features */ /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ #define FSL_FEATURE_ADC16_HAS_PGA (0) /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ #define FSL_FEATURE_ADC16_HAS_DMA (1) /* @brief Has differential mode (bitfield SC1x[DIFF]). */ #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) /* @brief Has FIFO (bit SC4[AFDEP]). */ #define FSL_FEATURE_ADC16_HAS_FIFO (0) /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ #define FSL_FEATURE_ADC16_FIFO_SIZE (0) /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) /* @brief Has HW averaging (bit SC3[AVGE]). */ #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) /* @brief Has offset correction (register OFS). */ #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) /* @brief Maximum ADC resolution. */ #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) /* FLEXCAN module features */ /* @brief Message buffer size */ #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) /* @brief Has doze mode support (register bit field MCR[DOZE]). */ #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) /* @brief Has extended bit timing register (register CBT). */ #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) /* @brief Has bitfield name BUF31TO0M. */ #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) /* @brief Number of interrupt vectors. */ #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) /* CMP module features */ /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ #define FSL_FEATURE_CMP_HAS_DMA (1) /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) /* @brief Has DAC Test function in CMP (register DACTEST). */ #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) /* CRC module features */ /* @brief Has data register with name CRC */ #define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* DAC module features */ /* @brief Define the size of hardware buffer */ #define FSL_FEATURE_DAC_BUFFER_SIZE (16) /* @brief Define whether the buffer supports watermark event detection or not. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) /* @brief Define whether the buffer supports watermark selection detection or not. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) /* @brief Define whether FIFO buffer mode is available or not. */ #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) /* @brief Define whether swing buffer mode is available or not.. */ #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) /* EDMA module features */ /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) /* @brief Total number of DMA channels on all modules. */ #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) /* @brief Has DMA_Error interrupt vector. */ #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) /* DMAMUX module features */ /* @brief Number of DMA channels (related to number of register CHCFGn). */ #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) /* @brief Total number of DMA channels on all modules. */ #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) /* ENET module features */ /* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */ #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0) /* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */ #define FSL_FEATURE_ENET_SUPPORT_PTP (1) /* @brief Number of associated interrupt vectors. */ #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) /* EWM module features */ /* @brief Has clock select (register CLKCTRL). */ #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) /* @brief Has clock prescaler (register CLKPRESCALER). */ #define FSL_FEATURE_EWM_HAS_PRESCALER (0) /* FLEXBUS module features */ /* No feature definitions */ /* FLASH module features */ #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ defined(CPU_MK64FN1M0VMD12) /* @brief Is of type FTFA. */ #define FSL_FEATURE_FLASH_IS_FTFA (0) /* @brief Is of type FTFE. */ #define FSL_FEATURE_FLASH_IS_FTFE (1) /* @brief Is of type FTFL. */ #define FSL_FEATURE_FLASH_IS_FTFL (0) /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) /* @brief Has EEPROM region protection (register FEPROT). */ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) /* @brief Has data flash region protection (register FDPROT). */ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) /* @brief Has flash cache control in FMC module. */ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) /* @brief Has flash cache control in MCM module. */ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) /* @brief Has flash cache control in MSCM module. */ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) /* @brief P-Flash sector size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) /* @brief P-Flash write unit size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) /* @brief P-Flash data path width. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) /* @brief P-Flash block swap feature. */ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) /* @brief P-Flash protection region count. */ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) /* @brief Has FlexNVM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) /* @brief FlexNVM block count. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) /* @brief FlexNVM block size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) /* @brief FlexNVM sector size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) /* @brief FlexNVM write unit size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) /* @brief FlexNVM data path width. */ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) /* @brief Has FlexRAM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) /* @brief FlexRAM size. */ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) /* @brief Has 0x00 Read 1s Block command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) /* @brief Has 0x01 Read 1s Section command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) /* @brief Has 0x02 Program Check command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) /* @brief Has 0x03 Read Resource command. */ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) /* @brief Has 0x06 Program Longword command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) /* @brief Has 0x07 Program Phrase command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) /* @brief Has 0x08 Erase Flash Block command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) /* @brief Has 0x09 Erase Flash Sector command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) /* @brief Has 0x0B Program Section command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) /* @brief Has 0x40 Read 1s All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) /* @brief Has 0x41 Read Once command. */ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) /* @brief Has 0x43 Program Once command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) /* @brief Has 0x44 Erase All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) /* @brief Has 0x45 Verify Backdoor Access Key command. */ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) /* @brief Has 0x46 Swap Control command. */ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) /* @brief Has 0x49 Erase All Blocks Unsecure command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x4B Erase All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x80 Program Partition command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) /* @brief Has 0x81 Set FlexRAM Function command. */ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) /* @brief P-Flash Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Read resource command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Read resource command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Program check command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) #elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) /* @brief Is of type FTFA. */ #define FSL_FEATURE_FLASH_IS_FTFA (0) /* @brief Is of type FTFE. */ #define FSL_FEATURE_FLASH_IS_FTFE (1) /* @brief Is of type FTFL. */ #define FSL_FEATURE_FLASH_IS_FTFL (0) /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) /* @brief Has EEPROM region protection (register FEPROT). */ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) /* @brief Has data flash region protection (register FDPROT). */ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) /* @brief Has flash cache control in FMC module. */ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) /* @brief Has flash cache control in MCM module. */ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) /* @brief Has flash cache control in MSCM module. */ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) /* @brief P-Flash sector size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) /* @brief P-Flash write unit size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) /* @brief P-Flash data path width. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) /* @brief P-Flash block swap feature. */ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) /* @brief P-Flash protection region count. */ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) /* @brief Has FlexNVM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) /* @brief FlexNVM block count. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) /* @brief FlexNVM block size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072) /* @brief FlexNVM sector size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096) /* @brief FlexNVM write unit size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) /* @brief FlexNVM data path width. */ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16) /* @brief Has FlexRAM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) /* @brief FlexRAM size. */ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) /* @brief Has 0x00 Read 1s Block command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) /* @brief Has 0x01 Read 1s Section command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) /* @brief Has 0x02 Program Check command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) /* @brief Has 0x03 Read Resource command. */ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) /* @brief Has 0x06 Program Longword command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) /* @brief Has 0x07 Program Phrase command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) /* @brief Has 0x08 Erase Flash Block command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) /* @brief Has 0x09 Erase Flash Sector command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) /* @brief Has 0x0B Program Section command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) /* @brief Has 0x40 Read 1s All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) /* @brief Has 0x41 Read Once command. */ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) /* @brief Has 0x43 Program Once command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) /* @brief Has 0x44 Erase All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) /* @brief Has 0x45 Verify Backdoor Access Key command. */ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) /* @brief Has 0x46 Swap Control command. */ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) /* @brief Has 0x49 Erase All Blocks Unsecure command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x4B Erase All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x80 Program Partition command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) /* @brief Has 0x81 Set FlexRAM Function command. */ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) /* @brief P-Flash Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) /* @brief P-Flash Read resource command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16) /* @brief FlexNVM Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16) /* @brief FlexNVM Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16) /* @brief FlexNVM Read resource command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) /* @brief FlexNVM Program check command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000) /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000) /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000) /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000) /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000) /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000) /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000) /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000) /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ defined(CPU_MK64FN1M0VMD12) */ /* FTM module features */ /* @brief Number of channels. */ #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ ((x) == FTM0 ? (8) : \ ((x) == FTM1 ? (2) : \ ((x) == FTM2 ? (2) : \ ((x) == FTM3 ? (8) : (-1))))) /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) /* @brief Has extended deadtime value. */ #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) /* @brief Enable pwm output for the module. */ #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) /* @brief Has half-cycle reload for the module. */ #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) /* @brief Has reload interrupt. */ #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) /* @brief Has reload initialization trigger. */ #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) /* @brief Has no QDCTRL. */ #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) /* GPIO module features */ /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) /* @brief Has port input disable register (PIDR). */ #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) /* @brief Has dedicated interrupt vector. */ #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) /* I2C module features */ /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ #define FSL_FEATURE_I2C_HAS_SMBUS (1) /* @brief Maximum supported baud rate in kilobit per second. */ #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) /* @brief Has DMA support (register bit C1[DMAEN]). */ #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) /* @brief Maximum width of the glitch filter in number of bus clocks. */ #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) /* @brief Has control of the drive capability of the I2C pins. */ #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) /* @brief Has double buffering support (register S2). */ #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) /* @brief Has double buffer enable. */ #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) /* SAI module features */ /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ #define FSL_FEATURE_SAI_FIFO_COUNT (8) /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) /* @brief Ihe interrupt source number */ #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) /* @brief Has register of MCR. */ #define FSL_FEATURE_SAI_HAS_MCR (1) /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (1) /* LLWU module features */ /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) /* @brief Has pins 8-15 connected to LLWU device. */ #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) /* @brief Maximum number of internal modules connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) /* @brief Number of digital filters. */ #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) /* @brief Has MF register. */ #define FSL_FEATURE_LLWU_HAS_MF (0) /* @brief Has PF register. */ #define FSL_FEATURE_LLWU_HAS_PF (0) /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) /* @brief Has no internal module wakeup flag register. */ #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) /* @brief Has external pin 0 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) /* @brief Has external pin 1 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) /* @brief Has external pin 2 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) /* @brief Has external pin 3 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) /* @brief Has external pin 4 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) /* @brief Has external pin 5 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) /* @brief Has external pin 6 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) /* @brief Has external pin 7 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) /* @brief Has external pin 8 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) /* @brief Has external pin 9 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) /* @brief Has external pin 10 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) /* @brief Has external pin 11 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) /* @brief Has external pin 12 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) /* @brief Has external pin 13 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) /* @brief Has external pin 14 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) /* @brief Has external pin 15 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) /* @brief Has external pin 16 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) /* @brief Has external pin 17 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) /* @brief Has external pin 18 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) /* @brief Has external pin 19 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) /* @brief Has external pin 20 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) /* @brief Has external pin 21 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) /* @brief Has external pin 22 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) /* @brief Has external pin 23 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) /* @brief Has external pin 24 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) /* @brief Has external pin 25 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) /* @brief Has external pin 26 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) /* @brief Has external pin 27 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) /* @brief Has external pin 28 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) /* @brief Has external pin 29 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) /* @brief Has external pin 30 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) /* @brief Has external pin 31 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) /* @brief Index of port of external pin. */ #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) /* @brief Number of external pin port on specified port. */ #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) /* @brief Has internal module 0 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) /* @brief Has internal module 1 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) /* @brief Has internal module 2 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) /* @brief Has internal module 3 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) /* @brief Has internal module 4 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) /* @brief Has internal module 5 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) /* @brief Has internal module 6 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) /* @brief Has internal module 7 connected to LLWU device. */ #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) /* @brief Has Version ID Register (LLWU_VERID). */ #define FSL_FEATURE_LLWU_HAS_VERID (0) /* @brief Has Parameter Register (LLWU_PARAM). */ #define FSL_FEATURE_LLWU_HAS_PARAM (0) /* @brief Width of registers of the LLWU. */ #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) /* @brief Has DMA Enable register (LLWU_DE). */ #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) /* LPTMR module features */ /* @brief Has shared interrupt handler with another LPTMR module. */ #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) /* @brief Whether LPTMR counter is 32 bits width. */ #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) /* MCG module features */ /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) /* @brief The PLL clock is divided by 2 before VCO divider. */ #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) /* @brief FRDIV supports 1280. */ #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) /* @brief FRDIV supports 1536. */ #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) /* @brief MCGFFCLK divider. */ #define FSL_FEATURE_MCG_FFCLK_DIV (1) /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ #define FSL_FEATURE_MCG_HAS_RTC_32K (1) /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ #define FSL_FEATURE_MCG_HAS_PLL1 (0) /* @brief Has 48MHz internal oscillator. */ #define FSL_FEATURE_MCG_HAS_IRC_48M (1) /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ #define FSL_FEATURE_MCG_HAS_OSC1 (0) /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ #define FSL_FEATURE_MCG_HAS_LOLRE (1) /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ #define FSL_FEATURE_MCG_USE_OSCSEL (1) /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) /* @brief TBD */ #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ #define FSL_FEATURE_MCG_HAS_PLL (1) /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ #define FSL_FEATURE_MCG_HAS_FLL (1) /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) /* @brief Has external clock monitor (register bit C6[CME]). */ #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) /* @brief Has PEI mode or PBI mode. */ #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) /* @brief Reset clock mode is BLPI. */ #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) /* interrupt module features */ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) /* OSC module features */ /* @brief Has OSC1 external oscillator. */ #define FSL_FEATURE_OSC_HAS_OSC1 (0) /* @brief Has OSC0 external oscillator. */ #define FSL_FEATURE_OSC_HAS_OSC0 (0) /* @brief Has OSC external oscillator (without index). */ #define FSL_FEATURE_OSC_HAS_OSC (1) /* @brief Number of OSC external oscillators. */ #define FSL_FEATURE_OSC_OSC_COUNT (1) /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) /* PDB module features */ /* @brief Define the count of supporting ADC pre-trigger for each channel. */ #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) /* @brief Has DAC support. */ #define FSL_FEATURE_PDB_HAS_DAC (1) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) /* PIT module features */ /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_PIT_TIMER_COUNT (4) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) /* @brief Has timer enable control. */ #define FSL_FEATURE_PIT_HAS_MDIS (1) /* PMC module features */ /* @brief Has Bandgap Enable In VLPx Operation support. */ #define FSL_FEATURE_PMC_HAS_BGEN (1) /* @brief Has Bandgap Buffer Enable. */ #define FSL_FEATURE_PMC_HAS_BGBE (1) /* @brief Has Bandgap Buffer Drive Select. */ #define FSL_FEATURE_PMC_HAS_BGBDS (0) /* @brief Has Low-Voltage Detect Voltage Select support. */ #define FSL_FEATURE_PMC_HAS_LVDV (1) /* @brief Has Low-Voltage Warning Voltage Select support. */ #define FSL_FEATURE_PMC_HAS_LVWV (1) /* @brief Has LPO. */ #define FSL_FEATURE_PMC_HAS_LPO (0) /* @brief Has VLPx option PMC_REGSC[VLPO]. */ #define FSL_FEATURE_PMC_HAS_VLPO (0) /* @brief Has acknowledge isolation support. */ #define FSL_FEATURE_PMC_HAS_ACKISO (1) /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ #define FSL_FEATURE_PMC_HAS_REGFPM (0) /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ #define FSL_FEATURE_PMC_HAS_REGONS (1) /* @brief Has PMC_HVDSC1. */ #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) /* @brief Has PMC_PARAM. */ #define FSL_FEATURE_PMC_HAS_PARAM (0) /* @brief Has PMC_VERID. */ #define FSL_FEATURE_PMC_HAS_VERID (0) /* PORT module features */ /* @brief Has control lock (register bit PCR[LK]). */ #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) /* @brief Has open drain control (register bit PCR[ODE]). */ #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) /* @brief Has DMA request (register bit field PCR[IRQC] values). */ #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) /* @brief Has pull resistor selection available. */ #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) /* @brief Has pull resistor enable (register bit PCR[PE]). */ #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) /* @brief Has slew rate control (register bit PCR[SRE]). */ #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) /* @brief Has passive filter (register bit field PCR[PFE]). */ #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Has separate drive strength register (HDRVE). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) /* @brief Has glitch filter (register IOFLT). */ #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) /* @brief Defines width of PCR[MUX] field. */ #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) /* @brief Has dedicated interrupt vector. */ #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) /* RCM module features */ /* @brief Has Loss-of-Lock Reset support. */ #define FSL_FEATURE_RCM_HAS_LOL (1) /* @brief Has Loss-of-Clock Reset support. */ #define FSL_FEATURE_RCM_HAS_LOC (1) /* @brief Has JTAG generated Reset support. */ #define FSL_FEATURE_RCM_HAS_JTAG (1) /* @brief Has EzPort generated Reset support. */ #define FSL_FEATURE_RCM_HAS_EZPORT (1) /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ #define FSL_FEATURE_RCM_HAS_EZPMS (1) /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ #define FSL_FEATURE_RCM_HAS_BOOTROM (0) /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ #define FSL_FEATURE_RCM_HAS_SSRS (0) /* @brief Has Version ID Register (RCM_VERID). */ #define FSL_FEATURE_RCM_HAS_VERID (0) /* @brief Has Parameter Register (RCM_PARAM). */ #define FSL_FEATURE_RCM_HAS_PARAM (0) /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ #define FSL_FEATURE_RCM_HAS_SRIE (0) /* @brief Width of registers of the RCM. */ #define FSL_FEATURE_RCM_REG_WIDTH (8) /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ #define FSL_FEATURE_RCM_HAS_CORE1 (0) /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ #define FSL_FEATURE_RCM_HAS_MDM_AP (1) /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ #define FSL_FEATURE_RCM_HAS_WAKEUP (1) /* RTC module features */ #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) /* @brief Has wakeup pin. */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) /* @brief Has wakeup pin selection (bit field CR[WPS]). */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) /* @brief Has read/write access control (registers WAR and RAR). */ #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_SECURITY (1) /* @brief Has RTC_CLKIN available. */ #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) /* @brief Has prescaler adjust for LPO. */ #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (0) /* @brief Has Timer Seconds Interrupt Configuration field. */ #define FSL_FEATURE_RTC_HAS_TSIC (0) /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (0) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) /* @brief Has Tamper Detect Register (register TDR). */ #define FSL_FEATURE_RTC_HAS_TDR (0) /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ #define FSL_FEATURE_RTC_HAS_TDR_STF (0) /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) /* @brief Has Tamper Time Seconds Register (register TTSR). */ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) /* @brief Has wakeup pin. */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) /* @brief Has wakeup pin selection (bit field CR[WPS]). */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) /* @brief Has read/write access control (registers WAR and RAR). */ #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_SECURITY (0) /* @brief Has RTC_CLKIN available. */ #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) /* @brief Has prescaler adjust for LPO. */ #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (0) /* @brief Has Timer Seconds Interrupt Configuration field. */ #define FSL_FEATURE_RTC_HAS_TSIC (0) /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (0) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) /* @brief Has Tamper Detect Register (register TDR). */ #define FSL_FEATURE_RTC_HAS_TDR (0) /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ #define FSL_FEATURE_RTC_HAS_TDR_STF (0) /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) /* @brief Has Tamper Time Seconds Register (register TTSR). */ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */ /* SDHC module features */ /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) /* SIM module features */ /* @brief Has USB FS divider. */ #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) /* @brief Has FTM module(s) configuration. */ #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) /* @brief Number of FTM modules. */ #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) /* @brief Number of FTM triggers with selectable source. */ #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) /* @brief Has TPM module(s) configuration. */ #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) /* @brief The highest TPM module index. */ #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) /* @brief Has TPM module with index 0. */ #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) /* @brief Has device die ID (register bit field SDID[DIEID]). */ #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) /* @brief Has miscellanious control register (register MCR). */ #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) /* @brief Has COP watchdog (registers COPC and SRVCOP). */ #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ #define FSL_FEATURE_SIM_HAS_COP_STOP (0) /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) /* SMC module features */ /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ #define FSL_FEATURE_SMC_HAS_PSTOPO (0) /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ #define FSL_FEATURE_SMC_HAS_LPOPO (0) /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ #define FSL_FEATURE_SMC_HAS_PORPO (1) /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ #define FSL_FEATURE_SMC_HAS_LPWUI (1) /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) /* @brief Has stop submode. */ #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) /* @brief Has stop submode 0(VLLS0). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) /* @brief Has stop submode 1(VLLS1). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) /* @brief Has stop submode 2(VLLS2). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) /* @brief Has SMC_PARAM. */ #define FSL_FEATURE_SMC_HAS_PARAM (0) /* @brief Has SMC_VERID. */ #define FSL_FEATURE_SMC_HAS_VERID (0) /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) /* @brief Has tamper reset (register bit SRS[TAMPER]). */ #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) /* @brief Has security violation reset (register bit SRS[SECVIO]). */ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* DSPI module features */ /* @brief Receive/transmit FIFO size in number of items. */ #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ ((x) == SPI0 ? (4) : \ ((x) == SPI1 ? (1) : \ ((x) == SPI2 ? (1) : (-1)))) /* @brief Maximum transfer data width in bits. */ #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) /* @brief Number of chip select pins. */ #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) /* @brief Has chip select strobe capability on the PCS5 pin. */ #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) /* @brief Has 16-bit data transfer support. */ #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ ((x) == SPI0 ? (1) : \ ((x) == SPI1 ? (0) : \ ((x) == SPI2 ? (0) : (-1)))) /* SYSMPU module features */ /* @brief Specifies number of descriptors available. */ #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) /* @brief Has process identifier support. */ #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) /* @brief Total number of MPU slave. */ #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) /* @brief Total number of MPU master. */ #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) /* SysTick module features */ /* @brief Systick has external reference clock. */ #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) /* @brief Systick external reference clock is core clock divided by this value. */ #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) /* UART module features */ #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_UART_HAS_FIFO (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) /* @brief Infrared (modulation) is supported. */ #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) /* @brief 2 bits long stop bit is available. */ #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) /* @brief If 10-bit mode is supported. */ #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) /* @brief Peripheral type. */ #define FSL_FEATURE_UART_IS_SCI (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ ((x) == UART0 ? (8) : \ ((x) == UART1 ? (8) : \ ((x) == UART2 ? (1) : \ ((x) == UART3 ? (1) : \ ((x) == UART4 ? (1) : \ ((x) == UART5 ? (1) : (-1))))))) /* @brief Maximal data width without parity bit. */ #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) /* @brief Maximal data width with parity bit. */ #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) /* @brief Has improved smart card (ISO7816 protocol) support. */ #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) /* @brief Has local operation network (CEA709.1-B protocol) support. */ #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ ((x) == UART0 ? (1) : \ ((x) == UART1 ? (1) : \ ((x) == UART2 ? (1) : \ ((x) == UART3 ? (1) : \ ((x) == UART4 ? (0) : \ ((x) == UART5 ? (0) : (-1))))))) #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_UART_HAS_FIFO (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) /* @brief Infrared (modulation) is supported. */ #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) /* @brief 2 bits long stop bit is available. */ #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) /* @brief If 10-bit mode is supported. */ #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) /* @brief Peripheral type. */ #define FSL_FEATURE_UART_IS_SCI (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ ((x) == UART0 ? (8) : \ ((x) == UART1 ? (8) : \ ((x) == UART2 ? (1) : \ ((x) == UART3 ? (1) : \ ((x) == UART4 ? (1) : (-1)))))) /* @brief Maximal data width without parity bit. */ #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) /* @brief Maximal data width with parity bit. */ #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) /* @brief Has improved smart card (ISO7816 protocol) support. */ #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) /* @brief Has local operation network (CEA709.1-B protocol) support. */ #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ ((x) == UART0 ? (1) : \ ((x) == UART1 ? (1) : \ ((x) == UART2 ? (1) : \ ((x) == UART3 ? (1) : \ ((x) == UART4 ? (0) : (-1)))))) #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) */ /* USB module features */ /* @brief KHCI module instance count */ #define FSL_FEATURE_USB_KHCI_COUNT (1) /* @brief HOST mode enabled */ #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) /* @brief OTG mode enabled */ #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) /* @brief Size of the USB dedicated RAM */ #define FSL_FEATURE_USB_KHCI_USB_RAM (0) /* @brief Has KEEP_ALIVE_CTRL register */ #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) /* @brief Has the Dynamic SOF threshold compare support */ #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) /* @brief Has the VBUS detect support */ #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) /* @brief Has the IRC48M module clock support */ #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) /* @brief Number of endpoints supported */ #define FSL_FEATURE_USB_ENDPT_COUNT (16) /* VREF module features */ /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) /* @brief If high/low buffer mode supported */ #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) /* @brief Module has also low reference (registers VREFL/VREFH) */ #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) /* @brief Has VREF_TRM4. */ #define FSL_FEATURE_VREF_HAS_TRM4 (0) /* WDOG module features */ /* @brief Watchdog is available. */ #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) /* @brief Has Wait mode support. */ #define FSL_FEATURE_WDOG_HAS_WAITEN (1) #endif /* _MK64F12_FEATURES_H_ */ ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/MK64FN1M0xxx12_flash.scf ================================================ #! armcc -E /* ** ################################################################### ** Processors: MK64FN1M0CAJ12 ** MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** ** Compiler: Keil ARM C/C++ Compiler ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 ** Build: b170817 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ #define m_interrupts_start 0x00000000 #define m_interrupts_size 0x00000400 #define m_flash_config_start 0x00000400 #define m_flash_config_size 0x00000010 #define m_text_start 0x00000410 #define m_text_size 0x000FFBF0 #define m_data_start 0x1FFF0000 #define m_data_size 0x00010000 #define m_data_2_start 0x20000000 #define m_data_2_size 0x00030000 /* Sizes */ #if (defined(__stack_size__)) #define Stack_Size __stack_size__ #else #define Stack_Size 0x0400 #endif #if (defined(__heap_size__)) #define Heap_Size __heap_size__ #else #define Heap_Size 0x0400 #endif LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address * (RESET,+FIRST) } ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address * (FlashConfig) } ER_m_text m_text_start m_text_size { ; load address = execution address * (InRoot$$Sections) .ANY (+RO) } RW_m_data m_data_start m_data_size { ; RW data .ANY (+RW +ZI) } RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data .ANY (+RW +ZI) } ARM_LIB_HEAP ((ImageLimit(RW_m_data_2) == m_data_2_start) ? m_data_2_start : +0) EMPTY Heap_Size { ; Heap region growing up } ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down } } ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/MK64FN1M0xxx12_ram.scf ================================================ #! armcc -E /* ** ################################################################### ** Processors: MK64FN1M0CAJ12 ** MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** ** Compiler: Keil ARM C/C++ Compiler ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 ** Build: b170817 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** ################################################################### */ #define m_interrupts_start 0x1FFF0000 #define m_interrupts_size 0x00000400 #define m_text_start 0x1FFF0400 #define m_text_size 0x0000FC00 #define m_data_start 0x20000000 #define m_data_size 0x00030000 /* Sizes */ #if (defined(__stack_size__)) #define Stack_Size __stack_size__ #else #define Stack_Size 0x0400 #endif #if (defined(__heap_size__)) #define Heap_Size __heap_size__ #else #define Heap_Size 0x0400 #endif LR_m_text m_text_start m_text_size { ; load region size_region ER_m_text m_text_start m_text_size { ; load address = execution address * (InRoot$$Sections) .ANY (+RO) } RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } } LR_m_interrupts m_interrupts_start m_interrupts_size { VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address * (RESET,+FIRST) } } LR_m_interrupts_ram m_interrupts_start m_interrupts_size { VECTOR_RAM m_interrupts_start m_interrupts_size { ; load address = execution address .ANY (.m_interrupts_ram) } } ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/RTE_Device.h ================================================ /* * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H /* UART select, UART0-UART5 */ /* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins in the application for enabling according instance. */ #define RTE_USART0 1 #define RTE_USART0_DMA_EN 1 #define RTE_USART1 0 #define RTE_USART1_DMA_EN 0 #define RTE_USART2 0 #define RTE_USART2_DMA_EN 0 #define RTE_USART3 0 #define RTE_USART3_DMA_EN 0 #define RTE_USART4 0 #define RTE_USART4_DMA_EN 0 #define RTE_USART5 0 #define RTE_USART5_DMA_EN 0 /* UART RX Buffer configuration. */ #define USART_RX_BUFFER_LEN 64 #define USART0_RX_BUFFER_ENABLE 1 #define USART1_RX_BUFFER_ENABLE 0 #define USART2_RX_BUFFER_ENABLE 0 #define USART3_RX_BUFFER_ENABLE 0 #define USART4_RX_BUFFER_ENABLE 0 #define USART5_RX_BUFFER_ENABLE 0 #define RTE_USART0_DMA_TX_CH 0 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 #define RTE_USART0_DMA_RX_CH 1 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 #define RTE_USART1_DMA_TX_CH 0 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 #define RTE_USART1_DMA_RX_CH 1 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 #define RTE_USART2_DMA_TX_CH 0 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 #define RTE_USART2_DMA_RX_CH 1 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 #define RTE_USART3_DMA_TX_CH 0 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 #define RTE_USART3_DMA_RX_CH 1 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 #define RTE_USART4_DMA_TX_CH 0 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 #define RTE_USART4_DMA_RX_CH 1 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 #define RTE_USART5_DMA_TX_CH 0 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 #define RTE_USART5_DMA_RX_CH 1 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 /* I2C select, I2C0 - I2C2. */ /* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins in the application for enabling according instance. */ #define RTE_I2C0 0 #define RTE_I2C0_DMA_EN 0 #define RTE_I2C1 0 #define RTE_I2C1_DMA_EN 0 #define RTE_I2C2 0 #define RTE_I2C2_DMA_EN 0 /*I2C configuration*/ #define RTE_I2C0_Master_DMA_BASE DMA0 #define RTE_I2C0_Master_DMA_CH 0 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 #define RTE_I2C1_Master_DMA_BASE DMA0 #define RTE_I2C1_Master_DMA_CH 1 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 #define RTE_I2C2_Master_DMA_BASE DMA0 #define RTE_I2C2_Master_DMA_CH 2 #define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0 #define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2 /* SPI select, DSPI0 - DSPI2. */ /* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins in the application for enabling according instance. */ #define RTE_SPI0 0 #define RTE_SPI0_DMA_EN 0 #define RTE_SPI1 0 #define RTE_SPI1_DMA_EN 0 #define RTE_SPI2 0 #define RTE_SPI2_DMA_EN 0 /* DSPI configuration. */ #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 #define RTE_SPI0_DMA_TX_CH 0 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 #define RTE_SPI0_DMA_RX_CH 1 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 #define RTE_SPI0_DMA_LINK_CH 2 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 #define RTE_SPI1_DMA_TX_CH 4 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 #define RTE_SPI1_DMA_RX_CH 3 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 #define RTE_SPI1_DMA_LINK_CH 2 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 #define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 #define RTE_SPI2_DMA_TX_CH 6 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 #define RTE_SPI2_DMA_RX_CH 7 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 #define RTE_SPI2_DMA_LINK_DMA_BASE DMA0 #define RTE_SPI2_DMA_LINK_CH 8 #endif /* __RTE_DEVICE_H */ ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/fsl_device_registers.h ================================================ /* * The Clear BSD License * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted (subject to the limitations in the disclaimer below) provided * that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef __FSL_DEVICE_REGISTERS_H__ #define __FSL_DEVICE_REGISTERS_H__ /* * Include the cpu specific register header files. * * The CPU macro should be declared in the project or makefile. */ #if (defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || \ defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || \ defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)) #define K64F12_SERIES /* CMSIS-style register definitions */ #include "MK64F12.h" /* CPU specific feature definitions */ #include "MK64F12_features.h" #else #error "No valid CPU defined!" #endif #endif /* __FSL_DEVICE_REGISTERS_H__ */ /******************************************************************************* * EOF ******************************************************************************/ ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/startup_MK64F12.s ================================================ ; * --------------------------------------------------------------------------------------- ; * @file: startup_MK64F12.s ; * @purpose: CMSIS Cortex-M4 Core Device Startup File ; * MK64F12 ; * @version: 2.9 ; * @date: 2016-3-21 ; * @build: b170730 ; * --------------------------------------------------------------------------------------- ; * ; * Copyright 1997-2016 Freescale Semiconductor, Inc. ; * Copyright 2016-2017 NXP ; * Redistribution and use in source and binary forms, with or without modification, ; * are permitted provided that the following conditions are met: ; * ; * 1. Redistributions of source code must retain the above copyright notice, this list ; * of conditions and the following disclaimer. ; * ; * 2. Redistributions in binary form must reproduce the above copyright notice, this ; * list of conditions and the following disclaimer in the documentation and/or ; * other materials provided with the distribution. ; * ; * 3. Neither the name of the copyright holder nor the names of its ; * contributors may be used to endorse or promote products derived from this ; * software without specific prior written permission. ; * ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; * ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * ; *****************************************************************************/ PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ;NMI Handler DCD HardFault_Handler ;Hard Fault Handler DCD MemManage_Handler ;MPU Fault Handler DCD BusFault_Handler ;Bus Fault Handler DCD UsageFault_Handler ;Usage Fault Handler DCD 0 ;Reserved DCD 0 ;Reserved DCD 0 ;Reserved DCD 0 ;Reserved DCD SVC_Handler ;SVCall Handler DCD DebugMon_Handler ;Debug Monitor Handler DCD 0 ;Reserved DCD PendSV_Handler ;PendSV Handler DCD SysTick_Handler ;SysTick Handler ;External Interrupts DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete DCD DMA_Error_IRQHandler ;DMA Error Interrupt DCD MCM_IRQHandler ;Normal Interrupt DCD FTFE_IRQHandler ;FTFE Command complete interrupt DCD Read_Collision_IRQHandler ;Read Collision Interrupt DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit DCD WDOG_EWM_IRQHandler ;WDOG Interrupt DCD RNG_IRQHandler ;RNG Interrupt DCD I2C0_IRQHandler ;I2C0 interrupt DCD I2C1_IRQHandler ;I2C1 interrupt DCD SPI0_IRQHandler ;SPI0 Interrupt DCD SPI1_IRQHandler ;SPI1 Interrupt DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt DCD UART0_LON_IRQHandler ;UART0 LON interrupt DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt DCD UART0_ERR_IRQHandler ;UART0 Error interrupt DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt DCD UART1_ERR_IRQHandler ;UART1 Error interrupt DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt DCD UART2_ERR_IRQHandler ;UART2 Error interrupt DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt DCD UART3_ERR_IRQHandler ;UART3 Error interrupt DCD ADC0_IRQHandler ;ADC0 interrupt DCD CMP0_IRQHandler ;CMP0 interrupt DCD CMP1_IRQHandler ;CMP1 interrupt DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt DCD CMT_IRQHandler ;CMT interrupt DCD RTC_IRQHandler ;RTC interrupt DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt DCD PDB0_IRQHandler ;PDB0 Interrupt DCD USB0_IRQHandler ;USB0 interrupt DCD USBDCD_IRQHandler ;USBDCD Interrupt DCD Reserved71_IRQHandler ;Reserved interrupt 71 DCD DAC0_IRQHandler ;DAC0 interrupt DCD MCG_IRQHandler ;MCG Interrupt DCD LPTMR0_IRQHandler ;LPTimer interrupt DCD PORTA_IRQHandler ;Port A interrupt DCD PORTB_IRQHandler ;Port B interrupt DCD PORTC_IRQHandler ;Port C interrupt DCD PORTD_IRQHandler ;Port D interrupt DCD PORTE_IRQHandler ;Port E interrupt DCD SWI_IRQHandler ;Software interrupt DCD SPI2_IRQHandler ;SPI2 Interrupt DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt DCD UART4_ERR_IRQHandler ;UART4 Error interrupt DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt DCD UART5_ERR_IRQHandler ;UART5 Error interrupt DCD CMP2_IRQHandler ;CMP2 interrupt DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt DCD DAC1_IRQHandler ;DAC1 interrupt DCD ADC1_IRQHandler ;ADC1 interrupt DCD I2C2_IRQHandler ;I2C2 interrupt DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt DCD CAN0_Error_IRQHandler ;CAN0 error interrupt DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt DCD SDHC_IRQHandler ;SDHC interrupt DCD ENET_1588_Timer_IRQHandler ;Ethernet MAC IEEE 1588 Timer Interrupt DCD ENET_Transmit_IRQHandler ;Ethernet MAC Transmit Interrupt DCD ENET_Receive_IRQHandler ;Ethernet MAC Receive Interrupt DCD ENET_Error_IRQHandler ;Ethernet MAC Error and miscelaneous Interrupt DCD DefaultISR ;102 DCD DefaultISR ;103 DCD DefaultISR ;104 DCD DefaultISR ;105 DCD DefaultISR ;106 DCD DefaultISR ;107 DCD DefaultISR ;108 DCD DefaultISR ;109 DCD DefaultISR ;110 DCD DefaultISR ;111 DCD DefaultISR ;112 DCD DefaultISR ;113 DCD DefaultISR ;114 DCD DefaultISR ;115 DCD DefaultISR ;116 DCD DefaultISR ;117 DCD DefaultISR ;118 DCD DefaultISR ;119 DCD DefaultISR ;120 DCD DefaultISR ;121 DCD DefaultISR ;122 DCD DefaultISR ;123 DCD DefaultISR ;124 DCD DefaultISR ;125 DCD DefaultISR ;126 DCD DefaultISR ;127 DCD DefaultISR ;128 DCD DefaultISR ;129 DCD DefaultISR ;130 DCD DefaultISR ;131 DCD DefaultISR ;132 DCD DefaultISR ;133 DCD DefaultISR ;134 DCD DefaultISR ;135 DCD DefaultISR ;136 DCD DefaultISR ;137 DCD DefaultISR ;138 DCD DefaultISR ;139 DCD DefaultISR ;140 DCD DefaultISR ;141 DCD DefaultISR ;142 DCD DefaultISR ;143 DCD DefaultISR ;144 DCD DefaultISR ;145 DCD DefaultISR ;146 DCD DefaultISR ;147 DCD DefaultISR ;148 DCD DefaultISR ;149 DCD DefaultISR ;150 DCD DefaultISR ;151 DCD DefaultISR ;152 DCD DefaultISR ;153 DCD DefaultISR ;154 DCD DefaultISR ;155 DCD DefaultISR ;156 DCD DefaultISR ;157 DCD DefaultISR ;158 DCD DefaultISR ;159 DCD DefaultISR ;160 DCD DefaultISR ;161 DCD DefaultISR ;162 DCD DefaultISR ;163 DCD DefaultISR ;164 DCD DefaultISR ;165 DCD DefaultISR ;166 DCD DefaultISR ;167 DCD DefaultISR ;168 DCD DefaultISR ;169 DCD DefaultISR ;170 DCD DefaultISR ;171 DCD DefaultISR ;172 DCD DefaultISR ;173 DCD DefaultISR ;174 DCD DefaultISR ;175 DCD DefaultISR ;176 DCD DefaultISR ;177 DCD DefaultISR ;178 DCD DefaultISR ;179 DCD DefaultISR ;180 DCD DefaultISR ;181 DCD DefaultISR ;182 DCD DefaultISR ;183 DCD DefaultISR ;184 DCD DefaultISR ;185 DCD DefaultISR ;186 DCD DefaultISR ;187 DCD DefaultISR ;188 DCD DefaultISR ;189 DCD DefaultISR ;190 DCD DefaultISR ;191 DCD DefaultISR ;192 DCD DefaultISR ;193 DCD DefaultISR ;194 DCD DefaultISR ;195 DCD DefaultISR ;196 DCD DefaultISR ;197 DCD DefaultISR ;198 DCD DefaultISR ;199 DCD DefaultISR ;200 DCD DefaultISR ;201 DCD DefaultISR ;202 DCD DefaultISR ;203 DCD DefaultISR ;204 DCD DefaultISR ;205 DCD DefaultISR ;206 DCD DefaultISR ;207 DCD DefaultISR ;208 DCD DefaultISR ;209 DCD DefaultISR ;210 DCD DefaultISR ;211 DCD DefaultISR ;212 DCD DefaultISR ;213 DCD DefaultISR ;214 DCD DefaultISR ;215 DCD DefaultISR ;216 DCD DefaultISR ;217 DCD DefaultISR ;218 DCD DefaultISR ;219 DCD DefaultISR ;220 DCD DefaultISR ;221 DCD DefaultISR ;222 DCD DefaultISR ;223 DCD DefaultISR ;224 DCD DefaultISR ;225 DCD DefaultISR ;226 DCD DefaultISR ;227 DCD DefaultISR ;228 DCD DefaultISR ;229 DCD DefaultISR ;230 DCD DefaultISR ;231 DCD DefaultISR ;232 DCD DefaultISR ;233 DCD DefaultISR ;234 DCD DefaultISR ;235 DCD DefaultISR ;236 DCD DefaultISR ;237 DCD DefaultISR ;238 DCD DefaultISR ;239 DCD DefaultISR ;240 DCD DefaultISR ;241 DCD DefaultISR ;242 DCD DefaultISR ;243 DCD DefaultISR ;244 DCD DefaultISR ;245 DCD DefaultISR ;246 DCD DefaultISR ;247 DCD DefaultISR ;248 DCD DefaultISR ;249 DCD DefaultISR ;250 DCD DefaultISR ;251 DCD DefaultISR ;252 DCD DefaultISR ;253 DCD DefaultISR ;254 DCD 0xFFFFFFFF ; Reserved for user TRIM value __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors ; Flash Configuration ; 16-byte flash configuration field that stores default protection settings (loaded on reset) ; and security information that allows the MCU to restrict access to the FTFL module. ; Backdoor Comparison Key ; Backdoor Comparison Key 0. <0x0-0xFF:2> ; Backdoor Comparison Key 1. <0x0-0xFF:2> ; Backdoor Comparison Key 2. <0x0-0xFF:2> ; Backdoor Comparison Key 3. <0x0-0xFF:2> ; Backdoor Comparison Key 4. <0x0-0xFF:2> ; Backdoor Comparison Key 5. <0x0-0xFF:2> ; Backdoor Comparison Key 6. <0x0-0xFF:2> ; Backdoor Comparison Key 7. <0x0-0xFF:2> BackDoorK0 EQU 0xFF BackDoorK1 EQU 0xFF BackDoorK2 EQU 0xFF BackDoorK3 EQU 0xFF BackDoorK4 EQU 0xFF BackDoorK5 EQU 0xFF BackDoorK6 EQU 0xFF BackDoorK7 EQU 0xFF ; ; Program flash protection bytes (FPROT) ; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. ; Each bit protects a 1/32 region of the program flash memory. ; FPROT0 ; Program Flash Region Protect Register 0 ; 1/32 - 8/32 region ; FPROT0.0 ; FPROT0.1 ; FPROT0.2 ; FPROT0.3 ; FPROT0.4 ; FPROT0.5 ; FPROT0.6 ; FPROT0.7 nFPROT0 EQU 0x00 FPROT0 EQU nFPROT0:EOR:0xFF ; ; FPROT1 ; Program Flash Region Protect Register 1 ; 9/32 - 16/32 region ; FPROT1.0 ; FPROT1.1 ; FPROT1.2 ; FPROT1.3 ; FPROT1.4 ; FPROT1.5 ; FPROT1.6 ; FPROT1.7 nFPROT1 EQU 0x00 FPROT1 EQU nFPROT1:EOR:0xFF ; ; FPROT2 ; Program Flash Region Protect Register 2 ; 17/32 - 24/32 region ; FPROT2.0 ; FPROT2.1 ; FPROT2.2 ; FPROT2.3 ; FPROT2.4 ; FPROT2.5 ; FPROT2.6 ; FPROT2.7 nFPROT2 EQU 0x00 FPROT2 EQU nFPROT2:EOR:0xFF ; ; FPROT3 ; Program Flash Region Protect Register 3 ; 25/32 - 32/32 region ; FPROT3.0 ; FPROT3.1 ; FPROT3.2 ; FPROT3.3 ; FPROT3.4 ; FPROT3.5 ; FPROT3.6 ; FPROT3.7 nFPROT3 EQU 0x00 FPROT3 EQU nFPROT3:EOR:0xFF ; ; ; Data flash protection byte (FDPROT) ; Each bit protects a 1/8 region of the data flash memory. ; (Program flash only devices: Reserved) ; FDPROT.0 ; FDPROT.1 ; FDPROT.2 ; FDPROT.3 ; FDPROT.4 ; FDPROT.5 ; FDPROT.6 ; FDPROT.7 nFDPROT EQU 0x00 FDPROT EQU nFDPROT:EOR:0xFF ; ; EEPROM protection byte (FEPROT) ; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. ; (Program flash only devices: Reserved) ; FEPROT.0 ; FEPROT.1 ; FEPROT.2 ; FEPROT.3 ; FEPROT.4 ; FEPROT.5 ; FEPROT.6 ; FEPROT.7 nFEPROT EQU 0x00 FEPROT EQU nFEPROT:EOR:0xFF ; ; Flash nonvolatile option byte (FOPT) ; Allows the user to customize the operation of the MCU at boot time. ; LPBOOT ; <0=> Low-power boot ; <1=> Normal boot ; EZPORT_DIS ; <0=> EzPort operation is disabled ; <1=> EzPort operation is enabled FOPT EQU 0xFF ; ; Flash security byte (FSEC) ; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", ; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! ; SEC ; <2=> MCU security status is unsecure ; <3=> MCU security status is secure ; Flash Security ; FSLACC ; <2=> Freescale factory access denied ; <3=> Freescale factory access granted ; Freescale Failure Analysis Access Code ; MEEN ; <2=> Mass erase is disabled ; <3=> Mass erase is enabled ; KEYEN ; <2=> Backdoor key access enabled ; <3=> Backdoor key access disabled ; Backdoor Key Security Enable FSEC EQU 0xFE ; ; IF :LNOT::DEF:RAM_TARGET AREA FlashConfig, DATA, READONLY __FlashConfig DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 DCB FSEC , FOPT , FEPROT , FDPROT ENDIF AREA |.text|, CODE, READONLY ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main IF :LNOT::DEF:RAM_TARGET REQUIRE FlashConfig ENDIF CPSID I ; Mask interrupts LDR R0, =0xE000ED08 LDR R1, =__Vectors STR R1, [R0] LDR R2, [R1] MSR MSP, R2 LDR R0, =SystemInit BLX R0 CPSIE i ; Unmask interrupts LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler\ PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler\ PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler\ PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler\ PROC EXPORT SysTick_Handler [WEAK] B . ENDP DMA0_IRQHandler\ PROC EXPORT DMA0_IRQHandler [WEAK] LDR R0, =DMA0_DriverIRQHandler BX R0 ENDP DMA1_IRQHandler\ PROC EXPORT DMA1_IRQHandler [WEAK] LDR R0, =DMA1_DriverIRQHandler BX R0 ENDP DMA2_IRQHandler\ PROC EXPORT DMA2_IRQHandler [WEAK] LDR R0, =DMA2_DriverIRQHandler BX R0 ENDP DMA3_IRQHandler\ PROC EXPORT DMA3_IRQHandler [WEAK] LDR R0, =DMA3_DriverIRQHandler BX R0 ENDP DMA4_IRQHandler\ PROC EXPORT DMA4_IRQHandler [WEAK] LDR R0, =DMA4_DriverIRQHandler BX R0 ENDP DMA5_IRQHandler\ PROC EXPORT DMA5_IRQHandler [WEAK] LDR R0, =DMA5_DriverIRQHandler BX R0 ENDP DMA6_IRQHandler\ PROC EXPORT DMA6_IRQHandler [WEAK] LDR R0, =DMA6_DriverIRQHandler BX R0 ENDP DMA7_IRQHandler\ PROC EXPORT DMA7_IRQHandler [WEAK] LDR R0, =DMA7_DriverIRQHandler BX R0 ENDP DMA8_IRQHandler\ PROC EXPORT DMA8_IRQHandler [WEAK] LDR R0, =DMA8_DriverIRQHandler BX R0 ENDP DMA9_IRQHandler\ PROC EXPORT DMA9_IRQHandler [WEAK] LDR R0, =DMA9_DriverIRQHandler BX R0 ENDP DMA10_IRQHandler\ PROC EXPORT DMA10_IRQHandler [WEAK] LDR R0, =DMA10_DriverIRQHandler BX R0 ENDP DMA11_IRQHandler\ PROC EXPORT DMA11_IRQHandler [WEAK] LDR R0, =DMA11_DriverIRQHandler BX R0 ENDP DMA12_IRQHandler\ PROC EXPORT DMA12_IRQHandler [WEAK] LDR R0, =DMA12_DriverIRQHandler BX R0 ENDP DMA13_IRQHandler\ PROC EXPORT DMA13_IRQHandler [WEAK] LDR R0, =DMA13_DriverIRQHandler BX R0 ENDP DMA14_IRQHandler\ PROC EXPORT DMA14_IRQHandler [WEAK] LDR R0, =DMA14_DriverIRQHandler BX R0 ENDP DMA15_IRQHandler\ PROC EXPORT DMA15_IRQHandler [WEAK] LDR R0, =DMA15_DriverIRQHandler BX R0 ENDP DMA_Error_IRQHandler\ PROC EXPORT DMA_Error_IRQHandler [WEAK] LDR R0, =DMA_Error_DriverIRQHandler BX R0 ENDP I2C0_IRQHandler\ PROC EXPORT I2C0_IRQHandler [WEAK] LDR R0, =I2C0_DriverIRQHandler BX R0 ENDP I2C1_IRQHandler\ PROC EXPORT I2C1_IRQHandler [WEAK] LDR R0, =I2C1_DriverIRQHandler BX R0 ENDP SPI0_IRQHandler\ PROC EXPORT SPI0_IRQHandler [WEAK] LDR R0, =SPI0_DriverIRQHandler BX R0 ENDP SPI1_IRQHandler\ PROC EXPORT SPI1_IRQHandler [WEAK] LDR R0, =SPI1_DriverIRQHandler BX R0 ENDP I2S0_Tx_IRQHandler\ PROC EXPORT I2S0_Tx_IRQHandler [WEAK] LDR R0, =I2S0_Tx_DriverIRQHandler BX R0 ENDP I2S0_Rx_IRQHandler\ PROC EXPORT I2S0_Rx_IRQHandler [WEAK] LDR R0, =I2S0_Rx_DriverIRQHandler BX R0 ENDP UART0_LON_IRQHandler\ PROC EXPORT UART0_LON_IRQHandler [WEAK] LDR R0, =UART0_LON_DriverIRQHandler BX R0 ENDP UART0_RX_TX_IRQHandler\ PROC EXPORT UART0_RX_TX_IRQHandler [WEAK] LDR R0, =UART0_RX_TX_DriverIRQHandler BX R0 ENDP UART0_ERR_IRQHandler\ PROC EXPORT UART0_ERR_IRQHandler [WEAK] LDR R0, =UART0_ERR_DriverIRQHandler BX R0 ENDP UART1_RX_TX_IRQHandler\ PROC EXPORT UART1_RX_TX_IRQHandler [WEAK] LDR R0, =UART1_RX_TX_DriverIRQHandler BX R0 ENDP UART1_ERR_IRQHandler\ PROC EXPORT UART1_ERR_IRQHandler [WEAK] LDR R0, =UART1_ERR_DriverIRQHandler BX R0 ENDP UART2_RX_TX_IRQHandler\ PROC EXPORT UART2_RX_TX_IRQHandler [WEAK] LDR R0, =UART2_RX_TX_DriverIRQHandler BX R0 ENDP UART2_ERR_IRQHandler\ PROC EXPORT UART2_ERR_IRQHandler [WEAK] LDR R0, =UART2_ERR_DriverIRQHandler BX R0 ENDP UART3_RX_TX_IRQHandler\ PROC EXPORT UART3_RX_TX_IRQHandler [WEAK] LDR R0, =UART3_RX_TX_DriverIRQHandler BX R0 ENDP UART3_ERR_IRQHandler\ PROC EXPORT UART3_ERR_IRQHandler [WEAK] LDR R0, =UART3_ERR_DriverIRQHandler BX R0 ENDP SPI2_IRQHandler\ PROC EXPORT SPI2_IRQHandler [WEAK] LDR R0, =SPI2_DriverIRQHandler BX R0 ENDP UART4_RX_TX_IRQHandler\ PROC EXPORT UART4_RX_TX_IRQHandler [WEAK] LDR R0, =UART4_RX_TX_DriverIRQHandler BX R0 ENDP UART4_ERR_IRQHandler\ PROC EXPORT UART4_ERR_IRQHandler [WEAK] LDR R0, =UART4_ERR_DriverIRQHandler BX R0 ENDP UART5_RX_TX_IRQHandler\ PROC EXPORT UART5_RX_TX_IRQHandler [WEAK] LDR R0, =UART5_RX_TX_DriverIRQHandler BX R0 ENDP UART5_ERR_IRQHandler\ PROC EXPORT UART5_ERR_IRQHandler [WEAK] LDR R0, =UART5_ERR_DriverIRQHandler BX R0 ENDP I2C2_IRQHandler\ PROC EXPORT I2C2_IRQHandler [WEAK] LDR R0, =I2C2_DriverIRQHandler BX R0 ENDP CAN0_ORed_Message_buffer_IRQHandler\ PROC EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP CAN0_Bus_Off_IRQHandler\ PROC EXPORT CAN0_Bus_Off_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP CAN0_Error_IRQHandler\ PROC EXPORT CAN0_Error_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP CAN0_Tx_Warning_IRQHandler\ PROC EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP CAN0_Rx_Warning_IRQHandler\ PROC EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP CAN0_Wake_Up_IRQHandler\ PROC EXPORT CAN0_Wake_Up_IRQHandler [WEAK] LDR R0, =CAN0_DriverIRQHandler BX R0 ENDP SDHC_IRQHandler\ PROC EXPORT SDHC_IRQHandler [WEAK] LDR R0, =SDHC_DriverIRQHandler BX R0 ENDP ENET_1588_Timer_IRQHandler\ PROC EXPORT ENET_1588_Timer_IRQHandler [WEAK] LDR R0, =ENET_1588_Timer_DriverIRQHandler BX R0 ENDP ENET_Transmit_IRQHandler\ PROC EXPORT ENET_Transmit_IRQHandler [WEAK] LDR R0, =ENET_Transmit_DriverIRQHandler BX R0 ENDP ENET_Receive_IRQHandler\ PROC EXPORT ENET_Receive_IRQHandler [WEAK] LDR R0, =ENET_Receive_DriverIRQHandler BX R0 ENDP ENET_Error_IRQHandler\ PROC EXPORT ENET_Error_IRQHandler [WEAK] LDR R0, =ENET_Error_DriverIRQHandler BX R0 ENDP Default_Handler\ PROC EXPORT DMA0_DriverIRQHandler [WEAK] EXPORT DMA1_DriverIRQHandler [WEAK] EXPORT DMA2_DriverIRQHandler [WEAK] EXPORT DMA3_DriverIRQHandler [WEAK] EXPORT DMA4_DriverIRQHandler [WEAK] EXPORT DMA5_DriverIRQHandler [WEAK] EXPORT DMA6_DriverIRQHandler [WEAK] EXPORT DMA7_DriverIRQHandler [WEAK] EXPORT DMA8_DriverIRQHandler [WEAK] EXPORT DMA9_DriverIRQHandler [WEAK] EXPORT DMA10_DriverIRQHandler [WEAK] EXPORT DMA11_DriverIRQHandler [WEAK] EXPORT DMA12_DriverIRQHandler [WEAK] EXPORT DMA13_DriverIRQHandler [WEAK] EXPORT DMA14_DriverIRQHandler [WEAK] EXPORT DMA15_DriverIRQHandler [WEAK] EXPORT DMA_Error_DriverIRQHandler [WEAK] EXPORT MCM_IRQHandler [WEAK] EXPORT FTFE_IRQHandler [WEAK] EXPORT Read_Collision_IRQHandler [WEAK] EXPORT LVD_LVW_IRQHandler [WEAK] EXPORT LLWU_IRQHandler [WEAK] EXPORT WDOG_EWM_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT I2C0_DriverIRQHandler [WEAK] EXPORT I2C1_DriverIRQHandler [WEAK] EXPORT SPI0_DriverIRQHandler [WEAK] EXPORT SPI1_DriverIRQHandler [WEAK] EXPORT I2S0_Tx_DriverIRQHandler [WEAK] EXPORT I2S0_Rx_DriverIRQHandler [WEAK] EXPORT UART0_LON_DriverIRQHandler [WEAK] EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] EXPORT UART0_ERR_DriverIRQHandler [WEAK] EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] EXPORT UART1_ERR_DriverIRQHandler [WEAK] EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] EXPORT UART2_ERR_DriverIRQHandler [WEAK] EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] EXPORT UART3_ERR_DriverIRQHandler [WEAK] EXPORT ADC0_IRQHandler [WEAK] EXPORT CMP0_IRQHandler [WEAK] EXPORT CMP1_IRQHandler [WEAK] EXPORT FTM0_IRQHandler [WEAK] EXPORT FTM1_IRQHandler [WEAK] EXPORT FTM2_IRQHandler [WEAK] EXPORT CMT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT RTC_Seconds_IRQHandler [WEAK] EXPORT PIT0_IRQHandler [WEAK] EXPORT PIT1_IRQHandler [WEAK] EXPORT PIT2_IRQHandler [WEAK] EXPORT PIT3_IRQHandler [WEAK] EXPORT PDB0_IRQHandler [WEAK] EXPORT USB0_IRQHandler [WEAK] EXPORT USBDCD_IRQHandler [WEAK] EXPORT Reserved71_IRQHandler [WEAK] EXPORT DAC0_IRQHandler [WEAK] EXPORT MCG_IRQHandler [WEAK] EXPORT LPTMR0_IRQHandler [WEAK] EXPORT PORTA_IRQHandler [WEAK] EXPORT PORTB_IRQHandler [WEAK] EXPORT PORTC_IRQHandler [WEAK] EXPORT PORTD_IRQHandler [WEAK] EXPORT PORTE_IRQHandler [WEAK] EXPORT SWI_IRQHandler [WEAK] EXPORT SPI2_DriverIRQHandler [WEAK] EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] EXPORT UART4_ERR_DriverIRQHandler [WEAK] EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] EXPORT UART5_ERR_DriverIRQHandler [WEAK] EXPORT CMP2_IRQHandler [WEAK] EXPORT FTM3_IRQHandler [WEAK] EXPORT DAC1_IRQHandler [WEAK] EXPORT ADC1_IRQHandler [WEAK] EXPORT I2C2_DriverIRQHandler [WEAK] EXPORT CAN0_DriverIRQHandler [WEAK] EXPORT SDHC_DriverIRQHandler [WEAK] EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] EXPORT ENET_Transmit_DriverIRQHandler [WEAK] EXPORT ENET_Receive_DriverIRQHandler [WEAK] EXPORT ENET_Error_DriverIRQHandler [WEAK] EXPORT DefaultISR [WEAK] DMA0_DriverIRQHandler DMA1_DriverIRQHandler DMA2_DriverIRQHandler DMA3_DriverIRQHandler DMA4_DriverIRQHandler DMA5_DriverIRQHandler DMA6_DriverIRQHandler DMA7_DriverIRQHandler DMA8_DriverIRQHandler DMA9_DriverIRQHandler DMA10_DriverIRQHandler DMA11_DriverIRQHandler DMA12_DriverIRQHandler DMA13_DriverIRQHandler DMA14_DriverIRQHandler DMA15_DriverIRQHandler DMA_Error_DriverIRQHandler MCM_IRQHandler FTFE_IRQHandler Read_Collision_IRQHandler LVD_LVW_IRQHandler LLWU_IRQHandler WDOG_EWM_IRQHandler RNG_IRQHandler I2C0_DriverIRQHandler I2C1_DriverIRQHandler SPI0_DriverIRQHandler SPI1_DriverIRQHandler I2S0_Tx_DriverIRQHandler I2S0_Rx_DriverIRQHandler UART0_LON_DriverIRQHandler UART0_RX_TX_DriverIRQHandler UART0_ERR_DriverIRQHandler UART1_RX_TX_DriverIRQHandler UART1_ERR_DriverIRQHandler UART2_RX_TX_DriverIRQHandler UART2_ERR_DriverIRQHandler UART3_RX_TX_DriverIRQHandler UART3_ERR_DriverIRQHandler ADC0_IRQHandler CMP0_IRQHandler CMP1_IRQHandler FTM0_IRQHandler FTM1_IRQHandler FTM2_IRQHandler CMT_IRQHandler RTC_IRQHandler RTC_Seconds_IRQHandler PIT0_IRQHandler PIT1_IRQHandler PIT2_IRQHandler PIT3_IRQHandler PDB0_IRQHandler USB0_IRQHandler USBDCD_IRQHandler Reserved71_IRQHandler DAC0_IRQHandler MCG_IRQHandler LPTMR0_IRQHandler PORTA_IRQHandler PORTB_IRQHandler PORTC_IRQHandler PORTD_IRQHandler PORTE_IRQHandler SWI_IRQHandler SPI2_DriverIRQHandler UART4_RX_TX_DriverIRQHandler UART4_ERR_DriverIRQHandler UART5_RX_TX_DriverIRQHandler UART5_ERR_DriverIRQHandler CMP2_IRQHandler FTM3_IRQHandler DAC1_IRQHandler ADC1_IRQHandler I2C2_DriverIRQHandler CAN0_DriverIRQHandler SDHC_DriverIRQHandler ENET_1588_Timer_DriverIRQHandler ENET_Transmit_DriverIRQHandler ENET_Receive_DriverIRQHandler ENET_Error_DriverIRQHandler DefaultISR LDR R0, =DefaultISR BX R0 ENDP ALIGN END ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/startup_MK64F12.s.0000 ================================================ ;/***************************************************************************** ; * @file: startup_MK64F12.s ; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the ; * MK64F12 ; * @version: 2.3 ; * @date: 2014-1-24 ; * ; * Copyright: 1997 - 2014 Freescale Semiconductor, Inc. All Rights Reserved. ;* ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * ; *****************************************************************************/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete DCD DMA_Error_IRQHandler ; DMA Error Interrupt DCD MCM_IRQHandler ; Normal Interrupt DCD FTFE_IRQHandler ; FTFE Command complete interrupt DCD Read_Collision_IRQHandler ; Read Collision Interrupt DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning DCD LLW_IRQHandler ; Low Leakage Wakeup DCD Watchdog_IRQHandler ; WDOG Interrupt DCD RNG_IRQHandler ; RNG Interrupt DCD I2C0_IRQHandler ; I2C0 interrupt DCD I2C1_IRQHandler ; I2C1 interrupt DCD SPI0_IRQHandler ; SPI0 Interrupt DCD SPI1_IRQHandler ; SPI1 Interrupt DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt DCD UART0_LON_IRQHandler ; UART0 LON interrupt DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt DCD UART0_ERR_IRQHandler ; UART0 Error interrupt DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt DCD UART1_ERR_IRQHandler ; UART1 Error interrupt DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt DCD UART2_ERR_IRQHandler ; UART2 Error interrupt DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt DCD UART3_ERR_IRQHandler ; UART3 Error interrupt DCD ADC0_IRQHandler ; ADC0 interrupt DCD CMP0_IRQHandler ; CMP0 interrupt DCD CMP1_IRQHandler ; CMP1 interrupt DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt DCD CMT_IRQHandler ; CMT interrupt DCD RTC_IRQHandler ; RTC interrupt DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt DCD PDB0_IRQHandler ; PDB0 Interrupt DCD USB0_IRQHandler ; USB0 interrupt DCD USBDCD_IRQHandler ; USBDCD Interrupt DCD Reserved71_IRQHandler ; Reserved interrupt 71 DCD DAC0_IRQHandler ; DAC0 interrupt DCD MCG_IRQHandler ; MCG Interrupt DCD LPTimer_IRQHandler ; LPTimer interrupt DCD PORTA_IRQHandler ; Port A interrupt DCD PORTB_IRQHandler ; Port B interrupt DCD PORTC_IRQHandler ; Port C interrupt DCD PORTD_IRQHandler ; Port D interrupt DCD PORTE_IRQHandler ; Port E interrupt DCD SWI_IRQHandler ; Software interrupt DCD SPI2_IRQHandler ; SPI2 Interrupt DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt DCD UART4_ERR_IRQHandler ; UART4 Error interrupt DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt DCD UART5_ERR_IRQHandler ; UART5 Error interrupt DCD CMP2_IRQHandler ; CMP2 interrupt DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt DCD DAC1_IRQHandler ; DAC1 interrupt DCD ADC1_IRQHandler ; ADC1 interrupt DCD I2C2_IRQHandler ; I2C2 interrupt DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt DCD CAN0_Error_IRQHandler ; CAN0 error interrupt DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt DCD SDHC_IRQHandler ; SDHC interrupt DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 Timer Interrupt DCD ENET_Transmit_IRQHandler ; Ethernet MAC Transmit Interrupt DCD ENET_Receive_IRQHandler ; Ethernet MAC Receive Interrupt DCD ENET_Error_IRQHandler ; Ethernet MAC Error and miscelaneous Interrupt DCD DefaultISR ; 102 DCD DefaultISR ; 103 DCD DefaultISR ; 104 DCD DefaultISR ; 105 DCD DefaultISR ; 106 DCD DefaultISR ; 107 DCD DefaultISR ; 108 DCD DefaultISR ; 109 DCD DefaultISR ; 110 DCD DefaultISR ; 111 DCD DefaultISR ; 112 DCD DefaultISR ; 113 DCD DefaultISR ; 114 DCD DefaultISR ; 115 DCD DefaultISR ; 116 DCD DefaultISR ; 117 DCD DefaultISR ; 118 DCD DefaultISR ; 119 DCD DefaultISR ; 120 DCD DefaultISR ; 121 DCD DefaultISR ; 122 DCD DefaultISR ; 123 DCD DefaultISR ; 124 DCD DefaultISR ; 125 DCD DefaultISR ; 126 DCD DefaultISR ; 127 DCD DefaultISR ; 128 DCD DefaultISR ; 129 DCD DefaultISR ; 130 DCD DefaultISR ; 131 DCD DefaultISR ; 132 DCD DefaultISR ; 133 DCD DefaultISR ; 134 DCD DefaultISR ; 135 DCD DefaultISR ; 136 DCD DefaultISR ; 137 DCD DefaultISR ; 138 DCD DefaultISR ; 139 DCD DefaultISR ; 140 DCD DefaultISR ; 141 DCD DefaultISR ; 142 DCD DefaultISR ; 143 DCD DefaultISR ; 144 DCD DefaultISR ; 145 DCD DefaultISR ; 146 DCD DefaultISR ; 147 DCD DefaultISR ; 148 DCD DefaultISR ; 149 DCD DefaultISR ; 150 DCD DefaultISR ; 151 DCD DefaultISR ; 152 DCD DefaultISR ; 153 DCD DefaultISR ; 154 DCD DefaultISR ; 155 DCD DefaultISR ; 156 DCD DefaultISR ; 157 DCD DefaultISR ; 158 DCD DefaultISR ; 159 DCD DefaultISR ; 160 DCD DefaultISR ; 161 DCD DefaultISR ; 162 DCD DefaultISR ; 163 DCD DefaultISR ; 164 DCD DefaultISR ; 165 DCD DefaultISR ; 166 DCD DefaultISR ; 167 DCD DefaultISR ; 168 DCD DefaultISR ; 169 DCD DefaultISR ; 170 DCD DefaultISR ; 171 DCD DefaultISR ; 172 DCD DefaultISR ; 173 DCD DefaultISR ; 174 DCD DefaultISR ; 175 DCD DefaultISR ; 176 DCD DefaultISR ; 177 DCD DefaultISR ; 178 DCD DefaultISR ; 179 DCD DefaultISR ; 180 DCD DefaultISR ; 181 DCD DefaultISR ; 182 DCD DefaultISR ; 183 DCD DefaultISR ; 184 DCD DefaultISR ; 185 DCD DefaultISR ; 186 DCD DefaultISR ; 187 DCD DefaultISR ; 188 DCD DefaultISR ; 189 DCD DefaultISR ; 190 DCD DefaultISR ; 191 DCD DefaultISR ; 192 DCD DefaultISR ; 193 DCD DefaultISR ; 194 DCD DefaultISR ; 195 DCD DefaultISR ; 196 DCD DefaultISR ; 197 DCD DefaultISR ; 198 DCD DefaultISR ; 199 DCD DefaultISR ; 200 DCD DefaultISR ; 201 DCD DefaultISR ; 202 DCD DefaultISR ; 203 DCD DefaultISR ; 204 DCD DefaultISR ; 205 DCD DefaultISR ; 206 DCD DefaultISR ; 207 DCD DefaultISR ; 208 DCD DefaultISR ; 209 DCD DefaultISR ; 210 DCD DefaultISR ; 211 DCD DefaultISR ; 212 DCD DefaultISR ; 213 DCD DefaultISR ; 214 DCD DefaultISR ; 215 DCD DefaultISR ; 216 DCD DefaultISR ; 217 DCD DefaultISR ; 218 DCD DefaultISR ; 219 DCD DefaultISR ; 220 DCD DefaultISR ; 221 DCD DefaultISR ; 222 DCD DefaultISR ; 223 DCD DefaultISR ; 224 DCD DefaultISR ; 225 DCD DefaultISR ; 226 DCD DefaultISR ; 227 DCD DefaultISR ; 228 DCD DefaultISR ; 229 DCD DefaultISR ; 230 DCD DefaultISR ; 231 DCD DefaultISR ; 232 DCD DefaultISR ; 233 DCD DefaultISR ; 234 DCD DefaultISR ; 235 DCD DefaultISR ; 236 DCD DefaultISR ; 237 DCD DefaultISR ; 238 DCD DefaultISR ; 239 DCD DefaultISR ; 240 DCD DefaultISR ; 241 DCD DefaultISR ; 242 DCD DefaultISR ; 243 DCD DefaultISR ; 244 DCD DefaultISR ; 245 DCD DefaultISR ; 246 DCD DefaultISR ; 247 DCD DefaultISR ; 248 DCD DefaultISR ; 249 DCD DefaultISR ; 250 DCD DefaultISR ; 251 DCD DefaultISR ; 252 DCD DefaultISR ; 253 DCD DefaultISR ; 254 DCD DefaultISR ; 255 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors ; Flash Configuration ; 16-byte flash configuration field that stores default protection settings (loaded on reset) ; and security information that allows the MCU to restrict acces to the FTFL module. ; Backdoor Comparison Key ; Backdoor Key 0 <0x0-0xFF:2> ; Backdoor Key 1 <0x0-0xFF:2> ; Backdoor Key 2 <0x0-0xFF:2> ; Backdoor Key 3 <0x0-0xFF:2> ; Backdoor Key 4 <0x0-0xFF:2> ; Backdoor Key 5 <0x0-0xFF:2> ; Backdoor Key 6 <0x0-0xFF:2> ; Backdoor Key 7 <0x0-0xFF:2> BackDoorK0 EQU 0xFF BackDoorK1 EQU 0xFF BackDoorK2 EQU 0xFF BackDoorK3 EQU 0xFF BackDoorK4 EQU 0xFF BackDoorK5 EQU 0xFF BackDoorK6 EQU 0xFF BackDoorK7 EQU 0xFF ; ; Program flash protection bytes (FPROT) ; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. ; Each bit protects a 1/32 region of the program flash memory. ; FPROT0 ; Program flash protection bytes ; 1/32 - 8/32 region ; FPROT0.0 ; FPROT0.1 ; FPROT0.2 ; FPROT0.3 ; FPROT0.4 ; FPROT0.5 ; FPROT0.6 ; FPROT0.7 nFPROT0 EQU 0x00 FPROT0 EQU nFPROT0:EOR:0xFF ; ; FPROT1 ; Program Flash Region Protect Register 1 ; 9/32 - 16/32 region ; FPROT1.0 ; FPROT1.1 ; FPROT1.2 ; FPROT1.3 ; FPROT1.4 ; FPROT1.5 ; FPROT1.6 ; FPROT1.7 nFPROT1 EQU 0x00 FPROT1 EQU nFPROT1:EOR:0xFF ; ; FPROT2 ; Program Flash Region Protect Register 2 ; 17/32 - 24/32 region ; FPROT2.0 ; FPROT2.1 ; FPROT2.2 ; FPROT2.3 ; FPROT2.4 ; FPROT2.5 ; FPROT2.6 ; FPROT2.7 nFPROT2 EQU 0x00 FPROT2 EQU nFPROT2:EOR:0xFF ; ; FPROT3 ; Program Flash Region Protect Register 3 ; 25/32 - 32/32 region ; FPROT3.0 ; FPROT3.1 ; FPROT3.2 ; FPROT3.3 ; FPROT3.4 ; FPROT3.5 ; FPROT3.6 ; FPROT3.7 nFPROT3 EQU 0x00 FPROT3 EQU nFPROT3:EOR:0xFF ; ; ; Data flash protection byte (FDPROT) ; Each bit protects a 1/8 region of the data flash memory. ; (Program flash only devices: Reserved) ; FDPROT.0 ; FDPROT.1 ; FDPROT.2 ; FDPROT.3 ; FDPROT.4 ; FDPROT.5 ; FDPROT.6 ; FDPROT.7 nFDPROT EQU 0x00 FDPROT EQU nFDPROT:EOR:0xFF ; ; EEPROM protection byte (FEPROT) ; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. ; (Program flash only devices: Reserved) ; FEPROT.0 ; FEPROT.1 ; FEPROT.2 ; FEPROT.3 ; FEPROT.4 ; FEPROT.5 ; FEPROT.6 ; FEPROT.7 nFEPROT EQU 0x00 FEPROT EQU nFEPROT:EOR:0xFF ; ; Flash nonvolatile option byte (FOPT) ; Allows the user to customize the operation of the MCU at boot time. ; LPBOOT ; <0=> Low-power boot ; <1=> normal boot ; EZPORT_DIS ; <0=> EzPort operation is enabled ; <1=> EzPort operation is disabled FOPT EQU 0xFF ; ; Flash security byte (FSEC) ; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", ; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! ; SEC ; <2=> MCU security status is unsecure ; <3=> MCU security status is secure ; Flash Security ; This bits define the security state of the MCU. ; FSLACC ; <2=> Freescale factory access denied ; <3=> Freescale factory access granted ; Freescale Failure Analysis Access Code ; This bits define the security state of the MCU. ; MEEN ; <2=> Mass erase is disabled ; <3=> Mass erase is enabled ; Mass Erase Enable Bits ; Enables and disables mass erase capability of the FTFL module ; KEYEN ; <2=> Backdoor key access enabled ; <3=> Backdoor key access disabled ; Backdoor key Security Enable ; These bits enable and disable backdoor key access to the FTFL module. FSEC EQU 0xFE ; ; IF :LNOT::DEF:RAM_TARGET AREA |.ARM.__at_0x400|, CODE, READONLY DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 DCB FPROT0, FPROT1, FPROT2, FPROT3 DCB FSEC, FOPT, FEPROT, FDPROT ENDIF AREA |.text|, CODE, READONLY ;init_data_bss ; User defined function for data and bs memory segment initialization. ; Weak definition to be replaced by user code. init_data_bss PROC EXPORT init_data_bss [WEAK] BX R14 ENDP ; Reset Handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =init_data_bss BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT DMA0_IRQHandler [WEAK] EXPORT DMA1_IRQHandler [WEAK] EXPORT DMA2_IRQHandler [WEAK] EXPORT DMA3_IRQHandler [WEAK] EXPORT DMA4_IRQHandler [WEAK] EXPORT DMA5_IRQHandler [WEAK] EXPORT DMA6_IRQHandler [WEAK] EXPORT DMA7_IRQHandler [WEAK] EXPORT DMA8_IRQHandler [WEAK] EXPORT DMA9_IRQHandler [WEAK] EXPORT DMA10_IRQHandler [WEAK] EXPORT DMA11_IRQHandler [WEAK] EXPORT DMA12_IRQHandler [WEAK] EXPORT DMA13_IRQHandler [WEAK] EXPORT DMA14_IRQHandler [WEAK] EXPORT DMA15_IRQHandler [WEAK] EXPORT DMA_Error_IRQHandler [WEAK] EXPORT MCM_IRQHandler [WEAK] EXPORT FTFE_IRQHandler [WEAK] EXPORT Read_Collision_IRQHandler [WEAK] EXPORT LVD_LVW_IRQHandler [WEAK] EXPORT LLW_IRQHandler [WEAK] EXPORT Watchdog_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT I2C0_IRQHandler [WEAK] EXPORT I2C1_IRQHandler [WEAK] EXPORT SPI0_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT I2S0_Tx_IRQHandler [WEAK] EXPORT I2S0_Rx_IRQHandler [WEAK] EXPORT UART0_LON_IRQHandler [WEAK] EXPORT UART0_RX_TX_IRQHandler [WEAK] EXPORT UART0_ERR_IRQHandler [WEAK] EXPORT UART1_RX_TX_IRQHandler [WEAK] EXPORT UART1_ERR_IRQHandler [WEAK] EXPORT UART2_RX_TX_IRQHandler [WEAK] EXPORT UART2_ERR_IRQHandler [WEAK] EXPORT UART3_RX_TX_IRQHandler [WEAK] EXPORT UART3_ERR_IRQHandler [WEAK] EXPORT ADC0_IRQHandler [WEAK] EXPORT CMP0_IRQHandler [WEAK] EXPORT CMP1_IRQHandler [WEAK] EXPORT FTM0_IRQHandler [WEAK] EXPORT FTM1_IRQHandler [WEAK] EXPORT FTM2_IRQHandler [WEAK] EXPORT CMT_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT RTC_Seconds_IRQHandler [WEAK] EXPORT PIT0_IRQHandler [WEAK] EXPORT PIT1_IRQHandler [WEAK] EXPORT PIT2_IRQHandler [WEAK] EXPORT PIT3_IRQHandler [WEAK] EXPORT PDB0_IRQHandler [WEAK] EXPORT USB0_IRQHandler [WEAK] EXPORT USBDCD_IRQHandler [WEAK] EXPORT Reserved71_IRQHandler [WEAK] EXPORT DAC0_IRQHandler [WEAK] EXPORT MCG_IRQHandler [WEAK] EXPORT LPTimer_IRQHandler [WEAK] EXPORT PORTA_IRQHandler [WEAK] EXPORT PORTB_IRQHandler [WEAK] EXPORT PORTC_IRQHandler [WEAK] EXPORT PORTD_IRQHandler [WEAK] EXPORT PORTE_IRQHandler [WEAK] EXPORT SWI_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT UART4_RX_TX_IRQHandler [WEAK] EXPORT UART4_ERR_IRQHandler [WEAK] EXPORT UART5_RX_TX_IRQHandler [WEAK] EXPORT UART5_ERR_IRQHandler [WEAK] EXPORT CMP2_IRQHandler [WEAK] EXPORT FTM3_IRQHandler [WEAK] EXPORT DAC1_IRQHandler [WEAK] EXPORT ADC1_IRQHandler [WEAK] EXPORT I2C2_IRQHandler [WEAK] EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] EXPORT CAN0_Bus_Off_IRQHandler [WEAK] EXPORT CAN0_Error_IRQHandler [WEAK] EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] EXPORT CAN0_Wake_Up_IRQHandler [WEAK] EXPORT SDHC_IRQHandler [WEAK] EXPORT ENET_1588_Timer_IRQHandler [WEAK] EXPORT ENET_Transmit_IRQHandler [WEAK] EXPORT ENET_Receive_IRQHandler [WEAK] EXPORT ENET_Error_IRQHandler [WEAK] EXPORT DefaultISR [WEAK] DMA0_IRQHandler DMA1_IRQHandler DMA2_IRQHandler DMA3_IRQHandler DMA4_IRQHandler DMA5_IRQHandler DMA6_IRQHandler DMA7_IRQHandler DMA8_IRQHandler DMA9_IRQHandler DMA10_IRQHandler DMA11_IRQHandler DMA12_IRQHandler DMA13_IRQHandler DMA14_IRQHandler DMA15_IRQHandler DMA_Error_IRQHandler MCM_IRQHandler FTFE_IRQHandler Read_Collision_IRQHandler LVD_LVW_IRQHandler LLW_IRQHandler Watchdog_IRQHandler RNG_IRQHandler I2C0_IRQHandler I2C1_IRQHandler SPI0_IRQHandler SPI1_IRQHandler I2S0_Tx_IRQHandler I2S0_Rx_IRQHandler UART0_LON_IRQHandler UART0_RX_TX_IRQHandler UART0_ERR_IRQHandler UART1_RX_TX_IRQHandler UART1_ERR_IRQHandler UART2_RX_TX_IRQHandler UART2_ERR_IRQHandler UART3_RX_TX_IRQHandler UART3_ERR_IRQHandler ADC0_IRQHandler CMP0_IRQHandler CMP1_IRQHandler FTM0_IRQHandler FTM1_IRQHandler FTM2_IRQHandler CMT_IRQHandler RTC_IRQHandler RTC_Seconds_IRQHandler PIT0_IRQHandler PIT1_IRQHandler PIT2_IRQHandler PIT3_IRQHandler PDB0_IRQHandler USB0_IRQHandler USBDCD_IRQHandler Reserved71_IRQHandler DAC0_IRQHandler MCG_IRQHandler LPTimer_IRQHandler PORTA_IRQHandler PORTB_IRQHandler PORTC_IRQHandler PORTD_IRQHandler PORTE_IRQHandler SWI_IRQHandler SPI2_IRQHandler UART4_RX_TX_IRQHandler UART4_ERR_IRQHandler UART5_RX_TX_IRQHandler UART5_ERR_IRQHandler CMP2_IRQHandler FTM3_IRQHandler DAC1_IRQHandler ADC1_IRQHandler I2C2_IRQHandler CAN0_ORed_Message_buffer_IRQHandler CAN0_Bus_Off_IRQHandler CAN0_Error_IRQHandler CAN0_Tx_Warning_IRQHandler CAN0_Rx_Warning_IRQHandler CAN0_Wake_Up_IRQHandler SDHC_IRQHandler ENET_1588_Timer_IRQHandler ENET_Transmit_IRQHandler ENET_Receive_IRQHandler ENET_Error_IRQHandler DefaultISR B . ENDP ALIGN ; User Initial Stack & Heap IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/system_MK64F12.c ================================================ /* ** ################################################################### ** Processors: MK64FN1M0CAJ12 ** MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** MK64FX512VDC12 ** MK64FX512VLL12 ** MK64FX512VLQ12 ** MK64FX512VMD12 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 ** Build: b170713 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** - rev. 2.4 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** - rev. 2.5 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** Module access macro module_BASES replaced by module_BASE_PTRS. ** - rev. 2.6 (2014-08-28) ** Update of system files - default clock configuration changed. ** Update of startup files - possibility to override DefaultISR added. ** - rev. 2.7 (2014-10-14) ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. ** - rev. 2.8 (2015-02-19) ** Renamed interrupt vector LLW to LLWU. ** - rev. 2.9 (2016-03-21) ** Added MK64FN1M0CAJ12 part. ** GPIO - renamed port instances: PTx -> GPIOx. ** ** ################################################################### */ /*! * @file MK64F12 * @version 2.9 * @date 2016-03-21 * @brief Device specific configuration file for MK64F12 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ #include #include "fsl_device_registers.h" /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ #if (DISABLE_WDOG) /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; #endif /* (DISABLE_WDOG) */ } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate (void) { uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ uint16_t Divider; if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { /* Output of FLL or PLL is selected */ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { /* FLL is selected */ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { /* External reference clock is selected */ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { case 0x00U: MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ break; case 0x01U: MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ break; case 0x02U: default: MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ break; } if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { switch (MCG->C1 & MCG_C1_FRDIV_MASK) { case 0x38U: Divider = 1536U; break; case 0x30U: Divider = 1280U; break; default: Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); break; } } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); } MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ /* Select correct multiplier to calculate the MCG output clock */ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { case 0x00U: MCGOUTClock *= 640U; break; case 0x20U: MCGOUTClock *= 1280U; break; case 0x40U: MCGOUTClock *= 1920U; break; case 0x60U: MCGOUTClock *= 2560U; break; case 0x80U: MCGOUTClock *= 732U; break; case 0xA0U: MCGOUTClock *= 1464U; break; case 0xC0U: MCGOUTClock *= 2197U; break; case 0xE0U: MCGOUTClock *= 2929U; break; default: break; } } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ /* PLL is selected */ Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); MCGOUTClock *= Divider; /* Calculate the MCG output clock */ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { /* Internal reference clock is selected */ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { /* External reference clock is selected */ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { case 0x00U: MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ break; case 0x01U: MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ break; case 0x02U: default: MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ break; } } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ /* Reserved value */ return; } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); } ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/system_MK64F12.c.0000 ================================================ /* ** ################################################################### ** Processor: MK64FN1M0VMD12 ** Compilers: ARM Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.3, 2014-01-24 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright: 2014 Freescale, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-29) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** ** ################################################################### */ /*! * @file MK64F12 * @version 2.3 * @date 2014-01-24 * @brief Device specific configuration file for MK64F12 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ #include #include "MK64F12.h" #define DISABLE_WDOG 1 #define CLOCK_SETUP 0 /* Predefined clock setups 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode Default part configuration. Reference clock source for MCG module is the slow internal clock source 32.768kHz Core clock = 20.97MHz, BusClock = 20.97MHz 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Maximum achievable clock frequency configuration. Reference clock source for MCG module is an external clock source 50MHz Core clock = 120MHz, BusClock = 60MHz 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication The clock settings is ready for Very Low Power Run mode. Core clock = 4MHz, BusClock = 4MHz 3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz The clock settings is ready for Very Low Power Run mode. Core clock = 32.768kHz, BusClock = 32.768kHz 4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode USB clock setup USB clock divider is set for USB to receive 48MHz input clock. Reference clock source for MCG module is an external clock source 50MHz USB clock divider is set for USB to receive 48MHz input clock. Core clock = 120MHz, BusClock = 60MHz */ /*---------------------------------------------------------------------------- Define clock source values *----------------------------------------------------------------------------*/ #if (CLOCK_SETUP == 0) #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */ #elif (CLOCK_SETUP == 1) #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ #elif (CLOCK_SETUP == 2) #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ #elif (CLOCK_SETUP == 3) #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */ #elif (CLOCK_SETUP == 4) #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ #endif /* (CLOCK_SETUP == 4) */ /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ #if (DISABLE_WDOG) /* Disable the WDOG module */ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG->STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; #endif /* (DISABLE_WDOG) */ #if (CLOCK_SETUP == 0) /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x01) | SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */ /* SIM->SOPT2: PLLFLLSEL=0 */ SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ /* SIM->SOPT1: OSC32KSEL=3 */ SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* Switch to FEI Mode */ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; /* MCG->C2: LOCRE0=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ MCG->C2 = MCG_C2_RANGE(0x00); /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* OSC->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC->CR = OSC_CR_ERCLKEN_MASK; /* MCG->C7: OSCSEL=0 */ MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ MCG->C5 = MCG_C5_PRDIV0(0x00); /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG->C6 = MCG_C6_VDIV0(0x00); while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ } while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ } #elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4) /* SIM->SCGC5: PORTA=1 */ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x02) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM->SOPT2: PLLFLLSEL=1 */ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM->SOPT1: OSC32KSEL=3 */ SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* PORTA->PCR[18]: ISF=0,MUX=0 */ PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG->C2: LOCRE0=0,??=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */ MCG->C2 = MCG_C2_RANGE(0x02); /* OSC->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC->CR = OSC_CR_ERCLKEN_MASK; /* MCG->C7: OSCSEL=0 */ MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK); /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ MCG->C5 = MCG_C5_PRDIV0(0x13); /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */ MCG->C6 = MCG_C6_VDIV0(0x18); while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18)); while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK); while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } #if (CLOCK_SETUP == 4) /* Set USB input clock to 48MHz */ /* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)( SIM_CLKDIV2_USBDIV(0x03) )) | (uint32_t)( SIM_CLKDIV2_USBDIV(0x04) | SIM_CLKDIV2_USBFRAC_MASK )); #endif #elif (CLOCK_SETUP == 2) /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x00) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM->SOPT2: PLLFLLSEL=0 */ SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ /* SIM->SOPT1: OSC32KSEL=3 */ SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* MCG->SC: FCRDIV=0 */ MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07)); /* Switch to FBI Mode */ /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = MCG_C1_CLKS(0x01) | MCG_C1_FRDIV(0x00) | MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; /* MCG->C2: LOCRE0=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=1 */ MCG->C2 = (MCG_C2_RANGE(0x00) | MCG_C2_IRCS_MASK); /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* OSC->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC->CR = OSC_CR_ERCLKEN_MASK; /* MCG->C7: OSCSEL=0 */ MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ MCG->C5 = MCG_C5_PRDIV0(0x00); /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG->C6 = MCG_C6_VDIV0(0x00); while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ } while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ } /* Switch to BLPI Mode */ /* MCG->C2: LOCRE0=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=1,IRCS=1 */ MCG->C2 = (MCG_C2_RANGE(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK); while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ } while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */ } #elif (CLOCK_SETUP == 3) /* SIM->SCGC6: RTC=1 */ SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */ /* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ RTC->CR &= (uint32_t)~(uint32_t)( RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK ); /* RTC->CR: OSCE=1 */ RTC->CR |= RTC_CR_OSCE_MASK; /* RTC->CR: CLKO=0 */ RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK); } /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x00) | SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */ /* SIM->SOPT1: OSC32KSEL=2 */ SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)( SIM_SOPT1_OSC32KSEL(0x01) )) | (uint32_t)( SIM_SOPT1_OSC32KSEL(0x02) )); /* System oscillator drives 32 kHz clock for various peripherals */ /* Switch to FBE Mode */ /* MCG->C2: LOCRE0=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ MCG->C2 = MCG_C2_RANGE(0x00); /* OSC->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC->CR = OSC_CR_ERCLKEN_MASK; /* MCG->C7: OSCSEL=1 */ MCG->C7 |= MCG_C7_OSCSEL_MASK; /* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK); /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ MCG->C5 = MCG_C5_PRDIV0(0x00); /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG->C6 = MCG_C6_VDIV0(0x00); while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to BLPE Mode */ /* MCG->C2: LOCRE0=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=1,IRCS=0 */ MCG->C2 = (MCG_C2_RANGE(0x00) | MCG_C2_LP_MASK); while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } #endif } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate (void) { uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ uint8_t Divider; if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { /* Output of FLL or PLL is selected */ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { /* FLL is selected */ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { /* External reference clock is selected */ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) { MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ } /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) */ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ /* Select correct multiplier to calculate the MCG output clock */ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { case 0x0u: MCGOUTClock *= 640u; break; case 0x20u: MCGOUTClock *= 1280u; break; case 0x40u: MCGOUTClock *= 1920u; break; case 0x60u: MCGOUTClock *= 2560u; break; case 0x80u: MCGOUTClock *= 732u; break; case 0xA0u: MCGOUTClock *= 1464u; break; case 0xC0u: MCGOUTClock *= 2197u; break; case 0xE0u: MCGOUTClock *= 2929u; break; default: break; } } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ /* PLL is selected */ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); MCGOUTClock *= Divider; /* Calculate the MCG output clock */ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { /* Internal reference clock is selected */ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { /* External reference clock is selected */ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ /* Reserved value */ return; } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); } ================================================ FILE: example/build/mdk/RTE/Device/MK64FN1M0xxx12/system_MK64F12.h ================================================ /* ** ################################################################### ** Processors: MK64FN1M0CAJ12 ** MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** MK64FX512VDC12 ** MK64FX512VLL12 ** MK64FX512VLQ12 ** MK64FX512VMD12 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** MCUXpresso Compiler ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.9, 2016-03-21 ** Build: b170713 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** - rev. 2.4 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** - rev. 2.5 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** Module access macro module_BASES replaced by module_BASE_PTRS. ** - rev. 2.6 (2014-08-28) ** Update of system files - default clock configuration changed. ** Update of startup files - possibility to override DefaultISR added. ** - rev. 2.7 (2014-10-14) ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. ** - rev. 2.8 (2015-02-19) ** Renamed interrupt vector LLW to LLWU. ** - rev. 2.9 (2016-03-21) ** Added MK64FN1M0CAJ12 part. ** GPIO - renamed port instances: PTx -> GPIOx. ** ** ################################################################### */ /*! * @file MK64F12 * @version 2.9 * @date 2016-03-21 * @brief Device specific configuration file for MK64F12 (header file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ #ifndef _SYSTEM_MK64F12_H_ #define _SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { #endif #include #ifndef DISABLE_WDOG #define DISABLE_WDOG 1 #endif /* Define clock source values */ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ /* RTC oscillator setting */ /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ /* Low power mode enable */ /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ /** * @brief System clock frequency (core clock) * * The system clock frequency supplied to the SysTick timer and the processor * core clock. This variable can be used by the user application to setup the * SysTick timer or configure other parameters. It may also be used by debugger to * query the frequency of the debug timer or configure the trace clock speed * SystemCoreClock is initialized with a correct predefined value. */ extern uint32_t SystemCoreClock; /** * @brief Setup the microcontroller system. * * Typically this function configures the oscillator (PLL) that is part of the * microcontroller device. For systems with variable clock speed it also updates * the variable SystemCoreClock. SystemInit is called from startup_device file. */ void SystemInit (void); /** * @brief Updates the SystemCoreClock variable. * * It must be called whenever the core clock is changed during program * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates * the current core clock. */ void SystemCoreClockUpdate (void); #ifdef __cplusplus } #endif #endif /* _SYSTEM_MK64F12_H_ */ ================================================ FILE: example/build/mdk/RTE/_FRDM-K64/RTE_Components.h ================================================ /* * Auto generated Run-Time-Environment Component Configuration File * *** Do not modify ! *** * * Project: 'Blinky' * Target: 'FRDM-K64' */ #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H /* * Define the Device Header File: */ #define CMSIS_device_header "MK64F12.h" #define RTE_Compiler_IO_STDIN /* Compiler I/O: STDIN */ #define RTE_Compiler_IO_STDIN_User /* Compiler I/O: STDIN User */ #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ #endif /* RTE_COMPONENTS_H */ ================================================ FILE: example/build/mdk/RTE/_FastModel/RTE_Components.h ================================================ /* * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * * Project: 'Blinky' * Target: 'FastModel' */ #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H /* * Define the Device Header File: */ #define CMSIS_device_header "ARMCM4_FP.h" /* Keil.ARM Compiler::Compiler:I/O:STDIN:User:1.2.0 */ #define RTE_Compiler_IO_STDIN /* Compiler I/O: STDIN */ #define RTE_Compiler_IO_STDIN_User /* Compiler I/O: STDIN User */ /* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ #endif /* RTE_COMPONENTS_H */ ================================================ FILE: example/build/mdk/RTE/_V2M-MPS2/RTE_Components.h ================================================ /* * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * * Project: 'Blinky' * Target: 'V2M-MPS2' */ #ifndef RTE_COMPONENTS_H #define RTE_COMPONENTS_H /* * Define the Device Header File: */ #define CMSIS_device_header "ARMCM4_FP.h" /* Keil.ARM Compiler::Compiler:I/O:STDIN:User:1.2.0 */ #define RTE_Compiler_IO_STDIN /* Compiler I/O: STDIN */ #define RTE_Compiler_IO_STDIN_User /* Compiler I/O: STDIN User */ /* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ #endif /* RTE_COMPONENTS_H */ ================================================ FILE: example/menu_example.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ //#include ".\app_platform\app_platform.h" #include "utilities/compiler.h" #include "utilities/ooc.h" #undef this #define this (*ptThis) /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define __declare_menu_item_template(__NAME) \ typedef struct __##__NAME __NAME; #define declare_menu_item_template(__NAME) \ __declare_menu_item_template(__NAME) #define __def_menu_item_template(__NAME) \ struct __##__NAME { \ menu_item_t; #define def_menu_item_template(__NAME) \ __def_menu_item_template(__NAME) #define end_def_menu_item_template(__NAME) \ }; #define __def_menu(__NAME, __PARENT, __ENGINE, __TEMPLATE) \ extern const menu_t c_tMenu##__NAME; \ __TEMPLATE c_tMenu##__NAME##Items[] = { #define def_menu(__NAME, __PARENT, __ENGINE) \ __def_menu(__NAME, (__PARENT), (__ENGINE), default_menu_item_t) #define def_menu_ex(__NAME, __PARENT, __ENGINE, __TEMPLATE) \ __def_menu(__NAME, (__PARENT), (__ENGINE), __TEMPLATE) #define __end_def_menu(__NAME, __PARENT, __ENGINE, __TEMPLATE) \ }; \ const menu_t c_tMenu##__NAME = { \ (menu_item_t *)c_tMenu##__NAME##Items, \ (sizeof(c_tMenu##__NAME##Items)/sizeof(__TEMPLATE)), \ (menu_t *)(__PARENT), \ (__ENGINE), \ }; #define end_def_menu(__NAME, __PARENT, __ENGINE) \ __end_def_menu(__NAME, (__PARENT), (__ENGINE), default_menu_item_t) #define end_def_menu_ex(__NAME, __PARENT, __ENGINE, __TEMPLATE) \ __end_def_menu(__NAME, (__PARENT), (__ENGINE), __TEMPLATE) #define __extern_menu(__NAME) extern const menu_t c_tMenu##__NAME; #define extern_menu(__NAME) __extern_menu(__NAME) #define __menu(__NAME) c_tMenu##__NAME #define menu(__NAME) __menu(__NAME) #define __menu_item(__HANDLER, __CHILD_MENU, ...) \ { \ (__HANDLER), \ (menu_t *)(__CHILD_MENU), \ __VA_ARGS__, \ }, #define menu_item(__HANDLER, __CHILD_MENU, ...) \ __menu_item((__HANDLER), (__CHILD_MENU), __VA_ARGS__) /*============================ TYPES =========================================*/ typedef struct __menu_item menu_item_t; typedef struct __menu menu_t; typedef fsm_rt_t menu_item_handler_t(menu_item_t *); struct __menu_item { menu_item_handler_t *fnHandle; //!< handler menu_t *ptChild; //!< Child Menu }; typedef struct __menu_engine_cb menu_engine_cb_t; typedef fsm_rt_t menu_engine_t(menu_engine_cb_t *); struct __menu { menu_item_t *ptItems; //!< menu item list uint_fast8_t chCount; //!< menu item count menu_t *ptParent; //!< parent menu; menu_engine_t *fnEngine; //!< engine for process current menu }; struct __menu_engine_cb { uint_fast8_t tState; const menu_t *ptCurrentMenu; uint_fast8_t chCurrentItemIndex; }; /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ declare_menu_item_template(default_menu_item_t) def_menu_item_template(default_menu_item_t) //! depends on your application, you can add/remove/change following members char *pchTitle; //!< Menu Title char *pchDescription; //!< Description for this menu item char chShortCutKey; //!< Shortcut Key value in current menu end_def_menu_item_template(default_menu_item_t) extern fsm_rt_t default_menu_engine(menu_engine_cb_t *ptMenu); extern fsm_rt_t top_menu_item_a_handler(menu_item_t *ptItem); extern fsm_rt_t top_menu_item_b_handler(menu_item_t *ptItem); extern fsm_rt_t top_menu_item_c_handler(menu_item_t *ptItem); extern_menu(lv2_menu_A) def_menu(TopMenu, NULL, default_menu_engine) menu_item( top_menu_item_a_handler, &menu(lv2_menu_A), "Top Menu A", "This is Top Menu A" ) menu_item( top_menu_item_b_handler, NULL, "Top Menu B", "This is Top Menu B" ) menu_item( top_menu_item_c_handler, NULL, "Top Menu C", "This is Top Menu C" ) end_def_menu(TopMenu, NULL, default_menu_engine) fsm_rt_t top_menu_item_a_handler(menu_item_t *ptItem) { return fsm_rt_cpl; } fsm_rt_t top_menu_item_b_handler(menu_item_t *ptItem) { return fsm_rt_cpl; } fsm_rt_t top_menu_item_c_handler(menu_item_t *ptItem) { return fsm_rt_cpl; } typedef enum { KEY_NULL = 0, KEY_DOWN, KEY_UP, KEY_ENTER, KEY_ESC, } key_t; extern key_t get_key(void); fsm_rt_t default_menu_engine(menu_engine_cb_t *ptThis) { #define DEFAULT_MENU_ENGINE_RESET_FSM() \ do { this.tState = START; } while(0) enum { START = 0, READ_KEY_EVENT, KEY_PROCESS, RUN_ITEM_HANDLER }; key_t tKey; default_menu_item_t *ptItem; switch(this.tState) { case START: this.tState++; case READ_KEY_EVENT: tKey = get_key(); if (KEY_NULL == tKey) { break; } case KEY_PROCESS: switch (tKey) { case KEY_DOWN: this.chCurrentItemIndex++; if (this.chCurrentItemIndex >= this.ptCurrentMenu->chCount) { this.chCurrentItemIndex = 0; } break; case KEY_UP: if (0 == this.chCurrentItemIndex) { this.chCurrentItemIndex = this.ptCurrentMenu->chCount - 1; } break; case KEY_ENTER: { ptItem = &((default_menu_item_t *)this.ptCurrentMenu->ptItems) [this.chCurrentItemIndex]; if (NULL != ptItem->fnHandle) { this.tState = RUN_ITEM_HANDLER; } else if (NULL != ptItem->ptChild) { this.ptCurrentMenu = ptItem->ptChild; this.chCurrentItemIndex = 0; DEFAULT_MENU_ENGINE_RESET_FSM(); return fsm_rt_cpl; } } break; case KEY_ESC: //! return to upper menu if (NULL != this.ptCurrentMenu->ptParent) { this.ptCurrentMenu = this.ptCurrentMenu->ptParent; this.chCurrentItemIndex = 0; DEFAULT_MENU_ENGINE_RESET_FSM(); return fsm_rt_cpl; } break; default: break; } break; case RUN_ITEM_HANDLER: ptItem = &((default_menu_item_t *)this.ptCurrentMenu->ptItems) [this.chCurrentItemIndex]; fsm_rt_t tFSM = ptItem->fnHandle((menu_item_t *)ptItem); if (IS_FSM_ERR(tFSM)) { //! report error DEFAULT_MENU_ENGINE_RESET_FSM(); return tFSM; } else if (fsm_rt_cpl == tFSM) { DEFAULT_MENU_ENGINE_RESET_FSM(); return fsm_rt_cpl; } break; } return fsm_rt_on_going; } extern fsm_rt_t lv2_menu_item_a_handler(menu_item_t *ptItem); def_menu(lv2_menu_A, &menu(TopMenu), default_menu_engine) menu_item( lv2_menu_item_a_handler, NULL, "Lv2 Menu A", "This is Lv2 Menu A" ) end_def_menu(lv2_menu_A, &menu(TopMenu), default_menu_engine) fsm_rt_t lv2_menu_item_a_handler(menu_item_t *ptItem) { return fsm_rt_cpl; } key_t get_key(void) { return KEY_NULL; } fsm_rt_t menu_task(menu_engine_cb_t *ptThis) { do { /* this validation code could be removed for release version */ if (NULL == ptThis) { break; } else if (NULL == this.ptCurrentMenu) { break; } else if (NULL == this.ptCurrentMenu->fnEngine) { break; } else if (NULL == this.ptCurrentMenu->ptItems) { break; } else if (0 == this.ptCurrentMenu->chCount) { break; } return this.ptCurrentMenu->fnEngine(ptThis); } while(false); return fsm_rt_err; } static menu_engine_cb_t s_tMyMenu = { .ptCurrentMenu = &menu(TopMenu), }; void example_menu_task(void) { menu_task(&s_tMyMenu); } ================================================ FILE: example/scheduler_example.c ================================================ /**************************************************************************** * Copyright 2018 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_platform\app_platform.h" #include /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define __def_fnfsm(__NAME, __CALL_DEEPTH, ...) \ declare_class(fsm(__NAME)) \ def_class(fsm(__NAME)) \ __VA_ARGS__ \ end_def_class(fsm(__NAME)) \ NO_INIT volatile safe_call_stack_item_t \ s_tfsm_##__NAME##CallStack[(__CALL_DEEPTH)+1]; \ extern fsm_rt_t fsm_##__NAME##_start(void *pArg, void *pTask); #define def_fnfsm(__NAME, ...) __def_fnfsm(__NAME, __VA_ARGS__) #define end_def_fnfsm(__NAME, ...) #define __def_fnfsm_state(__STATE) \ static fsm_rt_t fsm_##__STATE(void *pArg, void *pTask); #define def_fnfsm_state(__STATE) __def_fnfsm_state(__STATE) #define implement_fnfsm(__NAME, ...) \ \ fsm_rt_t fsm_##__NAME##_start(void *pArg, void *pTask) \ { \ fsm_rt_t tFSMReturn = fsm_rt_on_going; \ class_internal(pArg, ptThis, fsm_##__NAME##_t); \ if (NULL == ptThis) { \ return fsm_rt_err; \ } \ __VA_ARGS__; \ return tFSMReturn; \ } #define __fnfsm_state(__STATE, ...) \ static fsm_rt_t fsm_##__STATE(void *pArg, void *pTask) \ { \ fsm_rt_t tFSMReturn = fsm_rt_on_going; \ class_internal(pArg, ptThis, fsm_print_str_t); \ { \ __VA_ARGS__; \ } \ return tFSMReturn; \ } #define fnfsm_state(__STATE, ...) __fnfsm_state(__STATE, __VA_ARGS__) #define __fnfsm_transfer_to(__STATE) \ do { \ SCHEDULER.Call(pTask, fsm_##__STATE, pArg, false); \ fnfsm_on_going(); \ } while(0) #define fnfsm_transfer_to(__STATE) __fnfsm_transfer_to(__STATE) #define __fnfsm_update_state_to(__STATE) \ do { \ tFSMReturn = fsm_##__STATE(pArg, pTask); \ } while(0) #define fnfsm_update_state_to(__STATE) __fnfsm_update_state_to(__STATE) #define __fnfsm_cpl(__NAME) \ do { \ fnfsm_reset(__NAME); \ return fsm_rt_cpl; \ } while(0) #define fnfsm_cpl(__NAME) __fnfsm_cpl(__NAME) #define fnfsm_on_going() return fsm_rt_on_going; #define __fnfsm_reset(__NAME) \ do { \ SCHEDULER.Call(pTask, fsm_##__NAME##_start, pArg, false); \ }while(0) #define fnfsm_reset(__NAME) __fnfsm_reset(__NAME) #define fnfsm_body(...) __VA_ARGS__ #ifndef on_start # define on_start(...) __VA_ARGS__ #endif #ifndef def_params # define def_params(...) __VA_ARGS__ #endif #ifndef args # define args(...) ,__VA_ARGS__ #endif /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ def_fnfsm(print_str, 0, def_params( uint8_t *pchSrc; ) ) def_fnfsm_state(check) def_fnfsm_state(putchar) end_def_fnfsm(print_str) implement_fnfsm(print_str, on_start( //fnfsm_transfer_to(check); fnfsm_update_state_to(check); ) ) fnfsm_body( fnfsm_state(check, if (0 == *(this.pchSrc)) { fnfsm_cpl(print_str); } fnfsm_transfer_to(putchar); ) fnfsm_state(putchar, if (STREAM_OUT.Stream.WriteByte(*this.pchSrc)) { this.pchSrc++; fnfsm_transfer_to(check); } ) ) ================================================ FILE: example/system.c ================================================ /**************************************************************************** * Copyright 2018 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_platform\app_platform.h" #include /*============================ MACROS ========================================*/ #ifndef FRAME_BUFFER_SIZE # warning No defined FRAME_BUFFER_SIZE, default value 512 is used # define FRAME_BUFFER_SIZE (512) #endif #ifndef DELAY_OBJ_POOL_SIZE # warning No defined DELAY_OBJ_POOL_SIZE, default value 4 is used # define DELAY_OBJ_POOL_SIZE (4) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ static volatile uint32_t s_wMSTicks = 0; NO_INIT es_simple_frame_t s_tFrame; NO_INIT multiple_delay_t s_tDelayService; NO_INIT telegraph_engine_t s_tTelegraphEngine; /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*---------------------------------------------------------------------------- SysTick / Timer0 IRQ Handler *----------------------------------------------------------------------------*/ void SysTick_Handler (void) { /*! 1ms timer event handler */ s_wMSTicks++; if (!(s_wMSTicks % 1000)) { static volatile uint16_t wValue = 0; //printf("%s [%08x]\r\n", "Hello world!", wValue++); //STREAM_OUT.Stream.Flush(); } MULTIPLE_DELAY.Dependent.TimerTickService(&s_tDelayService); /*! call application platform 1ms event handler */ app_platform_1ms_event_handler(); } static void system_init(void) { //! initialise multiple delay service do { NO_INIT static multiple_delay_item_t s_tDelayObjPool[DELAY_OBJ_POOL_SIZE]; MULTIPLE_DELAY_CFG ( &s_tDelayService, (uint8_t *)s_tDelayObjPool, sizeof(s_tDelayObjPool) ); } while(false); SysTick_Config(SystemCoreClock / 1000); //!< Generate interrupt every 1 ms } #if DEMO_MULTIPLE_DELAY == ENABLED static void app_2000ms_delay_timeout_event_handler(multiple_delay_report_status_t tStatus, void *pObj) { static volatile uint16_t wValue = 0; printf("%s [%08x]\r\n", "Hello world!", wValue++); STREAM_OUT.Stream.Flush(); //! request again MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 2000, //!< request delay 2000ms MULTIPLE_DELAY_LOW_PRIORITY, //!< priority is low NULL, //!< no tag &app_2000ms_delay_timeout_event_handler); //!< timout event handler } static void app_3000ms_delay_timeout_event_handler(multiple_delay_report_status_t tStatus, void *pObj) { static volatile uint16_t wValue = 0; printf("%s [%08x]\r\n", "Apple!", wValue++); STREAM_OUT.Stream.Flush(); //! request again MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 3000, //!< request delay 3000ms MULTIPLE_DELAY_LOW_PRIORITY, //!< priority is low NULL, //!< no tag &app_3000ms_delay_timeout_event_handler); //!< timout event handler } static void app_1500ms_delay_timeout_event_handler(multiple_delay_report_status_t tStatus, void *pObj) { static volatile uint16_t wValue = 0; printf("%s [%08x]\r\n", "Orange!", wValue++); STREAM_OUT.Stream.Flush(); //! request again MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 1500, //!< request delay 1500ms MULTIPLE_DELAY_NORMAL_PRIORITY, //!< priority is normal NULL, //!< no tag &app_1500ms_delay_timeout_event_handler); //!< timout event handler } #endif #if DEMO_FRAME_USE_BLOCK_MODE == ENABLED static block_t * frame_parser(block_t *ptBlock, void *ptObj) { #define DEMO_STRING "Hello world!\r\n" do { if (NULL == ptBlock) { break; } uint8_t *pchBuffer = BLOCK.Buffer.Get(ptBlock); memcpy(&pchBuffer[1], DEMO_STRING, sizeof(DEMO_STRING)); BLOCK.Size.Set(ptBlock, sizeof(DEMO_STRING)+1); } while(false); return ptBlock; } #else static uint_fast16_t frame_parser(mem_block_t tMemory, uint_fast16_t hwSize) { return hwSize; } #endif static void app_init(void) { //! initialise simple frame service do { NO_INIT static uint8_t s_chFrameBuffer[FRAME_BUFFER_SIZE]; i_pipe_t s_tPipe = { .ReadByte = (STREAM_IN.Stream.ReadByte), .WriteByte = (STREAM_OUT.Stream.WriteByte), .Stream = { .Read = STREAM_IN.Stream.Read, .Write = STREAM_OUT.Stream.Write, }, }; #if DEMO_FRAME_USE_BLOCK_MODE == ENABLED NO_INIT static union { block_t tBlock; uint8_t chBuffer[FRAME_BUFFER_SIZE + sizeof(block_t)]; } s_tBuffer; /* typedef struct { void * pBuffer; union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint_fast8_t chAdapterID; } block_cfg_t; */ do { const block_cfg_t tCFG = { .pBuffer = NULL, .BlockSize = sizeof(s_tBuffer), //.IsNoWrite = false, //.IsNoRead = false, //.IsNoDirectAccess = false, //.chAdapterID = BLOCK_FREE_TO_ANY }; BLOCK.Init(&s_tBuffer.tBlock, (block_cfg_t *)&tCFG); } while(0); #endif //! initialise simple frame service ES_SIMPLE_FRAME_CFG( &s_tFrame, &s_tPipe, #if DEMO_FRAME_USE_BLOCK_MODE == ENABLED &frame_parser, .bStaticBufferMode = false, .ptBlock = &s_tBuffer.tBlock, .pTag = &s_tTelegraphEngine #else &frame_parser, s_chFrameBuffer, sizeof(s_chFrameBuffer) #endif ); } while(false); #if DEMO_MULTIPLE_DELAY == ENABLED MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 2000, //!< request delay 2000ms MULTIPLE_DELAY_LOW_PRIORITY, //!< priority is low NULL, //!< no tag &app_2000ms_delay_timeout_event_handler); //!< timout event handler //! request again MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 3000, //!< request delay 3000ns MULTIPLE_DELAY_LOW_PRIORITY, //!< priority is low NULL, //!< no tag &app_3000ms_delay_timeout_event_handler); //!< timout event handler //! request again MULTIPLE_DELAY.RequestDelay(&s_tDelayService, 1500, st delay 1500ms MULTIPLE_DELAY_NORMAL_PRIORITY, //!< priority is normal NULL, //!< no tag &app_1500ms_delay_timeout_event_handler); //!< timout event handler #endif } /*---------------------------------------------------------------------------- Main function *----------------------------------------------------------------------------*/ int main (void) { system_init(); app_init(); printf("for any string you entered, it will echo it back immediatly.\r\n"); while (true) { #if false if (fsm_rt_cpl == ES_SIMPLE_FRAME.Task(&s_tFrame)) { STREAM_OUT.Stream.Flush(); } #else uint8_t chByte; if (STREAM_IN.Stream.ReadByte(&chByte)) { STREAM_OUT.Stream.WriteByte(chByte ); //printf("0x%02x ", chByte); } else { STREAM_OUT.Stream.Flush(); } #endif #if DEMO_MULTIPLE_DELAY == ENABLED MULTIPLE_DELAY.Task(&s_tDelayService); #endif extern void example_menu_task(void); example_menu_task(); } } ================================================ FILE: sources/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __APP_CFG__ #define __APP_CFG__ /*============================ INCLUDES ======================================*/ //! \brief import head files #ifdef __USER_APP_CFG_H__ #include __USER_APP_CFG_H__ #else /*============================ MACROS ========================================*/ /*----------------------------------------------------------------------------* * Hardware Abstruct Layer Configuration * *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------* * Scheduler Configuration * *----------------------------------------------------------------------------*/ //! \name configure safe task service:1.2K for current configuration //! @{ #define TASK_SCHEDULER ENABLED #define SAFE_TASK_THREAD_SYNC ENABLED //!< disable semaphore support #define SAFE_TASK_CRITICAL_SECTION ENABLED //!< enable critical support #define SAFE_TASK_CALL_STACK ENABLED #define SAFE_TASK_USE_RESERVED_SYSTEM_RAM DISABLED #define SAFE_TASK_QUEUE_POOL_SIZE (1ul) //!< task queue pool size #define SAFE_TASK_POOL_SIZE (8ul) //!< task pool size //! @} /*----------------------------------------------------------------------------* * Component Configuration * *----------------------------------------------------------------------------*/ #define USE_MAL_PAGE_FREE_ACCESS ENABLED #define USE_COMPONENT_MAL_SDF_W25QXXXX DISABLED #define USE_COMPONENT_MAL_SRAM ENABLED #define USE_COMPONENT_SW_SDIO DISABLED #define USE_COMPONENT_BOOTLOADER DISABLED /*----------------------------------------------------------------------------* * Service Configuration * *----------------------------------------------------------------------------*/ #define USE_SERVICE_ES_SIMPLE_FRAME ENABLED #define USE_SERVICE_XMODEM DISABLED #define USE_SERVICE_MULTIPLE_DELAY ENABLED #define USE_SERVICE_TELEGRAPH_ENGINE ENABLED #define USE_SERVICE_BLOCK ENABLED #define USE_SERVICE_BLOCK_QUEUE ENABLED #define USE_SERVICE_STREAM_TO_BLOCK ENABLED #define USE_SERVICE_GUI_TGUI DISABLED #if USE_SERVICE_GUI_TGUI == ENABLED # define TGUI_SIZE_INT_TYPE TGUI_MEDIUM # define TGUI_COLOR_BITS TGUI_4BITS #endif #define CRC7_OPTIMIZE CRC_OPT_SPEED #define CRC8_OPTIMIZE CRC_OPT_BALANCE #define CRC8_ROHC_OPTIMIZE CRC_OPT_BALANCE #define CRC16_MODBUS_OPTIMIZE CRC_OPT_BALANCE #define CRC16_USB_OPTIMIZE CRC_OPT_BALANCE #define CRC16_CCITT_FALSE_OPTIMIZE CRC_OPT_BALANCE #define CRC32_IEEE802_3_OPTIMIZE CRC_OPT_BALANCE #define CRC32_OPTIMIZE CRC_OPT_BALANCE //! @} #endif //! \name CRC configuration //! @{ #define CRC_OPT_SIZE 2 #define CRC_OPT_BALANCE 1 #define CRC_OPT_SPEED 0 /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*============================ INCLUDES ======================================*/ #endif ================================================ FILE: sources/gmsi/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __PLATFORM_APP_CFG__ #define __PLATFORM_APP_CFG__ /*============================ INCLUDES ======================================*/ #ifdef __STORE_ENVIRONMENT_CFG_IN_HEADER_FILE__ #include "environment_cfg.h" #endif //! \brief import head files #include "utilities\compiler.h" #include "utilities\usebits.h" #include "utilities\simple_fsm.h" #include "utilities\tiny_fsm.h" #include "utilities\communicate.h" #include "utilities\template\template.h" #include "utilities\delegate.h" /*============================ MACROS ========================================*/ #define ENABLED 1 #define DISABLED 0 /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*============================ INCLUDES ======================================*/ #include "..\app_cfg.h" #endif ================================================ FILE: sources/gmsi/arch/app_cfg.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __ARCH_APP_CFG_H__ #define __ARCH_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/arch/arch.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __ARCH_H__ #define __ARCH_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #ifndef __GMSI_ARCH_HEADER # error no specified architecture #endif #include __GMSI_ARCH_HEADER /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize architecture * \param none * \retval true initialization succeeded. * \retval false initialization failed */ extern bool arch_init( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/arch/arm/app_cfg.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __ARCH_ARM_APP_CFG_H__ #define __ARCH_ARM_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/arch/arm/cortex-m/app_cfg.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __ARCH_CORTEX_M_APP_CFG_H__ #define __ARCH_CORTEX_M_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/arch/arm/cortex-m/arch_cortex-m.c ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize architecture * \param none * \retval true initialization succeeded. * \retval false initialization failed */ bool arch_init( void ) { //! add code here return true; } /* EOF */ ================================================ FILE: sources/gmsi/arch/arm/cortex-m/arch_cortex-m.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __ARCH_CORTEX_M_H__ #define __ARCH_CORTEX_M_H__ /*============================ INCLUDES ======================================*/ #include "./app_cfg.h" #include "./perf_counter/perf_counter.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize architecture * \param none * \retval true initialization succeeded. * \retval false initialization failed */ extern bool arch_init( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/default.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ __weak void SCHEDULER_INIT(void) { } /* EOF */ ================================================ FILE: sources/gmsi/gmsi.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include "./app_cfg.h" #include "./arch/arch.h" #include "./hal/hal.h" #include "./service/service.h" /*============================ MACROS ========================================*/ //! \name GMSI Interface Type //! @{ //! general purpose interface for normal MCU applicatoin #define GENERAL_PURPOSE 0 //! @} #define GMSI_PURPOSE GENERAL_PURPOSE /*! \brief interface version *! \note Change this when new generation of interface is released */ #define GMSI_INTERFACE_VERSION 1 /*! \brief major version for specified gsf interface *! \note major version is rarely changed */ #define GMSI_MAJOR_VERSION 1 /*! \brief minor version for normal maintaince *! \note update this for function update and bug fixing */ #define GMSI_MINOR_VERSION 0 /*! \brief GSF version * (InterfaceType, InterfaceVersion, MajorVersion, MinorVersion) */ #define GMSI_VERSION { \ GMSI_PURPOSE, \ GMSI_INTERFACE_VERSION, \ GMSI_MAJOR_VERSION, \ GMSI_MINOR_VERSION, \ } /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ //! \name gmsi version info //! @{ const struct { uint8_t chPurpose; //!< software framework purpose uint8_t chInterface; //!< interface version uint8_t chMajor; //!< major version uint8_t chMinor; //!< minor version } GMSIVersion = GMSI_VERSION; //! @} /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize platform * \param none * \retval true platform initialization succeeded. * \retval false platform initialization failed */ bool gmsi_platform_init( void ) { bool bResult = false; do { /* initialise architecture */ if (!arch_init()) { break; } /*! initialize hardware abstract layer */ if ( !hal_init() ) { break; } /*! initialize system services */ if ( !service_init() ) { break; } bResult = true; } while(false); #ifdef AFETER_SYSTEM_INIT AFETER_SYSTEM_INIT #endif return bResult; } /* EOF */ ================================================ FILE: sources/gmsi/gmsi.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __GMSI_FRAMEWORK_H__ #define __GMSI_FRAMEWORK_H__ /*============================ INCLUDES ======================================*/ #include "./app_cfg.h" #include "./arch/arch.h" #include "./hal/hal.h" #include "./service\/service.h" /*============================ MACROS ========================================*/ //! \name GMSI Interface Type //! @{ //! general purpose interface for normal MCU applicatoin #define GENERAL_PURPOSE 0 //! @} /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ //! \name gmsi version info //! @{ extern const struct { uint8_t chPurpose; //!< software framework purpose uint8_t chInterface; //!< interface version uint8_t chMajor; //!< major version uint8_t chMinor; //!< minor version } GMSIVersion; //! @} /*============================ PROTOTYPES ====================================*/ /*! \note initialize platform * \param none * \retval true platform initialization succeeded. * \retval false platform initialization failed */ extern bool gmsi_platform_init( void ); #endif ================================================ FILE: sources/gmsi/hal/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __HAL_APP_CFG_H__ #define __HAL_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/bsp/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __BSP_APP_CFG_H__ #define __BSP_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/bsp/bsp.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\component\component.h" #include "..\..\service\service.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize board specific package * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ bool bsp_init( void ) { //! add code here return true; } /* EOF */ ================================================ FILE: sources/gmsi/hal/bsp/bsp.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __BSP_H__ #define __BSP_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize board specific package * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ extern bool bsp_init( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/app_cfg.h ================================================ /*************************************************************************** * Copyright(C)2009-2012 by Gorgon Meducer * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU Lesser General Public License as * * published by the Free Software Foundation; either version 2 of the * * License, or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU Lesser General Public * * License along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __COMPONENT_APP_CFG_H__ #define __COMPONENT_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/bootloader/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __COMPONENT_BOOTLOADER_APP_CFG_H__ #define __COMPONENT_BOOTLOADER_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/bootloader/bootloader.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\..\..\service\service.h" #if USE_COMPONENT_BOOTLOADER == ENABLED /*============================ MACROS ========================================*/ #ifndef IAP_VERSION # define IAP_VERSION 1,0 #endif #ifndef IAP_RSP_ERROR # define IAP_RSP_ERROR 0xF0 #endif #ifndef IAP_RSP_ERROR_BL_OVERLAP # define IAP_RSP_ERROR_BL_OVERLAP 0xF1 #endif #ifndef IAP_RSP_OK # define IAP_RSP_OK 0xAC #endif # define IAP_CMD_ACK 0x01 # define IAP_CMD_WRITE_MEMORY 0x02 # define IAP_CMD_READ_MEMORY 0x03 # define IAP_CMD_CHIP_ERASE 0x04 # define IAP_CMD_RESUME 0x05 # define IAP_CMD_VERIFY_MEMORY 0x06 # define IAP_CMD_PROTECT_MEMORY 0x07 # define IAP_CMD_UNPROTECT_MEMORY 0x08 # define IAP_CMD_SECURE 0x09 #ifndef IAP_VERSION_STRING # define IAP_VERSION_STRING "Snail Bootloader" #endif #define IAP_16BIT_ADDR 0 #define IAP_32BIT_ADDR _BV(7) #ifndef IAP_ADDRESS_BIT_LENGTH # define IAP_ADDRESS_BIT_LENGTH IAP_16BIT_ADDR #endif #ifndef IAP_CFG_A # define IAP_CFG_A 0 #endif #ifndef IAP_CFG_B # define IAP_CFG_B 0 #endif #ifndef IAP_CFG_C # define IAP_CFG_C 0 #endif #ifndef IAP_DATA_BUFFER_SIZE # define IAP_DATA_BUFFER_SIZE 256 # warning no defined IAP_DATA_BUFFER_SIZE, default value 256 used. #endif #ifndef IAP_DEVICE_SIGNATURE # define IAP_DEVICE_SIGNATURE 'G','S','P' #endif #if IAP_SUPPORT_UID == ENABLED # ifndef IAP_UID_BIT_SIZE # error no defined IAP_UID_BIT_SIZE # endif # ifndef IAP_GET_UID_ADDRESS # error no defined IAP_GET_UID_ADDRESS() # endif # ifndef IAP_UID_DATA_TYPE # error no defined IAP_UID_DATA_TYPE # endif #endif #ifndef BL_MEMORY_TYPE_SET # define BL_MEMORY_TYPE_SET {0} # warning no bootloader memory type defined, please add support with macro\ BL_MEMORTY_TYPE_SET and\ BL_MEM_TYPE(__ID, __WRITE, __READ, __VERIFY, __EREASE, __PROTECT, __UNPROTECT, __SECURE) #endif #ifndef IAP_RESUME # define IAP_RESUME(__ADDRESS, __SIZE) (0) #endif #ifndef IAP_IS_DATA_DECRYPTION_ENABLED # define IAP_IS_DATA_DECRYPTION_ENABLED() (true) #endif #ifndef IAP_IS_SYSTEM_SECURED # define IAP_IS_SYSTEM_SECURED() (false) #endif #ifndef IAP_IS_DATA_PERMUTATE_ENABLED # define IAP_IS_DATA_PERMUTATE_ENABLED() (false) #endif #ifndef IAP_FRAME_PERMUTATE_DATA # define IAP_FRAME_PERMUTATE_DATA(__ADDRESS, __SIZE) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define SET_IAP_REPLY(__CMD) do {pchStream[0] = (__CMD);} while(0) #define BL_MEM_TYPE(__ID, __WRITE, __READ, __VERIFY, __EREASE, __PROTECT, __UNPROTECT, __SECURE) \ {(__ID), 0xFF, __WRITE, __READ, __VERIFY, __EREASE, __PROTECT, __UNPROTECT, __SECURE}, #define BL_MEM_TYPE_EX(__ID, __MSK,__WRITE, __READ, __VERIFY, __EREASE, __PROTECT, __UNPROTECT, __SECURE) \ {(__ID), (__MSK), __WRITE, __READ, __VERIFY, __EREASE, __PROTECT, __UNPROTECT, __SECURE}, /*============================ TYPES =========================================*/ //! \brief bootloader command handler typedef uint_fast16_t bl_cmd_handler_t(uint8_t *pchStream, uint_fast16_t hwSize); #if __IS_COMPILER_IAR__ #pragma pack(1) #endif //! \name bootloader command item //! @{ typedef struct { uint8_t chCMD; //!< command bl_cmd_handler_t *fnHandler; //!< command handler }bl_cmd_item_t; //! @} #if __IS_COMPILER_IAR__ #pragma pack() #endif #define MEM_ACCESS_WRITE 0 #define MEM_ACCESS_READ 1 #define MEM_ACCESS_VERIFY 2 #define MEM_ACCESS_ERASE 3 #define MEM_ACCESS_PROTECT 4 #define MEM_ACCESS_UNPROTECT 5 #define MEM_ACCESS_SECURE 6 //! \name memory support item //! @{ typedef struct { uint8_t chType; //!< memory type uint8_t chMask; //!< command mask union { bl_cmd_handler_t *fnAccess[7]; struct { bl_cmd_handler_t *fnWrite; //!< write memory bl_cmd_handler_t *fnRead; //!< read memory bl_cmd_handler_t *fnVerify; //!< verify memory bl_cmd_handler_t *fnErase; //!< erase whole memory bl_cmd_handler_t *fnProtect; //!< protect memory block bl_cmd_handler_t *fnUnprotect; //!< unprotect memory block bl_cmd_handler_t *fnSecurty; //!< security memory }method; }_; }bl_mem_t; //! @} #if IAP_DATA_ENCRYPT_AES == ENABLED //! \name aes decryption //! @{ typedef struct { uint16_t hwOffset; aes_key_t chKey; aes_data_t chDataMask; }aes_decrypt_t; //! @} #endif /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ static uint_fast16_t cmd_ack_handler(uint8_t *pchStream, uint_fast16_t hwSize); static uint_fast16_t cmd_memory_handler( uint8_t *pchStream, uint_fast16_t hwSize, uint_fast8_t chIndex); #if IAP_SUPPORT_WRITE_MEMORY == ENABLED static uint_fast16_t cmd_write_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_READ_MEMORY == ENABLED static uint_fast16_t cmd_read_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_CHIP_ERASE == ENABLED static uint_fast16_t cmd_chip_erase_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_RESUME == ENABLED static uint_fast16_t cmd_resume_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_VERIFY_MEMORY == ENABLED static uint_fast16_t cmd_verify_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_PROTECT_MEMORY == ENABLED static uint_fast16_t cmd_protect_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_UNPROTECT_MEMORY == ENABLED static uint_fast16_t cmd_unprotect_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif #if IAP_SUPPORT_SECURE == ENABLED static uint_fast16_t cmd_secure_handler(uint8_t *pchStream, uint_fast16_t hwSize); #endif /*============================ LOCAL VARIABLES ===============================*/ //! \brief command map FLASH static bl_cmd_item_t c_tCMDMap[]= { {IAP_CMD_ACK, &cmd_ack_handler}, //!< 0x01: Acknowledge #if IAP_SUPPORT_WRITE_MEMORY == ENABLED {IAP_CMD_WRITE_MEMORY, &cmd_write_memory_handler}, //!< 0x02: Write memory #endif #if IAP_SUPPORT_READ_MEMORY == ENABLED {IAP_CMD_READ_MEMORY, &cmd_read_memory_handler}, //!< 0x03: Read Memory #endif #if IAP_SUPPORT_CHIP_ERASE == ENABLED {IAP_CMD_CHIP_ERASE, &cmd_chip_erase_handler}, //!< 0x04: Chip Erase #endif #if IAP_SUPPORT_RESUME == ENABLED {IAP_CMD_RESUME, &cmd_resume_handler}, //!< 0x05: Resume #endif #if IAP_SUPPORT_VERIFY_MEMORY == ENABLED {IAP_CMD_VERIFY_MEMORY, &cmd_verify_memory_handler}, //!< 0x06: Verify memory #endif #if IAP_SUPPORT_PROTECT_MEMORY == ENABLED {IAP_CMD_PROTECT_MEMORY, &cmd_protect_memory_handler}, //!< 0x07: Protect memory #endif #if IAP_SUPPORT_UNPROTECT_MEMORY == ENABLED {IAP_CMD_UNPROTECT_MEMORY, &cmd_unprotect_memory_handler}, //!< 0x08: Unprotect memory #endif #if IAP_SUPPORT_SECURE == ENABLED {IAP_CMD_SECURE, &cmd_secure_handler}, //!< 0x09: Secure System #endif }; SECTION(".api_table") //! \brief bootloader memory set FLASH static bl_mem_t c_tMemory[]= { BL_MEMORY_TYPE_SET }; /*============================ IMPLEMENTATION ================================*/ /*! \brief bootloader command parser *! \param pchStream data block *! \param hwSize data block size *! \retval 0 failed in parsing *! \retval none-zero-size reply data size */ ROOT uint_fast16_t booloader_command_parser(uint8_t *pchStream, uint_fast16_t hwSize) { uint_fast8_t n = 0; uint_fast8_t chCMD = pchStream[0]; for (;n < UBOUND(c_tCMDMap);n++) { if (c_tCMDMap[n].chCMD == chCMD) { return c_tCMDMap[n].fnHandler(pchStream, hwSize); } } return 0; } /*! \brief bootloader ack command handler *! \param pchStream data block *! \param hwSize data block size *! \retval 0 failed in parsing *! \retval none-zero-size reply data size */ static uint_fast16_t cmd_ack_handler(uint8_t *pchStream, uint_fast16_t hwSize) { uint8_t chBuffer[12 #if IAP_SUPPORT_UID == ENABLED + IAP_UID_BIT_SIZE #endif #if IAP_SUPPORT_VER_STRING == ENABLED + sizeof(IAP_VERSION_STRING) #endif ] = { IAP_CMD_ACK, IAP_DEVICE_SIGNATURE, (uint8_t)(IAP_DATA_BUFFER_SIZE & 0x00FF), (IAP_DATA_BUFFER_SIZE >> 8), #if IAP_SUPPORT_WRITE_MEMORY == ENABLED _BV(0) | #endif #if IAP_SUPPORT_READ_MEMORY == ENABLED _BV(1) | #endif #if IAP_SUPPORT_CHIP_ERASE == ENABLED _BV(2) | #endif #if IAP_SUPPORT_RESUME == ENABLED _BV(3) | #endif #if IAP_SUPPORT_VERIFY_MEMORY == ENABLED _BV(4) | #endif #if IAP_SUPPORT_PROTECT_MEMORY == ENABLED _BV(5) | #endif #if IAP_SUPPORT_UNPROTECT_MEMORY == ENABLED _BV(6) | #endif #if IAP_SUPPORT_SECURE == ENABLED _BV(7) | #endif 0, IAP_CFG_A,IAP_CFG_B,IAP_CFG_C, IAP_ADDRESS_BIT_LENGTH | IAP_VERSION }; uint8_t *pchSrc = chBuffer; #if IAP_SUPPORT_VER_STRING == ENABLED const static uint8_t chVersionString[] = {IAP_VERSION_STRING}; #endif uint_fast8_t n = 12; do { *pchStream++ = *pchSrc++; } while (--n); #if IAP_SUPPORT_UID == ENABLED do { n = IAP_UID_BIT_SIZE / (sizeof(IAP_UID_DATA_TYPE) * 8); IAP_UID_DATA_TYPE *ptSrc = (IAP_UID_DATA_TYPE *)IAP_GET_UID_ADDRESS(); IAP_UID_DATA_TYPE *ptDes = (IAP_UID_DATA_TYPE *)pchStream; do { *ptDes++ = *ptSrc++; } while(--n); pchStream = (uint8_t *)ptDes; } while(false); #endif #if IAP_SUPPORT_VER_STRING == ENABLED for (n = 0;n < sizeof(chVersionString);n++) { *pchStream++ = chVersionString[n]; } #endif return 12 #if IAP_SUPPORT_UID == ENABLED + IAP_UID_BIT_SIZE #endif #if IAP_SUPPORT_VER_STRING == ENABLED + sizeof(IAP_VERSION_STRING) #endif ; } #if IAP_DATA_ENCRYPT_AES == ENABLED static void load_aes_key(uint8_t *pchKey) { uint32_t n = AES_KEY_SIZE; do { *pchKey++ ^= get_random_u8(); } while(--n); } static void aes_initialize_mask( uint8_t chKey, const uint8_t *pchMask, uint8_t *pchDes ) { uint32_t n = AES_KEY_SIZE; reset_random(); set_random_seed(chKey); do { *pchDes++ = *pchMask++ ^ get_random_u8(); } while(--n); } static void aes_decryption(uint8_t chKey, uint8_t *pchOrgStream, uint32_t wSize) { aes_decrypt_t tAES; wSize &= ~(AES_BLOCK_SIZE - 1); //! load first aes key do { const aes_key_t chKeyMask = { 0x11,0x45,0x76,0xCF,0xE0,0x2C,0xFE,0x38, 0x6D,0x9A,0x00,0xB2,0xA5,0x5A,0xFF,0x01}; aes_initialize_mask(chKey, chKeyMask, tAES.chKey); } while(false); //! load datamask do { const aes_data_t chDataMask = { 0x01,0x48,0xCC,0x7E,0x2F,0x6C,0xEE,0xCD, 0x55,0xAA,0x39,0xCA,0xBF,0x26,0x69,0x21}; aes_initialize_mask(chKey, chDataMask, tAES.chDataMask); } while(false); tAES.hwOffset = 0; //! load first aes key load_aes_key(tAES.chKey); //! decrypt do { uint32_t wOffset = tAES.hwOffset; uint8_t *pchStream = pchOrgStream + wOffset; uint8_t *pchMask = tAES.chDataMask; uint32_t n = AES_BLOCK_SIZE; do { uint8_t chTemp = *pchMask; *pchMask++ = *pchStream; *pchStream++ ^= chTemp; } while(--n); pchStream = pchOrgStream + wOffset; aes_prepare_decrypt(tAES.chKey); do { aes_decrypt(pchStream,tAES.chKey); } while(false); wOffset += AES_BLOCK_SIZE; if (wOffset >= wSize) { //! complete break; } else { load_aes_key(tAES.chKey); } tAES.hwOffset = wOffset; } while (true); } #endif static uint_fast16_t cmd_memory_handler( uint8_t *pchStream, uint_fast16_t hwSize, uint_fast8_t chIndex) { if (IAP_IS_SYSTEM_SECURED()) { do { if (MEM_ACCESS_ERASE == chIndex) { break; } #if defined(IAP_SECURE_CHECK_CODE) IAP_SECURE_CHECK_CODE #endif return 0; } while(false); } #if IAP_DATA_ENCRYPT_AES == ENABLED if (IAP_IS_DATA_DECRYPTION_ENABLED()) { aes_decryption(0xC5,pchStream+1,hwSize); } #endif #if IAP_DATA_PERMUTATE == ENABLED if (IAP_IS_DATA_PERMUTATE_ENABLED()) { IAP_FRAME_PERMUTATE_DATA( pchStream+1, hwSize ); } #endif do { uint_fast8_t chMemoryType = pchStream[1]; uint_fast8_t n; //! search for memory type for (n = 0; n < UBOUND(c_tMemory); n++) { FLASH bl_mem_t *ptMem = &c_tMemory[n]; if ( (chMemoryType & ptMem->chMask) != (ptMem->chType & ptMem->chMask)) { continue; } if (NULL == ptMem->_.fnAccess[chIndex]) { //! memory-write is not supported SET_IAP_REPLY(IAP_RSP_ERROR); break; } //! call specified memory command handler return ptMem->_.fnAccess[chIndex](pchStream, hwSize); } } while (false); //! illegal memorty type SET_IAP_REPLY(IAP_RSP_ERROR); return 1; } #if IAP_SUPPORT_WRITE_MEMORY == ENABLED static uint_fast16_t cmd_write_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_WRITE); } #endif #if IAP_SUPPORT_READ_MEMORY == ENABLED static uint_fast16_t cmd_read_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_READ); } #endif #if IAP_SUPPORT_CHIP_ERASE == ENABLED static uint_fast16_t cmd_chip_erase_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_ERASE); } #endif #if IAP_SUPPORT_RESUME == ENABLED static uint_fast16_t cmd_resume_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return IAP_RESUME(pchStream, hwSize); } #endif #if IAP_SUPPORT_VERIFY_MEMORY == ENABLED static uint_fast16_t cmd_verify_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_VERIFY); } #endif #if IAP_SUPPORT_PROTECT_MEMORY == ENABLED static uint_fast16_t cmd_protect_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_PROTECT); } #endif #if IAP_SUPPORT_UNPROTECT_MEMORY == ENABLED static uint_fast16_t cmd_unprotect_memory_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_UNPROTECT); } #endif #if IAP_SUPPORT_SECURE == ENABLED static uint_fast16_t cmd_secure_handler(uint8_t *pchStream, uint_fast16_t hwSize) { return cmd_memory_handler(pchStream, hwSize, MEM_ACCESS_SECURE); } #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/bootloader/bootloader.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __COMPONENT_BOOTLOADER_H__ #define __COMPONENT_BOOTLOADER_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_COMPONENT_BOOTLOADER == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \brief bootloader command handler typedef uint_fast16_t bl_cmd_handler_t(uint8_t *pchStream, uint_fast16_t hwSize); /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief bootloader command parser *! \param pchStream data block *! \param hwSize data block size *! \retval 0 failed in parsing *! \retval none-zero-size reply data size */ extern uint_fast16_t booloader_command_parser(uint8_t *pchStream, uint_fast16_t hwSize); #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/component.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\key\key.h" #include ".\memory\memory.h" #include ".\bootloader\bootloader.h" #include ".\sw_sdio\sw_sdio.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize components * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ bool component_init( void ) { //! add code here return true; } /* EOF */ ================================================ FILE: sources/gmsi/hal/component/component.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __COMPONENT_H__ #define __COMPONENT_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\key\key.h" #include ".\memory\memory.h" #include ".\bootloader\bootloader.h" #include ".\sw_sdio\sw_sdio.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize components * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ extern bool component_init( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __KEY_APP_CFG_H__ #define __KEY_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key.c ================================================ /**************************************************************************** * Copyright(C)2013-2014 by TanekLiang * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_COMPONENT_KEY == ENABLED #include ".\key_interface.h" #include ".\key_queue\key_queue.h" /*============================ MACROS ========================================*/ //! \brief Key Long Press Counts #ifndef KEY_LONG_TIME #warning You haven't define the MAXIMUM number of Key Long Press Counters, \ Default value 100 is used. You should define it with macro KEY_LONG_TIME. #define KEY_LONG_TIME (100u) #endif //! \brief Key Repeat Press Counts #ifndef KEY_REPEAT_TIME #warning You haven't define the MAXIMUM number of Key Repeat Press Counters, \ Default value 100 is used. You should define it with macro KEY_REPEAT_TIME. #define KEY_REPEAT_TIME (100u) #endif //! \brief Key Queue Size #ifndef KEY_QUEUE_SIZE #warning You haven't define the MAXIMUM number of Key Queue Buffer Size Counters, \ Default value 16 is used. You should define it with macro KEY_QUEUE_SIZE. #define KEY_QUEUE_SIZE (16u) #endif //! \brief Key Counter #ifndef KEY_COUNT #warning You haven't define the MAXIMUM number of Key Press Counters, \ Default value 100 is used. You should define it with macro KEY_COUNT. #define KEY_COUNT (100u) #endif //! \brief get key scan value #ifndef GET_KEY_SCAN_VALUE #error You haven't define the function of key value scan, the function prototype should be \ uint8_t GET_KEY_SCAN_VALUE(void), and should define it with macro GET_KEY_SCAN_VALUE. #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ //! \brief Key Frontend Message Buffer static key_t s_tKeyFrontendBuffer[KEY_QUEUE_SIZE]; //! \brief Key Detector message Buffer static key_t s_tKeyDetectorBuffer[KEY_QUEUE_SIZE]; //! \brief Key Frontend Queue static key_queue_t s_tKeyFrontendQueue; //! \brief Key Detector Queue static key_queue_t s_tKeyDetectorQueue; /*============================ PROTOTYPES ====================================*/ #define CHECK_KEY_START 0 #define CHECK_KEY_RESET_FSM() do{s_chState = 0;}while(0) #define CHECK_KEY_CHECKING 1 #define CHECK_KEY_SCAN 2 #define CHECK_KEY_FINISH 3 /*! \brief check key value *! \param pchKey key value *! \return state machine status */ static fsm_rt_t check_key(uint8_t* pchKey) { static uint8_t s_chState = CHECK_KEY_START; static uint16_t s_hwCount= 0; static uint8_t s_chKeyValue = KEY_NULL; static uint8_t s_chHisKeyValue = KEY_NULL; switch (s_chState) { case CHECK_KEY_START: s_hwCount= 0; s_chState = CHECK_KEY_CHECKING; //break; case CHECK_KEY_CHECKING: s_chKeyValue = GET_KEY_SCAN_VALUE(); if (s_chKeyValue == s_chHisKeyValue) { s_hwCount++; s_chState = CHECK_KEY_FINISH; } else { s_chState = CHECK_KEY_SCAN; } break; case CHECK_KEY_SCAN: if (0 == s_hwCount) { s_chHisKeyValue = s_chKeyValue; } else { s_hwCount--; } s_chState = CHECK_KEY_CHECKING; break; case CHECK_KEY_FINISH: if (KEY_COUNT > s_hwCount) { s_chState = CHECK_KEY_CHECKING; } else { *pchKey = s_chKeyValue; CHECK_KEY_RESET_FSM(); return fsm_rt_cpl; } break; } return fsm_rt_on_going; } #define KEY_FRONTEND_START 0 #define KEY_FRONTEND_RESET_FSM() do{s_chState = 0;}while(0) #define KEY_FRONTEND_CHECK 1 #define KEY_FRONTEND_SAME 2 #define KEY_FRONTEND_EDGE 3 /*! \brief key frontend *! \param none *! \return state machine status */ static bool key_frontend(void) { static uint8_t s_chState = KEY_FRONTEND_START; static uint8_t s_chNowKeyValue = KEY_NULL; static uint8_t s_chLastKeyValue = KEY_NULL; key_t tKey = {KEY_NULL, KEY_UP}; switch (s_chState) { case KEY_FRONTEND_START: s_chState = KEY_FRONTEND_CHECK; //break; case KEY_FRONTEND_CHECK: if (!check_key(&s_chNowKeyValue)) { s_chState = KEY_FRONTEND_SAME; } break; case KEY_FRONTEND_SAME: if (s_chLastKeyValue == s_chNowKeyValue) { s_chState = KEY_FRONTEND_CHECK; } else { s_chState = KEY_FRONTEND_EDGE; } break; case KEY_FRONTEND_EDGE: if (0 != s_chLastKeyValue) { tKey.tEvent = KEY_UP; tKey.chKeyValue = s_chLastKeyValue; key_enqueue(&s_tKeyFrontendQueue, &tKey); } if (0 != s_chNowKeyValue) { tKey.tEvent = KEY_DOWN; tKey.chKeyValue = s_chNowKeyValue; key_enqueue(&s_tKeyFrontendQueue, &tKey); } s_chLastKeyValue = s_chNowKeyValue; KEY_FRONTEND_RESET_FSM(); return fsm_rt_cpl; break; } return fsm_rt_on_going; } #define KEY_DECETOR_START 0 #define KEY_DECETOR_RESET_FSM() do{s_chState = 0;}while(0) #define KEY_DECETOR_DEQUEUE1 1 #define KEY_DECETOR_DOWN 2 #define KEY_DECETOR_DEQUEUE2 3 #define KEY_DECETOR_IS_UP_1 4 #define KEY_DECETOR_LONG_TIME 5 #define KEY_DECETOR_DEQUEUE3 6 #define KEY_DECETOR_REPEAT_TIME 7 #define KEY_DECETOR_REPEAT_ENQUEUE 8 #define KEY_DECETOR_IS_UP_2 9 /*! \brief key frontend *! \param none *! \return state machine status */ static fsm_rt_t key_decetor(void) { static uint8_t s_chState = KEY_DECETOR_START; static uint16_t s_hwLongCount = 0; static uint16_t s_hwRepeatCount = 0; static key_t s_tKeyDown; static key_t s_tKeyUp; switch (s_chState) { case KEY_DECETOR_START: s_hwLongCount = 0; s_hwRepeatCount = 0; s_chState = KEY_DECETOR_DEQUEUE1; //break; case KEY_DECETOR_DEQUEUE1: if (key_dequeue(&s_tKeyFrontendQueue, &s_tKeyDown)) { s_chState = KEY_DECETOR_DOWN; } /* else { } */ break; case KEY_DECETOR_DOWN: if (KEY_DOWN == s_tKeyDown.tEvent) { key_enqueue(&s_tKeyDetectorQueue, &s_tKeyDown); s_chState = KEY_DECETOR_DEQUEUE2; } else { s_chState = KEY_DECETOR_DEQUEUE1; } break; case KEY_DECETOR_DEQUEUE2: if (key_dequeue(&s_tKeyFrontendQueue, &s_tKeyUp)) { s_chState = KEY_DECETOR_IS_UP_1; } else { s_hwLongCount++; s_chState = KEY_DECETOR_LONG_TIME; } break; case KEY_DECETOR_IS_UP_1: if (KEY_UP != s_tKeyUp.tEvent) { s_chState = KEY_DECETOR_DEQUEUE2; } else { key_enqueue(&s_tKeyDetectorQueue, &s_tKeyUp); s_tKeyUp.tEvent = KEY_PRESSED; key_enqueue(&s_tKeyDetectorQueue, &s_tKeyUp); KEY_DECETOR_RESET_FSM(); return fsm_rt_cpl; } break; case KEY_DECETOR_LONG_TIME: if (KEY_LONG_TIME > s_hwLongCount) { s_chState = KEY_DECETOR_DEQUEUE2; } else { s_tKeyDown.tEvent = KEY_LONG_PRESSED; key_enqueue(&s_tKeyDetectorQueue, &s_tKeyDown); s_chState = KEY_DECETOR_DEQUEUE3; } break; case KEY_DECETOR_DEQUEUE3: if (key_dequeue(&s_tKeyFrontendQueue, &s_tKeyUp)) { s_chState = KEY_DECETOR_IS_UP_2; } else { s_hwRepeatCount++; s_chState = KEY_DECETOR_REPEAT_TIME; } break; case KEY_DECETOR_IS_UP_2: if (KEY_UP != s_tKeyUp.tEvent) { s_chState = KEY_DECETOR_DEQUEUE3; } else { key_enqueue(&s_tKeyDetectorQueue, &s_tKeyUp); KEY_DECETOR_RESET_FSM(); return fsm_rt_cpl; } break; case KEY_DECETOR_REPEAT_TIME: if (KEY_REPEAT_TIME > s_hwRepeatCount) { s_chState = KEY_DECETOR_DEQUEUE3; } else { s_hwRepeatCount = 0; s_chState = KEY_DECETOR_REPEAT_ENQUEUE; } break; case KEY_DECETOR_REPEAT_ENQUEUE: s_tKeyDown.tEvent = KEY_REPEAT; key_enqueue(&s_tKeyDetectorQueue, &s_tKeyDown); s_chState = KEY_DECETOR_DEQUEUE3; break; } return fsm_rt_on_going; } /*! \brief key task initialization *! \param none *! \return none */ void key_init(void) { key_queue_init(&s_tKeyFrontendQueue, s_tKeyFrontendBuffer, KEY_QUEUE_SIZE); key_queue_init(&s_tKeyDetectorQueue, s_tKeyDetectorBuffer, KEY_QUEUE_SIZE); } /*! \brief key task *! \param none *! \return none */ void key_task(void) { key_frontend(); key_decetor(); } /*! \brief get key *! \param ptKey Key Event *! \return true get key succeed *! \return false get key failed */ bool get_key(key_t* ptKey) { return key_dequeue(&s_tKeyDetectorQueue, ptKey); } #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key.h ================================================ /**************************************************************************** * Copyright(C)2013-2014 by TanekLiang * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __KEY_H__ #define __KEY_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_COMPONENT_KEY == ENABLED #include ".\key_interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief key task initialization *! \param none *! \return none */ extern void key_init(void); /*! \brief key task *! \param none *! \return none */ extern void key_task(void); /*! \brief get key event *! \param ptKey Key Event *! \return true get key succeed *! \return true get key failed */ extern bool get_key(key_event_t* ptKey); #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key_interface.h ================================================ /**************************************************************************** * Copyright(C)2013-2014 by TanekLiang * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __KEY_INTERFACE_H__ #define __KEY_INTERFACE_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ //! \brief No Button Pressed #define KEY_NULL 0 /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name key statues enum type //! @{ typedef enum{ KEY_DOWN = 0, //!< key press down KEY_UP, //!< key release KEY_PRESSED, //!< key pressed KEY_LONG_PRESSED, //!< key long pressed KEY_REPEAT, //!< key repeat }key_event_t; //! @} //! \name key event type //! @{ typedef struct{ uint8_t chKeyValue; //!< key value and the value 0 is reserve key_event_t tEvent; //!< key event type }key_t; //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key_queue/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __KEY_QUEUE_APP_CFG_H__ #define __KEY_QUEUE_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key_queue/key_queue.c ================================================ /*************************************************************************** * Copyright(C)2013-2014 by TanekLiang * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #include ".\app_cfg.h" #if USE_COMPONENT_KEY == ENABLED #include "..\key_interface.h" /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ declare_class(key_queue_t) //! \name key queue interface //! @{ def_class(key_queue_t) key_t *ptBuffer; uint16_t hwSize; uint16_t hwHead; uint16_t hwTail; uint16_t hwLength; end_def_class(key_queue_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief init key queue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message buffer *! \param size key size *! \return true key queue initialization succeed *! \return false key queue initialization failed */ bool key_queue_init(key_queue_t * ptQueue, key_t *ptKeyBuffer, uint16_t hwsize) { class(key_queue_t) *ptQ = (class(key_queue_t) *)ptQueue; bool bReturn = false; SAFE_ATOM_CODE( if((NULL != ptQ) && (NULL != ptKeyBuffer)){ ptQ->ptBuffer = ptKeyBuffer; ptQ->hwSize = hwsize; ptQ->hwHead = 0; ptQ->hwTail = 0; ptQ->hwLength = 0; bReturn = true; //!< update return value } ); return bReturn; } /*! \brief enqueue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message *! \return true key event enqueue succeed *! \return false key event enqueue failed */ bool key_enqueue(key_queue_t* ptQueue, key_t* ptKey) { class(key_queue_t) *ptQ = (class(key_queue_t) *)ptQueue; bool bReturn = false; if ((NULL == ptQueue) && (NULL == ptKey)) { return false; } SAFE_ATOM_CODE( if(ptQ->hwSize != ptQ->hwLength){ //!< the queue full //! add data to queue tail ptQ->ptBuffer[ptQ->hwTail] = *ptKey; ptQ->hwLength++; //!< update length if(ptQ->hwSize == ++ptQ->hwTail){ //!< update queue tail pointer ptQ->hwTail = 0; } bReturn = true; //!< update return value } ); return bReturn; } /*! \brief dequeue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message *! \return true key event dequeue succeed *! \return false key event dequeue failed */ bool key_dequeue(key_queue_t* ptQueue, key_t* ptKey) { class(key_queue_t) *ptQ = (class(key_queue_t) *)ptQueue; bool bReturn = false; if ((NULL == ptQueue) && (NULL == ptKey)) { return false; } SAFE_ATOM_CODE( if(0 != ptQ->hwLength){ //!< the queue empty //! read date form queue head *ptKey = ptQ->ptBuffer[ptQ->hwHead]; ptQ->hwLength--; //!< update length if(ptQ->hwSize == ++ptQ->hwHead){ //!< update queue head pointer ptQ->hwHead = 0; } bReturn = true; //!< update return value } ); return bReturn; } #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/key/key_queue/key_queue.h ================================================ /**************************************************************************** * Copyright(C)2013-2014 by TanekLiang * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __KEY_QUEUE_H__ #define __KEY_QUEUE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ DECLARE_CLASS(key_queue_t) //! \name key queue interface //! @{ EXTERN_CLASS(key_queue_t) key_t *ptBuffer; uint16_t hwSize; uint16_t hwHead; uint16_t hwTail; uint16_t hwLength; END_EXTERN_CLASS(key_queue_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief init key queue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message buffer *! \param size key size *! \return true key queue initialization succeed *! \return false key queue initialization failed */ extern bool key_queue_init(key_queue_t * ptQueue, key_t *ptKeyBuffer, uint16_t hwsize); /*! \brief enqueue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message *! \return true key event enqueue succeed *! \return false key event enqueue failed */ extern bool key_enqueue(key_queue_t* ptQueue, key_t* ptKey); /*! \brief dequeue *! \param ptQueue address of the target queue object *! \param ptKeyBuffer address of the key message *! \return true key event dequeue succeed *! \return false key event dequeue failed */ extern bool key_dequeue(key_queue_t* ptQueue, key_t* ptKey); #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __MEMORY_APP_CFG_H__ #define __MEMORY_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MEMORY_INTERFACE_H__ #define __MEMORY_INTERFACE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*! \brief prototype for memory access *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ typedef fsm_rt_t mem_access_t( void *pObj, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize); /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __MEMORY_MAL_APP_CFG_H__ #define __MEMORY_MAL_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MAL_INTERFACES_H__ #define __MAL_INTERFACES_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\interface.h" #include "..\page\page.h" //! \name memory status //! @{ #define MEM_READY_MSK _BV(0) #define MEM_BUSY_MSK _BV(1) //! \name mem_status_t //! @{ typedef enum { //! memory is not ready MEM_NOT_READY = 0x00, //! memory is ready and idle MEM_READY_IDLE = MEM_READY_MSK, //! memory is ready and busy MEM_READY_BUSY = MEM_READY_MSK | MEM_BUSY_MSK, } em_mem_status_t; //! @} //! @} //! \brief memory property //! @{ typedef enum { MEM_BLOCK_ACCESS = 0, //!< block access (default) MEM_RANDOM_ACCESS, //!< random access MEM_STREAM_ACCESS //!< stream access }em_mem_property_t; //! @} //! \name memory description block //! @{ typedef struct { uint16_t hwProperty; //!< memory property uint16_t hwPageSize; //!< memory page size (type) uint32_t wPageCount; //!< memory page count uint8_t chPageSizeBit; } mem_info_t; //! @} /*============================ DEPENDENT TYPES ===============================*/ declare_class(mem_t) //! \name memory control block //! @{ def_interface(i_mcb_t) mem_info_t (*Info) (mem_t *ptMal); fsm_rt_t (*Init) (mem_t *ptMal, void *ptCFG); fsm_rt_t (*Finish) (mem_t *ptMal); fsm_rt_t (*Open) (mem_t *ptMal); fsm_rt_t (*Close) (mem_t *ptMal); fsm_rt_t (*Config) (mem_t *ptMal, void *ptCFG); em_mem_status_t (*GetStatus)(mem_t *ptMal); end_def_interface(i_mcb_t) //! @} //! \name memory page access interface //! @{ def_interface(i_mem_page_t) fsm_rt_t (*PageWrite) ( mem_t *ptMal, uint32_t wPageAddress, void *ptBuffer); fsm_rt_t (*PageErase) ( mem_t *ptMal, uint32_t wPageAddress); fsm_rt_t (*PageRead) ( mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); fsm_rt_t (*PageVerify) ( mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); fsm_rt_t (*Erase) ( mem_t *ptMal); end_def_interface(i_mem_page_t) //! @} //! \name Memory Abstraction Layers //! @{ def_interface(i_mem_t) implement(i_mcb_t) implement(i_mem_page_t) end_def_interface(i_mem_t) //! @} //! \brief define abstract class mem_t def_class(mem_t, ref_interface(i_mem_t), page_t *ptPage; ) end_def_class(mem_t) //! \brief define abstract class mem_t extern_class(mem_t, ref_interface(i_mem_t), page_t *ptPage; ) end_extern_class(mem_t) /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/mal.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\interface.h" #include "..\page\page.h" /*============================ MACROS ========================================*/ #ifndef this # define this (*ptThis) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ declare_class(mem_helper_t) //! \name class mem_helper_t //! @{ def_class(mem_helper_t,, i_mem_t *ptMEM; //!< target mal interface void *ptTarget; //!< target object void *pPageBuffer; ) end_def_class(mem_helper_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \brief mal general page write *! \param hwAddress target memory address *! \param pchStream data buffer *! \return state machine state */ static fsm_rt_t mal_page_write( void *pObj, uint32_t wAddress, uint8_t *pchStream) { mem_t *ptThis = (mem_t *)pObj; const i_mem_t *ptMethod = this.ptMethod; if (NULL == ptMethod) { return fsm_rt_err; } else if (NULL == ptMethod->PageWrite) { return fsm_rt_cpl; } uint8_t chShift = ptMethod->Info(ptThis).chPageSizeBit; uint16_t hwPageSize = ptMethod->Info(ptThis).hwPageSize; return ptMethod->PageWrite( ptThis, wAddress >> chShift, //!< page address pchStream ); } /*! \brief mal general page read *! \param hwAddress target memory address *! \param pchStream data buffer *! \return state machine state */ static fsm_rt_t mal_page_read( void *pObj, uint32_t wAddress, uint8_t *pchStream) { mem_t *ptThis = (mem_t *)pObj; const i_mem_t *ptMethod = this.ptMethod; if (NULL == ptMethod) { return fsm_rt_err; } else if (NULL == ptMethod->PageRead) { return fsm_rt_cpl; } uint8_t chShift = ptMethod->Info(ptThis).chPageSizeBit; uint16_t hwPageSize = ptMethod->Info(ptThis).hwPageSize; return ptMethod->PageRead( ptThis, wAddress >> chShift, //!< page address wAddress & (_BV(chShift) - 1), //!< page offset pchStream, hwPageSize ); } /*! \brief mal general page erase *! \param hwAddress target memory address *! \return state machine state */ static fsm_rt_t mal_page_erase(void *pObj, uint32_t wAddress) { mem_t *ptThis = (mem_t *)pObj; const i_mem_t *ptMethod = this.ptMethod; if (NULL == ptMethod) { return fsm_rt_err; } else if (NULL == ptMethod->PageErase) { return fsm_rt_cpl; } uint8_t chShift = this.ptMethod->Info(ptThis).chPageSizeBit; return this.ptMethod->PageErase(ptThis, wAddress >> chShift); } /*! \brief read mal memory disregard page *! \param ptMEM memory object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ fsm_rt_t mal_mem_read( mem_t *ptMEM, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ) { class_internal(ptMEM, ptThis, mem_t); return read_memory_disregard_page( this.ptPage, hwAddress, pchStream, hwSize ); } /*! \brief write mal memory disregard page *! \param ptMEM memory object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ fsm_rt_t mal_mem_write( mem_t *ptMEM, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ) { class_internal(ptMEM, ptThis, mem_t); return write_memory_disregard_page( this.ptPage, hwAddress, pchStream, hwSize ); } /*! \brief initialize mal memory *! \param ptMEM target memory *! \param ptPage page obj *! \param pchBuffer page buffer *! \param tSize page size *! \return access result */ bool mal_mem_init(mem_t *ptMEM, page_t *ptPage, uint8_t *pchBuffer, page_size_t tSize) { class_internal(ptMEM, ptThis, mem_t); page_cfg_t tCFG = { .tIO = { .fnPageWrite = &mal_page_write, .fnPageRead = &mal_page_read, .fnPageErase = &mal_page_erase, }, pchBuffer, tSize, ptMEM }; this.ptPage = ptPage; return page_init(ptPage, &tCFG); } /*! \note initialize memory abstract layer * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ bool mal_init( void ) { return true; } /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/mal.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MAL_H__ #define __MAL_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\interface.h" #include ".\sdf_w25qxxx\sdf_w25qxxx.h" #include ".\sram\sram.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize memory abstract layer * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ extern bool mal_init( void ); /*! \brief read mal memory disregard page *! \param ptMEM memory object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ extern fsm_rt_t mal_mem_read( mem_t *ptMEM, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ); /*! \brief write mal memory disregard page *! \param ptMEM memory object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ extern fsm_rt_t mal_mem_write( mem_t *ptMEM, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ); #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/sdf_w25qxxx/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \brief import up level configuration #include "..\app_cfg.h" //! \brief component configuration #ifndef _USE_SERIAL_DATA_FLASH_CONFIG_H_ #define _USE_SERIAL_DATA_FLASH_CONFIG_H_ //! \name data flash access command //! @{ #define SDF_CMD_PROG_PAGE (0x02u) //!< page programming #define SDF_CMD_READ (0x03u) //!< read memory #define SDF_CMD_DISABLE_WRITE (0x04u) //!< disable write #define SDF_CMD_READ_STATUS_REG (0x05u) //!< read status register 1 #define SDF_CMD_ENABLE_WRITE (0x06u) //!< enable write #define SDF_CMD_SECTOR_ERASE (0x20u) //!< erase sector #define SDF_CMD_CHIP_ERASE (0xC7u) //!< erase chip #define SDF_CMD_READ_UNIQUE_ID (0x4Bu) //!< read unique-id #define SDF_CMD_READ_DEVICE_ID (0x90u) //!< read device ID //! @} //! \brief status register bit definition //! @{ #define BUSY (1 << 0) //!< busy flag #define WEL (1 << 1) //!< write enable latch flag //! @} #endif ================================================ FILE: sources/gmsi/hal/component/memory/mal/sdf_w25qxxx/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MAL_SPI_FLASH_INTERFACES_H__ #define __MAL_SPI_FLASH_INTERFACES_H__ /*============================ INCLUDES ======================================*/ #include "..\interface.h" /*============================ DEPENDENT TYPES ===============================*/ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/sdf_w25qxxx/sdf_w25qxxx.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ //! \brief import configurations #include ".\app_cfg.h" #include ".\interface.h" #include "..\..\page\page.h" #if USE_COMPONENT_MAL_SDF_W25QXXXX == ENABLED /*============================ MACROS ========================================*/ //! \brief command: read data #ifndef SDF_CMD_READ #error no defined command code for reading data: SDF_CMD_READ #endif //! \brief command: page programming #ifndef SDF_CMD_PROG_PAGE #error no defined command code for page programming : SDF_CMD_PROG_PAGE #endif //! \brief command: disable write #ifndef SDF_CMD_DISABLE_WRITE #error no defined command code to disable write : SDF_CMD_DISABLE_WRITE #endif //! \brief command: read state register #ifndef SDF_CMD_READ_STATUS_REG #error no defined command code to read status register : SDF_CMD_READ_STATUS_REG #endif //! \brief command: enable write #ifndef SDF_CMD_ENABLE_WRITE #error no defined command code to enable write : SDF_CMD_ENABLE_WRITE #endif //! \brief command: erase sector #ifndef SDF_CMD_SECTOR_ERASE #error no defined command code to erase sector : SDF_CMD_SECTOR_ERASE #endif //! \brief command: read unique id #ifndef SDF_CMD_READ_UNIQUE_ID #error no defined command code to read serial data flash unique ID: SDF_CMD_READ_UNIQUE_ID #endif //! \note serial data flash page size infomation //! @{ #ifndef SPI_FLASH_SIZE # define SPI_FLASH_SIZE (0x100000ul) #endif #define SPI_FLASH_PAGE_SIZE (4096ul) #define PROGRAM_SIZE (256ul) #define SPI_FLASH_PAGE_SIZE_BIT 12 //! @} #ifndef VERIFY_BUFFER_SIZE # define VERIFY_BUFFER_SIZE (16ul) #endif //!< serial device id for A company #ifndef SDF_DEVICE_ID #warning no defined serial data flash device id for vendor, default value 0xEF is used. #define SDF_DEVICE_ID (0xEF) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl initialize succeed. *! \retval fsm_rt_err initialize failed */ static fsm_rt_t sdf_init(mem_t *ptMal, void *ptCFG); /*! \brief finish serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash finish succeed. *! \retval fsm_rt_on_going serial data flash finish on-going */ static fsm_rt_t sdf_finish(mem_t *ptMal); /*! \brief get serial data flash module infomation *! *! \param ptMal memory abstract layer pointer *! *! \return memory infomation */ static mem_info_t sdf_info(mem_t *ptMal); /*! \brief open serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash open succeed. *! \retval fsm_rt_on_going serial data flash open on-going */ static fsm_rt_t sdf_open(mem_t *ptMal); /*! \brief close serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash finish succeed. *! \retval fsm_rt_on_going serial data flash finish on-going */ static fsm_rt_t sdf_close(mem_t *ptMal); /*! \brief get serial data flash module status *! *! \param ptMal memory abstract layer pointer *! *! \return serial data flash status */ static em_mem_status_t sdf_status(mem_t *ptMal); /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param ptBuffer page bufer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_write(mem_t *ptMal, uint32_t wPageAddress, void *ptBuffer); /*! \brief read specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_read(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); /*! \brief verify specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_verify(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); /*! \brief erase a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_erase(mem_t *ptMal, uint32_t wPageAddress); /*! \brief chip erase *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_chip_erase(mem_t *ptMal); extern bool SDF_SPI_INIT(void); extern fsm_rt_t SDF_SPI_OPEN(void); extern fsm_rt_t SDF_SPI_CLOSE(void); extern fsm_rt_t SDF_SPI_BYTE_EXCHANGE(uint8_t chByte, uint8_t *pchByte); extern void SDF_CLR_CS(void); extern void SDF_SET_CS(void); /*============================ GLOBAL VARIABLES ==============================*/ //! \brief serial data flash object const i_mem_t ISDF = { .base__i_mcb_t = { .Init = &sdf_init, .Finish = &sdf_finish, .Info = &sdf_info, .Open = &sdf_open, .Close = &sdf_close, .GetStatus = &sdf_status }, .base__i_mem_page_t = { .PageWrite = &sdf_page_write, .PageRead = &sdf_page_read, .PageVerify = &sdf_page_verify, .PageErase = &sdf_page_erase, .Erase = &sdf_chip_erase }, }; INIT_CLASS_OBJ ( mem_t, SDF, { .ptMethod = &ISDF } ); /*============================ LOCAL VARIABLES ===============================*/ //! \brief system state static volatile em_mem_status_t s_CurrentState = MEM_NOT_READY; /*============================ IMPLEMENTATION ================================*/ WEAK void SDF_CLR_WP(void){} WEAK void SDF_SET_WP(void){} WEAK void SDF_CLR_HOLD(void){} WEAK void SDF_SET_HOLD(void){} /****************************************************************************** * Base Function * ******************************************************************************/ //! \brief macro for exchanging multiple bytes with spi #ifndef SDF_SPI_STREAM_EXCHANGE //! \brief build-in stream exchange function #define SDF_SPI_STREAM_EXCHANGE(__OUT, __IN, __LEN) \ fsm_sdf_spi_stream_exchange((__OUT),(__IN),(__LEN)) #define SPI_STREAM_RESET_FSM() \ do{s_tState = SPI_STREAM_START;}while(false) /*! \brief spi stream exchange with external interface SDF_SPI_BYTE_EXCHANGE() *! *! \param pchOut output stream buffer (could be NULL) *! \param pchIn input stream buffer (could be NULL) *! \param wLength stream length *! *! \retval true FSM should keep running *! \retval false FSM complete. */ static fsm_rt_t fsm_sdf_spi_stream_exchange(uint8_t *pchOut, uint8_t *pchIn, uint32_t wLength) { static uint8_t *s_pchIn; static uint8_t *s_pchOut; static uint32_t s_wCounter; static enum { SPI_STREAM_START = 0, SPI_STREAM_WRITE_ONLY, SPI_STREAM_READ_ONLY, SPI_STREAM_READ_WRITE, } s_tState = SPI_STREAM_START; switch (s_tState) { case SPI_STREAM_START: //!< FSM start //! check parameter if ((NULL == pchIn && NULL == pchOut) || (0 == wLength)) { return fsm_rt_cpl; //!< doing nothing at all } else if (NULL == pchIn) { //! write only s_pchOut = pchOut; //!< initialize output pointer s_tState = SPI_STREAM_WRITE_ONLY; } else if (NULL == pchOut) { //! read only s_pchIn = pchIn; //!< initialize input pointer s_tState = SPI_STREAM_READ_ONLY; } else { //! read & write s_pchIn = pchIn; s_pchOut = pchOut; s_tState = SPI_STREAM_READ_WRITE; } s_wCounter = wLength; //!< initialize counter break; case SPI_STREAM_WRITE_ONLY: { //!< FSM start uint8_t chDumyRead = 0xFF; if (fsm_rt_cpl == SDF_SPI_BYTE_EXCHANGE((*s_pchOut), &chDumyRead)) { //! success s_pchOut++; if (0 == --s_wCounter) { SPI_STREAM_RESET_FSM(); return fsm_rt_cpl; } } break; } case SPI_STREAM_READ_ONLY: { //!< FSM start uint8_t chDumyWrite = 0xFF; if (fsm_rt_cpl == SDF_SPI_BYTE_EXCHANGE(chDumyWrite, s_pchIn)) { //! success s_pchIn++; if (0 == --s_wCounter) { SPI_STREAM_RESET_FSM(); return fsm_rt_cpl; } } break; } case SPI_STREAM_READ_WRITE: //!< FSM start if (fsm_rt_cpl == SDF_SPI_BYTE_EXCHANGE((*s_pchOut), s_pchIn)) { //! success s_pchIn++; s_pchOut++; if (0 == --s_wCounter) { SPI_STREAM_RESET_FSM(); return fsm_rt_cpl; } } break; } return fsm_rt_on_going; //!< state machine keep running } #endif #define CHECK_DEVICE_RESET_FSM() \ do{s_tState = CHECK_DEVICE_START;}while(0) /*! \brief wait device busy flag release *! *! \param none *! *! \retval fsm_rt_on_going device is busy *! \retval fsm_rt_cpl device is free */ static fsm_rt_t check_device_state(void) { static enum { CHECK_DEVICE_START = 0, CHECK_DEVICE_WRITE_COMMAND, CHECK_DEVICE_READ_STATUS, CHECK_DEVICE_SEND_DISABLE_WRITE, } s_tState = CHECK_DEVICE_START; switch (s_tState) { case CHECK_DEVICE_START: //!< FSM start SDF_CLR_CS(); //!< set #CS low s_tState = CHECK_DEVICE_WRITE_COMMAND; //break; case CHECK_DEVICE_WRITE_COMMAND: //!< write command if (fsm_rt_on_going == SDF_SPI_BYTE_EXCHANGE(SDF_CMD_READ_STATUS_REG, NULL)) { break; } //! complete s_tState = CHECK_DEVICE_READ_STATUS; //break; case CHECK_DEVICE_READ_STATUS: { //!< read status register uint8_t chStatus; if (fsm_rt_on_going == SDF_SPI_BYTE_EXCHANGE(0, &chStatus)) { break; } //! get status if (chStatus & BUSY) { //!< check busy break; } else { SDF_SET_CS(); //!< set #CS high //! system is free if ((chStatus & WEL)) { //!< check write enable latch //! we should disable write SDF_CLR_CS(); //!< set #CS low s_tState = CHECK_DEVICE_SEND_DISABLE_WRITE; } else { //! device is ready CHECK_DEVICE_RESET_FSM();//!< reset FSM return fsm_rt_cpl; } } } //break; case CHECK_DEVICE_SEND_DISABLE_WRITE: if (!SDF_SPI_BYTE_EXCHANGE(SDF_CMD_DISABLE_WRITE, NULL)) { //! complete SDF_SET_CS(); //!< set #CS high CHECK_DEVICE_RESET_FSM(); //!< reset FSM //! warning: do not return false here } break; } return fsm_rt_on_going; } #define W_CMD_AND_ADDR_RESET_FSM() \ do{s_tState = W_CMD_AND_ADDR_START;}while(0) /*! \brief common routine for write a 8bits command a 24bits address *! *! \param chCommand 8bits command *! \param wAddress 32bits address *! *! \retval fsm_rt_on_going FSM should keep running *! \retval fsm_rt_cpl FSM is completed. */ static fsm_rt_t write_command_and_address(uint8_t chCommand, uint32_t wAddress) { static uint8_t s_chAddressCounter; static enum { W_CMD_AND_ADDR_START = 0, W_CMD_AND_ADDR_WRITE_CMD, W_CMD_AND_ADDR_WRITE_ADDRESS, } s_tState = W_CMD_AND_ADDR_START; switch (s_tState) { case W_CMD_AND_ADDR_START: //!< FSM start s_tState = W_CMD_AND_ADDR_WRITE_CMD; //break; case W_CMD_AND_ADDR_WRITE_CMD: //!< write command if (fsm_rt_on_going == SDF_SPI_BYTE_EXCHANGE(chCommand, NULL)) { break; } s_chAddressCounter = 2; //! write command complete s_tState = W_CMD_AND_ADDR_WRITE_ADDRESS; //break; case W_CMD_AND_ADDR_WRITE_ADDRESS: //!< write address if (fsm_rt_cpl == SDF_SPI_BYTE_EXCHANGE(((uint8_t *)&wAddress)[s_chAddressCounter], NULL)) { if (0 == s_chAddressCounter) { //! write address complete W_CMD_AND_ADDR_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; } else { s_chAddressCounter--; } } break; } return fsm_rt_on_going; } #define READ_DID_RESET_FSM() do{s_tState = READ_DID_START;}while(0) /*! \brief read device ID *! *! \param pdwUID device ID *! *! \retval fsm_rt_err access failed or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY serial data flash is not ready *! \retval fsm_rt_on_going current access is on going. */ fsm_rt_t fsm_sdf_read_device_ID(uint16_t *phwDID) { NO_INIT static uint16_t s_hwDID; static enum { READ_DID_START = 0, READ_DID_CHECK_DEVICE, READ_DID_WRITE_COMMAND_AND_ADDRESS, READ_DID, } s_tState = READ_DID_START; switch (s_tState) { case READ_DID_START: if (NULL == phwDID) { return fsm_rt_err; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } //! set current state s_CurrentState = MEM_READY_BUSY; ) s_tState = READ_DID_CHECK_DEVICE; //break; case READ_DID_CHECK_DEVICE: if (fsm_rt_on_going == check_device_state()) { break; } SDF_CLR_CS(); //!< clr CS# //! flash is free s_tState = READ_DID_WRITE_COMMAND_AND_ADDRESS; //break; case READ_DID_WRITE_COMMAND_AND_ADDRESS: { uint32_t wDumyWrite = 0x00000000; if (fsm_rt_cpl == write_command_and_address(SDF_CMD_READ_DEVICE_ID, wDumyWrite)) { s_tState = READ_DID; } break; } case READ_DID: if (fsm_rt_cpl == SDF_SPI_STREAM_EXCHANGE(NULL,(uint8_t *)&s_hwDID, 2)) { *phwDID = s_hwDID; SDF_SET_CS(); //!< set #CS high SAFE_ATOM_CODE( //! set idle state s_CurrentState = MEM_READY_IDLE; ) READ_DID_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; //!< success } break; } return fsm_rt_on_going; } #define ENABLE_WRITE_RESET_FSM() do{s_tState = ENABLE_WRITE_START;}while(false) /*! \brief enable write *! *! \param none *! *! \retval true device is busy *! \retval false device is free */ static fsm_rt_t enable_write(void) { static enum { ENABLE_WRITE_START = 0, ENABLE_WRITE_SEND_COMMAND, } s_tState = ENABLE_WRITE_START; switch (s_tState) { case ENABLE_WRITE_START: SDF_CLR_CS(); //!< set #CS low s_tState = ENABLE_WRITE_SEND_COMMAND; //break; case ENABLE_WRITE_SEND_COMMAND: if (fsm_rt_cpl == SDF_SPI_BYTE_EXCHANGE(SDF_CMD_ENABLE_WRITE, NULL)) { //! write command complete SDF_SET_CS(); //!< set #CS high ENABLE_WRITE_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; } break; } return fsm_rt_on_going; } #define READ_UID_RESET_FSM() do {s_tState = READ_UID_START;}while(false) /*! \brief read unique ID *! *! \param pdwUID unique ID *! *! \retval fsm_rt_err access failed or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY serial data flash is not ready *! \retval fsm_rt_on_going current access is on going. */ fsm_rt_t fsm_sdf_read_unique_ID(uint64_t *pdwUID) { NO_INIT static uint64_t s_dwUID; static enum { READ_UID_START = 0, READ_UID_WRITE_COMMAND_AND_ADDRESS, READ_UID_CHECK_DEVICE, READ_UID, } s_tState = READ_UID_START; switch (s_tState) { case READ_UID_START: if (NULL == pdwUID) { return fsm_rt_err; } SAFE_ATOM_CODE ( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) s_tState = READ_UID_CHECK_DEVICE; //break; case READ_UID_CHECK_DEVICE: if (fsm_rt_on_going == check_device_state()) { break; } SDF_CLR_CS(); //!< clr CS# //! flash is free s_tState = READ_UID_WRITE_COMMAND_AND_ADDRESS; //break; case READ_UID_WRITE_COMMAND_AND_ADDRESS: { uint32_t wDumyWrite = 0x00000000; if (fsm_rt_cpl == write_command_and_address(SDF_CMD_READ_UNIQUE_ID, wDumyWrite)) { s_tState = READ_UID; } break; } case READ_UID: if (fsm_rt_cpl == SDF_SPI_STREAM_EXCHANGE(NULL,(uint8_t *)&s_dwUID, 8)) { *pdwUID = s_dwUID; SDF_SET_CS(); //!< set #CS high SAFE_ATOM_CODE ( //! set idle state s_CurrentState = MEM_READY_IDLE; ) READ_UID_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; //!< success } break; } return fsm_rt_on_going; } /****************************************************************************** * Interface * ******************************************************************************/ #define PAGE_INIT_RESET_FSM() do{s_tState = PAGE_INIT_START;}while(0) /*! \brief initialize serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl initialize succeed. *! \retval fsm_rt_err initialize failed */ static fsm_rt_t sdf_init(mem_t *ptMal, void *ptCFG) { static enum { PAGE_INIT_START = 0, SDF_INIT_SPI_OPEN, PAGE_INIT_READ, } s_tState = PAGE_INIT_START; NO_INIT static istate_t s_tIntState; switch (s_tState) { case PAGE_INIT_START: s_tIntState = GET_GLOBAL_INTERRUPT_STATE(); DISABLE_GLOBAL_INTERRUPT(); //! initialize spi interface if (!SDF_SPI_INIT()) { SET_GLOBAL_INTERRUPT_STATE(s_tIntState); return fsm_rt_err; } s_tState = SDF_INIT_SPI_OPEN; //break; case SDF_INIT_SPI_OPEN: { fsm_rt_t tFSM = SDF_SPI_OPEN(); if (IS_FSM_ERR(tFSM)) { PAGE_INIT_RESET_FSM(); SET_GLOBAL_INTERRUPT_STATE(s_tIntState); return fsm_rt_err; } else if (fsm_rt_cpl == tFSM) { SDF_SET_HOLD(); //!< always high SDF_CLR_WP(); //!< set protect s_CurrentState = MEM_READY_IDLE; //!< set current state SET_GLOBAL_INTERRUPT_STATE(s_tIntState); s_tState = PAGE_INIT_READ; } else { break; } } case PAGE_INIT_READ: { uint16_t hwID = 0; fsm_rt_t tFSM = fsm_sdf_read_device_ID(&hwID); if (IS_FSM_ERR(tFSM)) { PAGE_INIT_RESET_FSM(); return fsm_rt_err; } else if (fsm_rt_cpl == tFSM){ PAGE_INIT_RESET_FSM(); if (0 == hwID) { return fsm_rt_err; } else { return fsm_rt_cpl; } } } break; } return fsm_rt_on_going; } /*! \brief finish serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash finish succeed. *! \retval fsm_rt_on_going serial data flash finish on-going */ static fsm_rt_t sdf_finish(mem_t *ptMal) { if (fsm_rt_cpl == sdf_close(ptMal)) { SAFE_ATOM_CODE ( s_CurrentState = MEM_NOT_READY; //!< set idle state ) return fsm_rt_cpl; //!< success } else { return fsm_rt_on_going; } } /*! \brief get serial data flash module infomation *! *! \param ptMal memory abstract layer pointer *! *! \return memory infomation */ static mem_info_t sdf_info(mem_t *ptMal) { static const mem_info_t tReturn = { .hwProperty = MEM_BLOCK_ACCESS, .hwPageSize = SPI_FLASH_PAGE_SIZE, .wPageCount = SPI_FLASH_SIZE / SPI_FLASH_PAGE_SIZE, .chPageSizeBit = SPI_FLASH_PAGE_SIZE_BIT }; return tReturn; } /*! \brief open serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash open succeed. *! \retval fsm_rt_on_going serial data flash open on-going */ static fsm_rt_t sdf_open(mem_t *ptMal) { return SDF_SPI_OPEN(); } /*! \brief close serial data flash module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl serial data flash finish succeed. *! \retval fsm_rt_on_going serial data flash finish on-going */ static fsm_rt_t sdf_close(mem_t *ptMal) { return SDF_SPI_CLOSE(); } /*! \brief get serial data flash module status *! *! \param ptMal memory abstract layer pointer *! *! \return serial data flash status */ static em_mem_status_t sdf_status(mem_t *ptMal) { em_mem_status_t tResult; SAFE_ATOM_CODE( tResult = s_CurrentState; ) return tResult; } #define PAGE_PROGRAM_RESET_FSM() \ do{s_tState = PAGE_PROGRAM_START;}while(false) /*! \brief write a single page *! *! \param wAddress page address *! \param pchStream data buffer *! \param hwLength data length (0 means 256) *! *! \retval fsm_rt_cpl serial data flash program succeed. *! \retval fsm_rt_on_going serial data program finish on-going */ static fsm_rt_t sdf_page_program(uint32_t wPageAddress, uint8_t *pchStream) { static enum { PAGE_PROGRAM_START = 0, PAGE_PROGRAM_WRITE_COMMAND_ADDRESS, PAGE_PROGRAM_WRITE_DATA, PAGE_PROGRAM_CHECK, } s_tState = PAGE_PROGRAM_START; switch (s_tState) { case PAGE_PROGRAM_START: if (fsm_rt_on_going == enable_write()) { //!< enable write break; } SDF_SET_WP(); //!< relase protect SDF_CLR_CS(); //!< clr CS# s_tState = PAGE_PROGRAM_WRITE_COMMAND_ADDRESS; //break; case PAGE_PROGRAM_WRITE_COMMAND_ADDRESS: if (fsm_rt_on_going == write_command_and_address (SDF_CMD_PROG_PAGE, wPageAddress * PROGRAM_SIZE)) { break; } s_tState = PAGE_PROGRAM_WRITE_DATA; //break; case PAGE_PROGRAM_WRITE_DATA: if (fsm_rt_on_going == SDF_SPI_STREAM_EXCHANGE(pchStream, NULL, PROGRAM_SIZE)) { break; } //! write complete SDF_SET_CS(); //! set CS high SDF_CLR_WP(); //!< set protect s_tState = PAGE_PROGRAM_CHECK; //break; case PAGE_PROGRAM_CHECK: if (fsm_rt_cpl == check_device_state()) { //!< check state //! flash is free PAGE_PROGRAM_RESET_FSM(); return fsm_rt_cpl; } break; } return fsm_rt_on_going; } #define PAGE_WRITE_RESET_FSM() \ do{s_tState = PAGE_WRITE_START;}while(0) /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param ptBuffer page bufer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_write(mem_t *ptMal, uint32_t wPageAddress, void *ptBuffer) { static uint32_t s_wProgramIndex; static uint8_t *s_pchStream; static enum { PAGE_WRITE_START = 0, PAGE_WRITE_WRITE_PAGE, PAGE_WRITE_FINALIZE } s_tState = PAGE_WRITE_START; switch (s_tState) { case PAGE_WRITE_START: if ( (NULL == ptBuffer) || (wPageAddress >= (SPI_FLASH_SIZE / SPI_FLASH_PAGE_SIZE))) { return fsm_rt_err; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) s_wProgramIndex = 0; s_pchStream = ptBuffer; s_tState = PAGE_WRITE_WRITE_PAGE; //break; case PAGE_WRITE_WRITE_PAGE: if (fsm_rt_on_going == sdf_page_program( wPageAddress * (SPI_FLASH_PAGE_SIZE / PROGRAM_SIZE) + s_wProgramIndex, s_pchStream)) { break; } //! write complete s_wProgramIndex++; s_pchStream += PROGRAM_SIZE; if (s_wProgramIndex >= (SPI_FLASH_PAGE_SIZE / PROGRAM_SIZE)) { SAFE_ATOM_CODE ( s_CurrentState = MEM_READY_IDLE; //!< set idle state ) PAGE_WRITE_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; } break; } return fsm_rt_on_going; } #define SDF_READ_RANDROM_RESET_FSM() \ do { s_tState = SDF_READ_RANDROM_START; } while(0) /*! \brief random read *! *! \param ptMal memory abstract layer pointer *! \param wAddress address *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_read_random(mem_t *ptMal, uint32_t wAddress, uint8_t *pchStream, uint_fast16_t hwSize) { static enum { SDF_READ_RANDROM_START = 0, SDF_READ_RANDROM_CHECK_DEVICE, SDF_READ_RANDROM_WRITE_COMMAND_AND_ADDRESS, SDF_READ_RANDROM_FETCH_DATA } s_tState = SDF_READ_RANDROM_START; switch (s_tState) { case SDF_READ_RANDROM_START: if ( (NULL == pchStream) || (wAddress + hwSize > SPI_FLASH_SIZE)) { return fsm_rt_err; } else if (0 == hwSize) { return fsm_rt_cpl; } SAFE_ATOM_CODE ( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) s_tState = SDF_READ_RANDROM_CHECK_DEVICE; //break; case SDF_READ_RANDROM_CHECK_DEVICE: if (fsm_rt_on_going == check_device_state()) { break; } SDF_CLR_CS(); //!< clr CS# //! flash is free s_tState = SDF_READ_RANDROM_WRITE_COMMAND_AND_ADDRESS; //break; case SDF_READ_RANDROM_WRITE_COMMAND_AND_ADDRESS: if (fsm_rt_on_going == write_command_and_address(SDF_CMD_READ, wAddress)) { break; } s_tState = SDF_READ_RANDROM_FETCH_DATA; //break; case SDF_READ_RANDROM_FETCH_DATA: if (fsm_rt_cpl == SDF_SPI_STREAM_EXCHANGE( NULL,pchStream, hwSize)) { //! complete SDF_SET_CS(); //! set CS high SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) SDF_READ_RANDROM_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; //!< success } break; } return fsm_rt_on_going; } #define SDF_PAGEREAD_RESET_FSM() \ do { s_tState = SDF_PAGEREAD_START; } while(0) /*! \brief read a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_read(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize) { return sdf_read_random(ptMal, (wPageAddress * SPI_FLASH_PAGE_SIZE + hwOffset), pchStream, hwSize); } /*! \brief verify specified data *! *! \param ptMal memory abstract layer pointer *! \param pStream0 data stream 0 *! \param pStream0 data stream 0 *! \param hwSize data stream length *! *! \retval true data stream is same *! \retval false data stream is different */ static bool byte_compare(uint8_t *pStream0, uint8_t *pStream1, uint16_t hwSize) { if (NULL == pStream0 || NULL == pStream1) { return false; } while (hwSize--) { if (*pStream0++ != *pStream1++) { return false; } } return true; } #define SDF_READ_VERIFY_RESET_FSM() \ do { s_tState = SDF_VERIFY_START; } while(0) /*! \brief verify specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_verify(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize) { NO_INIT static uint8_t s_chVerifyBuffer[VERIFY_BUFFER_SIZE]; NO_INIT static uint32_t s_wAddress; NO_INIT static uint16_t s_hwSize; NO_INIT static uint16_t s_hwVerifySize; NO_INIT static uint8_t* s_pchStream; static enum { SDF_VERIFY_START = 0, SDF_VERIFY_CHECK_RANGE, SDF_VERIFY_READ, } s_tState = SDF_VERIFY_START; switch (s_tState) { case SDF_VERIFY_START: s_wAddress = wPageAddress * SPI_FLASH_PAGE_SIZE + hwOffset; if ((NULL == pchStream) || (s_wAddress + hwSize > SPI_FLASH_SIZE)) { return fsm_rt_err; } else if (0 == hwSize) { return fsm_rt_cpl; } s_hwSize = hwSize; s_hwVerifySize = 0; s_pchStream = pchStream; s_tState = SDF_VERIFY_CHECK_RANGE; //break; case SDF_VERIFY_CHECK_RANGE: if (0 == s_hwSize) { SDF_READ_VERIFY_RESET_FSM(); return fsm_rt_cpl; } if (s_hwSize > UBOUND(s_chVerifyBuffer)) { s_hwVerifySize = UBOUND(s_chVerifyBuffer); s_hwSize -= UBOUND(s_chVerifyBuffer); } else { s_hwVerifySize = s_hwSize; s_hwSize = 0; } s_tState = SDF_VERIFY_READ; //break; case SDF_VERIFY_READ: { fsm_rt_t tReturn = sdf_read_random(NULL, s_wAddress, s_chVerifyBuffer, s_hwVerifySize); if (fsm_rt_cpl == tReturn) { if (byte_compare(s_chVerifyBuffer, s_pchStream, s_hwVerifySize)) { s_pchStream += s_hwVerifySize; s_wAddress += s_hwVerifySize; s_tState = SDF_VERIFY_CHECK_RANGE; } else { SDF_READ_VERIFY_RESET_FSM(); return fsm_rt_err; } } else if (fsm_rt_on_going != tReturn) { return tReturn; } } break; } /*! add code here */ return fsm_rt_on_going; } #define PAGE_ERASE_RESET_FSM() \ do{s_tState = PAGE_ERASE_START;}while(false) /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_page_erase(mem_t *ptMal, uint32_t wPageAddress) { static enum { PAGE_ERASE_START = 0, PAGE_ERASE_ENABLE, PAGE_ERASE_WRITE_COMMAND_ADDRESS, PAGE_ERASE_WRITE_READY, } s_tState = PAGE_ERASE_START; switch (s_tState) { case PAGE_ERASE_START: if (wPageAddress >= (SPI_FLASH_SIZE / SPI_FLASH_PAGE_SIZE)) { return fsm_rt_err; } SAFE_ATOM_CODE ( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) s_tState = PAGE_ERASE_ENABLE; //break; case PAGE_ERASE_ENABLE: if (fsm_rt_on_going == enable_write()) { //!< enable write break; } SDF_SET_WP(); //!< relase protect SDF_CLR_CS(); //!< clr CS# s_tState = PAGE_ERASE_WRITE_COMMAND_ADDRESS; //break; case PAGE_ERASE_WRITE_COMMAND_ADDRESS: if (fsm_rt_on_going == write_command_and_address( SDF_CMD_SECTOR_ERASE, wPageAddress * SPI_FLASH_PAGE_SIZE)) { break; } //! complete SDF_SET_CS(); //!< set CS# SDF_CLR_WP(); //!< set protect s_tState = PAGE_ERASE_WRITE_READY; //break; case PAGE_ERASE_WRITE_READY: if (fsm_rt_cpl == check_device_state()) { //! complete SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) PAGE_ERASE_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; } break; } return fsm_rt_on_going; } #define CHIP_ERASE_RESET_FSM() \ do{s_tState = CHIP_ERASE_START;}while(false) /*! \brief chip erase *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sdf_chip_erase(mem_t *ptMal) { static enum { CHIP_ERASE_START = 0, CHIP_ERASE_ENABLE, CHIP_ERASE_WRITE_COMMAND_ADDRESS, CHIP_ERASE_WRITE_READY, } s_tState = CHIP_ERASE_START; switch (s_tState) { case CHIP_ERASE_START: SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) s_tState = CHIP_ERASE_ENABLE; //break; case CHIP_ERASE_ENABLE: if (fsm_rt_on_going == enable_write()) { //!< enable write break; } SDF_SET_WP(); //!< relase protect SDF_CLR_CS(); //!< clr CS# s_tState = CHIP_ERASE_WRITE_COMMAND_ADDRESS; //break; case CHIP_ERASE_WRITE_COMMAND_ADDRESS: if (fsm_rt_on_going == SDF_SPI_BYTE_EXCHANGE(SDF_CMD_CHIP_ERASE, NULL)) { break; } //! complete SDF_SET_CS(); //!< set CS# SDF_CLR_WP(); //!< set protect s_tState = CHIP_ERASE_WRITE_READY; //break; case CHIP_ERASE_WRITE_READY: if (fsm_rt_cpl == check_device_state()) { //! complete SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE; //!< set idle state ) CHIP_ERASE_RESET_FSM(); //!< reset FSM return fsm_rt_cpl; } break; } return fsm_rt_on_going; } /* End of File */ #endif ================================================ FILE: sources/gmsi/hal/component/memory/mal/sdf_w25qxxx/sdf_w25qxxx.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef _USE_MAL_SPI_FLASH_H_ #define _USE_MAL_SPI_FLASH_H_ /*============================ INCLUDES ======================================*/ #if USE_COMPONENT_MAL_SDF_W25QXXXX == ENABLED /*============================ MACROS ========================================*/ #define MAL_SDF_W25QXXX_PAGE_BUFFER_SIZE (4096ul) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize serial data flash module *! *! \param none *! *! \retval fsm_rt_cpl initialize succeed. *! \retval fsm_rt_err initialize failed */ extern fsm_rt_t sdf_init(void); /*! \brief read unique ID *! *! \param pdwUID unique ID *! *! \retval fsm_rt_err access failed or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY serial data flash is not ready *! \retval fsm_rt_on_going current access is on going. */ extern fsm_rt_t fsm_sdf_read_unique_ID(uint64_t *pdwUID); /*! \brief read device ID *! *! \param pdwUID device ID *! *! \retval fsm_rt_err access failed or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY serial data flash is not ready *! \retval fsm_rt_on_going current access is on going. */ extern fsm_rt_t fsm_sdf_read_device_ID(uint16_t *phwDID); /*============================ GLOBAL VARIABLES ==============================*/ //! SPI flash interface extern const i_mem_t ISDF; //! SPI flash static instance EXTERN_CLASS_OBJ(mem_t,SDF); #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/sram/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MAL_SRAM_APP_CFG_H__ #define __MAL_SRAM_APP_CFG_H__ /*============================ INCLUDES ======================================*/ //! \brief import up level configuration #include "..\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/hal/component/memory/mal/sram/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MAL_SRAM_INTERFACES_H__ #define __MAL_SRAM_INTERFACES_H__ /*============================ INCLUDES ======================================*/ #include "..\interface.h" /*============================ DEPENDENT TYPES ===============================*/ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/mal/sram/sram.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ //! \brief import configurations #include ".\app_cfg.h" #include ".\interface.h" #include "..\..\page\page.h" #if USE_COMPONENT_MAL_SRAM == ENABLED /*============================ MACROS ========================================*/ //! \note sram mal page size infomation //! @{ #ifndef SRAM_SIZE # define SRAM_SIZE (1024ul) #endif #define SRAM_PAGE_SIZE (512ul) #define SRAM_PAGE_SIZE_BIT 9 //! @} /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl initialize succeed. *! \retval fsm_rt_err initialize failed */ static fsm_rt_t sram_init(mem_t *ptMal, void *ptCFG); /*! \brief finish sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal finish succeed. *! \retval fsm_rt_on_going sram mal finish on-going */ static fsm_rt_t sram_finish(mem_t *ptMal); /*! \brief get sram mal module infomation *! *! \param ptMal memory abstract layer pointer *! *! \return memory infomation */ static mem_info_t sram_info(mem_t *ptMal); /*! \brief open sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal open succeed. *! \retval fsm_rt_on_going sram mal open on-going */ static fsm_rt_t sram_open(mem_t *ptMal); /*! \brief close sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal finish succeed. *! \retval fsm_rt_on_going sram mal finish on-going */ static fsm_rt_t sram_close(mem_t *ptMal); /*! \brief get sram mal module status *! *! \param ptMal memory abstract layer pointer *! *! \return sram mal status */ static em_mem_status_t sram_status(mem_t *ptMal); /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param ptBuffer page bufer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_write( mem_t *ptMal, uint32_t wPageAddress, void *ptBuffer); /*! \brief read specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_read( mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); /*! \brief verify specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_verify( mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize); /*! \brief erase a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_erase( mem_t *ptMal, uint32_t wPageAddress); /*! \brief chip erase *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_chip_erase(mem_t *ptMal); /*============================ GLOBAL VARIABLES ==============================*/ //! \brief sram mal object const i_mem_t I_SRAM = { .base__i_mcb_t = { .Init = &sram_init, .Finish = &sram_finish, .Info = &sram_info, .Open = &sram_open, .Close = &sram_close, .GetStatus = &sram_status }, .base__i_mem_page_t = { .PageWrite = &sram_page_write, .PageRead = &sram_page_read, .PageVerify = &sram_page_verify, .PageErase = &sram_page_erase, .Erase = &sram_chip_erase }, }; INIT_CLASS_OBJ( mem_t, SRAM, { .ptMethod = &I_SRAM, } ); /*============================ LOCAL VARIABLES ===============================*/ //! \brief system state static volatile em_mem_status_t s_CurrentState = MEM_NOT_READY; //! \brief sram mal buffer NO_INIT static uint8_t s_chSramBuffer[SRAM_SIZE]; /*============================ IMPLEMENTATION ================================*/ /*! \brief initialize sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl initialize succeed. *! \retval fsm_rt_err initialize failed */ static fsm_rt_t sram_init(mem_t *ptMal, void *ptCFG) { SAFE_ATOM_CODE ( if (MEM_NOT_READY == s_CurrentState) { s_CurrentState = MEM_READY_IDLE; } ) return fsm_rt_cpl; } /*! \brief finish sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal finish succeed. *! \retval fsm_rt_on_going sram mal finish on-going */ static fsm_rt_t sram_finish(mem_t *ptMal) { SAFE_ATOM_CODE ( s_CurrentState = MEM_NOT_READY; //!< set idle state ) return fsm_rt_cpl; //!< success } /*! \brief get sram mal module infomation *! *! \param ptMal memory abstract layer pointer *! *! \return memory infomation */ static mem_info_t sram_info(mem_t *ptMal) { static const mem_info_t tReturn = { .hwProperty = MEM_BLOCK_ACCESS, .hwPageSize = SRAM_PAGE_SIZE, .wPageCount = SRAM_SIZE / SRAM_PAGE_SIZE, .chPageSizeBit = SRAM_PAGE_SIZE_BIT, }; return tReturn; } /*! \brief open sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal open succeed. *! \retval fsm_rt_on_going sram mal open on-going */ static fsm_rt_t sram_open(mem_t *ptMal) { SAFE_ATOM_CODE ( if (MEM_NOT_READY == s_CurrentState) { s_CurrentState = MEM_READY_IDLE; } ) return fsm_rt_cpl; } /*! \brief close sram mal module *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_cpl sram mal finish succeed. *! \retval fsm_rt_on_going sram mal finish on-going */ static fsm_rt_t sram_close(mem_t *ptMal) { fsm_rt_t tResult = fsm_rt_on_going; SAFE_ATOM_CODE ( if (MEM_READY_BUSY != s_CurrentState) { s_CurrentState = MEM_NOT_READY; tResult = fsm_rt_cpl; } ) return tResult; } /*! \brief get sram mal module status *! *! \param ptMal memory abstract layer pointer *! *! \return sram mal status */ static em_mem_status_t sram_status(mem_t *ptMal) { em_mem_status_t tResult; SAFE_ATOM_CODE( tResult = s_CurrentState; ) return tResult; } /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param ptBuffer page bufer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_write(mem_t *ptMal, uint32_t wPageAddress, void *ptBuffer) { uint8_t *pchStream; if ( (NULL == ptBuffer) || (wPageAddress >= (SRAM_SIZE / SRAM_PAGE_SIZE))) { return fsm_rt_err; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) pchStream = ptBuffer; for (int i = 0; i < SRAM_PAGE_SIZE; i++) { s_chSramBuffer[i + wPageAddress * SRAM_PAGE_SIZE] = pchStream[i]; } SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) return fsm_rt_cpl; } /*! \brief read a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_read(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize) { uint32_t wOffset = wPageAddress * SRAM_PAGE_SIZE + hwOffset; if ( (NULL == pchStream) || (wOffset + hwSize > SRAM_SIZE)) { return fsm_rt_err; } else if (0 == hwSize) { return fsm_rt_cpl; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) for (int i = 0; i < hwSize; i++) { pchStream[i] = s_chSramBuffer[i + wOffset]; } SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) return fsm_rt_cpl; } /*! \brief verify specified data *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! \param hwOffset offset within a page *! \param pchStream data buffer *! \param hwSize buffer size *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_verify(mem_t *ptMal, uint32_t wPageAddress, uint_fast16_t hwOffset, uint8_t *pchStream, uint_fast16_t hwSize) { uint32_t wOffset = wPageAddress * SRAM_PAGE_SIZE + hwOffset; fsm_rt_t tResult = fsm_rt_cpl; if ( (NULL == pchStream) || (wOffset + hwSize > SRAM_SIZE)) { return fsm_rt_err; } else if (0 == hwSize) { return fsm_rt_cpl; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) for (int i = 0; i < hwSize; i++) { if (pchStream[i] != s_chSramBuffer[i + wOffset]) { tResult = fsm_rt_err; break; } } SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) return tResult; } /*! \brief write a sector *! *! \param ptMal memory abstract layer pointer *! \param wPageAddress page address *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_page_erase(mem_t *ptMal, uint32_t wPageAddress) { if ((wPageAddress >= (SRAM_SIZE / SRAM_PAGE_SIZE))) { return fsm_rt_err; } SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) for (int i = 0; i < SRAM_PAGE_SIZE; i++) { s_chSramBuffer[i + wPageAddress * SRAM_PAGE_SIZE] = 0xFF; } SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) return fsm_rt_cpl; } /*! \brief chip erase *! *! \param ptMal memory abstract layer pointer *! *! \retval fsm_rt_err current state is busy or illegal parameter *! \retval fsm_rt_cpl access succeed *! \retval GSF_ERR_NOT_READY system is busy *! \retval fsm_rt_on_going current access is on going. */ static fsm_rt_t sram_chip_erase(mem_t *ptMal) { SAFE_ATOM_CODE( //! whether system is initialized if (MEM_NOT_READY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return fsm_rt_err; } else if (MEM_READY_BUSY == s_CurrentState) { EXIT_SAFE_ATOM_CODE(); return (fsm_rt_t)GSF_ERR_NOT_READY; } s_CurrentState = MEM_READY_BUSY; //!< set current state ) for (int i = 0; i < SRAM_SIZE; i++) { s_chSramBuffer[i] = 0xFF; } SAFE_ATOM_CODE( s_CurrentState = MEM_READY_IDLE;//!< set idle state ) return fsm_rt_cpl; } /* End of File */ #endif ================================================ FILE: sources/gmsi/hal/component/memory/mal/sram/sram.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __MAL_SRAM_H__ #define __MAL_SRAM_H__ /*============================ INCLUDES ======================================*/ #if USE_COMPONENT_MAL_SRAM == ENABLED /*============================ MACROS ========================================*/ #define MAL_SRAM_PAGE_BUFFER_SIZE (512ul) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ //! sram mal interface extern const i_mem_t I_SDF_SRAM; //! sram mal static instance //extern mem_t SRAM; EXTERN_CLASS_OBJ( mem_t, SRAM ); #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/memory.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MEMORY_H__ #define __MEMORY_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\page\page.h" #include ".\mal\mal.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/page/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __MEM_PAGE_APP_CFG_H__ #define __MEM_PAGE_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/page/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MEMORY_PAGE_INTERFACE_H__ #define __MEMORY_PAGE_INTERFACE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*! \brief prototype for page access *! \param hwAddress target memory address *! \param pchStream data buffer *! \return state machine state */ typedef fsm_rt_t page_access_t( void *pObj, uint32_t wAddress, uint8_t *pchStream); //! \name page interface //! @{ declare_interface(i_page_t) def_interface(i_page_t) page_access_t *fnPageWrite; //!< write page page_access_t *fnPageRead; //!< read page fsm_rt_t (*fnPageErase)(void *pObj, uint32_t wAddress); //!< page erase end_def_interface(i_page_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/page/page.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\interface.h" /*============================ MACROS ========================================*/ #define this (*ptThis) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name memory page size //! @{ typedef enum { PAGE_SIZE_4, //!< 4 units PAGE_SIZE_8, //!< 8 units PAGE_SIZE_16, //!< 16 units PAGE_SIZE_32, //!< 32 units PAGE_SIZE_64, //!< 64 units PAGE_SIZE_128, //!< 128 units PAGE_SIZE_256, //!< 256 units PAGE_SIZE_512, //!< 512 units PAGE_SIZE_1024, //!< 1024 units PAGE_SIZE_2048, //!< 2048 units PAGE_SIZE_4096 //!< 4096 units }page_size_t; //! @} //! \name page configuration //! @{ typedef struct { i_page_t tIO; //!< IO uint8_t *pchBuffer; //!< page buffer page_size_t tPageSize; //!< page size(buffer size) void *pObj; }page_cfg_t; //! @} declare_class(page_t) //! \name class page_t //! @{ def_class(page_t,, const i_page_t tIO; void *pObj; uint8_t *pchBuffer; const uint16_t hwPageSize; locker_t bCritical; uint8_t bModified; uint8_t chFSMWrite; uint8_t chFSMRead; uint8_t *pchStream; uint16_t hwCount; uint32_t wAddress; uint32_t wPageAddress; ) end_def_class(page_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \brief validate specified page_t object *! \param ptPage page_t object *! \retval true target object is valid *! \retval false target object is invalid */ static bool is_page_interface_valid(page_t *ptPage) { class_internal(ptPage, ptThis, page_t); if ( (0 == this.hwPageSize) || (NULL == this.pchBuffer) || (NULL == this.tIO.fnPageErase) || (NULL == this.tIO.fnPageRead) || (NULL == this.tIO.fnPageWrite)) { return false; } return true; } /*! \brief initialize page service *! \param ptPage page_t object *! \param ptCFG configuration structure *! \retval true initialize succeed *! \retval false intizlization fail. */ bool page_init(page_t *ptPage, page_cfg_t *ptCFG) { class_internal(ptPage, ptThis, page_t); if (NULL == ptPage || NULL == ptCFG) { return false; } //! initialize page_t object TYPE_CONVERT(&(this.hwPageSize), uint16_t) = ((uint16_t)1 << (ptCFG->tPageSize + 2)) - 1; this.pchBuffer = ptCFG->pchBuffer; TYPE_CONVERT(&(this.tIO), i_page_t) = ptCFG->tIO; if (!is_page_interface_valid(ptPage)) { //! invalid interface return false; } this.pObj = ptCFG->pObj; this.chFSMRead = 0; this.chFSMWrite = 0; LOCK_INIT(this.bCritical); return true; } static void modify_leading_page(class(page_t) *ptThis) { if (this.bModified) { return ; } this.bModified = true; do { uint8_t *pchDes = this.pchBuffer; uint8_t *pchSrc = this.pchStream; uint32_t wAddress = this.wAddress; uint_fast16_t hwTemp = wAddress & this.hwPageSize; //! get data count uint_fast16_t hwCount = this.hwPageSize + 1 - hwTemp; hwCount = MIN(hwCount, this.hwCount); //! update data count this.hwCount -= hwCount; //! update address this.wAddress += hwCount; //! get destination address pchDes += hwTemp; if (NULL != this.pchStream) { //! copy content do { *pchDes++ = *pchSrc++; } while(--hwCount); //! update pointer this.pchStream = pchSrc; } else { //! fill 0xFF do { *pchDes++ = 0xFF; } while(--hwCount); } } while(false); } static void modify_final_page(class(page_t) *ptThis) { if (this.bModified) { return ; } this.bModified = true; do { uint8_t *pchDes = this.pchBuffer; uint8_t *pchSrc = this.pchStream; uint_fast16_t hwCount = this.hwCount; if (NULL != this.pchStream) { //! copy content do { *pchDes++ = *pchSrc++; } while (--hwCount); } else { //! fill 0xFF do { *pchDes++ = 0xFF; } while (--hwCount); } } while (false); } #define WRITE_START 0 #define WRITE_READ_FRONT_PAGE 1 #define WRITE_ERASE_LEADING_PAGE 2 #define WRITE_MODIFY_LEADING_PAGE 3 #define WRITE_PROG_LEADING_PAGE 4 #define WRITE_PAGES 5 #define WRITE_ERASE_PAGE 6 #define WRITE_PROG_PAGE 7 #define WRITE_READ_FINAL_PAGE 8 #define WRITE_ERASE_FINAL_PAGE 9 #define WRITE_MODIFY_FINAL_PAGE 10 #define WRITE_PROG_FINAL_PAGE 11 #define WRITE_RESET_FSM() do { chState = 0;} while(0) /*! \brief write memory disregard page *! \param ptPage page_t object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ fsm_rt_t write_memory_disregard_page( page_t *ptPage, uint32_t wAddress, uint8_t *pchStream, uint_fast16_t hwSize ) { class_internal(ptPage, ptThis, page_t); fsm_rt_t tfsm = fsm_rt_on_going; fsm_rt_t tSubFSM; if (NULL == ptPage) { return (fsm_rt_t)GSF_ERR_FAIL; } uint_fast8_t chState = this.chFSMWrite; //!< get state do { switch (chState) { case WRITE_START: //! validate page_t object if (/*NULL == pchStream ||*/ 0 == hwSize) { tfsm = fsm_rt_cpl; break; } else if (!is_page_interface_valid(ptPage)) { tfsm = (fsm_rt_t)GSF_ERR_NOT_AVAILABLE; break; } if (!ENTER_LOCK(&this.bCritical)) { break; } this.hwCount = hwSize; this.pchStream = pchStream; //this.hwSize = hwSize; this.wAddress = wAddress; //! write front unaligned if (wAddress & this.hwPageSize) { //! the address isn't aligned to page address this.wPageAddress = this.wAddress & (~this.hwPageSize); chState = WRITE_READ_FRONT_PAGE; } else { //! the address is aligned to page address chState = WRITE_PAGES; break; } case WRITE_READ_FRONT_PAGE: //! read target page tSubFSM = this.tIO.fnPageRead( this.pObj, this.wPageAddress, this.pchBuffer/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } this.bModified = false; chState = WRITE_ERASE_LEADING_PAGE; break; case WRITE_ERASE_LEADING_PAGE: //! erase target page tSubFSM = this.tIO.fnPageErase(this.pObj, this.wPageAddress); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { modify_leading_page(ptThis); break; } chState = WRITE_MODIFY_LEADING_PAGE; break; case WRITE_MODIFY_LEADING_PAGE: modify_leading_page(ptThis); chState = WRITE_PROG_LEADING_PAGE; break; case WRITE_PROG_LEADING_PAGE: //! program target page tSubFSM = this.tIO.fnPageWrite(this.pObj, this.wPageAddress, this.pchBuffer/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } chState = WRITE_PAGES; case WRITE_PAGES: this.wPageAddress = this.wAddress & (~this.hwPageSize); if (this.hwCount > this.hwPageSize) { chState = WRITE_ERASE_PAGE; } else if (this.hwCount) { //! final page chState = WRITE_READ_FINAL_PAGE; } else { //! complete tfsm = fsm_rt_cpl; LEAVE_LOCK(&this.bCritical); WRITE_RESET_FSM(); } break; case WRITE_ERASE_PAGE: //! erase target page tSubFSM = this.tIO.fnPageErase(this.pObj, this.wPageAddress); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } chState = WRITE_PROG_PAGE; break; case WRITE_PROG_PAGE: if (NULL != this.pchStream) { tSubFSM = this.tIO.fnPageWrite(this.pObj, this.wPageAddress, this.pchStream/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } } //! update do { uint_fast16_t hwTemp = this.hwPageSize + 1; if (NULL != this.pchStream) { this.pchStream += hwTemp; } this.wAddress += hwTemp; this.hwCount -= hwTemp; } while (0); chState = WRITE_PAGES; break; case WRITE_READ_FINAL_PAGE: //! read target page tSubFSM = this.tIO.fnPageRead( this.pObj, this.wPageAddress, this.pchBuffer/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } this.bModified = false; chState = WRITE_ERASE_FINAL_PAGE; break; case WRITE_ERASE_FINAL_PAGE: //! erase target page tSubFSM = this.tIO.fnPageErase(this.pObj, this.wPageAddress); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { modify_final_page(ptThis); break; } chState = WRITE_MODIFY_FINAL_PAGE; break; case WRITE_MODIFY_FINAL_PAGE: modify_final_page(ptThis); // do { // uint8_t *pchDes = this.pchBuffer; // uint8_t *pchSrc = this.pchStream; // uint_fast16_t hwCount = this.hwCount; // if (NULL != this.pchStream) { // //! copy content // do { // *pchDes++ = *pchSrc++; // } while (--hwCount); // } else { // //! fill 0xFF // do { // *pchDes++ = 0xFF; // } while (--hwCount); // } // } while (0); chState = WRITE_PROG_FINAL_PAGE; break; case WRITE_PROG_FINAL_PAGE: tSubFSM = this.tIO.fnPageWrite(this.pObj, this.wPageAddress, this.pchBuffer/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } //! complete tfsm = fsm_rt_cpl; LEAVE_LOCK(&this.bCritical); WRITE_RESET_FSM(); break; } } while(false); this.chFSMWrite = chState; //!< update state; return tfsm; } #define READ_START 0 #define READ_PAGE 1 #define READ_SET_BUFFER 2 #define READ_RESET_FSM() do { chState = 0; } while(0) /*! \brief read memory disregard page *! \param ptPage page_t object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ fsm_rt_t read_memory_disregard_page( page_t *ptPage, uint32_t wAddress, uint8_t *pchStream, uint_fast16_t hwSize ) { class_internal(ptPage, ptThis, page_t); fsm_rt_t tfsm = fsm_rt_on_going; fsm_rt_t tSubFSM; if (NULL == ptPage) { return (fsm_rt_t)GSF_ERR_FAIL; } uint_fast8_t chState = this.chFSMRead; //!< get state do { switch (chState) { case READ_START: //! validate page_t object if (NULL == pchStream || 0 == hwSize) { tfsm = fsm_rt_cpl; break; } else if (!is_page_interface_valid(ptPage)) { tfsm = (fsm_rt_t)GSF_ERR_NOT_AVAILABLE; break; } if (!ENTER_LOCK(&this.bCritical)) { break; } this.hwCount = hwSize; this.pchStream = pchStream; this.wAddress = wAddress; this.wPageAddress = this.wAddress & (~this.hwPageSize); //! read page chState = READ_PAGE; case READ_PAGE: //! read target page tSubFSM = this.tIO.fnPageRead( this.pObj, this.wPageAddress, this.pchBuffer/*, this.hwPageSize + 1*/); if (IS_FSM_ERR(tSubFSM)) { tfsm = tSubFSM; break; } else if (fsm_rt_cpl != tSubFSM) { break; } chState = READ_SET_BUFFER; break; case READ_SET_BUFFER: do { uint8_t *pchSrc = this.pchBuffer; uint8_t *pchDes = this.pchStream; uint32_t wAddress = this.wAddress; //! address mod pagesize uint_fast16_t hwTemp = wAddress & this.hwPageSize; //! get source address pchSrc += hwTemp; //! calculate count uint_fast16_t hwCount = this.hwPageSize + 1 - hwTemp; hwCount = MIN(this.hwCount, hwCount); //! update count this.hwCount -= hwCount; //! update address this.wAddress += hwCount; //! copy content do { *pchDes++ = *pchSrc++; }while(--hwCount); //! update pointer this.pchStream = pchDes; if (this.hwCount) { this.wPageAddress = this.wAddress & (~this.hwPageSize); chState = READ_PAGE; } else { READ_RESET_FSM(); LEAVE_LOCK(&this.bCritical); tfsm = fsm_rt_cpl; } } while (0); break; } } while(false); this.chFSMRead = chState; //!< update state; return tfsm; } /* EOF */ ================================================ FILE: sources/gmsi/hal/component/memory/page/page.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MEMORY_PAGE_H__ #define __MEMORY_PAGE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define PAGE_CFG(__PAGE, ...) \ do { \ page_cfg_t tCFG = {__VA_ARGS__};\ page_init((__PAGE),&tCFG); \ } while(false) /*============================ TYPES =========================================*/ //! \name memory page size //! @{ typedef enum { PAGE_SIZE_4, //!< 4 units PAGE_SIZE_8, //!< 8 units PAGE_SIZE_16, //!< 16 units PAGE_SIZE_32, //!< 32 units PAGE_SIZE_64, //!< 64 units PAGE_SIZE_128, //!< 128 units PAGE_SIZE_256, //!< 256 units PAGE_SIZE_512, //!< 512 units PAGE_SIZE_1024, //!< 1024 units PAGE_SIZE_2048, //!< 2048 units PAGE_SIZE_4096 //!< 4096 units }page_size_t; //! @} //! \name page configuration //! @{ typedef struct { i_page_t tIO; //!< IO uint8_t *pchBuffer; //!< page buffer page_size_t tPageSize; //!< page size(buffer size) void *pObj; }page_cfg_t; //! @} declare_class(page_t) //! \name class page_t //! @{ extern_class(page_t,, const i_page_t tIO; void *pObj; uint8_t *pchBuffer; const uint16_t hwPageSize; locker_t bCritical; uint8_t bModified; uint8_t chFSMWrite; uint8_t chFSMRead; uint8_t *pchStream; uint16_t hwCount; uint32_t wAddress; uint32_t wPageAddress; ) end_extern_class(page_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize page service *! \param ptPage page_t object *! \param ptCFG configuration structure *! \retval true initialize succeed *! \retval false intizlization fail. */ extern bool page_init(page_t *ptPage, page_cfg_t *ptCFG); /*! \brief write memory disregard page *! \param ptPage page_t object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ extern fsm_rt_t write_memory_disregard_page( page_t *ptPage, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ); /*! \brief read memory disregard page *! \param ptPage page_t object *! \param hwAddress target memory address *! \param pchStream data buffer *! \param hwSize target buffer size *! \return state machine state */ extern fsm_rt_t read_memory_disregard_page( page_t *ptPage, uint_fast16_t hwAddress, uint8_t *pchStream, uint_fast16_t hwSize ); #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/sw_sdio/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __SW_SDIO_APP_CFG_H__ #define __SW_SDIO_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/sw_sdio/sw_sdio.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_COMPONENT_SW_SDIO == ENABLED #include "..\..\..\service\service.h" /*============================ MACROS ========================================*/ //! SDIO PROTOCOL TIMING CONTRAL #define SDIO_ONE_CLOCK (1) //!< The number of SDIO clock #define SDIO_WORK_CLOCK (13) #define SDIO_RESPONSE_TIME (0x65) //!< Command response time #define SDIO_READ_TIME (0x1FFF) #define SDIO_BUSY_TIME (0x1FFF) #define SDIO_CMD (0) //!< Select CMD line #define SDIO_DATA (1) //!< Select DATA line #define SDIO_CLK_TIME (s_wClockPeriod) //!< SDIO clock counter #define SHORT_RESPONSE_LENGTH (6) #define LONG_RESPONSE_LENGTH (17) #define LAST_BLOK (1) #define SDIO_CLK_SYNC ((uint8_t)0x01) #define SDIO_CMD_SYNC ((uint8_t)0x02) #define SDIO_DATA_SYNC ((uint8_t)0x04) #define SDIO_SYNC_END ((uint8_t)0x07) #define SDIO_SYNC_RESET ((uint8_t)0x08) #define SDIO_LOW_SYNC1 ((uint8_t)0x10) #define SDIO_LOW_SYNC2 ((uint8_t)0x20) #define SDIO_HIGH_SYNC1 ((uint8_t)0x40) #define SDIO_HIGH_SYNC2 ((uint8_t)0x80) #define IS_SDIO_LOW_SYNC (SDIO_LOW_SYNC1 | SDIO_LOW_SYNC2) #define IS_SDIO_HIGH_SYNC (SDIO_HIGH_SYNC1 | SDIO_HIGH_SYNC2) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name sdio return value type //! @{ typedef enum { SDIO_ON_GOING = 0, //!< SDIO is transfering SDIO_CMD_SET = 1, //!< Command already send, but no response required SDIO_CMD_RESPONSE = 2, //!< Command already receive, CRC check passed SDIO_CMD_CRCFAIL = 3, //!< Command already receive, CRC check failed SDIO_CMD_TIMEOUT = 4, //!< Command response timeout SDIO_DATA_CRCFALL = 5, //!< Wirte or read data CRC check failed SDIO_DATA_PASSED = 6, //!< Wirte or read data and CRC check passed SDIO_DATA_TIMEOUT = 7, //!< read data timeout SDIO_DATA_ERROR = 8 , //!< Write or read data error } em_sdio_rt_t; //! @} //! \name sdio response type //! @{ typedef enum { SDIO_NO_RESPONSE = 0, SDIO_STANDARD_RESPONSE, //!< Response 48 bits format SDIO_EXPAND_RESPONSE, //!< Response 136 bits format SDIO_SYNCHRONOUS_RECEIVE, //!< Synchronous receive 48 bits response and data } em_sdio_response_t; //! @} //! \name sdio direction type //! @{ typedef enum { SDIO_READ = 0, SDIO_WRITE, } em_sdio_direction_t; //! @} //! \name sdio block size type //! @{ typedef enum { SDIO_1B_BLOCK = 1, SDIO_2B_BLOCK = 2, SDIO_4B_BLOCK = 4, SDIO_8B_BLOCK = 8, SDIO_16B_BLOCK = 16, SDIO_32B_BLOCK = 32, SDIO_64B_BLOCK = 64, SDIO_128B_BLOCK = 128, SDIO_256B_BLOCK = 256, SDIO_512B_BLOCK = 512, SDIO_1024B_BLOCK = 1024, SDIO_2048B_BLOCK = 2048 } em_sdio_block_size_t; //! @} //! \name sdio config clock //! @{ typedef struct { uint8_t chClockDiv; } sdio_cfg_t; //! @} //! \name sdio command format //! @{ #pragma pack(1) typedef union { uint8_t chCMDFrame[17]; struct { uint8_t Index : 6; //!< 0 - 5 uint8_t TransferBit : 1; //!< 6 uint8_t StartBit : 1; //!< 7 uint8_t chArguments[4]; uint8_t StopBit : 1; //!< 0 uint8_t CRC7 : 7; //!< 1 - 7 uint8_t chReserved[11]; }; } sdio_cmd_t; #pragma pack() //! @} /*============================ PROTOTYPES ====================================*/ //! clock pin extern void SET_SDIO_CLK(void); extern void CLR_SDIO_CLK(void); extern bool READ_SDIO_CLK(void); //! command pin extern void SET_SDIO_CMD(void); extern void CLR_SDIO_CMD(void); extern bool READ_SDIO_CMD(void); //! data pin extern void SET_SDIO_DATA(void); extern void CLR_SDIO_DATA(void); extern bool READ_SDIO_DATA(void); /*============================ GLOBAL VARIABLES ==============================*/ NO_INIT static sdio_cfg_t s_tSDIOCfg; //!< Config SDIO speed NO_INIT static uint8_t s_chSDIOClkSync; //!< read command and data synchronization /*============================ LOCAL VARIABLES ===============================*/ /*============================ IMPLEMENTATION ================================*/ /*! \brief four byte combination a word(big endian) *! \param pchDataAddr target data address *! \return combination word data */ static uint32_t byte_combination_word(uint8_t *pchDataAddr) { uint32_t wValue; wValue = (pchDataAddr[0] << 24) | (pchDataAddr[1] << 16) | (pchDataAddr[2] << 8) | pchDataAddr[3]; return wValue; } /*! \brief sdio work clock generator *! \param hwClockNumbres number of clocks *! \return state machine status */ #define SDIO_WORK_CLK_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_work_clk(uint16_t hwClockNumbres) { NO_INIT static uint16_t s_hwClockCount; NO_INIT static uint32_t s_wTimeCount; NO_INIT static uint32_t s_wClockPeriod; static enum { START = 0, SDIO_CLR_CLK_TIME, SDIO_SET_CLK_TIME, SDIO_CLOCK_COUNT, } s_tState = START; switch (s_tState) { case START: s_wTimeCount = 0; s_hwClockCount = hwClockNumbres; SAFE_ATOM_CODE( s_wClockPeriod = s_tSDIOCfg.chClockDiv; ); CLR_SDIO_CLK(); s_tState = SDIO_CLR_CLK_TIME; break; case SDIO_CLR_CLK_TIME: if (SDIO_CLK_TIME >= s_wTimeCount++) { break; } s_wTimeCount = 0; SET_SDIO_CLK(); s_tState = SDIO_SET_CLK_TIME; case SDIO_SET_CLK_TIME: if (SDIO_CLK_TIME >= s_wTimeCount++) { break; } s_wTimeCount = 0; s_tState = SDIO_CLOCK_COUNT; case SDIO_CLOCK_COUNT: if (0 == --s_hwClockCount) { SDIO_WORK_CLK_RESET_FSM(); return fsm_rt_cpl; } CLR_SDIO_CLK(); s_tState = SDIO_CLR_CLK_TIME; break; } return fsm_rt_on_going; } /*! \brief sdio work clock generator *! \param none *! \return state machine status */ #define SDIO_WORK_SYNC_RESET_FSM() do {s_tState = SDIO_SYNC_START;} while (0) static fsm_rt_t sdio_work_sync(void) { static uint8_t s_chClockCount = 0; static enum { SDIO_SYNC_START = 0, SDIO_LOW_SYNC, SDIO_HIGH_SYNC, SDIO_WORK_CLK, SDIO_WAIT_SYNC, } s_tState = SDIO_SYNC_START; switch (s_tState) { case SDIO_SYNC_START: if (!(SDIO_CLK_SYNC & s_chSDIOClkSync)) { //check synchronization break; } CLR_SDIO_CLK(); s_tState = SDIO_LOW_SYNC; //break; case SDIO_LOW_SYNC: if (IS_SDIO_LOW_SYNC != (s_chSDIOClkSync & IS_SDIO_LOW_SYNC)) { break; } SET_SDIO_CLK(); if (SDIO_SYNC_RESET & s_chSDIOClkSync) { SDIO_WORK_SYNC_RESET_FSM(); break; } s_tState = SDIO_HIGH_SYNC; case SDIO_HIGH_SYNC: if (IS_SDIO_HIGH_SYNC != (s_chSDIOClkSync & IS_SDIO_HIGH_SYNC)) { break; } s_chSDIOClkSync &= ~(IS_SDIO_LOW_SYNC | IS_SDIO_HIGH_SYNC); if (SDIO_SYNC_END != (SDIO_SYNC_END & s_chSDIOClkSync)) { SDIO_WORK_SYNC_RESET_FSM(); break; } s_tState = SDIO_WAIT_SYNC; //break; case SDIO_WAIT_SYNC: SDIO_WORK_SYNC_RESET_FSM(); if (SDIO_WORK_CLOCK == ++s_chClockCount) { s_chClockCount = 0; return fsm_rt_cpl; } break; } return fsm_rt_on_going; } /*! \brief sdio command response synchronization with read data *! \param none *! \return state machine status */ #define SDIO_CMD_SYNC_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_cmd_sync(void) { static enum { START = 0, CHECK_LOW_LEVEL, CHECK_HIGH_LEVEL, } s_tState = START; switch (s_tState) { case START: s_tState = CHECK_LOW_LEVEL; //break; case CHECK_LOW_LEVEL: if (READ_SDIO_CLK()) { break; } s_chSDIOClkSync |= SDIO_LOW_SYNC1; s_tState = CHECK_HIGH_LEVEL; case CHECK_HIGH_LEVEL: if (!READ_SDIO_CLK()) { break; } s_chSDIOClkSync |= SDIO_HIGH_SYNC1; SDIO_CMD_SYNC_RESET_FSM(); return fsm_rt_cpl; } return fsm_rt_on_going; } /*! \brief sdio read data synchronization with command response *! \param none *! \return state machine status */ #define SDIO_DATA_SYNC_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_data_sync(void) { static enum { START = 0, CHECK_LOW_LEVEL, CHECK_HIGH_LEVEL, } s_tState = START; switch (s_tState) { case START: s_tState = CHECK_LOW_LEVEL; //break; case CHECK_LOW_LEVEL: if (READ_SDIO_CLK()) { break; } s_chSDIOClkSync |= SDIO_LOW_SYNC2; s_tState = CHECK_HIGH_LEVEL; case CHECK_HIGH_LEVEL: if (!READ_SDIO_CLK()) { break; } s_chSDIOClkSync |= SDIO_HIGH_SYNC2; SDIO_DATA_SYNC_RESET_FSM(); return fsm_rt_cpl; } return fsm_rt_on_going; } /*! \brief read command line bit data *! \param phwReadBit read data bit variable *! \param chBitNumbers number of bits *! \return state machine status */ #define SDIO_READ_CMD_BIT_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_read_cmd_bit(uint16_t *phwReadBit, uint8_t chBitNumbers) { NO_INIT static uint8_t s_chReadCount; static enum { START = 0, SDIO_READ_DATA, SDIO_READ_CLOCK, SDIO_READ_COUNT, } s_tState = START; if (NULL == phwReadBit) { return fsm_rt_err; } switch (s_tState) { case START: *phwReadBit = 0; s_chReadCount = chBitNumbers; if (0 == chBitNumbers) { return fsm_rt_cpl; } s_tState = SDIO_READ_CLOCK; //break; case SDIO_READ_CLOCK: if (SDIO_CLK_SYNC & s_chSDIOClkSync) { if (fsm_rt_cpl != sdio_cmd_sync()) { break; } } else { if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK)) { break; } } s_tState = SDIO_READ_DATA; case SDIO_READ_DATA: *phwReadBit <<= 1; if (READ_SDIO_CMD()) { (*phwReadBit)++; } s_tState = SDIO_READ_COUNT; //break; case SDIO_READ_COUNT: if (0 == --s_chReadCount) { SDIO_READ_CMD_BIT_FSM(); return fsm_rt_cpl; } s_tState = SDIO_READ_CLOCK; break; } return fsm_rt_on_going; } /*! \brief read data line bit data *! \param phwReadBit read data bit variable *! \param chBitNumbers number of bits *! \return state machine status */ #define SDIO_READ_DATA_BIT_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_read_data_bit(uint16_t *phwReadBit, uint8_t chBitNumbers) { NO_INIT static uint8_t s_chReadCount; static enum { START = 0, SDIO_READ_DATA, SDIO_READ_CLOCK, SDIO_READ_COUNT, } s_tState = START; if (NULL == phwReadBit) { return fsm_rt_err; } switch (s_tState) { case START: *phwReadBit = 0; s_chReadCount = chBitNumbers; if (0 == s_chReadCount) { return fsm_rt_err; } s_tState = SDIO_READ_CLOCK; //break; case SDIO_READ_CLOCK: if (SDIO_CLK_SYNC & s_chSDIOClkSync) { if (fsm_rt_cpl != sdio_data_sync()) { break; } } else { if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK)) { break; } } s_tState = SDIO_READ_DATA; case SDIO_READ_DATA: *phwReadBit <<= 1; if (READ_SDIO_DATA()) { (*phwReadBit)++; } s_tState = SDIO_READ_COUNT; //break; case SDIO_READ_COUNT: if (0 == --s_chReadCount) { SDIO_READ_DATA_BIT_FSM(); return fsm_rt_cpl; } s_tState = SDIO_READ_CLOCK; break; } return fsm_rt_on_going; } /*! \brief sdio write data line or cmd line data bits *! \param hwWriteBit write data bit variable *! \param chBitNumbers the number of bits *! \param chDataOrCMD select data line or cmd line *! \return state machine status */ #define SDIO_WRITE_BYTE_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_write_bit( uint16_t hwWriteBit, uint8_t chBitNumbers, uint8_t chDataOrCMD) { NO_INIT static uint8_t s_chWriteCount; static enum { START = 0, SDIO_WRITE_BIT, SDIO_WRITE_CLOCK, SDIO_WRITE_COUNT, } s_tState = START; switch (s_tState) { case START: s_chWriteCount = chBitNumbers; if (0 == chBitNumbers) { return fsm_rt_err; } s_tState = SDIO_WRITE_BIT; //break; case SDIO_WRITE_BIT: if (0x0001 & (hwWriteBit >> (s_chWriteCount - 1 ))) { //!> MSB if (SDIO_DATA == chDataOrCMD) { SET_SDIO_DATA(); } else { SET_SDIO_CMD(); } } else { if (SDIO_DATA == chDataOrCMD) { CLR_SDIO_DATA(); } else { CLR_SDIO_CMD(); } } s_tState = SDIO_WRITE_CLOCK; //break; case SDIO_WRITE_CLOCK: if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK)) { break; } s_tState = SDIO_WRITE_COUNT; case SDIO_WRITE_COUNT: if (0 == --s_chWriteCount) { SDIO_WRITE_BYTE_RESET_FSM(); return fsm_rt_cpl; } s_tState = SDIO_WRITE_BIT; break; } return fsm_rt_on_going; } /*! \brief sdio write cmd *! \param chCMDIndex command index *! \param wArgument command argument *! \return state machine status */ #define SDIO_SENT_CMD_RESET_FSM() do {s_tState = START;} while(0) static fsm_rt_t sdio_write_cmd(uint8_t chCMDIndex, uint32_t wArgument) { NO_INIT static sdio_cmd_t s_tSDIOCMD; NO_INIT static uint8_t s_chWritrCount; static enum { START = 0, SDIO_WRITE_CMD, SDIO_CMD_COUNT, } s_tState = START; switch (s_tState) { case START: s_chWritrCount = 0; s_tSDIOCMD.StartBit = 0; //!< Always 0 s_tSDIOCMD.TransferBit = 1; //!< SDIO transfer to card s_tSDIOCMD.Index = chCMDIndex; //! SDIO data high byte first send, but single byte high bit frist sned //! Program already process big and little endian problem,any cpu platform can run s_tSDIOCMD.chArguments[0] = (uint8_t)(wArgument >> 24); s_tSDIOCMD.chArguments[1] = (uint8_t)(wArgument >> 16); s_tSDIOCMD.chArguments[2] = (uint8_t)(wArgument >> 8); s_tSDIOCMD.chArguments[3] = (uint8_t)(wArgument); s_tSDIOCMD.chCMDFrame[5] = CRC7_INIT; //!< Calculate CRC value crc7_stream_check(&s_tSDIOCMD.chCMDFrame[5], s_tSDIOCMD.chCMDFrame, 5); s_tSDIOCMD.chCMDFrame[5] = s_tSDIOCMD.chCMDFrame[5] << 1; s_tSDIOCMD.StopBit = 1; s_tState = SDIO_WRITE_CMD; //break; case SDIO_WRITE_CMD: if (fsm_rt_cpl != sdio_write_bit(s_tSDIOCMD.chCMDFrame[s_chWritrCount], 8, SDIO_CMD)) { break; } s_tState = SDIO_CMD_COUNT; case SDIO_CMD_COUNT: if (6 <= ++s_chWritrCount) { SDIO_SENT_CMD_RESET_FSM(); return fsm_rt_cpl; } s_tState = SDIO_WRITE_CMD; break; } return fsm_rt_on_going; } /*! \brief sdio read cmd *! \param ptSDIOStatus sdio read command status, refer to em_sdio_rt_t type *! \param tResponseExpected response type, refer to em_sdio_response_t type *! \param pwResponse save response value *! \return state machine status */ #define SDIO_RECEIVE_CMD_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_read_cmd( em_sdio_rt_t *ptSDIOStatus, em_sdio_response_t tResponseExpected, uint32_t *pwResponse ) { NO_INIT static sdio_cmd_t s_tSDIOCMD; NO_INIT static uint8_t s_chReadBitsCount; //!< The number of read bits NO_INIT static uint8_t s_chReadCount; //!< The number of read data NO_INIT static uint16_t s_hwReadData; //!< Save read out data NO_INIT static uint8_t s_chCRCValue; static enum { START = 0, SDIO_WAIT_CMD, SDIO_CMD_TIME, SDIO_READ_CMD, SDIO_STANDARD_CMD, SDIO_EXTEND_CMD, SDIO_WAIT_SYNC, } s_tState = START; if ((NULL == ptSDIOStatus) || (NULL == pwResponse)) { return fsm_rt_err; } switch (s_tState) { case START: s_chReadCount = 0; s_hwReadData = 0; s_chReadBitsCount = 0; *ptSDIOStatus = SDIO_CMD_RESPONSE; s_tState = SDIO_WAIT_CMD; //break; case SDIO_WAIT_CMD: if (fsm_rt_cpl != sdio_read_cmd_bit(&s_hwReadData, 1)) { break; } if (0 == s_hwReadData) { s_chReadCount = 0; s_chReadBitsCount = 7; s_tState = SDIO_READ_CMD; break; } else { s_chReadCount++; s_tState = SDIO_CMD_TIME; } case SDIO_CMD_TIME: if (SDIO_RESPONSE_TIME >= s_chReadCount) { s_tState = SDIO_WAIT_CMD; break; } if (SDIO_CLK_SYNC & s_chSDIOClkSync) { //!< needed to synchronization *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_CMD_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_CMD_TIMEOUT; //!< Command response timeout SDIO_RECEIVE_CMD_RESET_FSM(); return fsm_rt_cpl; case SDIO_READ_CMD: if (fsm_rt_cpl != sdio_read_cmd_bit(&s_hwReadData, s_chReadBitsCount)) { break; } s_chReadBitsCount = 8; s_tSDIOCMD.chCMDFrame[s_chReadCount++] = (uint8_t)s_hwReadData; if (SDIO_EXPAND_RESPONSE == tResponseExpected) { s_tState = SDIO_EXTEND_CMD; } else { s_tState = SDIO_STANDARD_CMD; } break; case SDIO_STANDARD_CMD: if (SHORT_RESPONSE_LENGTH != s_chReadCount ) { //!< short response s_tState = SDIO_READ_CMD; break; } s_chCRCValue = CRC7_INIT; crc7_stream_check(&s_chCRCValue, s_tSDIOCMD.chCMDFrame, 5); s_chCRCValue = (s_chCRCValue << 1) | 0x01; //! CRC + Stop bit check if ((s_chCRCValue != s_tSDIOCMD.chCMDFrame[5]) && (0xFF != s_tSDIOCMD.chCMDFrame[5])) { if (SDIO_CLK_SYNC & s_chSDIOClkSync) { *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_CMD_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_CMD_CRCFAIL; //!< CRC check failed } else { //! SDIO data high byte first receive, but single byte high bit frist receive //! Program already process big and little endian problem,any cpu platform can run *pwResponse = byte_combination_word(s_tSDIOCMD.chArguments); } if (SDIO_CLK_SYNC & s_chSDIOClkSync) { s_chSDIOClkSync |= SDIO_CMD_SYNC; s_tState = SDIO_WAIT_SYNC; break; } SDIO_RECEIVE_CMD_RESET_FSM(); return fsm_rt_cpl; case SDIO_EXTEND_CMD: if (LONG_RESPONSE_LENGTH != s_chReadCount) { //!< long response s_tState = SDIO_READ_CMD; break; } s_chCRCValue = CRC7_INIT; crc7_stream_check(&s_chCRCValue, &s_tSDIOCMD.chCMDFrame[1], 15); s_chCRCValue = (s_chCRCValue << 1) | 0x01; if (s_chCRCValue != s_tSDIOCMD.chCMDFrame[16]) { if (SDIO_CLK_SYNC & s_chSDIOClkSync) { *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_CMD_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_CMD_CRCFAIL; //!< CRC check failed } else { //! SDIO data high byte first receive, but single byte high bit frist receive //! Program already process big and little endian problem,any cpu platform can run pwResponse[0] = byte_combination_word(&s_tSDIOCMD.chCMDFrame[1]); //!> [127:96] pwResponse[1] = byte_combination_word(&s_tSDIOCMD.chCMDFrame[5]); //!> [95:64] pwResponse[2] = byte_combination_word(&s_tSDIOCMD.chCMDFrame[9]); //!> [63:32] pwResponse[3] = byte_combination_word(&s_tSDIOCMD.chCMDFrame[13]); //!> [31:1] } if (SDIO_CLK_SYNC & s_chSDIOClkSync) { s_chSDIOClkSync |= SDIO_CMD_SYNC; s_tState = SDIO_WAIT_SYNC; break; } SDIO_RECEIVE_CMD_RESET_FSM(); return fsm_rt_cpl; case SDIO_WAIT_SYNC: if (fsm_rt_cpl != sdio_read_cmd_bit(&s_hwReadData, 1)) { break; } if (SDIO_SYNC_RESET & s_chSDIOClkSync) { SDIO_RECEIVE_CMD_RESET_FSM(); return fsm_rt_cpl; } } return fsm_rt_on_going; } /*! \brief sdio write data *! \param tBlockSize set block size *! \param pchData data buffer pointer *! \param hwDataSize data size *! \return state machine status */ #define SDIO_WRITE_DATA_RESET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_write_data( em_sdio_block_size_t tBlockSize, uint8_t *pchData, uint16_t hwDataSize ) { NO_INIT static uint8_t *s_pchData; NO_INIT static uint16_t s_hwCRC16; //!< Use to crc check NO_INIT static uint16_t s_hwRestData; NO_INIT static uint16_t s_hwDataCount; NO_INIT static uint16_t s_hwBlockNumbers; static enum { START = 0, SDIO_WRITE_START, SDIO_WRITE_DATA, SDIO_WRITE_COUNT, SDIO_WRITE_CRC, SDIO_WRITE_STOP, SDIO_CHECK_CRC, SDIO_CHECK_BUSY, SDIO_WRITE_WAIT, } s_tState = START; if (NULL == pchData) { return fsm_rt_err; } switch (s_tState) { case START: s_hwRestData = 0; s_hwDataCount = 0; s_hwBlockNumbers = 0; s_hwCRC16 = CRC16_MODEM_INIT; s_pchData = pchData; if ((0 == (uint16_t)tBlockSize) && (0 == hwDataSize)) { return fsm_rt_err; } if (0 == hwDataSize % (uint16_t)tBlockSize) { s_hwRestData = (uint16_t)tBlockSize; s_hwBlockNumbers = hwDataSize / (uint16_t)tBlockSize; } else { s_hwRestData = hwDataSize % (uint16_t)tBlockSize; s_hwBlockNumbers = hwDataSize / (uint16_t)tBlockSize + 1; } CLR_SDIO_DATA(); s_tState = SDIO_WRITE_START; //break case SDIO_WRITE_START: if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK)) { break; } s_tState = SDIO_WRITE_DATA; case SDIO_WRITE_DATA: if (fsm_rt_cpl != sdio_write_bit((uint16_t)(*s_pchData), 8, SDIO_DATA)) { break; } crc16_modem_check(&s_hwCRC16, *s_pchData++); s_hwDataCount++; s_tState = SDIO_WRITE_COUNT; case SDIO_WRITE_COUNT: if (LAST_BLOK == s_hwBlockNumbers) { if (s_hwRestData == s_hwDataCount) { s_hwDataCount = 0; s_tState = SDIO_WRITE_CRC; } else { s_tState = SDIO_WRITE_DATA; break; } } else { if (tBlockSize == s_hwDataCount) { s_hwDataCount = 0; s_tState = SDIO_WRITE_CRC; } else { s_tState = SDIO_WRITE_DATA; break; } } case SDIO_WRITE_CRC: if (fsm_rt_cpl != sdio_write_bit(s_hwCRC16, 16, SDIO_DATA)) { break; } SET_SDIO_DATA(); //!< Write stop bit s_tState = SDIO_WRITE_STOP; case SDIO_WRITE_STOP: if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK * 3)) { break; } s_tState = SDIO_CHECK_CRC; case SDIO_CHECK_CRC: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwCRC16, 5)) { break; } //! start bit(always 0) + sdio card return 3 bit crc(only 010 is correct) + stop bit(always 1) = 00101 if (0x05 != s_hwCRC16) { SDIO_WRITE_DATA_RESET_FSM(); return fsm_rt_err; } s_tState = SDIO_CHECK_BUSY; case SDIO_CHECK_BUSY: //! The s_hwCRC16 saves receive stop bit if (fsm_rt_cpl != sdio_read_data_bit(&s_hwCRC16, 1)) { break; } if (0 == s_hwCRC16) { //!< SDIO bus is busy s_tState = SDIO_WRITE_WAIT; break; } if (LAST_BLOK == s_hwBlockNumbers) { SDIO_WRITE_DATA_RESET_FSM(); return fsm_rt_cpl; } s_hwBlockNumbers--; s_hwDataCount = 0; s_hwCRC16 = CRC16_MODEM_INIT; CLR_SDIO_DATA(); s_tState = SDIO_WRITE_START; break; case SDIO_WRITE_WAIT: if (SDIO_BUSY_TIME <= ++s_hwDataCount) { SDIO_WRITE_DATA_RESET_FSM(); return fsm_rt_err; } s_tState = SDIO_CHECK_BUSY; break; } return fsm_rt_on_going; } /*! \brief sdio read data *! \param ptSDIOStatus sdio read data status, refer to em_sdio_rt_t type *! \param tBlockSize set block size *! \param pchData data buffer pointer *! \param hwDataSize data size *! \return state machine status */ #define SDIO_READ_DATA_REAET_FSM() do {s_tState = START;} while (0) static fsm_rt_t sdio_read_data( em_sdio_rt_t *ptSDIOStatus, em_sdio_block_size_t tBlockSize, uint8_t *pchData, uint16_t hwDataSize ) { NO_INIT static uint8_t *s_pchData; NO_INIT static uint16_t s_hwCRC16; NO_INIT static uint16_t s_hwRestData; NO_INIT static uint16_t s_hwReadData; NO_INIT static uint16_t s_hwDataCount; NO_INIT static uint16_t s_hwBlockNumbers; static enum { START = 0, SDIO_READ_START, SDIO_READ_DATA, SDIO_READ_COUNT, SDIO_READ_CRC, SDIO_READ_STOP, SDIO_WAIT_SYNC, } s_tState = START; if ((NULL == ptSDIOStatus) || (NULL == pchData)) { return fsm_rt_err; } switch (s_tState) { case START: s_hwRestData = 0; s_hwDataCount = 0; s_hwBlockNumbers = 0; s_hwCRC16 = CRC16_MODEM_INIT; *ptSDIOStatus = SDIO_DATA_PASSED; s_pchData = pchData; if ((0 == ((uint16_t)tBlockSize) && (0 == hwDataSize))) { return fsm_rt_err; } if (0 == (hwDataSize % (uint16_t)tBlockSize)) { s_hwRestData = (uint16_t)tBlockSize; s_hwBlockNumbers = hwDataSize / (uint16_t)tBlockSize; } else { s_hwRestData = hwDataSize % (uint16_t)tBlockSize; s_hwBlockNumbers = hwDataSize / (uint16_t)tBlockSize + 1; } s_tState = SDIO_READ_START; //break; case SDIO_READ_START: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwReadData, 1)) { break; } if (0 == s_hwReadData) { //!< read start bit(start bit always 0) s_hwDataCount = 0; s_tState = SDIO_READ_DATA; break; } if (SDIO_READ_TIME != ++s_hwDataCount) { break; } if (SDIO_CLK_SYNC & s_chSDIOClkSync) { *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_DATA_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_DATA_TIMEOUT; SDIO_READ_DATA_REAET_FSM(); return fsm_rt_cpl; case SDIO_READ_DATA: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwReadData, 8)) { break; } *s_pchData++ = (uint8_t)s_hwReadData; crc16_modem_check(&s_hwCRC16, (uint8_t)s_hwReadData); s_hwDataCount++; s_tState = SDIO_READ_COUNT; case SDIO_READ_COUNT: if (LAST_BLOK == s_hwBlockNumbers) { if (s_hwRestData == s_hwDataCount) { s_hwDataCount = 0; s_tState = SDIO_READ_CRC; } else { s_tState = SDIO_READ_DATA; break; } } else { if (tBlockSize == s_hwDataCount) { s_hwDataCount = 0; s_tState = SDIO_READ_CRC; } else { s_tState = SDIO_READ_DATA; break; } } case SDIO_READ_CRC: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwReadData, 16)) { break; } if (s_hwCRC16 != s_hwReadData) { if (SDIO_CLK_SYNC & s_chSDIOClkSync) { *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_DATA_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_DATA_CRCFALL; SDIO_READ_DATA_REAET_FSM(); return fsm_rt_cpl; } s_tState = SDIO_READ_STOP; case SDIO_READ_STOP: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwReadData, 1)) { break; } if (0 == s_hwReadData) { //!< receive stop bit(The stop bit always 1) if (SDIO_CLK_SYNC & s_chSDIOClkSync) { *ptSDIOStatus = SDIO_DATA_ERROR; s_chSDIOClkSync |= SDIO_DATA_SYNC; s_tState = SDIO_WAIT_SYNC; break; } *ptSDIOStatus = SDIO_DATA_ERROR; SDIO_READ_DATA_REAET_FSM(); return fsm_rt_cpl; } if (LAST_BLOK == s_hwBlockNumbers) { s_chSDIOClkSync |= SDIO_DATA_SYNC; s_tState = SDIO_WAIT_SYNC; break; } s_hwBlockNumbers--; s_hwCRC16 = CRC16_MODEM_INIT; s_tState = SDIO_READ_START; break; case SDIO_WAIT_SYNC: if (fsm_rt_cpl != sdio_read_data_bit(&s_hwReadData, 1)) { break; } if (SDIO_SYNC_RESET & s_chSDIOClkSync) { s_chSDIOClkSync = 0; SDIO_RECEIVE_CMD_RESET_FSM(); return fsm_rt_cpl; } } return fsm_rt_on_going; } /*! \brief sdio initialize *! \param ptSDIOcfg sdio_cfg_t type pointer *! \return state machine status */ #define SDIO_INIT_RESET_FSM() do {s_tState = START;} while (0) fsm_rt_t sdio_init(sdio_cfg_t *ptSDIOCfg) { static enum { START = 0, INIT_CLOCK, } s_tState = START; if (NULL == ptSDIOCfg) { return fsm_rt_err; } switch (s_tState) { case START: SET_SDIO_DATA(); SET_SDIO_CMD(); SET_SDIO_CLK(); s_chSDIOClkSync = 0; SAFE_ATOM_CODE ( s_tSDIOCfg.chClockDiv = ptSDIOCfg->chClockDiv; ); s_tState = INIT_CLOCK; //break; case INIT_CLOCK: if (fsm_rt_cpl != sdio_work_clk(SDIO_ONE_CLOCK * 74)) { break; } SDIO_INIT_RESET_FSM(); return fsm_rt_cpl; } return fsm_rt_on_going; } /*! \brief sdio change clock frequency *! \param chClockDiv set sdio clock frequency *! \retval none */ void sdio_change_clock(uint8_t chClockDiv) { SAFE_ATOM_CODE ( s_tSDIOCfg.chClockDiv = chClockDiv; ); } /*! \brief sdio command transfer *! \param chCMDIndex command index *! \param wArgument command argument *! \param tResponseExpected response type, refer to em_sdio_response_t type *! \param pwResponse save response value *! \return sdio state, refer to em_sdio_rt_t type */ #define SDIO_CMD_TRANSFER_RESET_FSM() do {s_tState = START;} while (0) em_sdio_rt_t sdio_cmd_transfer( uint8_t chCMDIndex, uint32_t wArgument, em_sdio_response_t tResponseExpected, uint32_t *pwResponse ) { NO_INIT static em_sdio_rt_t s_tSDIOStatus; static enum { START = 0, SDIO_WRITE_CMD, //!< SDIO cmd bus sent command SDIO_READ_CMD, //!< Receive command response SDIO_WORK_CLK, //!< SDIO card work needed clk } s_tState = START; if (fsm_rt_cpl == sdio_work_sync()) { s_chSDIOClkSync |= SDIO_SYNC_RESET; } switch (s_tState) { case START: s_tState = SDIO_WRITE_CMD; //break; case SDIO_WRITE_CMD: if (fsm_rt_cpl != sdio_write_cmd(chCMDIndex, wArgument)) { break; } if (SDIO_NO_RESPONSE == tResponseExpected) { s_tState = SDIO_WORK_CLK; break; } else if (SDIO_SYNCHRONOUS_RECEIVE == tResponseExpected){ s_chSDIOClkSync |= SDIO_CLK_SYNC; } s_tState = SDIO_READ_CMD; case SDIO_READ_CMD: if (fsm_rt_cpl != sdio_read_cmd(&s_tSDIOStatus, tResponseExpected, pwResponse)) { break; } s_tState = SDIO_WORK_CLK; case SDIO_WORK_CLK: if (SDIO_SYNCHRONOUS_RECEIVE != tResponseExpected) { if (fsm_rt_cpl != sdio_work_clk(SDIO_WORK_CLOCK)) { break; } } SDIO_CMD_TRANSFER_RESET_FSM(); if (SDIO_NO_RESPONSE == tResponseExpected) { return SDIO_CMD_SET; } return s_tSDIOStatus; } return SDIO_ON_GOING; } /*! \brief sdio data transfer *! \param tDirection sdio transfer direction, refer to em_sdio_direction_t type *! \param tBlockSize set block size *! \param pchData data buffer pointer *! \param hwDataSize data size *! \return sdio state, refer to em_sdio_rt_t type */ #define SDIO_DATA_TRANSFER_RESET_FSM() do {s_tState = START;} while (0) em_sdio_rt_t sdio_data_transfer( em_sdio_direction_t tDirection, em_sdio_block_size_t tBlockSize, uint8_t *pchData, uint16_t hwDataSize ) { NO_INIT static em_sdio_rt_t s_tSDIOStatus; fsm_rt_t tFsmState; static enum { START = 0, SDIO_WRITE_DATA, SDIO_READ_DATA, SDIO_WORK_CLK, } s_tState = START; switch (s_tState) { case START: if (SDIO_WRITE == tDirection) { s_tState = SDIO_WRITE_DATA; } else { s_tState = SDIO_READ_DATA; } break; case SDIO_WRITE_DATA: tFsmState = sdio_write_data(tBlockSize, pchData, hwDataSize); if (fsm_rt_on_going == tFsmState) { break; } else if (fsm_rt_cpl == tFsmState) { s_tSDIOStatus = SDIO_DATA_PASSED; } else if (fsm_rt_err == tFsmState) { s_tSDIOStatus = SDIO_DATA_ERROR; } s_tState = SDIO_WORK_CLK; // break; case SDIO_WORK_CLK: if (fsm_rt_cpl != sdio_work_clk(SDIO_WORK_CLOCK)) { break; } SDIO_DATA_TRANSFER_RESET_FSM(); return s_tSDIOStatus; case SDIO_READ_DATA: if (!(SDIO_CLK_SYNC & s_chSDIOClkSync)) { break; } if (fsm_rt_cpl != sdio_read_data(&s_tSDIOStatus, tBlockSize, pchData, hwDataSize)) { break; } SDIO_DATA_TRANSFER_RESET_FSM(); return s_tSDIOStatus; } return SDIO_ON_GOING; } #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/component/sw_sdio/sw_sdio.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __SW_SDIO_H__ #define __SW_SDIO_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_COMPONENT_SW_SDIO == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name sdio config clock //! @{ typedef struct { uint8_t chClockDiv; } sdio_cfg_t; //! @} //! \name sdio return value type //! @{ typedef enum { SDIO_ON_GOING = 0, //!< SDIO is transfering SDIO_CMD_SET = 1, //!< Command already send, but no response required SDIO_CMD_RESPONSE = 2, //!< Command already receive, CRC check passed SDIO_CMD_CRCFAIL = 3, //!< Command already receive, CRC check failed SDIO_CMD_TIMEOUT = 4, //!< Command response timeout SDIO_DATA_CRCFALL = 5, //!< Wirte or read data CRC check failed SDIO_DATA_PASSED = 6, //!< Wirte or read data and CRC check passed SDIO_DATA_TIMEOUT = 7, //!< read data timeout SDIO_DATA_ERROR = 8 , //!< Write or read data error } em_sdio_rt_t; //! @} //! \name sdio response type //! @{ typedef enum { SDIO_NO_RESPONSE = 0, SDIO_STANDARD_RESPONSE, //!< Response 48 bits format SDIO_EXPAND_RESPONSE, //!< Response 136 bits format SDIO_SYNCHRONOUS_RECEIVE, //!< Synchronous receive 48 bits response and data } em_sdio_response_t; //! @} //! \name sdio direction type //! @{ typedef enum { SDIO_READ = 0, SDIO_WRITE, } em_sdio_direction_t; //! @} //! \name sdio block size type //! @{ typedef enum { SDIO_1B_BLOCK = 1, SDIO_2B_BLOCK = 2, SDIO_4B_BLOCK = 4, SDIO_8B_BLOCK = 8, SDIO_16B_BLOCK = 16, SDIO_32B_BLOCK = 32, SDIO_64B_BLOCK = 64, SDIO_128B_BLOCK = 128, SDIO_256B_BLOCK = 256, SDIO_512B_BLOCK = 512, SDIO_1024B_BLOCK = 1024, SDIO_2048B_BLOCK = 2048 } em_sdio_block_size_t; //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief sdio initialize *! \param ptSDIOcfg sdio_cfg_t type pointer *! \return state machine status */ extern fsm_rt_t sdio_init(sdio_cfg_t *ptSDIOCfg); /*! \brief sdio change clock frequency *! \param chClockDiv set sdio clock frequency *! \retval none */ extern void sdio_change_clock(uint8_t chClockDiv); /*! \brief sdio command transfer *! \param chCMDIndex command index *! \param wArgument command argument *! \param tResponseExpected response type, refer to em_sdio_response_t type *! \param pwResponse save response value *! \return sdio state, refer to em_sdio_rt_t type */ extern em_sdio_rt_t sdio_cmd_transfer( uint8_t chCMDIndex, uint32_t wArgument, em_sdio_response_t tResponseExpected, uint32_t *pwResponse); /*! \brief sdio data transfer *! \param tDirection sdio transfer direction, refer to em_sdio_direction_t type *! \param tBlockSize set block size *! \param pchData data buffer pointer *! \param hwDataSize data size *! \return sdio state, refer to em_sdio_rt_t type */ extern em_sdio_rt_t sdio_data_transfer( em_sdio_direction_t tDirection, em_sdio_block_size_t tBlockSize, uint8_t *pchData, uint16_t hwDataSize); #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/hal/hal.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\component\component.h" #include ".\bsp\bsp.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note initialize hardware abstract layer * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ bool hal_init( void ) { /*! initialize components */ if ( !component_init() ) { return false; } /*! initialize bsp */ if ( !bsp_init() ) { return false; } return true; } /* EOF */ ================================================ FILE: sources/gmsi/hal/hal.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __HAL_H__ #define __HAL_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\component\component.h" #include ".\bsp\bsp.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize hardware abstract layer * \param none * \retval true hal initialization succeeded. * \retval false hal initialization failed */ extern bool hal_init( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/service/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __USE_SERVICE_APP_CFG__ #define __USE_SERVICE_APP_CFG__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/app_cfg.h ================================================ /*************************************************************************** * Copyright(C)2009-2012 by Gorgon Meducer * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU Lesser General Public License as * * published by the Free Software Foundation; either version 2 of the * * License, or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU Lesser General Public * * License along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __USE_SERVICE_COMMUNICATION_APP_CFG__ #define __USE_SERVICE_COMMUNICATION_APP_CFG__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/communication.h ================================================ /*************************************************************************** * Copyright(C)2009-2012 by Gorgon Meducer * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU Lesser General Public License as * * published by the Free Software Foundation; either version 2 of the * * License, or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU Lesser General Public * * License along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ #ifndef __USE_COMMUNICATION_H__ #define __USE_COMMUNICATION_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\frame\frame.h" #include ".\xmodem\xmodem.h" #include ".\crc\crc.h" #include ".\telegraph_engine\telegraph_engine.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/crc/app_cfg.h ================================================ /*************************************************************************** * Copyright(C)2009-2010 by Gorgon Meducer * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU Lesser General Public License as * * published by the Free Software Foundation; either version 2 of the * * License, or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU Lesser General Public * * License along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __SERVICE_COMMUNICATION_CRC_APP_CFG_H__ #define __SERVICE_COMMUNICATION_CRC_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/crc/crc.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \brief crc16 *! \param pwCRCValue CRC Variable *! \param chData target byte *! \return CRC16 result */ uint16_t crc16_check(uint16_t *pwCRCValue,uint8_t chData) { uint16_t wCRC = (*pwCRCValue); chData ^= (uint8_t)((uint16_t)wCRC & 0x00FF); chData ^= chData << 4; (*pwCRCValue) = ((((uint16_t)chData << 8) | (wCRC >> 8)) ^ (uint8_t)(chData >> 4) ^ ((uint16_t)chData << 3)); return (*pwCRCValue); } uint16_t crc16_stream_check(uint16_t *pwCRCValue, uint8_t *pchStream, uint16_t hwSize) { if (NULL == pchStream || 0 == hwSize || NULL == pwCRCValue) { return 0; } do { crc16_check(pwCRCValue, *pchStream++); } while(--hwSize); return (*pwCRCValue); } /* EOF */ ================================================ FILE: sources/gmsi/service/communication/crc/crc.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __CRC_H__ #define __CRC_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ //! \brief CRC initialized value #define CRC_INIT (0xFFFF) #define CRC7_INIT (0x00) #define CRC8_INIT (0x00) #define CRC8_ROHC_INIT (0xFF) #define CRC16_MODBUS_INIT (0xFFFF) #define CRC16_USB_INIT (0xFFFF) #define CRC16_CCITT_FALSE_INIT (0xFFFF) #define CRC16_MODEM_INIT (0x0000) #define CRC32_INIT (0xFFFFFFFF) #define CRC32_IEEE802_3_INIT (0xFFFFFFFF) /*============================ MACROFIED FUNCTIONS ===========================*/ #define GMSI_CRC(__CRCVAL,__NEWCHAR) crc16_check(&(__CRCVAL),(__NEWCHAR)) #define GMSI_CRC16(__CRCVAL,__NEWCHAR) crc16_check(&(__CRCVAL),(__NEWCHAR)) #define GMSI_CRC8(__CRCVAL,__NEWCHAR) crc8_check(&(__CRCVAL),(__NEWCHAR)) #define GMSI_CRC32_IEEE802_3(__CRCVAL,__NEWCHAR) crc32_ieee802_3_check(&(__CRCVAL),(__NEWCHAR)) /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC7 result */ extern uint8_t crc7_stream_check( uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data byte *! \return CRC7 result */ extern uint8_t crc7_check(uint8_t *pchCRCValue, uint8_t chData); /*! \brief crc16 *! \param pwCRCValue CRC Variable *! \param chData target byte *! \return CRC16 result */ extern uint16_t crc16_check(uint16_t *pwCRCValue,uint8_t chData); extern uint16_t crc16_stream_check(uint16_t *pwCRCValue, uint8_t *pchStream, uint16_t hwSize); /*! \brief CRC8 *! \param pchCRCValue CRC Variable *! \param chData target byte *! \return CRC8 result */ extern uint8_t crc8_check(uint8_t *pchCRCValue, uint8_t chByte); /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ extern uint8_t crc8_stream_check( uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data byte *! \return CRC8 result */ extern uint8_t crc8_check(uint8_t *pchCRCValue, uint8_t chData); /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ extern uint8_t crc8_rohc_stream_check( uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC8 result */ extern uint8_t crc8_rohc_check(uint8_t *pchCRCValue, uint8_t chData); /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ extern uint16_t crc16_ccitt_false_stream_check( uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC16 result */ extern uint16_t crc16_ccitt_false_check(uint16_t *phwCRCValue, uint8_t chData); /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ extern uint16_t crc16_usb_stream_check( uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ extern uint16_t crc16_usb_check(uint16_t *phwCRCValue, uint8_t chData); /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ extern uint16_t crc16_modbus_stream_check( uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC16 result */ extern uint16_t crc16_modbus_check(uint16_t *phwCRCValue, uint8_t chData); /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ extern uint16_t crc16_modem_stream_check( uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC16 result */ extern uint16_t crc16_modem_check(uint16_t *phwCRCValue, uint8_t chData); /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ extern uint32_t crc32_ieee802_3_stream_check( uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ extern uint32_t crc32_ieee802_3_check(uint32_t *pwCRCValue, uint8_t chData); /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ extern uint32_t crc32_stream_check( uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength ); /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ extern uint32_t crc32_check(uint32_t *pwCRCValue, uint8_t chData); #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/crc/crc16.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ //! \berif This poly contains CRC16_MODBUS and CRC16_USB #define CRC16_POLY (0x8005) #define CRC16_CCITT_FALSE_POLY (0x1021) //!< Equal to CRC16 MODEM /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #if (CRC16_MODBUS_OPTIMIZE == CRC_OPT_SPEED) || (CRC16_USB_OPTIMIZE == CRC_OPT_SPEED) //! This table contains CRC16_MODBUS and CRC16_USB static const uint16_t c_hwCRC16Table[256] = { 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040, }; #endif #if (CRC16_MODBUS_OPTIMIZE == CRC_OPT_BALANCE) || (CRC16_USB_OPTIMIZE == CRC_OPT_BALANCE) static const uint16_t c_hwCRC16Tab[16] = { 0x0000, 0xCC01, 0xD801, 0x1400, 0xF001, 0x3C00, 0x2800, 0xE401, 0xA001, 0x6C00, 0x7800, 0xB401, 0x5000, 0x9C01, 0x8801, 0x4400, }; #endif #if (CRC16_CCITT_FALSE_OPTIMIZE == CRC_OPT_SPEED) || (CRC16_MODEM_OPTIMIZE == CRC_OPT_SPEED) //! this name is specific static const uint16_t c_hwCRC16_CCITT_Table[256] = { 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, }; #endif #if (CRC16_CCITT_FALSE_OPTIMIZE == CRC_OPT_BALANCE) || (CRC16_MODEM_OPTIMIZE == CRC_OPT_BALANCE) static const uint16_t c_hwCRC16_CCITT_Tab[16] = { 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, }; #endif /*============================ IMPLEMENTATION ================================*/ #if (CRC16_MODBUS_OPTIMIZE == CRC_OPT_SIZE) || (CRC16_USB_OPTIMIZE == CRC_OPT_SIZE) /*! \brief data reversal *! \param wValue need to reversal data *! \param chLength data bit length *! \return already reversal data */ static uint32_t data_reversal(uint32_t wValue, uint8_t chLength) { uint8_t i; uint32_t wTempValue = 0; for (i = 1; i < (chLength + 1); i++) { if (wValue & 0x01) { wTempValue |= ((uint32_t)1 << (chLength - i)); } wValue >>= 1; } return wTempValue; } #endif #if CRC16_USB_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_usb_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { hwCRC16 = ((*phwCRCValue) ^ (*pchData++)) & 0x00FF; hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); for (j = 0; j < 8; j++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_POLY; } else { hwCRC16 <<= 1; } } hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); *phwCRCValue = (*phwCRCValue >> 8) ^ hwCRC16; } return (*phwCRCValue = ~(*phwCRCValue)); } /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_usb_check(uint16_t *phwCRCValue, uint8_t chData) { uint32_t i; uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = ((*phwCRCValue) ^ chData) & 0x00FF; hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); for (i = 0; i < 8; i++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_POLY; } else { hwCRC16 <<= 1; } } hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); *phwCRCValue = (*phwCRCValue >> 8) ^ hwCRC16; return *phwCRCValue; } #endif #if CRC16_USB_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_usb_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (*pchData & 0x0F)]; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (*pchData++ >> 4)]; } return (*phwCRCValue = ~hwCRC16); } /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_usb_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (chData & 0x0F)]; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (chData >> 4)]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_USB_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_usb_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 >> 8) ^ c_hwCRC16Table[(hwCRC16 ^ *pchData++) & 0xFF]; } return (*phwCRCValue = ~hwCRC16); } /*! \brief CRC16 USB *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFF *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_usb_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 >> 8) ^ c_hwCRC16Table[(hwCRC16 ^ chData) & 0xFF]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_MODBUS_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modbus_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { hwCRC16 = ((*phwCRCValue) ^ (*pchData++)) & 0x00FF; hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); for (j = 0; j < 8; j++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_POLY; } else { hwCRC16 <<= 1; } } hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); *phwCRCValue = (*phwCRCValue >> 8) ^ hwCRC16; } return *phwCRCValue; } /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_modbus_check(uint16_t *phwCRCValue, uint8_t chData) { uint32_t i; uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = ((*phwCRCValue) ^ chData) & 0x00FF; hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); for (i = 0; i < 8; i++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_POLY; } else { hwCRC16 <<= 1; } } hwCRC16 = (uint16_t)data_reversal(hwCRC16, 16); *phwCRCValue = (*phwCRCValue >> 8) ^ hwCRC16; return *phwCRCValue; } #endif #if CRC16_MODBUS_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modbus_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (*pchData & 0x0F)]; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (*pchData++ >> 4)]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_modbus_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (chData & 0x0F)]; hwCRC16 = (hwCRC16 >> 4) ^ c_hwCRC16Tab[(hwCRC16 & 0x000F) ^ (chData >> 4)]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_MODBUS_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modbus_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 >> 8) ^ c_hwCRC16Table[(hwCRC16 ^ *pchData++) & 0xFF]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 MODBUS *! Poly: 0x8005 *! Init: 0xFFFF *! RefIn: True *! RefOut: True *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_modbus_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 >> 8) ^ c_hwCRC16Table[(hwCRC16 ^ chData) & 0xFF]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_CCITT_FALSE_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_ccitt_false_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { hwCRC16 = ((uint16_t)(*pchData++) << 8) ^ (*phwCRCValue & 0xFF00); for (j = 0; j < 8; j++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_CCITT_FALSE_POLY; } else { hwCRC16 <<= 1; } } *phwCRCValue = (*phwCRCValue << 8) ^ hwCRC16; } return *phwCRCValue; } /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC16 result */ uint16_t crc16_ccitt_false_check(uint16_t *phwCRCValue, uint8_t chData) { uint32_t i; uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = ((uint32_t)chData << 8) ^ (*phwCRCValue & 0xFF00); for (i = 0; i < 8; i++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_CCITT_FALSE_POLY; } else { hwCRC16 <<= 1; } } *phwCRCValue = (*phwCRCValue << 8) ^ hwCRC16; return *phwCRCValue; } #endif #if CRC16_CCITT_FALSE_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_ccitt_false_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (*pchData >> 4)]; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (*pchData++ & 0x0F)]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \return CRC16 result */ uint16_t crc16_ccitt_false_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (chData >> 4)]; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (chData & 0x0F)]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_CCITT_FALSE_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_ccitt_false_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 << 8) ^ c_hwCRC16_CCITT_Table[(hwCRC16 >> 8) ^ *pchData++]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 CCITT FALSE *! Poly: 0x1021 *! Init: 0xFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_ccitt_false_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 << 8) ^ c_hwCRC16_CCITT_Table[(hwCRC16 >> 8) ^ chData]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_MODEM_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modem_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { hwCRC16 = ((uint16_t)(*pchData++) << 8) ^ (*phwCRCValue & 0xFF00); for (j = 0; j < 8; j++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_CCITT_FALSE_POLY; } else { hwCRC16 <<= 1; } } *phwCRCValue = (*phwCRCValue << 8) ^ hwCRC16; } return *phwCRCValue; } /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC16 result */ uint16_t crc16_modem_check(uint16_t *phwCRCValue, uint8_t chData) { uint32_t i; uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = ((uint32_t)chData << 8) ^ (*phwCRCValue & 0xFF00); for (i = 0; i < 8; i++) { if (hwCRC16 & 0x8000) { hwCRC16 <<= 1; hwCRC16 ^= CRC16_CCITT_FALSE_POLY; } else { hwCRC16 <<= 1; } } *phwCRCValue = (*phwCRCValue << 8) ^ hwCRC16; return *phwCRCValue; } #endif #if CRC16_MODEM_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modem_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16 = 0; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (*pchData >> 4)]; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (*pchData++ & 0x0F)]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \return CRC16 result */ uint16_t crc16_modem_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16 = 0; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (chData >> 4)]; hwCRC16 = (hwCRC16 << 4) ^ c_hwCRC16_CCITT_Tab[(hwCRC16 >> 12) ^ (chData & 0x0F)]; return (*phwCRCValue = hwCRC16); } #endif #if CRC16_MODEM_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC16 result */ uint16_t crc16_modem_stream_check(uint16_t *phwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t hwCRC16; if ((NULL == phwCRCValue) || (NULL == pchData)) { return false; } hwCRC16 = *phwCRCValue; for (i = 0; i < wLength; i++) { hwCRC16 = (hwCRC16 << 8) ^ c_hwCRC16_CCITT_Table[(hwCRC16 >> 8) ^ *pchData++]; } return (*phwCRCValue = hwCRC16); } /*! \brief CRC16 XMODEM or ZMODEM or ACORN *! Poly: 0x1021 *! Init: 0x0000 *! RefIn: False *! RefOut: False *! XorOut: 0x0000 *! \param phwCRCValue CRC Variable *! \param pchData target data *! \return CRC16 result */ uint16_t crc16_modem_check(uint16_t *phwCRCValue, uint8_t chData) { uint16_t hwCRC16; if (NULL == phwCRCValue) { return false; } hwCRC16 = *phwCRCValue; hwCRC16 = (hwCRC16 << 8) ^ c_hwCRC16_CCITT_Table[(hwCRC16 >> 8) ^ chData]; return (*phwCRCValue = hwCRC16); } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/crc/crc32.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #define CRC32_IEEE802_3_POLY (0x04C11DB7) #define CRC32_POLY (0x04C11DB7) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #if CRC32_IEEE802_3_OPTIMIZE == CRC_OPT_SPEED //! CRC32 IEEE802_3 polynomial table static const uint32_t c_wCRC32IEEE802_3Table[256] = { 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, 0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9, 0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75, 0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011, 0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD, 0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039, 0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5, 0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81, 0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D, 0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49, 0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95, 0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1, 0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D, 0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE, 0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072, 0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16, 0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA, 0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE, 0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02, 0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066, 0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA, 0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E, 0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692, 0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6, 0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A, 0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E, 0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2, 0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686, 0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A, 0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637, 0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB, 0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F, 0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53, 0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47, 0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B, 0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF, 0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623, 0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7, 0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B, 0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F, 0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3, 0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7, 0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B, 0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F, 0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3, 0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640, 0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C, 0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8, 0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24, 0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30, 0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC, 0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088, 0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654, 0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0, 0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C, 0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18, 0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4, 0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0, 0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C, 0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668, 0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4, }; #endif #if CRC32_IEEE802_3_OPTIMIZE == CRC_OPT_BALANCE //! CRC32 IEEE802_3 polynomial table(half of byte) static const uint32_t c_wCRC32IEEE802_3Table[16] = { 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, }; #endif #if CRC32_OPTIMIZE == CRC_OPT_SPEED //! CRC32 polynomial table static const uint32_t c_wCRC32Table[256] = { 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D, }; #endif #if CRC32_OPTIMIZE == CRC_OPT_BALANCE //! CRC32 polynomial table(half of byte) static const uint32_t c_wCRC32Table[16] = { 0x00000000, 0x1DB71064, 0x3B6E20C8, 0x26D930AC, 0x76DC4190, 0x6B6B51F4, 0x4DB26158, 0x5005713C, 0xEDB88320, 0xF00F9344, 0xD6D6A3E8, 0xCB61B38C, 0x9B64C2B0, 0x86D3D2D4, 0xA00AE278, 0xBDBDF21C, }; #endif /*============================ IMPLEMENTATION ================================*/ #if CRC32_IEEE802_3_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_ieee802_3_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint32_t wCRC32 = 0; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { wCRC32 = ((uint32_t)(*pchData++) << 24) ^ (*pwCRCValue & 0xFF000000); for (j = 0; j < 8; j++) { if (wCRC32 & 0x80000000) { wCRC32 <<= 1; wCRC32 ^= CRC32_IEEE802_3_POLY; } else { wCRC32 <<= 1; } } *pwCRCValue = (*pwCRCValue << 8) ^ wCRC32; } return *pwCRCValue; } /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ uint32_t crc32_ieee802_3_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t i; uint32_t wCRC32 = 0; if (NULL == pwCRCValue) { return false; } wCRC32 = ((uint32_t)chData << 24) ^ (*pwCRCValue & 0xFF000000); for (i = 0; i < 8; i++) { if (wCRC32 & 0x80000000) { wCRC32 <<= 1; wCRC32 ^= CRC32_IEEE802_3_POLY; } else { wCRC32 <<= 1; } } *pwCRCValue = (*pwCRCValue << 8) ^ wCRC32; return *pwCRCValue; } #endif #if CRC32_IEEE802_3_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_ieee802_3_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint32_t wCRC32 = 0; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } wCRC32 = *pwCRCValue; for (i = 0; i < wLength; i++) { wCRC32 = (wCRC32 << 4) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 28) ^ (*pchData >> 4)]; wCRC32 = (wCRC32 << 4) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 28) ^ (*pchData++ & 0x0F)]; } return (*pwCRCValue = wCRC32); } /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \return CRC32 result */ uint32_t crc32_ieee802_3_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t wCRC32 = 0; if (NULL == pwCRCValue) { return false; } wCRC32 = *pwCRCValue; wCRC32 = (wCRC32 << 4) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 28) ^ (chData >> 4)]; wCRC32 = (wCRC32 << 4) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 28) ^ (chData & 0x0F)]; return (*pwCRCValue = wCRC32); } #endif #if CRC32_IEEE802_3_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_ieee802_3_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint32_t wCRC32; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } wCRC32 = *pwCRCValue; for (i = 0; i < wLength; i++) { wCRC32 = (wCRC32 << 8) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 24) ^ *pchData++]; } return (*pwCRCValue = wCRC32); } /*! \brief CRC32 IEEE802.3 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: False *! RefOut: False *! XorOut: 0x00000000 *! \param pwCRCValue CRC Variable *! \param pchData target data *! \return CRC32 result */ uint32_t crc32_ieee802_3_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t wCRC32; if (NULL == pwCRCValue) { return false; } wCRC32 = *pwCRCValue; wCRC32 = (wCRC32 << 8) ^ c_wCRC32IEEE802_3Table[(wCRC32 >> 24) ^ chData]; return (*pwCRCValue = wCRC32); } #endif #if CRC32_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint32_t wCRC32; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } wCRC32 = *pwCRCValue; for (i = 0; i < wLength; i++) { wCRC32 = (wCRC32 >> 8) ^ c_wCRC32Table[(wCRC32 ^ *pchData++) & 0xFF]; } return (*pwCRCValue = ~wCRC32); } /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ uint32_t crc32_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t wCRC32; if (NULL == pwCRCValue) { return false; } wCRC32 = *pwCRCValue; wCRC32 = (wCRC32 >> 8) ^ c_wCRC32Table[(wCRC32 ^ chData) & 0xFF]; return (*pwCRCValue = wCRC32); } #endif #if CRC32_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint32_t wCRC32; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } wCRC32 = *pwCRCValue; for (i = 0; i < wLength; i++) { wCRC32 = (wCRC32 >> 4) ^ c_wCRC32Table[(wCRC32 & 0x0000000F) ^ (*pchData & 0x0F)]; wCRC32 = (wCRC32 >> 4) ^ c_wCRC32Table[(wCRC32 & 0x0000000F) ^ (*pchData++ >> 4)]; } return (*pwCRCValue = ~wCRC32); } /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ uint32_t crc32_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t wCRC32; if (NULL == pwCRCValue) { return false; } wCRC32 = *pwCRCValue; wCRC32 = (wCRC32 >> 4) ^ c_wCRC32Table[(wCRC32 & 0x0000000F) ^ (chData & 0x0F)]; wCRC32 = (wCRC32 >> 4) ^ c_wCRC32Table[(wCRC32 & 0x0000000F) ^ (chData >> 4)]; return (*pwCRCValue = wCRC32); } #endif #if CRC32_OPTIMIZE == CRC_OPT_SIZE /*! \brief data reversal *! \param wValue need to reversal data *! \param chLength data bit length *! \return already reversal data */ static uint32_t data_reversal(uint32_t wValue, uint8_t chLength) { uint8_t i; uint32_t wTempValue = 0; for (i = 1; i < (chLength + 1); i++) { if (wValue & 0x01) { wTempValue |= ((uint32_t)1 << (chLength - i)); } wValue >>= 1; } return wTempValue; } /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC32 result */ uint32_t crc32_stream_check(uint32_t *pwCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint32_t wCRC32 = 0; if ((NULL == pwCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { wCRC32 = ((*pwCRCValue) ^ (*pchData++)) & 0x000000FF; wCRC32 = data_reversal(wCRC32, 32); for (j = 0; j < 8; j++) { if (wCRC32 & 0x80000000) { wCRC32 <<= 1; wCRC32 ^= CRC32_POLY; } else { wCRC32 <<= 1; } } wCRC32 = data_reversal(wCRC32, 32); *pwCRCValue = (*pwCRCValue >> 8) ^ wCRC32; } return (*pwCRCValue = ~*pwCRCValue); } /*! \brief CRC32 *! Poly: 0x04C11DB7 *! Init: 0xFFFFFFFF *! RefIn: True *! RefOut: True *! XorOut: 0xFFFFFFFF *! \param pwCRCValue CRC Variable *! \param pchData target data byte *! \return CRC32 result */ uint32_t crc32_check(uint32_t *pwCRCValue, uint8_t chData) { uint32_t i; uint32_t wCRC32 = 0; if (NULL == pwCRCValue) { return false; } wCRC32 = ((*pwCRCValue) ^ chData) & 0x000000FF; wCRC32 = data_reversal(wCRC32, 32); for (i = 0; i < 8; i++) { if (wCRC32 & 0x80000000) { wCRC32 <<= 1; wCRC32 ^= CRC32_POLY; } else { wCRC32 <<= 1; } } wCRC32 = data_reversal(wCRC32, 32); *pwCRCValue = (*pwCRCValue >> 8) ^ wCRC32; return (*pwCRCValue); } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/crc/crc7.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #define CRC7_POLY (0x89) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #if CRC7_OPTIMIZE == CRC_OPT_SPEED static const uint8_t c_chCRC7Table[256] = { 0x00, 0x09, 0x12, 0x1B, 0x24, 0x2D, 0x36, 0x3F, 0x48, 0x41, 0x5A, 0x53, 0x6C, 0x65, 0x7E, 0x77, 0x19, 0x10, 0x0B, 0x02, 0x3D, 0x34, 0x2F, 0x26, 0x51, 0x58, 0x43, 0x4A, 0x75, 0x7C, 0x67, 0x6E, 0x32, 0x3B, 0x20, 0x29, 0x16, 0x1F, 0x04, 0x0D, 0x7A, 0x73, 0x68, 0x61, 0x5E, 0x57, 0x4C, 0x45, 0x2B, 0x22, 0x39, 0x30, 0x0F, 0x06, 0x1D, 0x14, 0x63, 0x6A, 0x71, 0x78, 0x47, 0x4E, 0x55, 0x5C, 0x64, 0x6D, 0x76, 0x7F, 0x40, 0x49, 0x52, 0x5B, 0x2C, 0x25, 0x3E, 0x37, 0x08, 0x01, 0x1A, 0x13, 0x7D, 0x74, 0x6F, 0x66, 0x59, 0x50, 0x4B, 0x42, 0x35, 0x3C, 0x27, 0x2E, 0x11, 0x18, 0x03, 0x0A, 0x56, 0x5F, 0x44, 0x4D, 0x72, 0x7B, 0x60, 0x69, 0x1E, 0x17, 0x0C, 0x05, 0x3A, 0x33, 0x28, 0x21, 0x4F, 0x46, 0x5D, 0x54, 0x6B, 0x62, 0x79, 0x70, 0x07, 0x0E, 0x15, 0x1C, 0x23, 0x2A, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5A, 0x65, 0x6C, 0x77, 0x7E, 0x09, 0x00, 0x1B, 0x12, 0x2D, 0x24, 0x3F, 0x36, 0x58, 0x51, 0x4A, 0x43, 0x7C, 0x75, 0x6E, 0x67, 0x10, 0x19, 0x02, 0x0B, 0x34, 0x3D, 0x26, 0x2F, 0x73, 0x7A, 0x61, 0x68, 0x57, 0x5E, 0x45, 0x4C, 0x3B, 0x32, 0x29, 0x20, 0x1F, 0x16, 0x0D, 0x04, 0x6A, 0x63, 0x78, 0x71, 0x4E, 0x47, 0x5C, 0x55, 0x22, 0x2B, 0x30, 0x39, 0x06, 0x0F, 0x14, 0x1D, 0x25, 0x2C, 0x37, 0x3E, 0x01, 0x08, 0x13, 0x1A, 0x6D, 0x64, 0x7F, 0x76, 0x49, 0x40, 0x5B, 0x52, 0x3C, 0x35, 0x2E, 0x27, 0x18, 0x11, 0x0A, 0x03, 0x74, 0x7D, 0x66, 0x6F, 0x50, 0x59, 0x42, 0x4B, 0x17, 0x1E, 0x05, 0x0C, 0x33, 0x3A, 0x21, 0x28, 0x5F, 0x56, 0x4D, 0x44, 0x7B, 0x72, 0x69, 0x60, 0x0E, 0x07, 0x1C, 0x15, 0x2A, 0x23, 0x38, 0x31, 0x46, 0x4F, 0x54, 0x5D, 0x62, 0x6B, 0x70, 0x79, }; #endif #if CRC7_OPTIMIZE == CRC_OPT_BALANCE #error CRC7 NOT HAVE CRC_OPT_BALANCE, ONLY HAVE CRC_OPT_SPEED AND CRC_OPT_SIZE #endif /*============================ IMPLEMENTATION ================================*/ #if CRC7_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC7 result */ uint8_t crc7_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint8_t chCRC7 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { chCRC7 = (*pchData++) ^ (*pchCRCValue << 1); for (j = 0; j < 7; j++) { if (chCRC7 & 0x80) { chCRC7 ^= CRC7_POLY; } chCRC7 <<= 1; } if (chCRC7 & 0x80) { chCRC7 ^= CRC7_POLY; } *pchCRCValue = chCRC7; } return *pchCRCValue; } /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data byte *! \return CRC7 result */ uint8_t crc7_check(uint8_t *pchCRCValue, uint8_t chData) { uint32_t i; uint8_t chCRC7 = 0; if (NULL == pchCRCValue) { return false; } chCRC7 = chData ^ (*pchCRCValue << 1); for (i = 0; i < 7; i++) { if (chCRC7 & 0x80) { chCRC7 ^= CRC7_POLY; } chCRC7 <<= 1; } if (chCRC7 & 0x80) { chCRC7 ^= CRC7_POLY; } return ((*pchCRCValue) = chCRC7); } #endif #if CRC7_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC7 result */ uint8_t crc7_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint8_t chCRC7; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } chCRC7 = *pchCRCValue; for (i = 0; i < wLength; i++) { chCRC7 = c_chCRC7Table[(chCRC7 << 1) ^ *pchData++]; } return (*pchCRCValue = chCRC7); } /*! \brief CRC7 MMC SD *! Poly: 0x09 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC7 result */ uint8_t crc7_check(uint8_t *pchCRCValue, uint8_t chData) { uint8_t chCRC7; if (NULL == pchCRCValue) { return false; } chCRC7 = *pchCRCValue << 1; chCRC7 = c_chCRC7Table[chCRC7 ^ chData]; return (*pchCRCValue = chCRC7); } #endif ================================================ FILE: sources/gmsi/service/communication/crc/crc8.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #define CRC8_POLY (0x07) #define CRC8_ROHC_POLY (0x07) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #if CRC8_OPTIMIZE == CRC_OPT_SPEED static const uint8_t c_chCRC8Table[256] = { 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D, 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD, 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD, 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2, 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA, 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2, 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A, 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A, 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A, 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4, 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4, 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44, 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34, 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63, 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13, 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB, 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83, 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB, 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3, }; #endif #if CRC8_OPTIMIZE == CRC_OPT_BALANCE static const uint8_t c_chCRC8Table[16] = { 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, }; #endif #if CRC8_ROHC == CRC_OPT_SPEED //! this name is specific static const uint8_t c_chCRC8_ROHC_Table[256] = { 0x00, 0x91, 0xE3, 0x72, 0x07, 0x96, 0xE4, 0x75, 0x0E, 0x9F, 0xED, 0x7C, 0x09, 0x98, 0xEA, 0x7B, 0x1C, 0x8D, 0xFF, 0x6E, 0x1B, 0x8A, 0xF8, 0x69, 0x12, 0x83, 0xF1, 0x60, 0x15, 0x84, 0xF6, 0x67, 0x38, 0xA9, 0xDB, 0x4A, 0x3F, 0xAE, 0xDC, 0x4D, 0x36, 0xA7, 0xD5, 0x44, 0x31, 0xA0, 0xD2, 0x43, 0x24, 0xB5, 0xC7, 0x56, 0x23, 0xB2, 0xC0, 0x51, 0x2A, 0xBB, 0xC9, 0x58, 0x2D, 0xBC, 0xCE, 0x5F, 0x70, 0xE1, 0x93, 0x02, 0x77, 0xE6, 0x94, 0x05, 0x7E, 0xEF, 0x9D, 0x0C, 0x79, 0xE8, 0x9A, 0x0B, 0x6C, 0xFD, 0x8F, 0x1E, 0x6B, 0xFA, 0x88, 0x19, 0x62, 0xF3, 0x81, 0x10, 0x65, 0xF4, 0x86, 0x17, 0x48, 0xD9, 0xAB, 0x3A, 0x4F, 0xDE, 0xAC, 0x3D, 0x46, 0xD7, 0xA5, 0x34, 0x41, 0xD0, 0xA2, 0x33, 0x54, 0xC5, 0xB7, 0x26, 0x53, 0xC2, 0xB0, 0x21, 0x5A, 0xCB, 0xB9, 0x28, 0x5D, 0xCC, 0xBE, 0x2F, 0xE0, 0x71, 0x03, 0x92, 0xE7, 0x76, 0x04, 0x95, 0xEE, 0x7F, 0x0D, 0x9C, 0xE9, 0x78, 0x0A, 0x9B, 0xFC, 0x6D, 0x1F, 0x8E, 0xFB, 0x6A, 0x18, 0x89, 0xF2, 0x63, 0x11, 0x80, 0xF5, 0x64, 0x16, 0x87, 0xD8, 0x49, 0x3B, 0xAA, 0xDF, 0x4E, 0x3C, 0xAD, 0xD6, 0x47, 0x35, 0xA4, 0xD1, 0x40, 0x32, 0xA3, 0xC4, 0x55, 0x27, 0xB6, 0xC3, 0x52, 0x20, 0xB1, 0xCA, 0x5B, 0x29, 0xB8, 0xCD, 0x5C, 0x2E, 0xBF, 0x90, 0x01, 0x73, 0xE2, 0x97, 0x06, 0x74, 0xE5, 0x9E, 0x0F, 0x7D, 0xEC, 0x99, 0x08, 0x7A, 0xEB, 0x8C, 0x1D, 0x6F, 0xFE, 0x8B, 0x1A, 0x68, 0xF9, 0x82, 0x13, 0x61, 0xF0, 0x85, 0x14, 0x66, 0xF7, 0xA8, 0x39, 0x4B, 0xDA, 0xAF, 0x3E, 0x4C, 0xDD, 0xA6, 0x37, 0x45, 0xD4, 0xA1, 0x30, 0x42, 0xD3, 0xB4, 0x25, 0x57, 0xC6, 0xB3, 0x22, 0x50, 0xC1, 0xBA, 0x2B, 0x59, 0xC8, 0xBD, 0x2C, 0x5E, 0xCF, }; #endif #if CRC8_ROHC == CRC_OPT_BALANCE static const uint8_t c_chCRC8_ROHC_Table[16] = { 0x00, 0x1C, 0x38, 0x24, 0x70, 0x6C, 0x48, 0x54, 0xE0, 0xFC, 0xD8, 0xC4, 0x90, 0x8C, 0xA8, 0xB4, }; #endif /*============================ IMPLEMENTATION ================================*/ #if CRC8_ROHC == CRC_OPT_SIZE /*! \brief data reversal *! \param wValue need to reversal data *! \param chLength data bit length *! \return already reversal data */ static uint32_t data_reversal(uint32_t wValue, uint8_t chLength) { uint8_t i; uint32_t wTempValue = 0; for (i = 1; i < (chLength + 1); i++) { if (wValue & 0x01) { wTempValue |= ((uint32_t)1 << (chLength - i)); } wValue >>= 1; } return wTempValue; } #endif #if CRC8_ROHC == CRC_OPT_SIZE /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_rohc_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint8_t chCRC8 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { chCRC8 = (*pchCRCValue) ^ (*pchData++); chCRC8 = (uint8_t)data_reversal(chCRC8, 8); for (j = 0; j < 8; j++) { if (chCRC8 & 0x80) { chCRC8 <<= 1; chCRC8 ^= CRC8_ROHC_POLY; } else { chCRC8 <<= 1; } } chCRC8 = (uint8_t)data_reversal(chCRC8, 8); *pchCRCValue = chCRC8; } return *pchCRCValue; } /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC8 result */ uint8_t crc8_rohc_check(uint8_t *pchCRCValue, uint8_t chData) { uint32_t i; uint8_t chCRC8 = 0; if (NULL == pchCRCValue) { return false; } chCRC8 = (*pchCRCValue) ^ chData; chCRC8 = (uint8_t)data_reversal(chCRC8, 8); for (i = 0; i < 8; i++) { if (chCRC8 & 0x80) { chCRC8 <<= 1; chCRC8 ^= CRC8_ROHC_POLY; } else { chCRC8 <<= 1; } } chCRC8 = (uint8_t)data_reversal(chCRC8, 8); return (*pchCRCValue = chCRC8); } #endif #if CRC8_ROHC == CRC_OPT_BALANCE /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_rohc_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint8_t chCRC8 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } chCRC8 = *pchCRCValue; for (i = 0; i < wLength; i++) { chCRC8 = (chCRC8 >> 4) ^ c_chCRC8_ROHC_Table[(chCRC8 & 0x0F) ^ (*pchData & 0x0F)]; chCRC8 = (chCRC8 >> 4) ^ c_chCRC8_ROHC_Table[(chCRC8 & 0x0F) ^ (*pchData++ >> 4)]; } return (*pchCRCValue = chCRC8); } /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC8 result */ uint8_t crc8_rohc_check(uint8_t *pchCRCValue, uint8_t chData) { uint8_t chCRC8 = 0; if (NULL == pchCRCValue) { return false; } chCRC8 = *pchCRCValue; chCRC8 = (chCRC8 >> 4) ^ c_chCRC8_ROHC_Table[(chCRC8 & 0x0F) ^ (chData & 0x0F)]; chCRC8 = (chCRC8 >> 4) ^ c_chCRC8_ROHC_Table[(chCRC8 & 0x0F) ^ (chData >> 4)]; return (*pchCRCValue = chCRC8); } #endif #if CRC8_ROHC == CRC_OPT_SPEED /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_rohc_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint8_t chCRC8 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } chCRC8 = *pchCRCValue; for (i = 0; i < wLength; i++) { chCRC8 = c_chCRC8_ROHC_Table[chCRC8 ^ *pchData++]; } return (*pchCRCValue = chCRC8); } /*! \brief CRC8 ROHC *! Poly: 0x07 *! Init: 0xFF *! RefIn: True *! RefOut: True *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC8 result */ uint8_t crc8_rohc_check(uint8_t *pchCRCValue, uint8_t chData) { uint16_t chCRC8; if (NULL == pchCRCValue) { return false; } chCRC8 = *pchCRCValue; chCRC8 = c_chCRC8_ROHC_Table[chCRC8 ^ chData]; return (*pchCRCValue = chCRC8); } #endif #if CRC8_OPTIMIZE == CRC_OPT_SIZE /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i,j; uint8_t chCRC8 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } for (i = 0; i < wLength; i++) { chCRC8 = (*pchData++) ^ (*pchCRCValue); for (j = 0; j < 8; j++) { if (chCRC8 & 0x80) { chCRC8 <<= 1; chCRC8 ^= CRC8_POLY; } else { chCRC8 <<= 1; } } *pchCRCValue = chCRC8; } return *pchCRCValue; } /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data byte *! \return CRC8 result */ uint8_t crc8_check(uint8_t *pchCRCValue, uint8_t chData) { uint32_t i; uint8_t chCRC8 = 0; if (NULL == pchCRCValue) { return false; } chCRC8 = chData ^ (*pchCRCValue); for (i = 0; i < 8; i++) { if (chCRC8 & 0x80) { chCRC8 <<= 1; chCRC8 ^= CRC8_POLY; } else { chCRC8 <<= 1; } } return ((*pchCRCValue) = chCRC8); } #endif #if CRC8_OPTIMIZE == CRC_OPT_BALANCE /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint8_t chCRC8 = 0; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } chCRC8 = *pchCRCValue; for (i = 0; i < wLength; i++) { chCRC8 = (chCRC8 << 4) ^ c_chCRC8Table[(chCRC8 >> 4) ^ (*pchData >> 4)]; chCRC8 = (chCRC8 << 4) ^ c_chCRC8Table[(chCRC8 >> 4) ^ (*pchData++ & 0x0F)]; } return (*pchCRCValue = chCRC8); } /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \return CRC8 result */ uint8_t crc8_check(uint8_t *pchCRCValue, uint8_t chData) { uint8_t chCRC8 = 0; if (NULL == pchCRCValue) { return false; } chCRC8 = *pchCRCValue; chCRC8 = (chCRC8 << 4) ^ c_chCRC8Table[(chCRC8 >> 4) ^ (chData >> 4)]; chCRC8 = (chCRC8 << 4) ^ c_chCRC8Table[(chCRC8 >> 4) ^ (chData & 0x0F)]; return (*pchCRCValue = chCRC8); } #endif #if CRC8_OPTIMIZE == CRC_OPT_SPEED /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data stream address *! \param wLength the number of target data stream *! \return CRC8 result */ uint8_t crc8_stream_check(uint8_t *pchCRCValue, uint8_t *pchData, uint32_t wLength) { uint32_t i; uint16_t chCRC8; if ((NULL == pchCRCValue) || (NULL == pchData)) { return false; } chCRC8 = *pchCRCValue; for (i = 0; i < wLength; i++) { chCRC8 = c_chCRC8Table[chCRC8 ^ *pchData++]; } return (*pchCRCValue = chCRC8); } /*! \brief CRC8 *! Poly: 0x07 *! Init: 0x00 *! RefIn: False *! RefOut: False *! XorOut: 0x00 *! \param pchCRCValue CRC Variable *! \param pchData target data *! \return CRC8 result */ uint8_t crc8_check(uint8_t *pchCRCValue, uint8_t chData) { uint16_t chCRC8; if (NULL == pchCRCValue) { return false; } chCRC8 = *pchCRCValue; chCRC8 = c_chCRC8Table[chCRC8 ^ chData]; return (*pchCRCValue = chCRC8); } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/frame/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __USE_COMMUNICATION_FRAME_APP_CFG__ #define __USE_COMMUNICATION_FRAME_APP_CFG__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/frame/es_simple_frame/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __USE_ES_SIMPLE_FRAME_APP_CFG__ #define __USE_ES_SIMPLE_FRAME_APP_CFG__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/frame/es_simple_frame/es_simple_frame.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\iframe.h" #include "..\..\crc\crc.h" #include #if USE_SERVICE_ES_SIMPLE_FRAME == ENABLED #include "..\..\..\memory\block\block.h" #include "./es_simple_frame.h" /*============================ MACROS ========================================*/ //! \brief es-simple-frame-head #ifndef ES_SIMPLE_FRAME_HEAD # define ES_SIMPLE_FRAME_HEAD 0xAA #endif #ifndef ES_SIMPLE_FRAME_ERROR # define ES_SIMPLE_FRAME_ERROR 0xF0 #endif #ifndef this # define this (*ptThis) #endif #ifndef base # define base (*ptBase) #endif #ifndef target # define target (*ptTarget) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES Part One ================================*/ def_simple_fsm(es_simple_frame_decoder, def_params( i_pipe_t *ptPipe; //!< pipe union { frame_parser_t *fnParser; //!< parser frame_block_parser_t *fnBlockParser; }; bool bUnsupportFrame; block_t *ptBlock; void *pTag; implement(__es_simple_frame_fsm_internal) )) def_simple_fsm(es_simple_frame_encoder, def_params( i_pipe_t *ptPipe; //!< pipe implement(__es_simple_frame_fsm_internal) )) def_simple_fsm(es_simple_frame_decoder_wrapper, def_params( es_simple_frame_t *ptFrame; )) def_simple_fsm(es_simple_frame_encoder_wrapper, def_params( es_simple_frame_t *ptFrame; )) //! \name class: e-snail simple frame //! @{ def_class(es_simple_frame_t,, locker_t tMutex; inherit(fsm(es_simple_frame_decoder)) inherit(fsm(es_simple_frame_decoder_wrapper)) inherit(fsm(es_simple_frame_encoder)) inherit(fsm(es_simple_frame_encoder_wrapper)) bool bDynamicBufferMode; ) end_def_class(es_simple_frame_t) //! @} /*============================ PROTOTYPES ====================================*/ private extern_fsm_initialiser(es_simple_frame_decoder, args( i_pipe_t *ptPipe, void *fnParser, mem_block_t tMemory, block_t *ptBlock, void *pTag )) private extern_fsm_initialiser(es_simple_frame_encoder, args( i_pipe_t *ptPipe )) private extern_fsm_initialiser(es_simple_frame_decoder_wrapper, args( es_simple_frame_t *ptFrame )) private extern_fsm_initialiser(es_simple_frame_encoder_wrapper, args( es_simple_frame_t *ptFrame )) private extern_fsm_implementation(es_simple_frame_encoder, args( uint8_t *pchData, uint_fast16_t hwSize )); private extern_fsm_implementation(es_simple_frame_decoder); private extern_fsm_implementation(es_simple_frame_encoder_wrapper, args( uint8_t *pchBuffer, uint_fast16_t hwSize )); private extern_fsm_implementation(es_simple_frame_decoder_wrapper); private bool es_simple_frame_init( es_simple_frame_t *ptFrame, es_simple_frame_cfg_t *ptCFG); //private fsm_rt_t es_simple_frame_task(es_simple_frame_t *ptFrame); private fsm_rt_t encoder(es_simple_frame_t *ptFrame, uint8_t *pchBuffer, uint_fast16_t hwSize); private fsm_rt_t task(es_simple_frame_t *ptFrame); private fsm_rt_t decoder(es_simple_frame_t *ptFrame); private uint_fast16_t get_buffer_size ( es_simple_frame_t *ptFrame); /*============================ TYPES Part Two ================================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_es_simple_frame_t ES_SIMPLE_FRAME = { .Init = &es_simple_frame_init, .Task = &task, .Decoder = &decoder, .Encoder = &encoder, .Buffer = { .GetSize = &get_buffer_size, }, }; /*============================ IMPLEMENTATION ================================*/ private uint_fast16_t get_buffer_size ( es_simple_frame_t *ptFrame) { uint_fast32_t wSize = 0; class_internal(ptFrame, ptThis, es_simple_frame_t); do { if (NULL == ptThis) { break; } class_internal( ref_obj_as(this, fsm(es_simple_frame_decoder)), ptTarget, fsm(es_simple_frame_decoder)); if (NULL == target.ptBlock ) { wSize = target.nSize; } else { wSize = BLOCK.Size.Capability(target.ptBlock); } } while(false); return wSize; } /*! \brief initlialize es_simple_frame *! \param ptFrame es_simple_frame object *! \param ptCFG configuration object *! \retval true initliazation is successful *! \retval false failed in initialization */ private bool es_simple_frame_init( es_simple_frame_t *ptFrame, es_simple_frame_cfg_t *ptCFG) { class_internal(ptFrame, ptThis, es_simple_frame_t); if (NULL == ptFrame || NULL == ptCFG) { return false; } else if ( (NULL == ptFrame) || (NULL == ptCFG->ptPipe) //|| (NULL == ptCFG->pchBuffer) //|| (0 == ptCFG->hwSize ) || (NULL == ptCFG->fnParser)) { return false; } else if ( (NULL == ptCFG->ptPipe->ReadByte) || (NULL == ptCFG->ptPipe->WriteByte) || (NULL == ptCFG->ptPipe->Stream.Read) || (NULL == ptCFG->ptPipe->Stream.Write)) { return false; } memset((void *)ptFrame, 0, sizeof(es_simple_frame_t)); init_lock(&this.tMutex); do { if (!ptCFG->bStaticBufferMode) { this.bDynamicBufferMode = true; //! dynamic buffer mode if (NULL == ptCFG->ptBlock) { break; } else if (!BLOCK.Size.Get(ptCFG->ptBlock)) { //! empty memory block break; } if (NULL == init_fsm(es_simple_frame_decoder, ref_obj_as( this, fsm(es_simple_frame_decoder)), args(ptCFG->ptPipe, ptCFG->fnParser), (mem_block_t){NULL ,0}, ptCFG->ptBlock, ptCFG->pTag)) { break; } } else if (0 == ptCFG->nSize) { //! static buffer mode, empty buffer detected break; } else { this.bDynamicBufferMode = false; if (NULL == init_fsm(es_simple_frame_decoder, ref_obj_as( this, fsm(es_simple_frame_decoder)), args(ptCFG->ptPipe, ptCFG->fnParser), obj_convert_as((*ptCFG), mem_block_t), NULL, ptCFG->pTag)) { break; } } if (NULL == init_fsm(es_simple_frame_encoder, ref_obj_as( this, fsm(es_simple_frame_encoder)), args(ptCFG->ptPipe))) { break; } if (NULL == init_fsm(es_simple_frame_encoder_wrapper, ref_obj_as( this, fsm(es_simple_frame_encoder_wrapper)), args(ptFrame))) { break; } if (NULL == init_fsm(es_simple_frame_decoder_wrapper, ref_obj_as( this, fsm(es_simple_frame_decoder_wrapper)), args(ptFrame))) { break; } return true; } while(false); return false; } private fsm_initialiser(es_simple_frame_decoder, args( i_pipe_t *ptPipe, void *fnParser, mem_block_t tMemory, block_t *ptBlock, void *pTag )) init_body( if (NULL == ptPipe || NULL == fnParser) { abort_init(); } else if ((NULL == ptPipe->ReadByte) || (NULL == ptPipe->WriteByte)) { abort_init(); } else if ( (NULL == ptBlock) && ( (NULL == tMemory.pchBuffer) || (0 == tMemory.nSize)) ) { abort_init(); } memset( ref_obj_as(this, __es_simple_frame_fsm_internal), 0, sizeof(__es_simple_frame_fsm_internal)); if (NULL == ptBlock) { obj_convert_as(this, mem_block_t) = tMemory; this.fnParser = (frame_parser_t *)fnParser; } else { this.ptBlock = ptBlock; this.fnBlockParser = (frame_block_parser_t *)fnParser; } this.ptPipe = ptPipe; this.pTag = pTag; ) private fsm_rt_t decoder(es_simple_frame_t *ptFrame) { class_internal( ptFrame, ptThis, es_simple_frame_t); if (NULL == ptFrame) { return (fsm_rt_t)(GSF_ERR_INVALID_PTR); } return call_fsm(es_simple_frame_decoder, ref_obj_as(this, fsm(es_simple_frame_decoder))); } private fsm_implementation(es_simple_frame_decoder) { def_states ( WAIT_FOR_HEAD, WAIT_FOR_LENGTH_L, WAIT_FOR_LENGTH_H, WAIT_FOR_DATA, WAIT_FOR_CHECK_SUM_L, WAIT_FOR_CHECK_SUM_H ) uint8_t chData; body_begin(); on_start( if (NULL != this.ptBlock) { this.pchBuffer = BLOCK.Buffer.Get(this.ptBlock); BLOCK.Size.Reset(this.ptBlock); this.nSize = BLOCK.Size.Get(this.ptBlock); } if (NULL == this.ptPipe) { fsm_report(GSF_ERR_IO) } else if (NULL == this.ptPipe->ReadByte) { fsm_report(GSF_ERR_IO) } else if (NULL == this.pchBuffer) { fsm_report(GSF_ERR_INVALID_PTR); } else if (0 == this.nSize) { fsm_report(GSF_ERR_INVALID_PARAMETER); } this.hwCheckSUM = CRC_INIT; this.bUnsupportFrame = false; ) privilege_state(WAIT_FOR_HEAD, if (!this.ptPipe->ReadByte(&chData)) { fsm_wait_for_obj(); } if (ES_SIMPLE_FRAME_HEAD == chData) { update_state_to(WAIT_FOR_LENGTH_L); } ) state(WAIT_FOR_LENGTH_L) { if (!this.ptPipe->ReadByte(&chData)) { fsm_wait_for_obj(); } GMSI_CRC(this.hwCheckSUM, chData); ((uint8_t *)&this.hwLength)[0] = chData; update_state_to(WAIT_FOR_LENGTH_H); } state(WAIT_FOR_LENGTH_H) { if (!this.ptPipe->ReadByte(&chData)) { fsm_wait_for_obj(); } GMSI_CRC(this.hwCheckSUM, chData); ((uint8_t *)&this.hwLength)[1] = chData; if (0 == this.hwLength){ /* no data */ transfer_to(WAIT_FOR_CHECK_SUM_L); } else if (this.hwLength > this.nSize) { //! data is too big this.bUnsupportFrame = true; } this.hwCounter = 0; update_state_to(WAIT_FOR_DATA); } state(WAIT_FOR_DATA) { int32_t nRead = this.ptPipe->Stream.Read(this.pchBuffer + this.hwCounter, this.hwLength - this.hwCounter); if ( nRead > 0) { crc16_stream_check(&this.hwCheckSUM, this.pchBuffer + this.hwCounter, nRead); this.hwCounter += nRead; if (this.hwCounter >= this.hwLength) { //! get all data update_state_to(WAIT_FOR_CHECK_SUM_L); } } fsm_wait_for_obj(); } state(WAIT_FOR_CHECK_SUM_L) { if (!this.ptPipe->ReadByte(&chData)) { fsm_wait_for_obj(); } if (!(((uint8_t *)&this.hwCheckSUM)[0] == chData)) { reset_fsm(); fsm_on_going(); } update_state_to(WAIT_FOR_CHECK_SUM_H); } state(WAIT_FOR_CHECK_SUM_H) { if (!this.ptPipe->ReadByte(&chData)) { fsm_wait_for_obj(); } if (!(((uint8_t *)&this.hwCheckSUM)[1] == chData)) { reset_fsm(); fsm_on_going(); } if (this.bUnsupportFrame) { //! report unsupported frame this.hwLength = 1; this.pchBuffer[0] = ES_SIMPLE_FRAME_ERROR; } else if (NULL == this.ptBlock){ //! static buffer mode //! call parser this.hwLength = this.fnParser( obj_convert_as(this, mem_block_t), this.hwLength); } else { block_t *ptBlock = this.ptBlock; BLOCK.Size.Set(ptBlock, this.hwLength); //! dynamic buffer mode ptBlock = this.fnBlockParser(ptBlock, this.pTag); do { if (NULL == ptBlock) { this.hwLength = 0; break; } //! get reply this.ptBlock = ptBlock; this.hwLength = BLOCK.Size.Get(ptBlock); this.pchBuffer = BLOCK.Buffer.Get(ptBlock); } while(false); } fsm_cpl(); } body_end(); } private fsm_initialiser(es_simple_frame_decoder_wrapper, args( es_simple_frame_t *ptFrame )) init_body( if (NULL == ptFrame) { abort_init(); } this.ptFrame = ptFrame; ) private fsm_rt_t task(es_simple_frame_t *ptFrame) { class_internal( ptFrame, ptThis, es_simple_frame_t); if (NULL == ptFrame) { return (fsm_rt_t)(GSF_ERR_INVALID_PTR); } return call_fsm(es_simple_frame_decoder_wrapper, &base_obj(fsm(es_simple_frame_decoder_wrapper))); } private fsm_implementation(es_simple_frame_decoder_wrapper) def_states(DECODING, TRY_TO_LOCK, REPLY) fsm_rt_t tFSMReply; class_internal( this.ptFrame, ptBase, es_simple_frame_t); class_internal( ref_obj_as(base, fsm(es_simple_frame_decoder)), ptDecoder, fsm(es_simple_frame_decoder)); body( on_start( if (NULL == this.ptFrame) { fsm_report(fsm_rt_err) } ) state(DECODING, tFSMReply = call_fsm(es_simple_frame_decoder, ref_obj_as(base, fsm(es_simple_frame_decoder))); if (is_fsm_err(tFSMReply)) { fsm_report(tFSMReply); } else if (fsm_rt_cpl == tFSMReply) { if ( (ptDecoder->hwLength > 0) && (ptDecoder->hwLength <= ptDecoder->nSize)) { /* get something to reply */ transfer_to(TRY_TO_LOCK) } fsm_cpl(); } fsm_on_going(); ) state(TRY_TO_LOCK, if (!enter_lock(&base.tMutex)) { fsm_on_going(); } update_state_to(REPLY); ) state(REPLY, tFSMReply = call_fsm( es_simple_frame_encoder, ref_obj_as(base, fsm(es_simple_frame_encoder)), args( ptDecoder->pchBuffer, ptDecoder->hwLength )); if (is_fsm_err(tFSMReply)) { leave_lock(&base.tMutex); fsm_report(tFSMReply); } else if (fsm_rt_cpl == tFSMReply) { leave_lock(&base.tMutex); fsm_cpl(); } fsm_on_going(); ) ) private fsm_initialiser(es_simple_frame_encoder, args( i_pipe_t *ptPipe )) init_body( if (NULL == ptPipe) { abort_init(); } else if ((NULL == ptPipe->ReadByte) || (NULL == ptPipe->WriteByte)) { abort_init(); } memset(ref_obj_as(this, __es_simple_frame_fsm_internal), 0, sizeof(__es_simple_frame_fsm_internal)); this.ptPipe = ptPipe; ) private fsm_implementation(es_simple_frame_encoder, args( uint8_t *pchData, uint_fast16_t hwSize )) { def_states(SEND_HEAD, SEND_LENGTH_L, SEND_LENGTH_H, SEND_DATA, SEND_CRC_L, SEND_CRC_H) uint8_t chData; body_begin() on_start( if (NULL == pchData || 0 == hwSize) { fsm_report(GSF_ERR_INVALID_PARAMETER); } else if (NULL == this.ptPipe) { fsm_report(GSF_ERR_IO) } else if (NULL == this.ptPipe->WriteByte) { fsm_report(GSF_ERR_IO) } this.pchBuffer = pchData; this.hwLength = hwSize; this.hwCounter = 0; this.hwCheckSUM = CRC_INIT; update_state_to(SEND_HEAD); ) state(SEND_HEAD) { if (!this.ptPipe->WriteByte(ES_SIMPLE_FRAME_HEAD)) { fsm_on_going(); } update_state_to(SEND_LENGTH_L); } state(SEND_LENGTH_L) { chData = ((uint8_t *)&this.hwLength)[0]; if (!this.ptPipe->WriteByte(chData)) { fsm_on_going(); } GMSI_CRC(this.hwCheckSUM, chData); update_state_to(SEND_LENGTH_H); } state(SEND_LENGTH_H) { chData = ((uint8_t *)&this.hwLength)[1]; if (!this.ptPipe->WriteByte(chData)) { fsm_on_going(); } GMSI_CRC(this.hwCheckSUM, chData); update_state_to(SEND_DATA); } state(SEND_DATA) { int32_t nWrite = this.ptPipe->Stream.Write( this.pchBuffer + this.hwCounter, this.hwLength - this.hwCounter); if ( nWrite > 0) { crc16_stream_check(&this.hwCheckSUM, this.pchBuffer + this.hwCounter, nWrite); this.hwCounter += nWrite; if (this.hwCounter >= this.hwLength) { //! get all data update_state_to(SEND_CRC_L); } } fsm_wait_for_obj(); } state(SEND_CRC_L) { if (!this.ptPipe->WriteByte(((uint8_t *)&this.hwCheckSUM)[0])) { fsm_on_going(); } update_state_to(SEND_CRC_H); } state(SEND_CRC_H) { if (!this.ptPipe->WriteByte(((uint8_t *)&this.hwCheckSUM)[1])) { fsm_on_going(); } fsm_cpl(); } body_end(); } private fsm_initialiser(es_simple_frame_encoder_wrapper, args( es_simple_frame_t *ptFrame )) init_body( if (NULL == ptFrame) { abort_init(); } this.ptFrame = ptFrame; ) private fsm_rt_t encoder(es_simple_frame_t *ptFrame, uint8_t *pchBuffer, uint_fast16_t hwSize) { class_internal( ptFrame, ptThis, es_simple_frame_t); if (NULL == ptFrame) { return (fsm_rt_t)(GSF_ERR_INVALID_PTR); } return call_fsm(es_simple_frame_encoder_wrapper, &base_obj(fsm(es_simple_frame_encoder_wrapper)), args(pchBuffer, hwSize)); } private fsm_implementation(es_simple_frame_encoder_wrapper, args( uint8_t *pchBuffer, uint_fast16_t hwSize )) def_states(TRY_TO_LOCK, ENCODING) fsm_rt_t tFSMReply; class_internal( this.ptFrame, ptBase, es_simple_frame_t); body( on_start( if ( (NULL == this.ptFrame) || (NULL == pchBuffer) || (0 == hwSize)) { fsm_report(GSF_ERR_INVALID_PARAMETER) } ) state(TRY_TO_LOCK, if (!enter_lock(&base.tMutex)) { fsm_on_going(); } update_state_to(ENCODING); ) state(ENCODING, tFSMReply = call_fsm( es_simple_frame_encoder, ref_obj_as(base, fsm(es_simple_frame_encoder)), args( pchBuffer, hwSize )); if (is_fsm_err(tFSMReply)) { leave_lock(&base.tMutex); fsm_report(tFSMReply); } else if (fsm_rt_cpl == tFSMReply) { leave_lock(&base.tMutex); fsm_cpl(); } fsm_on_going(); ) ) #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/frame/es_simple_frame/es_simple_frame.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_ES_SIMPLE_FRAME_H__ #define __USE_ES_SIMPLE_FRAME_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\iframe.h" #if USE_SERVICE_ES_SIMPLE_FRAME == ENABLED #include "..\..\..\memory\block\block.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ //! \brief macro for es-simple frame initialization #define ES_SIMPLE_FRAME_CFG(__FRAME__, ...) \ do { \ es_simple_frame_cfg_t tCFG = {__VA_ARGS__}; \ ES_SIMPLE_FRAME.Init((__FRAME__),&tCFG); \ } while(false) /*============================ TYPES =========================================*/ def_structure(__es_simple_frame_fsm_internal) implement(mem_block_t) uint16_t hwLength; uint16_t hwCounter; uint16_t hwCheckSUM; end_def_structure(__es_simple_frame_fsm_internal) declare_simple_fsm(es_simple_frame_decoder) extern_simple_fsm(es_simple_frame_decoder, def_params( i_pipe_t *ptPipe; //!< pipe union { frame_parser_t *fnParser; //!< parser frame_block_parser_t *fnBlockParser; }; bool bUnsupportFrame; block_t *ptBlock; void *pTag; implement(__es_simple_frame_fsm_internal) )) declare_simple_fsm(es_simple_frame_encoder) extern_simple_fsm(es_simple_frame_encoder, def_params( i_pipe_t *ptPipe; //!< pipe implement(__es_simple_frame_fsm_internal) )) declare_class(es_simple_frame_t) declare_simple_fsm(es_simple_frame_decoder_wrapper) extern_simple_fsm(es_simple_frame_decoder_wrapper, def_params( es_simple_frame_t *ptFrame; )) declare_simple_fsm(es_simple_frame_encoder_wrapper) extern_simple_fsm(es_simple_frame_encoder_wrapper, def_params( es_simple_frame_t *ptFrame; )) //! \name class: e-snail simple frame //! @{ extern_class(es_simple_frame_t,, locker_t tMutex; inherit(fsm(es_simple_frame_decoder)) inherit(fsm(es_simple_frame_decoder_wrapper)) inherit(fsm(es_simple_frame_encoder)) inherit(fsm(es_simple_frame_encoder_wrapper)) bool bDynamicBufferMode; ) end_extern_class(es_simple_frame_t) //! @} //! \name es-simple frame configuration structure //! @{ typedef struct { i_pipe_t *ptPipe; void *fnParser; union { implement(mem_block_t) struct { bool bStaticBufferMode; block_t * ptBlock; }; }; void *pTag; }es_simple_frame_cfg_t; //! @} /*============================ PROTOTYPES ====================================*/ /*============================ TYPES Part Two ================================*/ //! \name frame interface //! @{ def_interface(i_es_simple_frame_t) bool (*Init) ( es_simple_frame_t *ptFrame, es_simple_frame_cfg_t *ptCFG); fsm_rt_t (*Task) ( es_simple_frame_t *ptFrame); fsm_rt_t (*Decoder) ( es_simple_frame_t *ptFrame); fsm_rt_t (*Encoder) ( es_simple_frame_t *ptFrame, uint8_t *pchData, uint_fast16_t hwSize); struct { uint_fast16_t (*GetSize) ( es_simple_frame_t *ptFrame); }Buffer; end_def_interface(i_es_simple_frame_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ extern const i_es_simple_frame_t ES_SIMPLE_FRAME; /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif #endif ================================================ FILE: sources/gmsi/service/communication/frame/frame.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_COMMUNICATION_FRAME_H__ #define __USE_COMMUNICATION_FRAME_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\es_simple_frame\es_simple_frame.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ INCLUDES ======================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/frame/iframe.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_COMMUNICATION_FRAME_INTERFACE_H__ #define __USE_COMMUNICATION_FRAME_INTERFACE_H__ /*============================ INCLUDES ======================================*/ #include "..\..\memory\block\block.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \brief prototype for frame parser typedef uint_fast16_t frame_parser_t(mem_block_t tMemory, uint_fast16_t hwSize); typedef block_t *frame_block_parser_t(block_t *ptBlock, void *pTag); /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ INCLUDES ======================================*/ #endif ================================================ FILE: sources/gmsi/service/communication/telegraph_engine/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __TELEGRAPH_ENGINE_APP_CFG_H__ #define __TELEGRAPH_ENGINE_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/telegraph_engine/telegraph_engine.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_TELEGRAPH_ENGINE == ENABLED #include #include "..\..\time\multiple_delay\multiple_delay.h" #include "..\..\memory\block\block.h" #include "..\..\time\multiple_delay\multiple_delay.h" #include "./telegraph_engine.h" /*============================ MACROS ========================================*/ #ifndef TELEGRAPH_ENGINE_FRAME_ERROR # define TELEGRAPH_ENGINE_FRAME_ERROR 0xF0 #endif #ifndef this # define this (*ptThis) #endif #ifndef base # define base (*ptBase) #endif #ifndef target # define target (*ptTarget) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #ifndef __TE_ATOM_ACCESS # define __TE_ATOM_ACCESS(...) SAFE_ATOM_CODE(__VA_ARGS__) #endif /*============================ TYPES =========================================*/ //! \name abstruct class telegraph, user telegraph should inherit from this class //! @{ def_class(telegraph_t, which(implement(__single_list_node_t)), telegraph_engine_t *ptEngine; telegraph_handler_t *fnHandler; multiple_delay_item_t *ptDelayItem; uint32_t wTimeout; block_t *ptOUTData; block_t *ptINData; ) end_def_class(telegraph_t) //! @} simple_fsm(telegraph_engine_task, def_params( telegraph_t *ptCurrent; ) ) //! \name telegraph engine //! @{ def_class(telegraph_engine_t, which( inherit(fsm(telegraph_engine_task)) inherit(pool_t)), struct { telegraph_t *ptHead; telegraph_t *ptTail; } Listener; struct { telegraph_t *ptHead; telegraph_t *ptTail; } Transmitter; telegraph_parser_t *fnDecoder; multiple_delay_t *ptDelayService; telegraph_engine_low_level_write_io_t *fnWriteIO; void *pIOTag; ) end_def_class(telegraph_engine_t) //! @} /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ private bool init(telegraph_engine_t *ptObj, telegraph_engine_cfg_t *ptCFG); private block_t * frontend(block_t *ptBlock, telegraph_engine_t *ptObj); private bool try_to_send_telegraph( telegraph_t *ptTelegraph, bool bListener); private bool try_to_listen( telegraph_t *ptTelegraph); private fsm_rt_t task(telegraph_engine_t *ptObj); private block_t *get_input_block(telegraph_t *ptTelegraph); private block_t *get_output_block(telegraph_t *ptTelegraph); private bool is_write_only_telegraph(telegraph_t *ptTelegraph); private bool is_read_only_telegraph(telegraph_t *ptTelegraph); private telegraph_t * telegraph_init( telegraph_engine_t *ptObj, telegraph_handler_t *fnHandler, uint32_t wTimeout, block_t *ptData); private void reset_input_block(telegraph_t *ptTelegraph); private void reset_output_block(telegraph_t *ptTelegraph); /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_telegraph_engine_t TELEGRAPH_ENGINE = { .Init = &init, .Task = &task, .Dependent = { .Parse = &frontend, }, .Telegraph = { .TryToSend = &try_to_send_telegraph, .Listen = &try_to_listen, .New = &telegraph_init, .Data = { .Input = { .Get = &get_input_block, .Reset = &reset_input_block, }, .Output = { .Get = &get_output_block, .Reset = &reset_output_block, }, }, .IsWriteOnly = &is_write_only_telegraph, .IsReadOnly = &is_read_only_telegraph, }, }; /*============================ IMPLEMENTATION ================================*/ private fsm_initialiser(telegraph_engine_task) init_body() private fsm_implementation(telegraph_engine_task) def_states(FETCH_TELEGRAPH, SEND_TELGRAPH, REGISTER_LISTENER) class_internal(ptThis, ptBase, telegraph_engine_t); body( on_start( if (NULL == base.fnWriteIO) { fsm_report(GSF_ERR_NOT_SUPPORT); } ) state(FETCH_TELEGRAPH, __TE_ATOM_ACCESS(){ LIST_QUEUE_DEQUEUE( base.Transmitter.ptHead, base.Transmitter.ptTail, this.ptCurrent); } if (NULL == this.ptCurrent) { fsm_cpl(); } update_state_to(SEND_TELGRAPH); ) state(SEND_TELGRAPH, { class_internal(this.ptCurrent, ptTarget, telegraph_t); fsm_rt_t tResult = (*(base.fnWriteIO))(this.ptCurrent, base.pIOTag ); if (IS_FSM_ERR(tResult)) { fsm_report(tResult); } else if (fsm_rt_cpl != tResult) { fsm_on_going(); } if (NULL == target.fnHandler) { //! free telegraph pool_free(ref_obj_as(base, pool_t), ptTarget); //! pure sender transfer_to(FETCH_TELEGRAPH); } else { update_state_to(REGISTER_LISTENER); } } ) state(REGISTER_LISTENER, //! add the target telegraph to listener list if (!try_to_listen(this.ptCurrent)) { fsm_on_going(); } transfer_to(FETCH_TELEGRAPH); ) ) private fsm_rt_t task(telegraph_engine_t *ptObj) { class_internal(ptObj, ptThis, telegraph_engine_t); if (NULL == ptThis) { return fsm_rt_err; } return call_fsm(telegraph_engine_task, ref_obj_as(this, fsm(telegraph_engine_task))); } private bool init(telegraph_engine_t *ptObj, telegraph_engine_cfg_t *ptCFG) { class_internal(ptObj, ptThis, telegraph_engine_t); do { if (NULL == ptThis || NULL == ptCFG) { break; } else if ( (NULL == ptCFG->tTelegraphPool.pchSrc) || (ptCFG->tTelegraphPool.nSize < sizeof(telegraph_t)) || (ptCFG->wTelegraphSize < sizeof(telegraph_t))) { break; } memset((void *)ptObj, 0, sizeof(telegraph_engine_t)); this.fnDecoder = ptCFG->fnDecoder; this.ptDelayService = ptCFG->ptDelayService; this.fnWriteIO = ptCFG->fnWriteIO; this.pIOTag = ptCFG->pIOTag; init_fsm( telegraph_engine_task, ref_obj_as(this, fsm(telegraph_engine_task))); //! initialise telegraph pool pool_init(ref_obj_as(this, pool_t), ptThis); //! add buffer to telegraph heap pool_add_heap( ref_obj_as(this, pool_t), ptCFG->tTelegraphPool.pObj, ptCFG->tTelegraphPool.nSize, ptCFG->wTelegraphSize); return true; } while(false); return false; } private telegraph_t * telegraph_init( telegraph_engine_t *ptObj, telegraph_handler_t *fnHandler, uint32_t wTimeout, block_t *ptData) { class_internal(ptObj, ptThis, telegraph_engine_t); do { if (NULL == ptThis) { break; } class_internal(pool_new(ref_obj_as(this, pool_t)), ptTarget, telegraph_t); if (NULL == ptTarget) { break; } memset(ptTarget, 0, sizeof(telegraph_t)); target.fnHandler = fnHandler; target.wTimeout = wTimeout; target.ptOUTData = ptData; target.ptINData = NULL; target.ptEngine = ptObj; return (telegraph_t *)ptTarget; } while(false); return NULL; } private void telegraph_timeout_event_handler( multiple_delay_report_status_t tStatus, void *pObj) { class_internal(pObj, ptTarget, telegraph_t); if (NULL == ptTarget) { return ; } class_internal(target.ptEngine, ptThis, telegraph_engine_t); if (NULL == ptThis) { return ; } __TE_ATOM_ACCESS (){ //! remove it from the listener queue LIST_QUEUE_REMOVE(this.Listener.ptHead, this.Listener.ptTail, ptTarget); } if (MULTIPLE_DELAY_TIMEOUT == tStatus) { do { target.ptINData = NULL; if (NULL != target.fnHandler) { //! call telegraph handler if (!(*target.fnHandler)(TELEGRAPH_TIMEOUT, (telegraph_t *)ptTarget)) { //! do not free the telegraph break; } } //! free telegraph pool_free(ref_obj_as(this, pool_t), ptTarget); } while(false); } } private bool is_write_only_telegraph(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); bool bResult = false; do { if (NULL == ptThis) { break; } bResult = (NULL == this.fnHandler); } while(false); return bResult; } private bool is_read_only_telegraph(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); bool bResult = false; do { if (NULL == ptThis) { break; } bResult = (NULL == this.ptOUTData); } while(false); return bResult; } private void reset_input_block(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); do { if (NULL == ptThis) { break; } this.ptINData = NULL; } while(false); } private block_t *get_input_block(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); block_t *ptBlock = NULL; do { if (NULL == ptThis) { break; } ptBlock = this.ptINData; } while(false); return ptBlock; } private void reset_output_block(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); do { if (NULL == ptThis) { break; } this.ptOUTData = NULL; } while(false); } private block_t *get_output_block(telegraph_t *ptTelegraph) { class_internal(ptTelegraph, ptThis, telegraph_t); block_t *ptBlock = NULL; do { if (NULL == ptThis) { break; } ptBlock = this.ptOUTData; } while(false); return ptBlock; } private bool try_to_listen( telegraph_t *ptTelegraph ) { return try_to_send_telegraph(ptTelegraph, true); } private bool try_to_send_telegraph( telegraph_t *ptTelegraph, bool bPureListener) { class(telegraph_engine_t) *ptThis = NULL; class_internal(ptTelegraph, ptTarget, telegraph_t); bool bResult = false; do { if (NULL == ptTelegraph) { break; } ptThis = (class(telegraph_engine_t) *)target.ptEngine; if (NULL == ptThis) { break; } if (bPureListener) { NOP(); //! telegraph for pure listening if ( (target.wTimeout > 0 && NULL == this.ptDelayService) //!< no delay service available || (NULL == this.fnDecoder) //!< no decoder || (NULL == target.fnHandler)) { //!< no listen callback available (pure sender) //! illegal parameters break; } //never do this! :target.ptOUTData = NULL; //! request timeout service if (target.wTimeout > 0) { target.ptDelayItem = MULTIPLE_DELAY.RequestDelay( this.ptDelayService, target.wTimeout, MULTIPLE_DELAY_HIGH_PRIORITY, ptTelegraph, &telegraph_timeout_event_handler); if (NULL == target.ptDelayItem) { //! insufficient delay slots break; } } else { target.ptDelayItem = NULL; } __TE_ATOM_ACCESS (){ //! add it to the listener queue LIST_QUEUE_ENQUEUE( this.Listener.ptHead, this.Listener.ptTail, ptTelegraph); } bResult = true; break; } //! normal telegraph if (NULL == this.fnWriteIO || NULL == target.ptOUTData) { break; } //! add telegraph to transmitter queue __TE_ATOM_ACCESS (){ //! add it to the listener queue LIST_QUEUE_ENQUEUE( this.Transmitter.ptHead, this.Transmitter.ptTail, ptTelegraph ); } bResult = true; } while(false); if ( (!bResult) && (NULL != ptThis) && (NULL != ptTarget)) { do { //! raise telegraph received event if (NULL != target.fnHandler) { //! call telegraph handler if (!(*target.fnHandler)(TELEGRAPH_ERROR, (telegraph_t *)ptTarget)) { //! do not free the telegraph break; } } //! free telegraph pool_free(ref_obj_as(this, pool_t), ptTarget); } while(false); } return bResult; } private block_t * frontend(block_t *ptBlock, telegraph_engine_t *ptObj) { class_internal(ptObj, ptThis, telegraph_engine_t); telegraph_t *ptItem; do { if (NULL == ptThis || NULL == ptBlock) { break; } else if (0 == BLOCK.Size.Get(ptBlock)) { break; } if (NULL == this.Listener.ptHead || NULL == this.fnDecoder) { //! there is pending telegraph break; } //__TE_ATOM_ACCESS ( ptItem = this.Listener.ptHead; //) do { class_internal(ptItem, ptTarget, telegraph_t); block_t *ptTempBlock = ptBlock; //! call frame parser frame_parsing_report_t tReport = this.fnDecoder(&ptTempBlock, ptItem); if (FRAME_UNMATCH != tReport) { if (tReport == FRAME_RECEIVED) { //! cancel delay service if ( (NULL != target.ptDelayItem) && (NULL != this.ptDelayService)) { MULTIPLE_DELAY.Cancel( this.ptDelayService, target.ptDelayItem); do { //! raise telegraph received event if (NULL != target.fnHandler) { target.ptINData = ptBlock; //! call telegraph handler if (!(*target.fnHandler)(TELEGRAPH_RECEIVED, (telegraph_t *)ptTarget)) { //! do not free the telegraph break; } } __TE_ATOM_ACCESS (){ __LIST_QUEUE_REMOVE(this.Listener.ptHead, this.Listener.ptTail, ptItem); } //! free telegraph pool_free(ref_obj_as(this, pool_t), ptItem); } while(false); } if (NULL != ptTempBlock) { ptBlock = ptTempBlock; } else { //! this should not happen while(1); } return ptBlock; //! frame is received } /*else if (FRAME_UNKNOWN == tReport) { //! unknown frame detected BLOCK.Size.Set(ptBlock, 0); } */ break; } __TE_ATOM_ACCESS (){ ptItem = (telegraph_t *)target.ptNext; } } while(NULL != ptItem); } while(false); BLOCK.Size.Set(ptBlock, 0); return ptBlock; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/telegraph_engine/telegraph_engine.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TELEGRAPH_ENGINE_H__ #define __TELEGRAPH_ENGINE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_TELEGRAPH_ENGINE == ENABLED #include "..\..\memory\block\block.h" #include "..\..\time\multiple_delay\multiple_delay.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define TELEGRAPH_ENGINE_CFG(__ADDR, ...) \ do { \ telegraph_engine_cfg_t tCFG = { \ __VA_ARGS__ \ }; \ \ TELEGRAPH_ENGINE.Init((__ADDR), &tCFG); \ } while(false) /*============================ TYPES =========================================*/ declare_class(telegraph_t) declare_class(telegraph_engine_t) //! \name telegraph report status //! @{ typedef enum { TELEGRAPH_ERROR = -1, //!< error detected during checking TELEGRAPH_RECEIVED = 0, //!< expected telegraph is received TELEGRAPH_TIMEOUT, //!< timeout TELEGRAPH_CANCELLED, //!< telegraph is cancelled by user } telegraph_report_t; //! @} //! \name telegraph report event handler prototype (delegate) //! \param tStatus the reason to report //! \param ptTelegraph target telegraph //! \retval true it's safe to free this telegraph //! \retval false do not free the telegraph typedef bool telegraph_handler_t (telegraph_report_t tStatus, telegraph_t *ptTelegraph); //! \name abstruct class telegraph, user telegraph should inherit from this class //! @{ extern_class(telegraph_t, which(implement(__single_list_node_t)), telegraph_engine_t *ptEngine; telegraph_handler_t *fnHandler; multiple_delay_item_t *ptDelayItem; uint32_t wTimeout; block_t *ptOUTData; block_t *ptINData; ) end_extern_class(telegraph_t) //! @} typedef enum { FRAME_UNKNOWN = -1, FRAME_UNMATCH = 0, FRAME_RECEIVED = 1, } frame_parsing_report_t; typedef frame_parsing_report_t telegraph_parser_t( block_t **pptBlock, //! memory buffer telegraph_t *ptItem); //! target telegraph typedef fsm_rt_t telegraph_engine_low_level_write_io_t(telegraph_t *ptItem, void *pObj); extern_simple_fsm(telegraph_engine_task, def_params( telegraph_t *ptCurrent; ) ) //! \name telegraph engine //! @{ extern_class(telegraph_engine_t, which( inherit(fsm(telegraph_engine_task)) inherit(pool_t)), struct { telegraph_t *ptHead; telegraph_t *ptTail; } Listener; struct { telegraph_t *ptHead; telegraph_t *ptTail; } Transmitter; telegraph_parser_t *fnDecoder; multiple_delay_t *ptDelayService; telegraph_engine_low_level_write_io_t *fnWriteIO; void *pIOTag; ) end_extern_class(telegraph_engine_t) //! @} typedef struct { mem_block_t tTelegraphPool; uint32_t wTelegraphSize; telegraph_parser_t *fnDecoder; multiple_delay_t *ptDelayService; telegraph_engine_low_level_write_io_t *fnWriteIO; void *pIOTag; } telegraph_engine_cfg_t; def_interface(i_telegraph_engine_t) bool (*Init) ( telegraph_engine_t *ptObj, telegraph_engine_cfg_t *ptCFG); fsm_rt_t (*Task) ( telegraph_engine_t *ptObj); struct { block_t * (*Parse) ( block_t *ptBlock, telegraph_engine_t *ptObj); } Dependent; struct { telegraph_t *(*New) ( telegraph_engine_t *ptObj, telegraph_handler_t *fnHandler, uint32_t wTimeout, block_t *ptData); bool (*TryToSend)( telegraph_t *ptTelegraph, bool bPureListener); bool (*Listen) ( telegraph_t *ptTelegraph); struct { struct { block_t *(*Get)(telegraph_t *ptTelegraph); void (*Reset)(telegraph_t *ptTelegraph); }Input; struct { block_t *(*Get)(telegraph_t *ptTelegraph); void (*Reset)(telegraph_t *ptTelegraph); }Output; } Data; bool (*IsWriteOnly) (telegraph_t *ptTelegraph); bool (*IsReadOnly) (telegraph_t *ptTelegraph); } Telegraph; end_def_interface(i_telegraph_engine_t) /*============================ GLOBAL VARIABLES ==============================*/ extern const i_telegraph_engine_t TELEGRAPH_ENGINE; /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/xmodem/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __TEMPLATE_XMODEM_APP_CFG_H__ #define __TEMPLATE_XMODEM_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/communication/xmodem/xmodem.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_XMODEM == ENABLED /*============================ MACROS ========================================*/ //! \name Xmodem Protocol Control Character //! @{ #define SOH 0x01 #define STX 0x02 #define EOT 0x04 #define ACK 0x06 #define NAK 0x15 #define CAN 0x18 #define CRC_C 0x43 //! @} //! \name Xmodem Protocol State Parameters //! @{ #define MAX_TRY_AGAN (10ul) #define XMODEM_DATA_BUFFER_SIZE (128ul) #define XMODEM_1K_DATA_BUFFER_SIZE (1024ul) //! @} //! \name Xmodem Protocol Extern Parameters //! @{ #ifndef TIMEOUT_ONE_SECOMD #define TIMEOUT_ONE_SECOMD (500ul) #endif #ifndef TIMEOUT_TEN_SECOMD #define TIMEOUT_TEN_SECOMD (5000ul) #endif #define fsm_rt_user_cancel ((fsm_rt_t)-2) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name xmodem receive configuration //! @{ typedef struct { uint8_t *pchBuffer; //!< receive buffer enum { XMODEM_BLOCK_SZ_256 = 0, XMODEM_BLOCK_SZ_1K, } tMode; } xmodem_t; //! @} //! \name xmodem receiver package state //! @{ typedef enum { PACKET_CPL = 0, //!< fsm complete PACKET_ON_GOING = 1, //!< fsm on-going PACKET_FAIL = 2, PACKET_CAN = 3, PACKET_NO_ERROR = 4, //!< the Sender send a EOT PACKET_NO_CHAR = 5, //!< received no char PACKET_TIMEOUT = 6, //!< read timeout PACKET_INCORRECT_HEADER = 7, //!< incorrect head char PACKET_INCORRECT_PACKET_NUMBER = 8, //!< incorrect packet number PACKET_DUPLICATE_PACKET_NUMBER = 9, //!< duplicate packet number PACKET_INCORRECT_CHECKOUT = 10, //!< incorrect checkout } xm_packet_t; //! @} //! \name xmodem receiver package //! @{ typedef struct { uint8_t chHead; //!< receiver package header uint8_t chBlk; //!< receiver package block counter uint8_t chNBlk; //!< receiver package block counter nverse code uint8_t chCheck[2]; //!< receiver package block checksum } packet_t; //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ //! buffer pointer NO_INIT static uint8_t *s_pchBuffer; //! receiver package header NO_INIT static uint8_t s_chHead; //! receiver package size NO_INIT static uint16_t s_hwBufferSize; /*============================ PROTOTYPES ====================================*/ /*----------------------------------------------------------------------------* * DEPENDENT INTERFACE * *----------------------------------------------------------------------------*/ /*! \brief xmodem lower layer byte write *! \param chByte xmodem usart write byte *! \return none */ extern bool xmodem_lower_layer_write(uint8_t chByte); /*! \brief xmodem lower layer byte read *! \param pchByte xmodem usart write byte *! \return none */ extern bool xmodem_lower_layer_read(uint8_t *pchByte); /*! \brief update next buffer or control transfer speed *! \param hwLength buffer length *! \return buffer address */ extern uint8_t * xmodem_call_back_receive(uint16_t hwLength); /*----------------------------------------------------------------------------* * BASE SUBROUTINE * *----------------------------------------------------------------------------*/ /*! \brief xmodem read with timeout *! \param pchByte read return value pointer *! \retval XM_ON_GOING FSM on-going *! \retval XM_CPL read data succeed *! \retval XM_TIMEOUT read data fail(timeout) */ static xm_packet_t xmodem_read_with_timeout(uint8_t * pchByte, uint32_t wTimeout); /*! \brief Cyclic Redundancy Check by 16 bit *! \param crc history crc value *! \retval CRC Check Value */ static uint16_t CRC_16_CCITT(uint16_t hwCRCValue, uint8_t chData); /*----------------------------------------------------------------------------* * RECEIVE SUBROUTINE * *----------------------------------------------------------------------------*/ /*! \brief xmodem receive 128 byte data *! \param none *! \retval XM_ON_GOING FSM on-going *! \retval XM_CPL FSM complete *! \retval XM_TIMEOUT timeout */ static xm_packet_t xmodem_rec_data(uint8_t * pchBuffer, bool chMode, uint16_t * pchCheck); /*! \brief xmodem receive checkout *! \param none *! \retval XM_ON_GOING FSM on-going *! \retval XM_CPL FSM complete *! \retval XM_TIMEOUT timeout */ static xm_packet_t xmodem_rec_checkout(uint8_t * pchBuffer, bool chMode); /*! \brief xmodem receive a package *! \param pchBuffer receive data buffer *! \param chMode CRC Mode or CKSUN Mode *! \retval PACKET_ON_GOING Receiving *! \retval PACKET_CPL Received *! \retval PACKET_NO_CHAR Not Char to be received *! \retval PACKET_TIMEOUT Receive Timeout *! \retval PACKET_INCORRECT_HEADER Incorrect Head Char *! \retval PACKET_INCORRECT_PACKET_NUMBER Incorrect Packet Number *! \retval PACKET_DUPLICATE_PACKET_NUMBER Duplicate Packet Number *! \retval PACKET_INCORRECT_CHECKOUT Incorrect Checkout */ static xm_packet_t xmodem_rec_package(uint8_t *pchBuffer, bool bCRCMode); /*============================ IMPLEMENTATION ================================*/ /*----------------------------------------------------------------------------* * XMODEM INTERFACE * *----------------------------------------------------------------------------*/ /*! \brief initialize xmodem receive service *! \param pchBuffer xmodem receive configuration * \retval true xmodem receive service initialization succeeded * \retval false xmodem receive service initialization failed */ bool xmodem_init(xmodem_t *ptCFG) { if ((NULL == ptCFG) || (NULL == ptCFG->pchBuffer)) { return false; } //! initialize buffer s_pchBuffer = ptCFG->pchBuffer; //! switch xmode mode if (XMODEM_BLOCK_SZ_256 == ptCFG->tMode ) { s_chHead = SOH; } else { s_chHead = STX; } return true; } #define XMODEM_REC_START 0 #define XMODEM_REC_RESET_FSM() do{s_chState = 0;}while(0) #define XMODEM_MODE_SEND 1 #define XMODEM_MODE_REC_PACKET 2 #define C_TRYING_COUNT 3 #define MODE_HS_CRC 1 #define MODE_HS_CKSUM 2 #define MODE_HS_FINSH 3 /*! \brief xmodem task *! \retrun fsm_rt_cpl xmodem transfer finish *! \retrun fsm_rt_on_going xmodem transfer on-going *! \retrun fsm_rt_on_err xmodem transfer error *! \retrun fsm_rt_user_cancel user cancel transfer */ fsm_rt_t xmodem_task(void) { static uint8_t s_chState = XMODEM_REC_START; static uint8_t s_chTryCount = 0; static uint8_t s_chSend = CRC_C; static uint8_t s_bMode = true; //!< true: CRC false:CKSUM static xm_packet_t s_tRec = PACKET_ON_GOING; static uint8_t s_chHandShake = MODE_HS_CRC; switch (s_chState) { case XMODEM_REC_START: if (NULL == s_pchBuffer) { return fsm_rt_err; } s_chTryCount = 0; s_chSend = CRC_C; s_bMode = true; s_tRec = PACKET_ON_GOING; s_chState = XMODEM_MODE_SEND; s_chHandShake = MODE_HS_CRC; //break; case XMODEM_MODE_SEND: if (xmodem_lower_layer_write(s_chSend)) { //!< send a char if (PACKET_CPL == s_tRec) { //!< xmodem receive CPL XMODEM_REC_RESET_FSM(); return fsm_rt_cpl; } else if (PACKET_CAN == s_tRec) { //!< xmodem receive fail XMODEM_REC_RESET_FSM(); return fsm_rt_user_cancel; } else if (PACKET_FAIL == s_tRec) { //!< xmodem receive fail XMODEM_REC_RESET_FSM(); return fsm_rt_err; } else { //!< xmodem receiving s_chState = XMODEM_MODE_REC_PACKET; } } break; case XMODEM_MODE_REC_PACKET: s_tRec = xmodem_rec_package(s_pchBuffer, s_bMode); //!< receive a frame switch (s_tRec) { /* case PACKET_ON_GOING: //!< xmodem receiving break; */ case PACKET_NO_ERROR: //!< xmodem receive a frame with no error s_chTryCount = 0; //break; case PACKET_DUPLICATE_PACKET_NUMBER: s_chHandShake = MODE_HS_FINSH; s_chSend = ACK; s_chState = XMODEM_MODE_SEND; break; case PACKET_CAN: //!< xmodem send cancel //break; case PACKET_CPL: //!< xmodem reveive CPL s_chSend = ACK; s_chState = XMODEM_MODE_SEND; break; case PACKET_FAIL: //!< xmodem receive fail s_chSend = CAN; s_chState = XMODEM_MODE_SEND; break; case PACKET_TIMEOUT: //!< xmode receive timeout //break; case PACKET_INCORRECT_HEADER: //!< xmode receive incorrect header //break; case PACKET_INCORRECT_PACKET_NUMBER: //!< xmode receive incorrect packet number //break; case PACKET_INCORRECT_CHECKOUT: //!< xmode receive incorrect checkout s_chHandShake = MODE_HS_FINSH; s_chTryCount++; if (MAX_TRY_AGAN > s_chTryCount) { s_chSend = NAK; s_chState = XMODEM_MODE_SEND; } else { XMODEM_REC_RESET_FSM(); return fsm_rt_err; } break; case PACKET_NO_CHAR: //!< no char to be received s_chTryCount++; //! switch CRC mode or CKSUM mode if (MODE_HS_CRC == s_chHandShake) { if (C_TRYING_COUNT == s_chTryCount) { s_chSend = NAK; s_bMode = false; s_chHandShake = MODE_HS_CKSUM; } else { s_chSend = CRC_C; } } else if (MODE_HS_CKSUM == s_chHandShake) { s_chSend = NAK; if (MAX_TRY_AGAN == s_chTryCount) { s_chHandShake = MODE_HS_FINSH; XMODEM_REC_RESET_FSM(); return fsm_rt_err; } } else { s_chSend = NAK; if (MAX_TRY_AGAN == s_chTryCount) { XMODEM_REC_RESET_FSM(); return fsm_rt_err; } } s_chState = XMODEM_MODE_SEND; break; } break; } return fsm_rt_on_going; } /*----------------------------------------------------------------------------* * BACE SUBROUTINE * *----------------------------------------------------------------------------*/ /*! \brief update next buffer or control transfer speed *! \param hwLength buffer length *! \return buffer address */ WEAK uint8_t * xmodem_call_back_receive(uint16_t hwLength) { return s_pchBuffer; } #define XMODEM_READ_START 0 #define XMODEM_READ_RESET_FSM() do{s_chState = 0;}while(0) #define XMODEM_READ_DOING 1 #define XMODEM_READ_DELAY 2 /*! \brief xmodem read with timeout *! \param pchByte read return value pointer *! \retval xm_on_going FSM on-going *! \retval xm_cpl read data succeed *! \retval xm_timeout read data fail(timeout) */ static xm_packet_t xmodem_read_with_timeout(uint8_t * pchByte, uint32_t wTimeout) { static uint8_t s_chState = XMODEM_READ_START; static uint32_t s_wTimeCount = 0; switch (s_chState) { case XMODEM_READ_START: s_wTimeCount = 0; s_chState = XMODEM_READ_DOING; //break; case XMODEM_READ_DOING: if (xmodem_lower_layer_read(pchByte)) { //!< read succeed XMODEM_READ_RESET_FSM(); return PACKET_CPL; } else { //!< read fail s_chState = XMODEM_READ_DELAY; } break; case XMODEM_READ_DELAY: //! wait timeout if (wTimeout > s_wTimeCount) { s_wTimeCount++; s_chState = XMODEM_READ_DOING; } else { XMODEM_READ_RESET_FSM(); return PACKET_TIMEOUT; } break; } return PACKET_ON_GOING; } /*! \brief Cyclic Redundancy Check by CRC-16-CCITT *! \param crc history crc value *! \retval CRC Check Value */ static uint16_t CRC_16_CCITT(uint16_t hwCRCValue, uint8_t chData) { uint8_t chTemp = 8; hwCRCValue = hwCRCValue ^ chData << 8; do { if (hwCRCValue & 0x8000) { hwCRCValue = hwCRCValue << 1 ^ 0x1021; } else { hwCRCValue = hwCRCValue << 1; } }while (--chTemp); return hwCRCValue; } /*----------------------------------------------------------------------------* * RECEIVE SUBROUTINE * *----------------------------------------------------------------------------*/ #define XMODEM_REC_START 0 #define XMODEM_REC_RESET_FSM() do{s_chState = 0;}while(0) #define XMODEM_REC_HEAD 2 #define XMODEM_REC_BLK 3 #define XMODEM_REC_NBLK 4 #define XMODEM_REC_DATA 5 #define XMODEM_REC_CHECKOUT 6 #define XMODEM_CHECK_FRAME 7 #define XMODEM_SAVE 8 #define REC_FRAME_SIZE (1024 + 5) #define REC_HEAD 0 #define REC_BLK 1 #define REC_NBLK 2 #define REC_DATA 3 #define REC_CHECK (1024 + 3) /*! \brief xmodem receive a package *! \param pchBuffer receive data buffer *! \param chMode CRC Mode or CKSUN Mode *! \retval PACKET_ON_GOING Receiving *! \retval PACKET_CPL Received *! \retval PACKET_NO_CHAR Not Char to be received *! \retval PACKET_TIMEOUT Receive Timeout *! \retval PACKET_INCORRECT_HEADER Incorrect Head Char *! \retval PACKET_INCORRECT_PACKET_NUMBER Incorrect Packet Number *! \retval PACKET_DUPLICATE_PACKET_NUMBER Duplicate Packet Number *! \retval PACKET_INCORRECT_CHECKOUT Incorrect Checkout */ static xm_packet_t xmodem_rec_package(uint8_t *pchBuffer, bool bCRCMode) { static uint8_t s_chState = XMODEM_REC_START; static uint16_t s_hwCheck = 0; static uint8_t s_chPacketNumber = 1; xm_packet_t tRead; //NO_INIT static uint8_t s_chFrame[REC_FRAME_SIZE]; NO_INIT static packet_t s_tFrame; NO_INIT static uint8_t chByte; switch (s_chState) { case XMODEM_REC_START: s_hwCheck = 0; s_chState = XMODEM_REC_HEAD; //break; case XMODEM_REC_HEAD: //!< receive header tRead = xmodem_read_with_timeout(&chByte, TIMEOUT_TEN_SECOMD); if (PACKET_CPL == tRead) { if (EOT == chByte) { s_chPacketNumber = 1; XMODEM_REC_RESET_FSM(); return PACKET_CPL; } else if (CAN == chByte) { s_chPacketNumber = 1; XMODEM_REC_RESET_FSM(); return PACKET_CAN; } else if ((STX == s_chHead) && (STX == chByte)) { s_hwBufferSize = XMODEM_1K_DATA_BUFFER_SIZE; } else { s_hwBufferSize = XMODEM_DATA_BUFFER_SIZE; } s_tFrame.chHead = chByte; s_chState = XMODEM_REC_BLK; } else if (PACKET_TIMEOUT == tRead) { XMODEM_REC_RESET_FSM(); return PACKET_NO_CHAR; } /*else { //! on-gong } */ break; case XMODEM_REC_BLK: //!< receive blk tRead = xmodem_read_with_timeout(&chByte, TIMEOUT_ONE_SECOMD); if (PACKET_CPL == tRead) { s_tFrame.chBlk = chByte; s_chState = XMODEM_REC_NBLK; } else if (PACKET_TIMEOUT == tRead) { XMODEM_REC_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_REC_NBLK: //!< receive 255 - blk tRead = xmodem_read_with_timeout(&chByte, TIMEOUT_ONE_SECOMD); if (PACKET_CPL == tRead) { s_tFrame.chNBlk = chByte; s_chState = XMODEM_REC_DATA; } else if (PACKET_TIMEOUT == tRead) { XMODEM_REC_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_REC_DATA: //!< receive 128 byte data tRead = xmodem_rec_data(s_pchBuffer, bCRCMode, &s_hwCheck); if (PACKET_CPL == tRead) { s_chState = XMODEM_REC_CHECKOUT; } else if (PACKET_TIMEOUT == tRead) { XMODEM_REC_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_REC_CHECKOUT: tRead = xmodem_rec_checkout(s_tFrame.chCheck, bCRCMode); if (PACKET_CPL == tRead) { s_chState = XMODEM_CHECK_FRAME; } else if (PACKET_TIMEOUT == tRead) { XMODEM_REC_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_CHECK_FRAME: //if (s_chHead != s_tFrame.chHead) { if ((STX != s_tFrame.chHead) && (SOH != s_tFrame.chHead) ) { XMODEM_REC_RESET_FSM(); return PACKET_INCORRECT_HEADER; } if (0xFF != (s_tFrame.chBlk ^ s_tFrame.chNBlk)) { XMODEM_REC_RESET_FSM(); return PACKET_INCORRECT_PACKET_NUMBER; } if ((s_chPacketNumber - 1) == s_tFrame.chBlk ) { XMODEM_REC_RESET_FSM(); return PACKET_DUPLICATE_PACKET_NUMBER; } if (s_chPacketNumber != s_tFrame.chBlk ) { XMODEM_REC_RESET_FSM(); return PACKET_FAIL; } if (bCRCMode) { if (s_hwCheck != ((uint16_t)s_tFrame.chCheck[0] * 256 + (uint16_t)s_tFrame.chCheck[1])) { XMODEM_REC_RESET_FSM(); return PACKET_INCORRECT_CHECKOUT; } } else { if ((uint8_t)s_hwCheck != s_tFrame.chCheck[0]) { XMODEM_REC_RESET_FSM(); return PACKET_INCORRECT_CHECKOUT; } } s_chPacketNumber++; s_chState = XMODEM_SAVE; break; case XMODEM_SAVE: { uint8_t * pchNext = xmodem_call_back_receive(s_hwBufferSize); if (NULL != pchNext) { s_pchBuffer = pchNext; XMODEM_REC_RESET_FSM(); return PACKET_NO_ERROR; } } break; } return PACKET_ON_GOING; } #define XMODEM_REC_DATA_START 0 #define XMODEM_REC_DATA_RESET_FSM() do{s_chState = 0;}while(0) #define XMODEM_REC_DATA_READ 1 #define XMODEM_REC_DATA_NEXT 2 /*! \brief xmodem receive 128 byte data *! \param none *! \retval XM_ON_GOING FSM on-going *! \retval XM_CPL FSM complete *! \retval XM_TIMEOUT timeout */ static xm_packet_t xmodem_rec_data(uint8_t * pchBuffer, bool chMode, uint16_t * pchCheck) { static uint8_t s_chState = XMODEM_REC_DATA_START; static uint16_t s_hwIndex = 0; xm_packet_t tRead; xm_packet_t tRetVal = PACKET_ON_GOING; uint8_t chByte; switch (s_chState) { case XMODEM_REC_DATA_START: s_hwIndex = 0; s_chState = XMODEM_REC_DATA_READ; //break; case XMODEM_REC_DATA_READ: tRead = xmodem_read_with_timeout(&chByte, TIMEOUT_ONE_SECOMD); if (PACKET_CPL == tRead) { //!< read succeed pchBuffer[s_hwIndex] = chByte; if (chMode) { *pchCheck = CRC_16_CCITT(*pchCheck, chByte); } else { *pchCheck += chByte; } s_chState = XMODEM_REC_DATA_NEXT; } else if (PACKET_TIMEOUT == tRead) { //!< timeout XMODEM_REC_DATA_RESET_FSM(); tRetVal = PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_REC_DATA_NEXT: s_hwIndex++; if (s_hwBufferSize > s_hwIndex) { s_chState = XMODEM_REC_DATA_READ; } else { XMODEM_REC_DATA_RESET_FSM(); return PACKET_CPL; } break; } return tRetVal; } #define XMODEM_REC_CHECKOUT_START 0 #define XMODEM_REC_CHECKOUT_RESET_FSM() do{s_chState = 0;}while(0) #define XMODEM_REC_CHECKOUT_HIGH 1 #define XMODEM_REC_CHECKOUT_LOW 2 #define XMODEM_REC_CHECKOUT_SAVE 3 #define XMODEM_REC_CHECKOUT_ACK 4 /*! \brief xmodem receive checkout *! \param none *! \retval XM_ON_GOING FSM on-going *! \retval XM_CPL FSM complete *! \retval XM_TIMEOUT timeout */ static xm_packet_t xmodem_rec_checkout(uint8_t * pchBuffer, bool chMode) { static uint8_t s_chState =XMODEM_REC_CHECKOUT_START; xm_packet_t tRunState; uint8_t chByte; switch (s_chState) { case XMODEM_REC_CHECKOUT_START: s_chState = XMODEM_REC_CHECKOUT_HIGH; //break; case XMODEM_REC_CHECKOUT_HIGH: tRunState = xmodem_read_with_timeout(&chByte, TIMEOUT_ONE_SECOMD); if (PACKET_CPL == tRunState) { //!< read succeed pchBuffer[0] = chByte; if (chMode) { s_chState = XMODEM_REC_CHECKOUT_LOW; } else { XMODEM_REC_CHECKOUT_RESET_FSM(); return PACKET_CPL; } } else if (PACKET_TIMEOUT == tRunState) { //!< timeout XMODEM_REC_CHECKOUT_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; case XMODEM_REC_CHECKOUT_LOW: tRunState = xmodem_read_with_timeout(&chByte, TIMEOUT_ONE_SECOMD); if (PACKET_CPL == tRunState) { //!< read succeed pchBuffer[1] = chByte; XMODEM_REC_CHECKOUT_RESET_FSM(); return PACKET_CPL; } else if (PACKET_TIMEOUT == tRunState) { //!< timeout XMODEM_REC_CHECKOUT_RESET_FSM(); return PACKET_TIMEOUT; } /*else { //! on-gong } */ break; } return PACKET_ON_GOING; } #endif /*EOF*/ ================================================ FILE: sources/gmsi/service/communication/xmodem/xmodem.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_SERVICE_XMODEM_H__ #define __USE_SERVICE_XMODEM_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_XMODEM == ENABLED /*============================ MACROS ========================================*/ #define fsm_rt_user_cancel ((fsm_rt_t)-2) /*============================ MACROFIED FUNCTIONS ===========================*/ #define XMODEM_CFG(__MODE, __BUFFER) \ do { \ xmodem_t tCFG = { \ .pchBuffer = __BUFFER, \ .tMode = __MODE \ }; \ xmodem_init(&tCFG); \ } while (0) /*============================ TYPES =========================================*/ //! \name xmodem receive configuration //! @{ typedef struct { uint8_t *pchBuffer; //!< receive buffer enum { XMODEM_BLOCK_SZ_256 = 0, XMODEM_BLOCK_SZ_1K, } tMode; } xmodem_t; //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize xmodem receive service *! \param pchBuffer xmodem receive configuration * \retval true xmodem receive service initialization succeeded * \retval false xmodem receive service initialization failed */ extern bool xmodem_init(xmodem_t *ptCFG); /*! \brief xmodem task *! \retrun fsm_rt_cpl xmodem transfer finish *! \retrun fsm_rt_on_going xmodem transfer on-going *! \retrun fsm_rt_on_err xmodem transfer error *! \retrun fsm_rt_user_cancel user cancel transfer */ extern fsm_rt_t xmodem_task(void); #endif #endif ================================================ FILE: sources/gmsi/service/encryption/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __ENCRYPTION_APP_CFG_H__ #define __ENCRYPTION_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } /* extern "C" */ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/encryption/encryption.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __ENCRYPTION_H__ #define __ENCRYPTION_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\random\random.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/encryption/random/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __RANDOM_APPLICATION_CONFIGURATION_H__ #define __RAMDOM_APPLICATION_CONFIGURATION_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } /* extern "C" */ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/encryption/random/random.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ //! \brief random seed static uint16_t s_hwRandomSeed = 0xAA55; /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \note set random generator seed * \param hwSeed random seed * \return none */ void set_random_seed( uint16_t hwSeed ) { s_hwRandomSeed ^= hwSeed; } /*! \note reset software random generator *! \param none *! \return none */ void reset_random( void ) { s_hwRandomSeed = 0xAA55; } /*! \note get a random integer * \param none * \return random integer value */ uint16_t get_random_u16( void ) { s_hwRandomSeed = 22695477ul * s_hwRandomSeed + 1; return s_hwRandomSeed; } /* EOF */ ================================================ FILE: sources/gmsi/service/encryption/random/random.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __RANDOM_H__ #define __RANDOM_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*! \note get a random byte * \param none * \return random integer value */ #define get_random_u8() get_random_u16() /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note set random generator seed * \param hwSeed random seed * \return none */ extern void set_random_seed( uint16_t hwSeed ); /*! \note reset software random generator *! \param none *! \return none */ extern void reset_random( void ); /*! \note get a random integer * \param none * \return random integer value */ extern uint16_t get_random_u16( void ); #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __GUI_APP_CFG_H__ #define __GUI_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/gui.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __GUI_H__ #define __GUI_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\tgui\tgui.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __TGUI_APP_CFG_H__ #define __TGUI_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/grid/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __TGUI_GRID_APP_CFG_H__ #define __TGUI_GRID_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/grid/grid.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_GUI_TGUI == ENABLED #include ".\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/grid/grid.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TGUI_GRID_H__ #define __TGUI_GRID_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_GUI_TGUI == ENABLED #include ".\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/grid/interface.h ================================================ /*************************************************************************** * Copyright(C)2009-2014 by Gorgon Meducer * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU Lesser General Public License as * * published by the Free Software Foundation; either version 2 of the * * License, or (at your option) any later version. * * * * This program is distributed in the hope that it will be useful, * * but WITHOUT ANY WARRANTY; without even the implied warranty of * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * * * You should have received a copy of the GNU Lesser General Public * * License along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ #ifndef __TGUI_GRID_INTERFACE_H__ #define __TGUI_GRID_INTERFACE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include "..\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name grid //! @{ typedef struct { union { int_fast8_t chX; int_fast8_t chLeft; }; union { int_fast8_t chY; int_fast8_t chTop; }; } grid_t; //! @} //! \name grid rectangle //! @{ typedef struct { union { grid_t; grid_t __grid_t; }; int_fast8_t chWidth; //!< Width in grid int_fast8_t chHeight; //!< Height in grid } grid_rect_t; //! @} //! \name grid brush //! @{ typedef struct { color_t tForeground; color_t tBackground; } grid_brush_t; //! @} //*! \name grid drawing context //! @{ DEF_INTERFACE(i_gdc_t, DEF_INTERFACE(grid_property_t) fsm_rt_t (*Set)(grid_t tGrid); fsm_rt_t (*Get)(grid_t *ptGrid); fsm_rt_t (*SaveCurrent)(void); fsm_rt_t (*Resume)(void); END_DEF_INTERFACE(grid_property_t) DEF_INTERFACE(grid_brush_property_t) fsm_rt_t (*Set)(grid_brush_t tBrush); grid_brush_t (*Get)(void); END_DEF_INTERFACE(grid_brush_property_t) ) const struct { int_fast8_t chWidth; int_fast8_t chHeight; } Info; grid_property_t Position; grid_brush_property_t Color; fsm_rt_t (*Clear)(void); fsm_rt_t (*Print)(uint8_t *pchString, uint_fast16_t hwSize); END_DEF_INTERFACE(i_gdc_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/interface.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TGUI_INTERFACE_H__ #define __TGUI_INTERFACE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ #if TGUI_SIZE_INT_TYPE == TGUI_TINY typedef int_fast8_t tgui_int_t; #elif TGUI_SIZE_INT_TYPE == TGUI_MEDIUM typedef int_fast16_t tgui_int_t; #else typedef int_fast32_t tgui_int_t; #endif //! \name point //! @{ typedef struct { union { tgui_int_t tX; tgui_int_t tLeft; }; union { tgui_int_t tY; tgui_int_t tTop; }; } point_t; //! @} //! \name rectangle //! @{ typedef struct { union { point_t; point_t __point_t; }; tgui_int_t tWidth; //!< Width in pix tgui_int_t tHeight; //!< Height in pix } rect_t; //! @} #if TGUI_COLOR_BITS == TGUI_24BITS typedef union { uint32_t tValue; struct { uint8_t chR; uint8_t chG; uint8_t ghB; }; } color_t; #elif TGUI_COLOR_BITS == TGUI_8BITS typedef union { uint8_t tValue; } color_t; #else /*TGUI_COLOR_BITS == TGUI_4BITS*/ typedef union { uint8_t tValue; } color_t; #endif /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/tgui.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_GUI_TGUI == ENABLED #include ".\interface.h" #include ".\grid\grid.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ bool tgui_init(void) { return true; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/gui/tgui/tgui.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TGUI_H__ #define __TGUI_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_GUI_TGUI == ENABLED #include ".\interface.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __USE_SERVICE_MEMORY_APP_CFG__ #define __USE_SERVICE_MEMORY_APP_CFG__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/memory/block/__class_block.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //#ifndef __CLASS_BLOCK_H__ /* deliberately comment this out! */ //#define __CLASS_BLOCK_H__ /*============================ INCLUDES ======================================*/ #include "app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define __BLOCK_FREE_TO(__N, __NUM) BLOCK_FREE_TO_##__N = __N+1, /*============================ TYPES =========================================*/ enum { BLOCK_FREE_TO_ANY = 0, MREPEAT(254, __BLOCK_FREE_TO, NULL) BLOCK_NO_FREE = 255 }; declare_class(block_t) //! \name special methods for accessing blocks //! \note the instance of i_block_methods_t should stored in ROM //! @{ def_interface(i_block_methods_t) void (*Free)(void *, block_t *ptBlock); //!< User specified free int_fast32_t (*Read)( void *pTarget, void *pBlockBuffer, void *pBuff, int_fast32_t wSize, uint_fast32_t wOffset); int_fast32_t (*Write)( void *pTarget, void *pBlockBuffer, const void *pBuff, int_fast32_t nSize, uint_fast32_t wOffset); end_def_interface(i_block_methods_t) //! @} typedef struct { void *pTarget; uint_fast8_t chID; const i_block_methods_t *ptMethods; //!< block methods } block_adapter_t; //! \brief fixed memory block used as stream buffer //! @{ def_class(block_t) implement(__single_list_node_t) uint8_t *pchBuffer; //!< buffer address union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint32_t Size : 24; uint32_t chAdapterID : 8; end_def_class(block_t); //! @} declare_class(block_pool_t) def_class(block_pool_t, which( inherit(pool_t) )) block_adapter_t *ptAdapter; end_def_class(block_pool_t, which( inherit(pool_t) )) typedef struct { void * pBuffer; union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint_fast8_t chAdapterID; } block_cfg_t; typedef struct { block_adapter_t *ptAdapter; }block_pool_cfg_t; def_interface(i_block_t) struct { bool (*Init) (block_pool_t *, block_pool_cfg_t *ptCFG); bool (*Add) (block_pool_t *, void *, uint_fast32_t, uint_fast32_t); block_t* (*New) (block_pool_t *); void (*Free) (block_pool_t *, block_t *); uint_fast32_t (*Count) (block_pool_t *ptObj); } Heap; block_t * (*Init) (block_t *ptBlock, block_cfg_t *ptCFG); struct { void (*Register)(block_adapter_t *ptAdaptors, uint_fast8_t chSize); } Adapter; struct { uint_fast32_t (*Get) (block_t *); void (*Set) (block_t *, uint_fast32_t); void (*Reset) (block_t *); uint_fast32_t (*Capability)(block_t *); } Size; struct { void * (*Get)(block_t *); bool (*Write) (block_t *ptObj, const void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); mem_block_t (*Read) (block_t *ptObj, void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); } Buffer; end_def_interface(i_block_t) /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ //#endif /* deliberately comment this out! */ ================================================ FILE: sources/gmsi/service/memory/block/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __BLOCK_APP_CFG_H__ #define __BLOCK_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/block/block.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_BLOCK == ENABLED #include "..\epool\epool.h" #include #include "./block.h" /*============================ MACROS ========================================*/ #ifndef this # define this (*ptThis) #endif #ifndef base # define base (*ptBase) #endif #ifndef target # define target (*ptTarget) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \brief fixed memory block used as stream buffer //! @{ def_class(block_t, which(implement(__single_list_node_t)), uint8_t *pchBuffer; //!< buffer address union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint32_t Size : 24; uint32_t chAdapterID : 8; ) end_def_class(block_t); //! @} def_class(block_pool_t, which( inherit(pool_t) ), block_adapter_t *ptAdapter; ) end_def_class(block_pool_t) /*============================ LOCAL VARIABLES ===============================*/ static struct { block_adapter_t *ptAdapters; uint_fast8_t chLength; }s_tBlockControl = {NULL, 0}; /*============================ PROTOTYPES ====================================*/ private void reset_block_size(block_t *ptObj); private void *get_block_buffer(block_t *ptObj); private void set_block_size(block_t *ptObj, uint_fast32_t wSize); private uint_fast32_t get_block_size(block_t *ptObj); private uint_fast32_t get_block_capability(block_t *ptObj); private bool block_pool_init(block_pool_t *ptObj, block_pool_cfg_t *ptCFG); private block_t *new_block(block_pool_t *ptObj); private void free_block(block_pool_t *ptObj, block_t *ptItem); private bool block_pool_add_heap( block_pool_t *ptObj, void *pBuffer, uint_fast32_t wSize, uint_fast32_t wItemSize); private block_t *init(block_t *ptBlock, block_cfg_t *ptCFG); private bool write_block_buffer(block_t *ptObj, const void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); private mem_block_t read_block_buffer(block_t *ptObj, void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); private uint_fast32_t get_free_block_count(block_pool_t *ptObj); //private void __free_block(void *pTarget, block_t *ptBlock); private void register_adaptors(block_adapter_t *ptAdaptors, uint_fast8_t chSize); /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_block_t BLOCK = { .Heap = { .Init = &block_pool_init, .Add = &block_pool_add_heap, .New = &new_block, .Free = &free_block, .Count = &get_free_block_count, }, .Init = &init, .Adapter = { .Register = ®ister_adaptors, }, .Size = { .Get = &get_block_size, .Set = &set_block_size, .Reset = &reset_block_size, .Capability = &get_block_capability, }, .Buffer = { .Get = &get_block_buffer, .Write = &write_block_buffer, .Read = &read_block_buffer, }, }; /*============================ IMPLEMENTATION ================================*/ private const block_adapter_t* __get_adapter_interface(block_t *ptItem) { class_internal(ptItem, ptThis, block_t); assert(NULL != ptThis); block_adapter_t *ptAdapter = NULL; do { uint_fast8_t chID = this.chAdapterID; if (0 == chID || 255 == chID) { break; } if (NULL == s_tBlockControl.ptAdapters) { break; } if (chID > s_tBlockControl.chLength) { break; } ptAdapter = &s_tBlockControl.ptAdapters[chID-1]; assert(NULL != ptAdapter->ptMethods); } while(0); return ptAdapter; } private void register_adaptors(block_adapter_t *ptAdaptors, uint_fast8_t chSize) { //!< this function could only be called once. assert(s_tBlockControl.ptAdapters == NULL); s_tBlockControl.ptAdapters = ptAdaptors; s_tBlockControl.chLength = chSize; } private block_t *init(block_t *ptBlock, block_cfg_t *ptCFG) { class_internal(ptBlock, ptThis, block_t); assert(NULL != ptBlock && NULL != ptCFG); do { if ( (ptCFG->BlockSize < sizeof(this)) && (NULL == ptCFG->pBuffer)) { break; } this.wCapability = ptCFG->wCapability; if (NULL != ptCFG->pBuffer) { this.pchBuffer = ptCFG->pBuffer; this.Size = ptCFG->BlockSize; } else { this.pchBuffer = ((uint8_t *)&this)+sizeof(this); this.Size = ptCFG->BlockSize - sizeof(this); this.BlockSize = this.Size; } this.chAdapterID = ptCFG->chAdapterID; } while(false); return ptBlock; } private void reset_block_size(block_t *ptObj) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj); if (!this.IsNoWrite) { //!< readonly this.Size = this.BlockSize; } } private void *get_block_buffer(block_t *ptObj) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj); if (this.IsNoDirectAccess) { return NULL; } return this.pchBuffer; } private bool write_block_buffer( block_t *ptObj, const void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj && NULL != pchSrc); bool bResult = false; do { if (0 == nSize) { break; } else if (this.IsNoWrite) { break; } uint_fast32_t wMaxSize = this.BlockSize - wOffsite; if (nSize > wMaxSize) { break; //!< too big to write } if (this.IsNoDirectAccess) { const block_adapter_t *ptAdapter = __get_adapter_interface(ptObj); if (NULL == ptAdapter) { break; } if (NULL == ptAdapter->ptMethods->Write) { break; } nSize = (*ptAdapter->ptMethods->Write)(ptAdapter->pTarget, this.pchBuffer, pchSrc, nSize, wOffsite); if (nSize < 0) { break; } } else { memcpy(((uint8_t *)get_block_buffer(ptObj))+wOffsite, pchSrc, nSize); } this.Size = nSize+wOffsite; bResult = true; } while(false); return bResult; } private mem_block_t read_block_buffer( block_t *ptObj, void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj && NULL != pchSrc); uint8_t *pchBuffer = NULL; mem_block_t tResult = {0}; bool bResult = false; do { if (0 == nSize) { break; } else if (this.IsNoRead) { break; } uint_fast32_t wMaxSize = this.BlockSize - wOffsite; if (this.IsNoDirectAccess) { nSize = MIN(nSize, wMaxSize); const block_adapter_t *ptAdapter = __get_adapter_interface(ptObj); if (NULL == ptAdapter) { break; } if (NULL == ptAdapter->ptMethods->Read) { break; } nSize = (*ptAdapter->ptMethods->Read)(ptAdapter->pTarget, this.pchBuffer, pchSrc, nSize, wOffsite); if (nSize < 0) { break; } pchBuffer = pchSrc; } else if (nSize <= wMaxSize) { pchBuffer = (uint8_t *)get_block_buffer(ptObj) + wOffsite; } else { pchBuffer = (uint8_t *)get_block_buffer(ptObj); nSize = wMaxSize; memcpy(pchSrc, pchBuffer+wOffsite, nSize); pchBuffer = pchSrc; } tResult.pchBuffer = pchBuffer; tResult.nSize = nSize; } while(false); return tResult; } private void set_block_size(block_t *ptObj, uint_fast32_t wSize) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj); if (this.IsNoWrite) { //! readonly return ; } this.Size = MIN(wSize, this.BlockSize); } private uint_fast32_t get_block_capability(block_t *ptObj) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj); return this.BlockSize; } private uint_fast32_t get_block_size(block_t *ptObj) { class_internal(ptObj, ptThis, block_t); assert(NULL != ptObj); return this.Size; } private bool block_pool_init(block_pool_t *ptObj, block_pool_cfg_t *ptCFG) { class_internal(ptObj, ptThis, block_pool_t); assert(NULL != ptObj); do { memset(ptObj, 0, sizeof(block_pool_t)); if (NULL != ptCFG) { this.ptAdapter = ptCFG->ptAdapter; } //! initialise pool if (!pool_init(ref_obj_as(this, pool_t), ptThis)) { break; } return true; } while(false); return false; } private uint32_t get_free_block_count(block_pool_t *ptObj) { class_internal(ptObj, ptThis, block_pool_t); assert(NULL != ptObj); return pool_get_item_count(ref_obj_as(this, pool_t)); } private block_t *new_block(block_pool_t *ptObj) { class_internal(ptObj, ptThis, block_pool_t); assert(NULL != ptObj); block_t *ptBlock = (block_t *)pool_new( REF_OBJ_AS(this, pool_t)); reset_block_size(ptBlock); return ptBlock; } private void free_block(block_pool_t *ptObj, block_t *ptItem) { class_internal(ptObj, ptThis, block_pool_t); class_internal(ptItem, ptTarget, block_t); if (NULL == ptItem) { return ; } do { uint_fast8_t chID = target.chAdapterID; assert(ptThis != NULL); if (BLOCK_NO_FREE == chID) { return ; } const block_adapter_t *ptAdapter = __get_adapter_interface(ptItem); if (NULL == ptAdapter) { break; } if (NULL != ptAdapter->ptMethods->Free) { (*ptAdapter->ptMethods->Free)(ptAdapter->pTarget, ptItem); } return ; } while(false); pool_free( REF_OBJ_AS(this, pool_t), ptItem); } private void pool_item_init_event_handler( void *pTarget, void *ptItem, uint_fast32_t wItemSize) { /* typedef struct { void * pBuffer; union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint_fast8_t chAdapterIndex; } block_cfg_t; */ class_internal(pTarget, ptThis, block_pool_t); uint_fast8_t chID = BLOCK_FREE_TO_ANY; if (NULL != this.ptAdapter) { chID = this.ptAdapter->chID; } block_cfg_t tCFG = { NULL, //!< use the rest memory of the block as buffer wItemSize, //!< total block size false, //!< allow write false, //!< allow read false, //!< allow direct access chID, //!< free to current heap }; init((block_t *)ptItem, &tCFG); } private bool block_pool_add_heap( block_pool_t *ptObj, void *pBuffer, uint_fast32_t hwSize, uint_fast32_t hwItemSize) { bool bResult = false; class_internal(ptObj, ptThis, block_pool_t); assert(NULL != ptObj && NULL != pBuffer); do { if ( (hwSize < hwItemSize) || (hwItemSize < sizeof(block_t)) || (0 == hwItemSize)) { break; } bResult = pool_add_heap_ex ( REF_OBJ_AS(this, pool_t), pBuffer, hwSize, hwItemSize, &pool_item_init_event_handler ); } while(false); return bResult; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/block/block.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __BLOCK_H__ #define __BLOCK_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_BLOCK == ENABLED #include "../epool/epool.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define __BLOCK_FREE_TO(__N, __NUM) BLOCK_FREE_TO_##__N = __N+1, /*============================ TYPES =========================================*/ enum { BLOCK_FREE_TO_ANY = 0, MACRO_REPEAT(254, __BLOCK_FREE_TO, NULL) BLOCK_NO_FREE = 255 }; declare_class(block_t) //! \name special methods for accessing blocks //! \note the instance of i_block_methods_t should stored in ROM //! @{ def_interface(i_block_methods_t) void (*Free)(void *, block_t *ptBlock); //!< User specified free int_fast32_t (*Read)( void *pTarget, void *pBlockBuffer, void *pBuff, int_fast32_t wSize, uint_fast32_t wOffset); int_fast32_t (*Write)( void *pTarget, void *pBlockBuffer, const void *pBuff, int_fast32_t nSize, uint_fast32_t wOffset); end_def_interface(i_block_methods_t) //! @} typedef struct { void *pTarget; uint_fast8_t chID; const i_block_methods_t *ptMethods; //!< block methods } block_adapter_t; //! \brief fixed memory block used as stream buffer //! @{ extern_class(block_t, which(implement(__single_list_node_t)), uint8_t *pchBuffer; //!< buffer address union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint32_t Size : 24; uint32_t chAdapterID : 8; ) end_extern_class(block_t) //! @} declare_class(block_pool_t) extern_class(block_pool_t, which( inherit(pool_t) ), block_adapter_t *ptAdapter; ) end_extern_class(block_pool_t) typedef struct { void * pBuffer; union { struct { uint32_t BlockSize : 24; uint32_t IsNoWrite : 1; uint32_t IsNoRead : 1; uint32_t IsNoDirectAccess : 1; uint32_t : 5; }; uint32_t wCapability; }; uint_fast8_t chAdapterID; } block_cfg_t; typedef struct { block_adapter_t *ptAdapter; }block_pool_cfg_t; def_interface(i_block_t) struct { bool (*Init) (block_pool_t *, block_pool_cfg_t *ptCFG); bool (*Add) (block_pool_t *, void *, uint_fast32_t, uint_fast32_t); block_t* (*New) (block_pool_t *); void (*Free) (block_pool_t *, block_t *); uint_fast32_t (*Count) (block_pool_t *ptObj); } Heap; block_t * (*Init) (block_t *ptBlock, block_cfg_t *ptCFG); struct { void (*Register)(block_adapter_t *ptAdaptors, uint_fast8_t chSize); } Adapter; struct { uint_fast32_t (*Get) (block_t *); void (*Set) (block_t *, uint_fast32_t); void (*Reset) (block_t *); uint_fast32_t (*Capability)(block_t *); } Size; struct { void * (*Get)(block_t *); bool (*Write) (block_t *ptObj, const void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); mem_block_t (*Read) (block_t *ptObj, void *pchSrc, int_fast32_t nSize, uint_fast32_t wOffsite); } Buffer; end_def_interface(i_block_t) extern const i_block_t BLOCK; /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/block_queue/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __BLOCK_QUEUE_APP_CFG_H__ #define __BLOCK_QUEUE_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/block_queue/block_queue.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_BLOCK_QUEUE == ENABLED #if USE_SERVICE_BLOCK != ENABLED #error The block_queue service requires the Block Service, please set USE_SERVICE_BLOCK to ENABLED in top app_cfg.h #endif #include "..\block\block.h" #include "./block_queue.h" #include /*============================ MACROS ========================================*/ #ifndef __BQ_ATOM_ACCESS # define __BQ_ATOM_ACCESS(...) SAFE_ATOM_CODE(__VA_ARGS__) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ declare_class(block_queue_t) def_class(block_queue_t,, //!< inherit from pool StreamBufferBlock block_t *ptListHead; //!< Queue Head block_t *ptListTail; //!< Queue Tail uint32_t wCount; ) end_def_class(block_queue_t) /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ private bool block_queue_init(block_queue_t *ptObj); private bool append_item_to_list(block_queue_t *ptObj, block_t *ptItem); private uint32_t get_item_count(block_queue_t *ptObj); private block_t *get_item_from_list(block_queue_t *ptObj); /*============================ IMPLEMENTATION ================================*/ /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_block_queue_t BLOCK_QUEUE = { .Init = &block_queue_init, .Enqueue = &append_item_to_list, .Dequeue = &get_item_from_list, .Count = &get_item_count, }; private bool block_queue_init(block_queue_t *ptObj) { class_internal(ptObj, ptThis, block_queue_t); do { if (NULL == ptThis) { break; } memset(ptThis, 0, sizeof(block_queue_t)); return true; } while(false); return false; } private bool append_item_to_list(block_queue_t *ptObj, block_t *ptItem) { class_internal(ptObj, ptThis, block_queue_t); if (NULL == ptThis || NULL == ptItem) { return false; } __BQ_ATOM_ACCESS (){ LIST_QUEUE_ENQUEUE(this.ptListHead, this.ptListTail, ptItem); this.wCount++; } return true; } private uint32_t get_item_count(block_queue_t *ptObj) { class_internal(ptObj, ptThis, block_queue_t); uint32_t wResult; //__BQ_ATOM_ACCESS ( wResult = this.wCount; //) return wResult; } private block_t *get_item_from_list(block_queue_t *ptObj) { class_internal(ptObj, ptThis, block_queue_t); block_t *ptResult = NULL; if (NULL == ptThis) { return NULL; } __BQ_ATOM_ACCESS (){ if (NULL != this.ptListHead) { LIST_QUEUE_DEQUEUE(this.ptListHead, this.ptListTail, ptResult); this.wCount--; } } return ptResult; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/block_queue/block_queue.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __BLOCK_QUEUE_H__ #define __BLOCK_QUEUE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_BLOCK_QUEUE == ENABLED #include "..\block\block.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \brief stream buffer control block //! @{ declare_class(stream_buffer_t) declare_class(block_queue_t) extern_class(block_queue_t,, //!< inherit from pool StreamBufferBlock block_t *ptListHead; //!< Queue Head block_t *ptListTail; //!< Queue Tail uint32_t wCount; ) end_extern_class(block_queue_t) def_interface(i_block_queue_t) bool (*Init) (block_queue_t *ptObj); bool (*Enqueue) (block_queue_t *ptObj, block_t *ptItem); block_t * (*Dequeue) (block_queue_t *ptObj); uint32_t (*Count) (block_queue_t *ptObj); end_def_interface(i_block_queue_t) /*============================ GLOBAL VARIABLES ==============================*/ extern const i_block_queue_t BLOCK_QUEUE; /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/epool/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __EPOOL_APP_CFG_H__ #define __EPOOL_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/epool/epool.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #ifndef __EPOOL_ATOM_ACCESS #define __EPOOL_ATOM_ACCESS(...) SAFE_ATOM_CODE(__VA_ARGS__) #endif #ifndef __EPOOL_MUTEX_TYPE #define __EPOOL_MUTEX_TYPE bool #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ declare_class(pool_t) def_class(pool_t,, __single_list_node_t *ptFreeList; uint_fast16_t tCounter; __EPOOL_MUTEX_TYPE tMutex; void * pTarget; ) end_def_class(pool_t) typedef void pool_item_init_event_handler_t(void *pTarget, void *pItem, uint_fast32_t hwItemSize); /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ bool pool_init(pool_t *ptPool, void *pTarget) { class_internal(ptPool, ptThis, pool_t); if (NULL == ptPool) { return false; } this.ptFreeList = NULL; this.tCounter = 0; this.pTarget = pTarget; return true; } bool pool_add_heap_ex( pool_t *ptPool, void *ptBuffer, uint_fast32_t wPoolSize, uint_fast32_t wItemSize, pool_item_init_event_handler_t *fnHandler) { class_internal(ptPool, ptThis, pool_t); if ((NULL == ptPool) || (NULL == ptBuffer) || (0 == wPoolSize) || (sizeof(void *) > wItemSize) || (wPoolSize < wItemSize)) { return false; } do { __EPOOL_ATOM_ACCESS(){ LIST_STACK_PUSH(this.ptFreeList, ptBuffer); this.tCounter++; } if (NULL != fnHandler) { (*fnHandler)(this.pTarget, ptBuffer, wItemSize); } ptBuffer = (void *)((uint8_t *)ptBuffer + wItemSize); wPoolSize -= wItemSize; } while( wPoolSize >= wItemSize); return true; } bool pool_add_heap( pool_t *ptPool, void *ptBuffer, uint_fast32_t wPoolSize, uint_fast32_t wItemSize) { return pool_add_heap_ex(ptPool, ptBuffer, wPoolSize, wItemSize, NULL); } void *pool_new(pool_t *ptPool) { __single_list_node_t *ptItem = NULL; class_internal(ptPool, ptThis, pool_t); if (NULL == ptPool) { return NULL; } __EPOOL_ATOM_ACCESS(){ do { if (NULL == ((class(pool_t) *)ptPool)->ptFreeList) { break; } LIST_STACK_POP(this.ptFreeList, ptItem); this.tCounter--; } while (false); } return (void *)ptItem; } void pool_free(pool_t *ptPool, void *ptItem) { class_internal(ptPool, ptThis, pool_t); if ((NULL == ptThis) || (NULL == ptItem)) { return; } __EPOOL_ATOM_ACCESS(){ LIST_STACK_PUSH(this.ptFreeList, ptItem); this.tCounter++; } } uint_fast32_t pool_get_item_count(pool_t *ptPool) { uint_fast32_t tCount = 0; class_internal(ptPool, ptThis, pool_t); do { if (NULL == ptThis) { break; } tCount = this.tCounter; } while(false); return tCount; } __EPOOL_MUTEX_TYPE *pool_get_mutex(pool_t *ptPool) { class_internal(ptPool, ptThis, pool_t); if (NULL == ptThis) { return NULL; } return &(this.tMutex); } void *pool_get_target(pool_t *ptPool) { class_internal(ptPool, ptThis, pool_t); assert(ptPool != NULL); return this.pTarget; } /*EOF*/ ================================================ FILE: sources/gmsi/service/memory/epool/epool.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __EPOOL_H__ #define __EPOOL_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ #define END_DEF_EPOOL(__NAME) #define END_EXTERN_EPOOL(__NAME) #ifndef __EPOOL_MUTEX_TYPE #define __EPOOL_MUTEX_TYPE bool #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define EPOOL(__NAME) __NAME##_pool_t #define EPOOL_ITEM(__NAME) __NAME##_pool_item_t #define EPOOL_MUTEX(__NAME, __EPOOL) \ __NAME##_pool_mutex((__EPOOL)) #define EPOOL_INIT(__NAME, __EPOOL) \ __NAME##_pool_init((__EPOOL)) #define EPOOL_ADD_HEAP(__NAME, __EPOOL, __BUFFER, __SIZE) \ __NAME##_pool_add_heap((__EPOOL), (__BUFFER), (__SIZE)) #define EPOOL_FREE(__NAME, __EPOOL, __ITEM) \ __NAME##_pool_free((__EPOOL), (__ITEM)) #define EPOOL_NEW(__NAME, __EPOOL) \ __NAME##_pool_new((__EPOOL)) #define EPOOL_ITEM_COUNT(__NAME, __EPOOL) \ __NAME##_get_pool_item_count((__EPOOL)) #define EXTERN_EPOOL(__NAME, __TYPE) \ declare_class(__NAME##_pool_item_t) \ extern_class(__NAME##_pool_item_t,, \ union { \ inherit(__single_list_node_t) \ __TYPE tMem; \ }; \ ) \ end_extern_class(__NAME##_pool_item_t) \ \ declare_class(__NAME##_pool_t); \ extern_class(__NAME##_pool_t,, \ inherit(pool_t)) \ end_extern_class(__NAME##_pool_t) \ \ extern bool __NAME##_pool_init(__NAME##_pool_t *ptPool); \ extern bool __NAME##_pool_add_heap( \ __NAME##_pool_t *ptPool, void *ptBuffer, uint_fast32_t tSize); \ extern __TYPE *__NAME##_pool_new(__NAME##_pool_t *ptPool); \ extern void __NAME##_pool_free(__NAME##_pool_t *ptPool, __TYPE *ptItem); \ extern uint_fast32_t __NAME##_get_pool_item_count(__NAME##_pool_t *ptPool); \ extern __EPOOL_MUTEX_TYPE *__NAME##_pool_mutex(__NAME##_pool_t *ptPool); #define DEF_EPOOL(__NAME, __TYPE) \ declare_class(__NAME##_pool_item_t) \ def_class(__NAME##_pool_item_t,, \ union { \ inherit(__single_list_node_t) \ __TYPE tMem; \ }; \ ) \ end_def_class(__NAME##_pool_item_t) \ \ declare_class(__NAME##_pool_t) \ def_class(__NAME##_pool_t,, \ inherit(pool_t)) \ end_def_class(__NAME##_pool_t) \ \ bool __NAME##_pool_init(__NAME##_pool_t *ptPool) \ { \ return pool_init((pool_t *)ptPool, NULL); \ } \ \ bool __NAME##_pool_add_heap( \ __NAME##_pool_t *ptPool, void *ptBuffer, uint_fast32_t tSize) \ { \ return pool_add_heap( (pool_t *)ptPool, ptBuffer, \ tSize, sizeof(__NAME##_pool_item_t)); \ } \ \ __TYPE *__NAME##_pool_new(__NAME##_pool_t *ptPool) \ { \ return (__TYPE *)pool_new((pool_t *)ptPool); \ } \ \ void __NAME##_pool_free(__NAME##_pool_t *ptPool, __TYPE *ptItem) \ { \ pool_free((pool_t *)ptPool, (void *)ptItem); \ } \ \ uint_fast32_t __NAME##_get_pool_item_count(__NAME##_pool_t *ptPool) \ { \ return pool_get_item_count((pool_t *)ptPool); \ } \ \ __EPOOL_MUTEX_TYPE *__NAME##_pool_mutex(__NAME##_pool_t *ptPool) \ { \ return pool_get_mutex((pool_t *)ptPool); \ } /*============================ TYPES =========================================*/ declare_class(pool_t) extern_class(pool_t,, __single_list_node_t *ptFreeList; uint_fast32_t tCounter; __EPOOL_MUTEX_TYPE tMutex; void * pTarget; ) end_extern_class(pool_t) typedef void pool_item_init_event_handler_t(void *pTarget, void *pItem, uint_fast32_t hwItemSize); /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ extern bool pool_init(pool_t *ptPool, void *); extern bool pool_add_heap(pool_t *ptPool, void *ptBuffer, uint_fast32_t tPoolSize, uint_fast32_t hwItemSize); extern bool pool_add_heap_ex( pool_t *ptPool, void *ptBuffer, uint_fast32_t hwPoolSize, uint_fast32_t hwItemSize, pool_item_init_event_handler_t *fnHandler); extern void *pool_new(pool_t *ptPool); extern void pool_free(pool_t *ptPool, void *ptItem); extern uint_fast32_t pool_get_item_count(pool_t *ptPool); extern __EPOOL_MUTEX_TYPE *pool_get_mutex(pool_t *ptPool); extern void *pool_get_target(pool_t *ptPool); #endif ================================================ FILE: sources/gmsi/service/memory/memory.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ ================================================ FILE: sources/gmsi/service/memory/memory.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_SERVICE_MEMORY_H__ #define __USE_SERVICE_MEMORY_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\epool\epool.h" #include ".\block\block.h" #include ".\block_queue\block_queue.h" #include ".\stream2block\stream2block.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/service/memory/stream2block/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __STREAM_2_BLOCK_APP_CFG_H__ #define __STREAM_2_BLOCK_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/stream2block/stream2block.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_STREAM_TO_BLOCK == ENABLED #include "..\block_queue\block_queue.h" #include "./stream2block.h" #include /*============================ MACROS ========================================*/ #if USE_SERVICE_BLOCK_QUEUE != ENABLED #error The Stream2Block service requires the Block Queue Service, please set USE_SERVICE_BLOCK_QUEUE to ENABLED in top app_cfg.h #endif #if USE_SERVICE_BLOCK != ENABLED #error The Stream2Block service requires the Block Service, please set USE_SERVICE_BLOCK to ENABLED in top app_cfg.h #endif #ifndef __SB_ATOM_ACCESS # define __SB_ATOM_ACCESS(...) SAFE_ATOM_CODE(__VA_ARGS__) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \note no thread safe queue is required DEF_QUEUE_U8(StreamBufferQueue, uint_fast32_t, bool) END_DEF_QUEUE_U8(StreamBufferQueue) //! \brief stream buffer control block //! @{ declare_class(stream_buffer_t) def_class(stream_buffer_t, which( inherit(block_queue_t) //!< inherit from block_queue_t inherit(QUEUE(StreamBufferQueue)) //!< inherit from queue StreamBufferQueue ), bool bIsOutput; //!< direction bool bIsQueueInitialised; //!< Indicate whether the queue has been inialised or not block_pool_t *ptBlockPool; //!< a reference to outside block pool block_t *ptUsedByQueue; //!< buffer block used by queue block_t *ptUsedByOutside; //!< buffer block lent out stream_buffer_req_event_t *fnRequestSend; //!< callback for triggering the first output transaction stream_buffer_req_event_t *fnRequestReceive; uint8_t chBlockReservedSize; stream_buffer_status_t tStatus; uint8_t chReservedBlock; uint8_t chBlockLimit; uint8_t chBlockCount; ) end_def_class(stream_buffer_t) //! @} /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ private bool stream_buffer_init( stream_buffer_t *ptObj, stream_buffer_cfg_t *ptCFG); private bool stream_read_byte( stream_buffer_t *ptObj, uint8_t *pchData); private bool stream_write_byte( stream_buffer_t *ptObj, uint_fast8_t chData); private int_fast32_t stream_read( stream_buffer_t *ptObj, uint8_t *pchData, int_fast32_t nSize); private int_fast32_t stream_write( stream_buffer_t *ptObj, uint8_t *pchData, int_fast32_t nSize); private block_t *request_next_buffer_block( stream_buffer_t *ptObj, block_t *ptOld); private block_t *get_next_block( stream_buffer_t *ptObj); private void return_block( stream_buffer_t *ptObj, block_t *ptOld); private bool stream_flush( stream_buffer_t *ptObj); private bool stream_write_block( stream_buffer_t *ptObj, block_t *ptBlock); private void __append_block_to_output_list( stream_buffer_t *ptObj, block_t *ptBlock); private stream_buffer_status_t get_status (stream_buffer_t *ptObj); private bool stream_dispose (stream_buffer_t *); /*============================ IMPLEMENTATION ================================*/ /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_stream_buffer_t STREAM_BUFFER = { .Init = &stream_buffer_init, .Status = &get_status, .Dispose = &stream_dispose, .Stream = { .ReadByte = &stream_read_byte, .WriteByte = &stream_write_byte, .Read = &stream_read, .Write = &stream_write, .WriteBlock = &stream_write_block, .Flush = &stream_flush, }, .Block = { .Exchange = &request_next_buffer_block, .GetNext = &get_next_block, .Return = &return_block, }, }; private bool stream_dispose (stream_buffer_t *ptObj) { class_internal(ptObj, ptThis, stream_buffer_t); bool bResult = false; do { if (NULL == ptThis) { break; } do { block_t *ptBlock = BLOCK_QUEUE.Dequeue( ref_obj_as(this, block_queue_t) ); if (NULL == ptBlock) { break; } //! stream is used for output BLOCK.Heap.Free(this.ptBlockPool, ptBlock); } while(true); if (NULL != this.ptUsedByQueue) { //! stream is used for output BLOCK.Heap.Free(this.ptBlockPool, this.ptUsedByQueue); } memset(ptThis, 0, sizeof(stream_buffer_t)); bResult = true; } while(false); return bResult; } private stream_buffer_status_t get_status (stream_buffer_t *ptObj) { class_internal(ptObj, ptThis, stream_buffer_t); stream_buffer_status_t tStatus = {0}; do { if (NULL == ptThis) { break; } tStatus = this.tStatus; } while(false); return tStatus; } private bool stream_buffer_init(stream_buffer_t *ptObj, stream_buffer_cfg_t *ptCFG) { bool bResult = false; do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptObj || NULL == ptCFG) { break; } else if (NULL == ptCFG->ptPool) { break; } __SB_ATOM_ACCESS(){ do { memset(ptObj, 0, sizeof(stream_buffer_t)); this.ptBlockPool = ptCFG->ptPool; this.bIsOutput = (ptCFG->tDirection == OUTPUT_STREAM); this.bIsQueueInitialised = false; this.ptUsedByQueue = NULL; this.ptUsedByOutside = NULL; if (this.bIsOutput) { this.fnRequestSend = ptCFG->fnRequestHandler; } else { this.fnRequestReceive = ptCFG->fnRequestHandler; } this.chReservedBlock = ptCFG->chReservedBlock; this.chBlockReservedSize = ptCFG->chBlockReservedSize; this.chBlockLimit = ptCFG->chBlockLimit; BLOCK_QUEUE.Init(ref_obj_as(this, block_queue_t)); this.tStatus.IsAvailable = true; this.tStatus.IsOutput = this.bIsOutput; this.tStatus.IsBlockBufferDrain = true; bResult = true; } while(false); } } while(false); return bResult; } private block_t *__get_new_block(stream_buffer_t *ptObj) { block_t *ptItem = NULL; class_internal(ptObj, ptThis, stream_buffer_t); if (BLOCK.Heap.Count (this.ptBlockPool) > this.chReservedBlock) { if (this.bIsOutput) { if (0 != this.chBlockLimit) { if (this.chBlockCount < this.chBlockLimit) { //! get a new block ptItem = BLOCK.Heap.New( this.ptBlockPool); if (NULL != ptItem) { this.chBlockCount++; } } } else { ptItem = BLOCK.Heap.New( this.ptBlockPool); if (NULL != ptItem) { this.chBlockCount++; } } } else { ptItem = BLOCK.Heap.New( this.ptBlockPool); } } if (NULL != ptItem) { //reserve block size uint32_t wSize = BLOCK.Size.Get(ptItem); if (this.chBlockReservedSize < wSize) { BLOCK.Size.Set(ptItem, wSize - this.chBlockReservedSize); } } return ptItem; } private block_t *get_next_block(stream_buffer_t *ptObj) { block_t *ptItem = NULL; class_internal(ptObj, ptThis, stream_buffer_t); do { if (NULL == ptThis) { break; } __SB_ATOM_ACCESS(){ if (this.bIsOutput) { //! find the next block from the list ptItem = BLOCK_QUEUE.Dequeue( ref_obj_as(this, block_queue_t)); if (0 == BLOCK_QUEUE.Count(ref_obj_as(this, block_queue_t))) { this.tStatus.IsBlockBufferDrain = true; } if (NULL != ptItem) { this.chBlockCount--; } } else { ptItem = __get_new_block(ptObj); } this.ptUsedByOutside = ptItem; } } while(false); return ptItem; } private void return_block(stream_buffer_t *ptObj, block_t *ptItem) { class_internal(ptObj, ptThis, stream_buffer_t); do { if (NULL == ptThis || NULL == ptItem) { break; } if (this.bIsOutput) { //! reset block size BLOCK.Size.Reset(ptItem); //! stream is used for output BLOCK.Heap.Free(this.ptBlockPool, ptItem); } else { __SB_ATOM_ACCESS(){ //! stream is used for input //! add block to the list BLOCK_QUEUE.Enqueue( ref_obj_as(this, block_queue_t), ptItem); this.tStatus.IsDataAvailable = true; this.tStatus.IsBlockBufferDrain = false; } } } while(false); } private block_t *request_next_buffer_block(stream_buffer_t *ptObj, block_t *ptOld) { block_t *ptItem = NULL; class_internal(ptObj, ptThis, stream_buffer_t); do { if (NULL == ptThis) { break; } if (this.bIsOutput) { if (NULL != ptOld) { //! reset block size BLOCK.Size.Reset(ptOld); //! stream is used for output BLOCK.Heap.Free(this.ptBlockPool, ptOld); } //! find the next block from the list ptItem = BLOCK_QUEUE.Dequeue( ref_obj_as(this, block_queue_t)); __SB_ATOM_ACCESS(){ if (0 == BLOCK_QUEUE.Count(ref_obj_as(this, block_queue_t))) { this.tStatus.IsBlockBufferDrain = true; } if (NULL != ptItem) { this.chBlockCount--; } this.ptUsedByOutside = ptItem; } } else { __SB_ATOM_ACCESS(){ if (NULL != ptOld) { /*if (BLOCK.Size.Get(ptOld) < BLOCK.Size.Capability(ptOld)) { NOP(); }*/ //! stream is used for input //! add block to the list BLOCK_QUEUE.Enqueue( ref_obj_as(this, block_queue_t), ptOld); this.tStatus.IsDataAvailable = true; this.tStatus.IsBlockBufferDrain = false; } ptItem = __get_new_block(ptObj); this.ptUsedByOutside = ptItem; } } } while(false); return ptItem; } private bool queue_init(stream_buffer_t *ptObj, bool bIsStreamForRead) { class_internal(ptObj, ptThis, stream_buffer_t); block_t *ptBlock; if (bIsStreamForRead) { if (NULL != this.ptUsedByQueue) { BLOCK.Size.Reset(this.ptUsedByQueue); BLOCK.Heap.Free( this.ptBlockPool, this.ptUsedByQueue); } __SB_ATOM_ACCESS (){ //! fetch a block from list, and initialise it as a full queue ptBlock = BLOCK_QUEUE.Dequeue( ref_obj_as(this, block_queue_t) ); if (NULL == ptBlock) { this.tStatus.IsDataAvailable = false; } if (0 == BLOCK_QUEUE.Count(ref_obj_as(this, block_queue_t))) { this.tStatus.IsBlockBufferDrain = true; } } if ( NULL == this.ptUsedByOutside) { if (NULL != this.fnRequestReceive) { (*this.fnRequestReceive)(ptObj); } } } else { //! add buffer to block list ( which is used as output list) do { if (NULL == this.ptUsedByQueue) { break; } //! use queue count as actual size BLOCK.Size.Set( this.ptUsedByQueue, GET_QUEUE_COUNT( StreamBufferQueue, REF_OBJ_AS(this, QUEUE(StreamBufferQueue)))); __append_block_to_output_list(ptObj, this.ptUsedByQueue); } while(false); ptBlock = __get_new_block(ptObj); } this.ptUsedByQueue = (block_t *)ptBlock; if (NULL == ptBlock) { //! queue is empty return false; } QUEUE_INIT_EX( StreamBufferQueue, //!< queue name REF_OBJ_AS(this, QUEUE(StreamBufferQueue)), //!< queue obj (uint8_t *)(BLOCK.Buffer.Get(ptBlock)), //!< buffer BLOCK.Size.Get(ptBlock), //!< buffer size bIsStreamForRead); //!< intialize method (initialise as full or initialise as empty) this.bIsQueueInitialised = true; return true; } private bool stream_flush(stream_buffer_t *ptObj) { class_internal(ptObj, ptThis, stream_buffer_t); bool bResult = false; do { if (NULL == ptThis) { break ; } if (this.bIsOutput) { if (this.bIsQueueInitialised) { if (0 != GET_QUEUE_COUNT(StreamBufferQueue, REF_OBJ_AS(this, QUEUE(StreamBufferQueue)))) { //! queue is not empty if (!queue_init(ptObj, false)) { this.bIsQueueInitialised = false; } } } bResult = ( NULL == TYPE_CONVERT( &(this.ptUsedByOutside), block_t * volatile)); } else { bResult = true; } } while(false); return bResult; } private bool stream_read_byte(stream_buffer_t *ptObj, uint8_t *pchData) { do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptThis || NULL == pchData) { break; } else if (this.bIsOutput) { break; } do { if (!this.bIsQueueInitialised) { if (!queue_init(ptObj, true)) { //! queue is empty return false; } } if (!DEQUEUE( StreamBufferQueue, REF_OBJ_AS(this, QUEUE(StreamBufferQueue)), pchData)) { this.bIsQueueInitialised = false; } else { return true; } } while(true); } while(false); return false; } private int_fast32_t stream_read( stream_buffer_t *ptObj, uint8_t *pchData, int_fast32_t nSize) { int_fast32_t nResult = -1; do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptThis || NULL == pchData || 0 == nSize) { break; } else if (this.bIsOutput) { break; } do { if (!this.bIsQueueInitialised) { if (!queue_init(ptObj, true)) { //! queue is empty break; } } nResult = DEQUEUE_BLOCK( StreamBufferQueue, REF_OBJ_AS( this, QUEUE(StreamBufferQueue)), pchData, nSize); if (nResult < 0) { this.bIsQueueInitialised = false; } else { break; } } while(true); } while(false); return nResult; } private int_fast32_t stream_write( stream_buffer_t *ptObj, uint8_t *pchData, int_fast32_t nSize) { int_fast32_t nResult = -1; do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptThis || NULL == pchData || 0 == nSize) { break; } else if (!this.bIsOutput) { break; } do { if (!this.bIsQueueInitialised) { if (!queue_init(ptObj, false)) { //! queue is empty break; } } nResult = ENQUEUE_BLOCK( StreamBufferQueue, REF_OBJ_AS( this, QUEUE(StreamBufferQueue)), pchData, nSize); if (nResult < 0) { this.bIsQueueInitialised = false; } else { break; } } while(true); } while(false); return nResult; } private bool stream_write_byte(stream_buffer_t *ptObj, uint_fast8_t chData) { do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptObj) { break; } else if (!this.bIsOutput) { break; } do { if (!this.bIsQueueInitialised) { if (!queue_init(ptObj, false)) { //! queue is empty return false; } } if (!ENQUEUE( StreamBufferQueue, REF_OBJ_AS(this, QUEUE(StreamBufferQueue)), chData)) { this.bIsQueueInitialised = false; } else { return true; } } while(true); } while(false); return false; } private void __append_block_to_output_list( stream_buffer_t *ptObj, block_t *ptBlock) { class_internal(ptObj, ptThis, stream_buffer_t); __SB_ATOM_ACCESS(){ BLOCK_QUEUE.Enqueue( ref_obj_as(this, block_queue_t), ptBlock); this.tStatus.IsBlockBufferDrain = false; } if (NULL == this.ptUsedByOutside ) { //! this is no transaction, we need to trigger one if (NULL != this.fnRequestSend) { (*this.fnRequestSend)(ptObj); } } } private bool stream_write_block(stream_buffer_t *ptObj, block_t *ptBlock) { do { class_internal(ptObj, ptThis, stream_buffer_t); if (NULL == ptThis || NULL == ptBlock) { break; } else if (!this.bIsOutput) { break; } //! write current block used by queue to output list do { if (0 == GET_QUEUE_COUNT(StreamBufferQueue, REF_OBJ_AS(this, QUEUE(StreamBufferQueue)))) { break; } if (!queue_init(ptObj, false)) { //! queue is empty this.bIsQueueInitialised = false; } } while(true); __append_block_to_output_list(ptObj, ptBlock); return true; } while(false); return false; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/memory/stream2block/stream2block.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __STREAM_2_BLOCK_H__ #define __STREAM_2_BLOCK_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_STREAM_TO_BLOCK == ENABLED #include "..\block_queue\block_queue.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #define STREAM_BUFFER_CFG(__ADDR, ...) \ do { \ stream_buffer_cfg_t tCFG = { \ __VA_ARGS__ \ }; \ \ STREAM_BUFFER.Init((__ADDR), &tCFG); \ } while(false) /*----------------------------------------------------------------------------* * common template * *----------------------------------------------------------------------------*/ #define __STREAM_BUFFER_COMMON(__NAME, __BLOCK_SIZE) \ declare_class( __NAME##_stream_buffer_block_t ) \ def_class(__NAME##_stream_buffer_block_t, which(inherit(block_t)), \ uint8_t chBuffer[__BLOCK_SIZE];) \ end_def_class(__NAME##_stream_buffer_block_t) \ extern_class(__NAME##_stream_buffer_block_t, which(inherit(block_t)), \ uint8_t chBuffer[__BLOCK_SIZE];) \ end_extern_class(__NAME##_stream_buffer_block_t) \ NO_INIT private stream_buffer_t s_t##__NAME##StreamBuffer; \ NO_INIT private block_pool_t s_t##__NAME##_BlockPool; \ \ private bool __NAME##_stream_buffer_init(stream_buffer_cfg_t *ptCFG) \ { \ BLOCK.Heap.Init(&s_t##__NAME##_BlockPool, NULL); \ return STREAM_BUFFER.Init(&s_t##__NAME##StreamBuffer, ptCFG); \ } \ private bool __NAME##_stream_add_buffer(void *pBuffer, uint_fast32_t wSize)\ { \ return BLOCK.Heap.Add(&s_t##__NAME##_BlockPool, \ pBuffer, wSize, sizeof(__NAME##_stream_buffer_block_t)); \ } \ private __NAME##_stream_buffer_block_t * __NAME##_stream_exchange_block( \ __NAME##_stream_buffer_block_t *ptOld) \ { \ return (__NAME##_stream_buffer_block_t *)STREAM_BUFFER.Block.Exchange( \ &s_t##__NAME##StreamBuffer, ref_obj_as((*ptOld), block_t)); \ } \ private __NAME##_stream_buffer_block_t *__NAME##_stream_get_next_block(void)\ { \ return (__NAME##_stream_buffer_block_t *)STREAM_BUFFER.Block.GetNext( \ &s_t##__NAME##StreamBuffer); \ } \ private void __NAME##_stream_return_block( \ __NAME##_stream_buffer_block_t *ptOld) \ { \ STREAM_BUFFER.Block.Return( \ &s_t##__NAME##StreamBuffer, ref_obj_as((*ptOld), block_t)); \ } \ #define __EXTERN_STREAM_BUFFER_COMMON(__NAME, __BLOCK_SIZE) \ declare_class( __NAME##_stream_buffer_block_t ) \ extern_class(__NAME##_stream_buffer_block_t, which(inherit(block_t)), \ uint8_t chBuffer[__BLOCK_SIZE];) \ end_extern_class(__NAME##_stream_buffer_block_t) /*----------------------------------------------------------------------------* * Output stream template * *----------------------------------------------------------------------------*/ #define OUTPUT_STREAM_BUFFER_CFG(__NAME, ...) \ do { \ stream_buffer_cfg_t tCFG = { \ .ptPool = &s_t##__NAME##_BlockPool, \ .tDirection = OUTPUT_STREAM, \ __VA_ARGS__ \ }; \ __NAME.Init(&tCFG); \ } while(false) #define __OUTPUT_STREAM_BUFFER_COMMON(__NAME) \ const struct { \ \ bool (*Init)(stream_buffer_cfg_t *); \ bool (*AddBuffer)(void *, uint_fast32_t ); \ \ struct { \ bool (*WriteByte)(uint_fast8_t); \ int_fast32_t (*Write)(uint8_t *, int_fast32_t ); \ bool (*Flush)(void); \ } Stream; \ \ struct { \ __NAME##_stream_buffer_block_t *(*Exchange) \ ( __NAME##_stream_buffer_block_t * ); \ __NAME##_stream_buffer_block_t *(*GetNext) (void); \ void (*Return) (__NAME##_stream_buffer_block_t *); \ } Block; \ \ } __NAME #define __DEF_OUTPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __STREAM_BUFFER_COMMON(__NAME, (__BLOCK_SIZE)) \ private bool __NAME##_stream_write_byte(uint_fast8_t chData) \ { \ return STREAM_BUFFER.Stream.WriteByte( \ &s_t##__NAME##StreamBuffer, chData); \ } \ private int_fast32_t __NAME##_stream_write(uint8_t *pchSrc, int_fast32_t nSize)\ { \ return STREAM_BUFFER.Stream.Write( &s_t##__NAME##StreamBuffer, \ pchSrc, \ nSize); \ } \ private bool __NAME##_stream_flush(void) \ { \ return STREAM_BUFFER.Stream.Flush(&s_t##__NAME##StreamBuffer); \ } \ __OUTPUT_STREAM_BUFFER_COMMON(__NAME) = { \ .Init = &__NAME##_stream_buffer_init, \ .AddBuffer = &__NAME##_stream_add_buffer, \ .Stream = { \ .WriteByte = &__NAME##_stream_write_byte, \ .Write = &__NAME##_stream_write, \ .Flush = &__NAME##_stream_flush, \ }, \ .Block = { \ .Exchange = &__NAME##_stream_exchange_block, \ .GetNext = &__NAME##_stream_get_next_block, \ .Return = &__NAME##_stream_return_block, \ }, \ }; #define DEF_OUTPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __DEF_OUTPUT_STREAM_BUFFER(__NAME, (__BLOCK_SIZE)) #define END_DEF_OUTPUT_STREAM_BUFFER(__NAME) #define __EXTERN_OUTPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __EXTERN_STREAM_BUFFER_COMMON(__NAME, (__BLOCK_SIZE)) \ extern __OUTPUT_STREAM_BUFFER_COMMON(__NAME); #define EXTERN_OUTPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __EXTERN_OUTPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) #define END_EXTERN_OUTPUT_STREAM_BUFFER(__NAME) /*----------------------------------------------------------------------------* * Output stream seraial port adapter template * *----------------------------------------------------------------------------*/ #define __EXTERN_STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME) \ extern void __NAME##_insert_serial_port_tx_cpl_event_handler(void); \ extern void __NAME##_output_stream_adapter_init(void); #define EXTERN_STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME) \ __EXTERN_STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME) #define __STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME, __BLOCK_COUNT) \ extern void __NAME##_serial_port_enable_tx_cpl_interrupt(void); \ extern void __NAME##_serial_port_disbale_tx_cpl_interrupt(void); \ extern void __NAME##_serial_port_fill_byte(uint8_t chByte); \ \ NO_INIT private volatile struct { \ __NAME##_stream_buffer_block_t *ptBlock; \ uint8_t *pchBuffer; \ uint16_t hwSize; \ uint16_t hwIndex; \ } s_t##__NAME##StreamOutService; \ private void __NAME##_request_send(void) \ { \ s_t##__NAME##StreamOutService.ptBlock = __NAME.Block.Exchange( \ s_t##__NAME##StreamOutService.ptBlock); \ __NAME##_stream_buffer_block_t *ptBlock = \ s_t##__NAME##StreamOutService.ptBlock; \ if (NULL != ptBlock) { \ s_t##__NAME##StreamOutService.pchBuffer = \ (uint8_t *)BLOCK.Buffer.Get(ref_obj_as((*ptBlock), block_t)); \ s_t##__NAME##StreamOutService.hwSize = \ BLOCK.Size.Get(ref_obj_as((*ptBlock), block_t)); \ s_t##__NAME##StreamOutService.hwIndex = 0; \ \ __IRQ_SAFE { \ __NAME##_serial_port_enable_tx_cpl_interrupt(); \ \ __NAME##_serial_port_fill_byte( \ s_t##__NAME##StreamOutService.pchBuffer \ [s_t##__NAME##StreamOutService.hwIndex++]); \ } \ } \ } \ void __NAME##_insert_serial_port_tx_cpl_event_handler(void) \ { \ if ( (NULL == s_t##__NAME##StreamOutService.pchBuffer) \ || (0 == s_t##__NAME##StreamOutService.hwSize)) { \ /* it appears output service is cancelled */ \ __NAME##_serial_port_disbale_tx_cpl_interrupt(); \ return ; \ } \ \ if ( s_t##__NAME##StreamOutService.hwIndex \ >= s_t##__NAME##StreamOutService.hwSize) { \ __NAME##_serial_port_disbale_tx_cpl_interrupt(); \ __NAME##_request_send(); \ } else { \ __NAME##_serial_port_fill_byte( \ s_t##__NAME##StreamOutService.pchBuffer[ \ s_t##__NAME##StreamOutService.hwIndex++]); \ } \ } \ private void __NAME##_output_stream_req_send_event_handler( \ stream_buffer_t *ptObj) \ { \ if (NULL == ptObj) { \ return ; \ } \ \ __NAME##_request_send(); \ } \ void __NAME##_output_stream_adapter_init(void) \ { \ NO_INIT private __NAME##_stream_buffer_block_t \ s_tBlocks[__BLOCK_COUNT]; \ OUTPUT_STREAM_BUFFER_CFG( \ __NAME, \ &__NAME##_output_stream_req_send_event_handler \ ); \ \ __NAME.AddBuffer(s_tBlocks, sizeof(s_tBlocks)); \ memset((void *)&s_t##__NAME##StreamOutService, 0, \ sizeof(s_t##__NAME##StreamOutService)); \ } #define STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME, __BLOCK_COUNT) \ __STREAM_OUT_SERIAL_PORT_ADAPTER(__NAME, (__BLOCK_COUNT)) /*----------------------------------------------------------------------------* * Input stream template * *----------------------------------------------------------------------------*/ #define INPUT_STREAM_BUFFER_CFG(__NAME, ...) \ do { \ stream_buffer_cfg_t tCFG = { \ .ptPool = &s_t##__NAME##_BlockPool, \ .tDirection = INPUT_STREAM, \ __VA_ARGS__ \ }; \ __NAME.Init(&tCFG); \ } while(false) #define __INPUT_STREAM_BUFFER_COMMON(__NAME) \ const struct { \ \ bool (*Init)(stream_buffer_cfg_t *); \ bool (*AddBuffer)(void *, uint_fast32_t ); \ \ struct { \ bool (*ReadByte)(uint8_t *); \ int_fast32_t (*Read)(uint8_t *, int_fast32_t ); \ } Stream; \ \ struct { \ __NAME##_stream_buffer_block_t *(*Exchange) \ ( __NAME##_stream_buffer_block_t * ); \ __NAME##_stream_buffer_block_t *(*GetNext) (void); \ void (*Return) (__NAME##_stream_buffer_block_t *); \ } Block; \ \ } __NAME #define __DEF_INPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __STREAM_BUFFER_COMMON(__NAME, (__BLOCK_SIZE)) \ private bool __NAME##_stream_read_byte(uint8_t *pchData) \ { \ return STREAM_BUFFER.Stream.ReadByte( \ &s_t##__NAME##StreamBuffer, pchData); \ } \ private int_fast32_t __NAME##_stream_read(uint8_t *pchSrc, int_fast32_t nSize)\ { \ return STREAM_BUFFER.Stream.Read( &s_t##__NAME##StreamBuffer, \ pchSrc, \ nSize); \ } \ __INPUT_STREAM_BUFFER_COMMON(__NAME) = { \ .Init = &__NAME##_stream_buffer_init, \ .AddBuffer = &__NAME##_stream_add_buffer, \ .Stream = { \ .ReadByte = &__NAME##_stream_read_byte, \ .Read = &__NAME##_stream_read, \ }, \ .Block = { \ .Exchange = &__NAME##_stream_exchange_block, \ .GetNext = &__NAME##_stream_get_next_block, \ .Return = &__NAME##_stream_return_block, \ }, \ }; #define DEF_INPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __DEF_INPUT_STREAM_BUFFER(__NAME, (__BLOCK_SIZE)) #define END_DEF_INPUT_STREAM_BUFFER(__NAME) #define __EXTERN_INPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __EXTERN_STREAM_BUFFER_COMMON(__NAME, (__BLOCK_SIZE)) \ extern __INPUT_STREAM_BUFFER_COMMON(__NAME); #define EXTERN_INPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) \ __EXTERN_INPUT_STREAM_BUFFER(__NAME, __BLOCK_SIZE) #define END_EXTERN_INPUT_STREAM_BUFFER(__NAME) /*----------------------------------------------------------------------------* * Input stream seraial port adapter template * *----------------------------------------------------------------------------*/ #define __EXTERN_STREAM_IN_SERIAL_PORT_ADAPTER(__NAME) \ extern void __NAME##_1ms_event_handler(void); \ extern void __NAME##_insert_serial_port_rx_cpl_event_handler(void); \ extern void __NAME##_input_stream_adapter_init(void); #define EXTERN_STREAM_IN_SERIAL_PORT_ADAPTER(__NAME) \ __EXTERN_STREAM_IN_SERIAL_PORT_ADAPTER(__NAME) #define __STREAM_IN_SERIAL_PORT_ADAPTER(__NAME, __BLOCK_COUNT) \ extern void __NAME##_serial_port_enable_rx_cpl_interrupt(void); \ extern void __NAME##_serial_port_disable_rx_cpl_interrupt(void); \ extern uint8_t __NAME##_serial_port_get_byte(void); \ NO_INIT private volatile struct { \ __NAME##_stream_buffer_block_t *ptBlock; \ uint8_t *pchBuffer; \ uint_fast16_t hwSize; \ uint_fast16_t hwIndex; \ uint_fast16_t hwTimeoutCounter; \ } s_t##__NAME##StreamInService; \ private void __NAME##_request_read(void) \ { \ s_t##__NAME##StreamInService.ptBlock = \ __NAME.Block.Exchange( \ s_t##__NAME##StreamInService.ptBlock); \ __NAME##_stream_buffer_block_t *ptReadBuffer = \ s_t##__NAME##StreamInService.ptBlock; \ if (NULL != ptReadBuffer) { \ if (0 == BLOCK.Size.Get(ref_obj_as(*ptReadBuffer, block_t))) { \ return ; \ } \ s_t##__NAME##StreamInService.pchBuffer = \ BLOCK.Buffer.Get(ref_obj_as(*ptReadBuffer, block_t)); \ s_t##__NAME##StreamInService.hwSize = \ BLOCK.Size.Get(ref_obj_as(*ptReadBuffer, block_t)); \ s_t##__NAME##StreamInService.hwIndex = 0; \ __NAME##_serial_port_enable_rx_cpl_interrupt(); \ } \ } \ void __NAME##_1ms_event_handler(void) \ { \ if (s_t##__NAME##StreamInService.hwTimeoutCounter) { \ s_t##__NAME##StreamInService.hwTimeoutCounter--; \ if (0 == s_t##__NAME##StreamInService.hwTimeoutCounter) { \ /*! timeout! */ \ if (0 != s_t##__NAME##StreamInService.hwIndex) { \ BLOCK.Size.Set( \ ref_obj_as(*s_t##__NAME##StreamInService.ptBlock, block_t), \ s_t##__NAME##StreamInService.hwIndex); \ __NAME##_request_read(); \ } \ } \ } \ } \ private void __NAME##_reset_stream_in_rx_timer(void) \ { \ SAFE_ATOM_CODE (){ \ s_t##__NAME##StreamInService.hwTimeoutCounter = \ STREAM_IN_RCV_TIMEOUT; \ } \ } \ private void __NAME##_input_stream_req_read_event_handler( \ stream_buffer_t *ptObj) \ { \ if (NULL == ptObj) { \ return ; \ } \ \ __NAME##_request_read(); \ } \ void __NAME##_insert_serial_port_rx_cpl_event_handler(void) \ { \ __NAME##_reset_stream_in_rx_timer(); \ \ if ( (NULL == s_t##__NAME##StreamInService.pchBuffer) \ || (0 == s_t##__NAME##StreamInService.hwSize)) { \ /* it appears receive service is cancelled */ \ __NAME##_serial_port_disable_rx_cpl_interrupt(); \ return ; \ } \ \ s_t##__NAME##StreamInService.pchBuffer \ [s_t##__NAME##StreamInService.hwIndex++] = \ __NAME##_serial_port_get_byte(); \ if ( s_t##__NAME##StreamInService.hwIndex \ >= s_t##__NAME##StreamInService.hwSize) { \ __NAME##_serial_port_disable_rx_cpl_interrupt(); \ __NAME##_request_read(); \ } \ } \ void __NAME##_input_stream_adapter_init(void) \ { \ NO_INIT private __NAME##_stream_buffer_block_t \ s_tBlocks[__BLOCK_COUNT]; \ INPUT_STREAM_BUFFER_CFG( \ __NAME, \ &__NAME##_input_stream_req_read_event_handler \ ); \ \ __NAME.AddBuffer(s_tBlocks, sizeof(s_tBlocks)); \ memset((void *)&s_t##__NAME##StreamInService, 0, \ sizeof(s_t##__NAME##StreamInService)); \ } #define STREAM_IN_SERIAL_PORT_ADAPTER(__NAME, __BLOCK_COUNT) \ __STREAM_IN_SERIAL_PORT_ADAPTER(__NAME, (__BLOCK_COUNT)) /*============================ TYPES =========================================*/ //! \note no thread safe queue is required EXTERN_QUEUE_U8(StreamBufferQueue, uint_fast32_t, bool) END_EXTERN_QUEUE_U8(StreamBufferQueue) //! \brief stream buffer control block //! @{ declare_class(stream_buffer_t) typedef void stream_buffer_req_event_t(stream_buffer_t *ptThis); typedef union { struct { uint8_t IsAvailable :1; uint8_t IsOutput :1; uint8_t IsDataAvailable :1; uint8_t IsBlockBufferDrain :1; uint8_t :4; }; uint8_t tValue; } stream_buffer_status_t; extern_class(stream_buffer_t, which( inherit(block_queue_t) //!< inherit from block_queue_t inherit(QUEUE(StreamBufferQueue)) //!< inherit from queue StreamBufferQueue ), bool bIsOutput; //!< direction bool bIsQueueInitialised; //!< Indicate whether the queue has been inialised or not block_pool_t *ptBlockPool; //!< a reference to outside block pool block_t *ptUsedByQueue; //!< buffer block used by queue block_t *ptUsedByOutside; //!< buffer block lent out stream_buffer_req_event_t *fnRequestSend; //!< callback for triggering the first output transaction stream_buffer_req_event_t *fnRequestReceive; uint8_t chBlockReservedSize; stream_buffer_status_t tStatus; uint8_t chReservedBlock; uint8_t chBlockLimit; uint8_t chBlockCount; ) end_extern_class(stream_buffer_t) //! @} typedef struct { block_pool_t *ptPool; enum { INPUT_STREAM = 0, OUTPUT_STREAM } tDirection; stream_buffer_req_event_t *fnRequestHandler; uint_fast8_t chBlockReservedSize; uint_fast8_t chReservedBlock; uint8_t chBlockLimit; }stream_buffer_cfg_t; def_interface(i_stream_buffer_t) bool (*Init) (stream_buffer_t *, stream_buffer_cfg_t *); stream_buffer_status_t (*Status) (stream_buffer_t *); bool (*Dispose) (stream_buffer_t *); struct { bool (*ReadByte) (stream_buffer_t *, uint8_t *); bool (*WriteByte) (stream_buffer_t *, uint_fast8_t); int_fast32_t (*Read) (stream_buffer_t *, uint8_t *, int_fast32_t ); int_fast32_t (*Write) (stream_buffer_t *, uint8_t *, int_fast32_t ); bool (*WriteBlock) (stream_buffer_t *, block_t *ptBlock); bool (*Flush) (stream_buffer_t *ptObj); } Stream; struct { block_t* (*Exchange) (stream_buffer_t *, block_t *); block_t* (*GetNext) (stream_buffer_t *); void (*Return) (stream_buffer_t *, block_t *); } Block; end_def_interface(i_stream_buffer_t) /*============================ GLOBAL VARIABLES ==============================*/ extern const i_stream_buffer_t STREAM_BUFFER; /*============================ PROTOTYPES ====================================*/ #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __SCHEDULER_APPLICATION_CONFIGURATION_H__ #define __SCHEDULER_APPLICATION_CONFIGURATION_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/scheduler.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\task.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ //! \brief task queue pool size #ifndef SAFE_TASK_QUEUE_POOL_SIZE # define SAFE_TASK_QUEUE_POOL_SIZE (1u) # warning No defined SAFE_TASK_QUEUE_POOL_SIZE, use default value 1u. #endif //! \brief task pool size #ifndef SAFE_TASK_POOL_SIZE # define SAFE_TASK_POOL_SIZE (4u) # warning No defined SAFE_TASK_POOL_SIZE, use default value 4u. #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name task queue control block //! @{ typedef volatile struct __safe_task_queue SAFE_TASK_QUEUE; struct __safe_task_queue { safe_task_t * pHead; //!< queue head safe_task_t * pTail; //!< queue tail #if SAFE_TASK_QUEUE_POOL_SIZE > 1 uint8_t chBit; SAFE_TASK_QUEUE *ptNext; #endif }; //! @} #if SAFE_TASK_QUEUE_POOL_SIZE > 1 #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #endif //! \brief free task queue list //! @{ NO_INIT struct { SAFE_TASK_QUEUE *ptQHead; SAFE_TASK_QUEUE *ptQTail; } s_tFreeTaskQueueList; //! @} #endif //! \name co-operation scheduler interface //! @{ DEF_INTERFACE(scheduler_t) void (*Init)(void); //void (*Finish)(void); bool (*HeapInit)(void *, uint16_t); #if SAFE_TASK_CALL_STACK == ENABLED void *(*NewTask)(safe_task_func_t *, void *, volatile safe_call_stack_item_t *, uint8_t ); #else void *(*NewTask)( safe_task_func_t *, void * ); #endif bool (*Scheduler)( void ); bool (*Call)( void *, safe_task_func_t * , void * , bool); bool (*CallEx)( void *, safe_task_func_t *, void *, safe_task_func_t *, void *, bool ); #if SAFE_TASK_THREAD_SYNC == ENABLED event_t *(*CreateEvent)(event_t *, bool , bool ); void (*SetEvent)(event_t *); void (*ResetEvent)(event_t *); bool (*WaitForSingleObject)(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED void (*LeaveCriticalSection)(critical_section_t *); # endif #endif END_DEF_INTERFACE(scheduler_t) //! @} #endif #if TASK_SCHEDULER == ENABLED /*============================ PROTOTYPES ====================================*/ static bool _register_task( safe_task_t *pTask ); extern void scheduler_init( void ); extern void scheduler_finish( void ); extern bool task_pool_init(void *pHeap, uint16_t hwSize); #if SAFE_TASK_CALL_STACK == ENABLED extern void *register_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ); #else extern void *register_task( safe_task_func_t *fnRoutine, void *pArg ); #endif extern bool scheduler( void ); extern bool call_task( void *pT, safe_task_func_t *fnRoutine , void *pArg , bool bSubcall); extern bool call_task_ex( void *pT, safe_task_func_t *fnRoutine, void *pArg, safe_task_func_t *fnReturnRoutine, void *pReturnArg, bool bSubcall ) ; #if SAFE_TASK_THREAD_SYNC == ENABLED extern event_t *create_event(event_t *, bool bManualReset, bool bInitialState); extern void set_event(event_t *); extern void reset_event(event_t *); extern bool wait_for_single_object(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED extern void leave_critical_section(critical_section_t *); # endif #endif /*============================ GLOBAL VARIABLES ==============================*/ #endif #if TASK_SCHEDULER == ENABLED #if defined(LIB_GENERATION) ROOT #endif SECTION(".api_table") //! \brief ES-scheduler const scheduler_t SCHEDULER = { &scheduler_init, //!< initialize //&scheduler_finish, //!< finish &task_pool_init, //!< add task heap ®ister_task, //!< register task &scheduler, //!< scheduler &call_task, //!< call task &call_task_ex, //!< call task extended version #if SAFE_TASK_THREAD_SYNC == ENABLED &create_event, //!< create event &set_event, //!< set event &reset_event, //!< reset event &wait_for_single_object, //!< wait for single object # if SAFE_TASK_CRITICAL_SECTION == ENABLED &leave_critical_section //!< leave critical section # endif #endif }; #endif #if TASK_SCHEDULER == ENABLED /*============================ LOCAL VARIABLES ===============================*/ #if SAFE_TASK_POOL_SIZE > 0 //! \brief task pool #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #else # if __IS_COMPILER_IAR__ # pragma location = ".app_ram_noinit" # endif #endif NO_INIT static safe_task_t s_TaskPool[SAFE_TASK_POOL_SIZE]; #endif #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #else # if __IS_COMPILER_IAR__ # pragma location = ".app_ram_noinit" # endif #endif //! \brief task queue pool NO_INIT static SAFE_TASK_QUEUE s_TaskQueuePool[SAFE_TASK_QUEUE_POOL_SIZE]; //! \brief task locker #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #endif NO_INIT volatile locker_t s_SchedulerLocker; #if SAFE_TASK_QUEUE_POOL_SIZE > 1 #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #endif NO_INIT static uint8_t s_chIdleFlag; #endif /*============================ IMPLEMENTATION ================================*/ #if SAFE_TASK_QUEUE_POOL_SIZE > 1 #if __IS_COMPILER_IAR__ # pragma optimize=no_size_constraints #endif static void free_task_queue(SAFE_TASK_QUEUE *ptQueue) { /* LOCK( s_SchedulerLocker, ptQueue->ptNext = NULL; if (NULL == s_tFreeTaskQueueList.ptQTail) { s_tFreeTaskQueueList.ptQHead = ptQueue; } else { s_tFreeTaskQueueList.ptQTail->ptNext = ptQueue; } s_tFreeTaskQueueList.ptQTail = ptQueue; ) */ SAFE_ATOM_CODE( ptQueue->ptNext = NULL; if (NULL == s_tFreeTaskQueueList.ptQTail) { s_tFreeTaskQueueList.ptQHead = ptQueue; } else { s_tFreeTaskQueueList.ptQTail->ptNext = ptQueue; } s_tFreeTaskQueueList.ptQTail = ptQueue; ) } #if __IS_COMPILER_IAR__ # pragma optimize=no_size_constraints #endif static SAFE_TASK_QUEUE *get_free_task_queue(void) { SAFE_TASK_QUEUE *ptQueue; /* LOCK( s_SchedulerLocker, ptQueue = s_tFreeTaskQueueList.ptQHead; if (NULL != ptQueue) { s_tFreeTaskQueueList.ptQHead = ptQueue->ptNext; if (NULL == s_tFreeTaskQueueList.ptQHead) { //! it is the last item. s_tFreeTaskQueueList.ptQTail = s_tFreeTaskQueueList.ptQHead; } ptQueue->ptNext = NULL; } ) */ SAFE_ATOM_CODE( ptQueue = s_tFreeTaskQueueList.ptQHead; if (NULL != ptQueue) { s_tFreeTaskQueueList.ptQHead = ptQueue->ptNext; if (NULL == s_tFreeTaskQueueList.ptQHead) { //! it is the last item. s_tFreeTaskQueueList.ptQTail = s_tFreeTaskQueueList.ptQHead; } ptQueue->ptNext = NULL; } ) return ptQueue; } #endif /*! \brief add a task control block to a specified task control queue * \param pTaskQueue a pointer of a task queue control block * \param pTask a pointer of a task control block * \retval false failed to add task to queue * \retval true succeeded in adding task to queue */ static bool add_task_to_queue( SAFE_TASK_QUEUE *pTaskQueue, safe_task_t *pTask ) { #if 0 if ((NULL == pTaskQueue) || (NULL == pTask)) { return false; } #endif pTask->pNext = NULL; if (NULL == pTaskQueue->pTail) { pTaskQueue->pHead = pTask; //!< update task head #if SAFE_TASK_QUEUE_POOL_SIZE > 1 LOCK( s_SchedulerLocker, s_chIdleFlag |= _BV(pTaskQueue->chBit); ) #endif } else { pTaskQueue->pTail->pNext = pTask; //!< add a new task to tail } pTaskQueue->pTail = pTask; //!< add a new task to queue return true; } /*! \brief get a task control block from a specified task control queue * \param pTaskQueue a pointer of a task queue control block * \param pTask a pointer of a task control block * \retval NULL failed to get a task from queue * \retval true succeeded in adding task to queue */ static safe_task_t *get_task_from_queue(SAFE_TASK_QUEUE *pTaskQueue) { safe_task_t *pTask = pTaskQueue->pHead; if (NULL != pTask) { /* update queue */ pTaskQueue->pHead = pTask->pNext; /* check whether queue is empty */ if (NULL == pTaskQueue->pHead) { pTaskQueue->pTail = NULL; //! update tail #if SAFE_TASK_QUEUE_POOL_SIZE > 1 LOCK( s_SchedulerLocker, s_chIdleFlag &= ~_BV(pTaskQueue->chBit); ) #endif } } return pTask; } #if __IS_COMPILER_IAR__ # pragma optimize=no_size_constraints #endif /*! \brief scheduler function * \retval true system is busy * \retval false system is idle */ bool scheduler( void ) { #if SAFE_TASK_QUEUE_POOL_SIZE > 1 bool bResult = true; do { #if SAFE_TASK_CALL_STACK == ENABLED volatile class(safe_call_stack_item_t) *ptRoutine; #endif SAFE_TASK_QUEUE *ptQueue = get_free_task_queue(); if (NULL == ptQueue) { //! no free task queue break; } do { safe_task_t *pTask = get_task_from_queue(ptQueue); free_task_queue(ptQueue); if (NULL == pTask) { break; } pTask->bStateChanged = false; #if SAFE_TASK_CALL_STACK == ENABLED ptRoutine = pTask->pStack; /*if (NULL != ptRoutine->fnRoutine)*/ { /* run task routine */ fsm_rt_t tState = ptRoutine->fnRoutine(ptRoutine->pArg, (void *)pTask); #else /*if (NULL != pTask->fnProcess)*/ { /* run task routine */ fsm_rt_t tState = pTask->fnProcess(pTask->pArg, (void *)pTask); #endif if (fsm_rt_cpl == tState) { if (pTask->bStateChanged) { while(!_register_task(pTask)); //!< re-add this task to queue break; #if SAFE_TASK_CALL_STACK == ENABLED } else if (task_pop(pTask)) { //!< return /* re-add this task to queue */ while(!_register_task(pTask)); break; #endif } #if SAFE_TASK_THREAD_SYNC == ENABLED } else if (fsm_rt_wait_for_obj == tState) { /* wait for semaphore object, task is blocked */ if (NULL == pTask->ptFlag) { pTask->bSignalRaised = false; //! wait...this should not be happen! while(!_register_task(pTask)); //!< re-add this task to queue break; } /* LOCK ( pTask->ptFlag->tLocker, if (pTask->ptFlag->bSignal) { //! signal already set pTask->bThreadBlocked = false; while(!_register_task(pTask)); //!< re-add this task to queue pTask->bSignalRaised = true; //!< set task flag pTask->ptFlag = NULL; } else { //! event is not raised pTask->bThreadBlocked = true; } ) */ SAFE_ATOM_CODE( if (pTask->ptFlag->bSignal) { //! signal already set pTask->bThreadBlocked = false; while(!_register_task(pTask)); //!< re-add this task to queue pTask->bSignalRaised = true; //!< set task flag pTask->ptFlag = NULL; } else { //! event is not raised pTask->bThreadBlocked = true; } ) break; #endif } else /*if (fsm_rt_on_going == tState)*/ { while(!_register_task(pTask)); //!< re-add this task to queue break; } } free_task(pTask); //!< free task } while(false); } while(false); LOCK(s_SchedulerLocker, bResult = s_chIdleFlag ? true : false; ) return bResult; #else safe_task_t *pTask; /*LOCK( s_SchedulerLocker, pTask = get_task_from_queue(s_TaskQueuePool); if (NULL == pTask) { EXIT_LOCK(); return false; } )*/ __IRQ_SAFE { pTask = get_task_from_queue(s_TaskQueuePool); } if (NULL == pTask) { return false; } do { #if SAFE_TASK_CALL_STACK == ENABLED volatile class(safe_call_stack_item_t) *ptRoutine; #endif pTask->bStateChanged = false; #if SAFE_TASK_CALL_STACK == ENABLED ptRoutine = pTask->pStack; /*if (NULL != ptRoutine->fnRoutine)*/ { /* run task routine */ fsm_rt_t tState = ptRoutine->fnRoutine(ptRoutine->pArg, (void *)pTask); #else /*if (NULL != pTask->fnProcess)*/ { /* run task routine */ fsm_rt_t tState = pTask->fnProcess(pTask->pArg, (void *)pTask); #endif if (fsm_rt_cpl == tState) { if (pTask->bStateChanged) { while(!_register_task(pTask)); //!< re-add this task to queue break; #if SAFE_TASK_CALL_STACK == ENABLED } else if (task_pop(pTask)) { //!< return /* re-add this task to queue */ while(!_register_task(pTask)); break; #endif } #if SAFE_TASK_THREAD_SYNC == ENABLED } else if (fsm_rt_wait_for_obj == tState) { /* wait for semaphore object, task is blocked */ if (NULL == pTask->ptFlag) { pTask->bSignalRaised = false; //! wait...this should not happen! while(!_register_task(pTask)); //!< re-add this task to queue break; } /* LOCK ( pTask->ptFlag->tLocker, if (pTask->ptFlag->bSignal) { //! signal already set pTask->bThreadBlocked = false; while(!_register_task(pTask)); //!< re-add this task to queue pTask->bSignalRaised = true; //!< set task flag pTask->ptFlag = NULL; } else { //! event is not raised pTask->bThreadBlocked = true; } ) */ __IRQ_SAFE { if (pTask->ptFlag->bSignal) { //! signal already set pTask->bThreadBlocked = false; while(!_register_task(pTask)); //!< re-add this task to queue pTask->bSignalRaised = true; //!< set task flag pTask->ptFlag = NULL; } else { //! event is not raised pTask->bThreadBlocked = true; } } break; #endif } else /*if (fsm_rt_on_going == tState)*/ { while(!_register_task(pTask)); //!< re-add this task to queue break; } } free_task(pTask); //!< free task } while(false); return true; #endif } #if SAFE_TASK_THREAD_SYNC == ENABLED /*! \brief initialize task event *! \param ptEvent event object *! \param bManualReset flag that indicates whether the event should reset to *! inactived state automatically. *! \param bInitialState event initial state, either set or not. *! \return pointer for event object */ event_t *create_event(event_t *pEvent, bool bManualReset, bool bInitialState) { class(fsm_flag_t) *ptEvent = (class(fsm_flag_t) *)pEvent; do { if (NULL == ptEvent) { break; } #if 0 LOCK_INIT(ptEvent->tLocker); //!< initialize thread locker #endif ptEvent->bSignal = bInitialState; //!< set initial state ptEvent->bManualReset = bManualReset; //!< manual reset flag ptEvent->ptHead = NULL; ptEvent->ptTail = NULL; } while(0); return (event_t *)ptEvent; } /*! \brief set task event *! \param ptEvent pointer for task event *! \return none */ void set_event(event_t *pEvent) { class(fsm_flag_t) *ptEvent = (class(fsm_flag_t) *)pEvent; if (NULL == ptEvent) { return ; } #if 0 LOCK( ptEvent->tLocker, //! wake up blocked tasks safe_task_t *pTask = ptEvent->ptHead; while(NULL != pTask) { if (pTask->bThreadBlocked) { pTask->bThreadBlocked = false; while (!_register_task(pTask)); //!< register task } pTask->ptFlag = NULL; pTask->bSignalRaised = true; //!< set task flag pTask = pTask->pNext; } ptEvent->ptTail = NULL; ptEvent->ptHead = NULL; //!< clear tasks ptEvent->bSignal = true; // if (ptEvent->bManualReset) { // ptEvent->bSignal = true; //!< set flag // } else { // ptEvent->bSignal = false; //!< set flag // } ) #else __IRQ_SAFE { //! wake up blocked tasks safe_task_t *pTask = ptEvent->ptHead; while(NULL != pTask) { if (pTask->bThreadBlocked) { pTask->bThreadBlocked = false; while (!_register_task(pTask)); //!< register task } pTask->ptFlag = NULL; pTask->bSignalRaised = true; //!< set task flag pTask = pTask->pNext; } ptEvent->ptTail = NULL; ptEvent->ptHead = NULL; //!< clear tasks ptEvent->bSignal = true; // if (ptEvent->bManualReset) { // ptEvent->bSignal = true; //!< set flag // } else { // ptEvent->bSignal = false; //!< set flag // } } #endif } # if SAFE_TASK_CRITICAL_SECTION == ENABLED /*! \brief try to enter critical section *! \param critical section item *! \return none */ void leave_critical_section(critical_section_t *ptCritical) { class(fsm_flag_t) *ptEvent = (class(fsm_flag_t) *)ptCritical; if (NULL == ptEvent) { return ; } #if 0 LOCK( ptEvent->tLocker, if (!ptEvent->bSignal) { //! wake up blocked tasks safe_task_t *ptTask = ptEvent->ptHead; if (NULL == ptTask) { ptEvent->bSignal = true; } else { ptEvent->bSignal = false; //!< set flag //! remove task from queue list ptEvent->ptHead = ptTask->pNext; if (NULL == ptEvent->ptHead) { ptEvent->ptTail = NULL; } ptTask->pNext = NULL; //! release critical section for the target task if (ptTask->bThreadBlocked) { ptTask->bThreadBlocked = false; while (!_register_task(ptTask)); //!< register task } ptTask->ptFlag = NULL; ptTask->bSignalRaised = true; //!< set task flag } } ) #else __IRQ_SAFE { if (!ptEvent->bSignal) { //! wake up blocked tasks safe_task_t *ptTask = ptEvent->ptHead; if (NULL == ptTask) { ptEvent->bSignal = true; } else { ptEvent->bSignal = false; //!< set flag //! remove task from queue list ptEvent->ptHead = ptTask->pNext; if (NULL == ptEvent->ptHead) { ptEvent->ptTail = NULL; } ptTask->pNext = NULL; //! release critical section for the target task if (ptTask->bThreadBlocked) { ptTask->bThreadBlocked = false; while (!_register_task(ptTask)); //!< register task } ptTask->ptFlag = NULL; ptTask->bSignalRaised = true; //!< set task flag } } } #endif } #endif /*! \brief reset specified task event *! \param ptEvent task event pointer *! \return none */ void reset_event(event_t *pEvent) { class(fsm_flag_t) *ptEvent = (class(fsm_flag_t) *)pEvent; if (NULL == ptEvent) { return ; } #if 0 LOCK(ptEvent->tLocker, ptEvent->bSignal = false; ) #else __IRQ_SAFE { ptEvent->bSignal = false; } #endif } /*! \brief wait for a specified task event *! \param ptEvent target event item *! \param pTask parasitifer task *! \retval true event raised *! \retval false event haven't raised yet. */ bool wait_for_single_object(fsm_flag_t *ptFlag, void *ptTask) { bool bResult = true; safe_task_t *pTask = (safe_task_t *)ptTask; class(fsm_flag_t) *ptEvent = (class(fsm_flag_t) *)ptFlag; if (NULL == ptEvent) { return bResult; //!< wait nothing } #if 0 LOCK(ptEvent->tLocker, bResult = ptEvent->bSignal; if (!ptEvent->bManualReset) { ptEvent->bSignal = false; } if (NULL != pTask) { if (bResult) { pTask->bSignalRaised = false; } else if (pTask->bSignalRaised) { pTask->bSignalRaised = false; bResult = true; } else { //! add task to the wait list pTask->pNext = NULL; if (NULL == ptEvent->ptTail) { ptEvent->ptHead = pTask; } else { ptEvent->ptTail->pNext = pTask; } ptEvent->ptTail = pTask; pTask->ptFlag = ptEvent; pTask->bThreadBlocked = false; bResult = false; } } ) #else __IRQ_SAFE { bResult = ptEvent->bSignal; if (!ptEvent->bManualReset) { ptEvent->bSignal = false; } if (NULL != pTask) { if (bResult) { pTask->bSignalRaised = false; } else if (pTask->bSignalRaised) { pTask->bSignalRaised = false; bResult = true; } else { //! add task to the wait list pTask->pNext = NULL; if (NULL == ptEvent->ptTail) { ptEvent->ptHead = pTask; } else { ptEvent->ptTail->pNext = pTask; } ptEvent->ptTail = pTask; pTask->ptFlag = ptEvent; pTask->bThreadBlocked = false; bResult = false; } } } #endif return bResult; } /* event_t tEvent; STATE(Demo) BEGIN if (!wait_for_single_object(&tEvent, THIS_TASK)) { WAIT_FOR_OBJ; } ... END */ #endif //#pragma optimize=speed /*! \brief add a task control block to task queue * \param pTask task control block * \retval false failed to add a task control block * \retval true succeeded in add a task */ static bool _register_task( safe_task_t *pTask ) { bool bResult = true; #if 0 if (NULL == pTask) { return false; } #endif #if SAFE_TASK_QUEUE_POOL_SIZE > 1 SAFE_TASK_QUEUE *ptTaskQueue = get_free_task_queue(); if (NULL != ptTaskQueue) { bResult = add_task_to_queue(ptTaskQueue,pTask); free_task_queue(ptTaskQueue); } #else /*LOCK( s_SchedulerLocker, if (!add_task_to_queue(&s_TaskQueuePool[0],pTask)) { bResult = false; } )*/ __IRQ_SAFE { if (!add_task_to_queue(&s_TaskQueuePool[0],pTask)) { bResult = false; } } #endif return bResult; } #if __IS_COMPILER_IAR__ # pragma optimize=no_size_constraints #endif /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param fnReturnRoutine return to this routine when FSM completed * \param pReturnArg argument for return routine * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ bool call_task_ex( void *pT, safe_task_func_t *fnRoutine, void *pArg, safe_task_func_t *fnReturnRoutine, void *pReturnArg, bool bSubcall ) { safe_task_t *pTask = (safe_task_t *)pT; if ( (NULL == pTask) || (!check_task_key(pTask->pchKey)) || (NULL == fnRoutine) || (NULL == fnReturnRoutine)) { return false; } #if SAFE_TASK_CALL_STACK == ENABLED if ( bSubcall ) { //! push task if (!task_push_ex(pTask,fnReturnRoutine, pReturnArg)) { return false; } } do { volatile class(safe_call_stack_item_t) *ptRoutine = pTask->pStack; ptRoutine->fnRoutine = fnRoutine; ptRoutine->pArg = pArg; } while (false); #else pTask->fnProcess = fnRoutine; pTask->pArg = pArg; #endif pTask->bStateChanged = true; //! issue found here, in rom, it is return false return true; } #if __IS_COMPILER_IAR__ # pragma optimize=no_size_constraints #endif /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ bool call_task( void *pT, safe_task_func_t *fnRoutine , void *pArg , bool bSubcall) { safe_task_t *pTask = (safe_task_t *)pT; if (NULL == pTask) { return false; } #if SAFE_TASK_CALL_STACK == ENABLED do { volatile class(safe_call_stack_item_t) *ptRoutine = pTask->pStack; return call_task_ex( pT, fnRoutine, pArg, ptRoutine->fnRoutine, ptRoutine->pArg, bSubcall); } while (false); #else return call_task_ex( pT, fnRoutine, pArg, pTask->fnProcess, pTask->pArg, bSubcall); #endif } #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \param pStack a return stack buffer * \param chStackSize return stack size * \return task handle */ void *register_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ) #else /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \return task handle */ void *register_task( safe_task_func_t *fnRoutine, void *pArg ) #endif { #if SAFE_TASK_CALL_STACK == ENABLED /*! try to create a new task control block */ safe_task_t *pTask = new_task( fnRoutine, pArg, pStack, chStackSize ); #else /*! try to create a new task control block */ safe_task_t *pTask = new_task( fnRoutine, (void *)pArg ); #endif if (NULL != pTask) { //! register a task if (_register_task(pTask)) { return (void *)pTask; } } //! free task free_task(pTask); return NULL; } /*! \brief finish scheduler * \param none * \return none */ void scheduler_finish( void ) { //! initialize ciritical locker #if 0 LOCK_INIT(s_TaskLocker); #endif LOCK_INIT(s_SchedulerLocker); #if SAFE_TASK_QUEUE_POOL_SIZE > 1 s_chIdleFlag = _BV(SAFE_TASK_QUEUE_POOL_SIZE)-1; OBJECT_INIT_ZERO(s_tFreeTaskQueueList); #endif OBJECT_INIT_ZERO(s_TaskQueuePool); s_pFreeList = NULL; } /*! \brief initialize scheduler * \param none * \return none */ void scheduler_init( void ) { scheduler_finish(); #if SAFE_TASK_POOL_SIZE > 0 task_pool_init((void *)s_TaskPool,sizeof(s_TaskPool)); #endif #if SAFE_TASK_QUEUE_POOL_SIZE > 1 //! add task queue to free list do { uint_fast8_t n = UBOUND(s_TaskQueuePool); SAFE_TASK_QUEUE *ptQueue = s_TaskQueuePool; do { ptQueue->chBit = n-1; free_task_queue(ptQueue++); } while(--n); } while (false); #endif } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/scheduler.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __SCHEDULER_H__ #define __SCHEDULER_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #if SAFE_TASK_CALL_STACK == ENABLED #define NEW_FSM_WITH_ARG(__NAME, __ROUTINE, __ARG) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ &(__ARG),\ g_##__NAME##CallStack,\ UBOUND(g_##__NAME##CallStack)\ )) #define NEW_FSM(__NAME, __ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL,\ g_##__NAME##CallStack,\ UBOUND(g_##__NAME##CallStack)\ )) #define FSM(__NAME, __STACK_SIZE) \ NO_INIT volatile safe_call_stack_item_t g_##__NAME##CallStack[(__STACK_SIZE)+1];\ #define STATIC_FSM(__NAME) FSM(__NAME, 0) #define NEW_STATIC_FSM(__NAME,__ROUTINE) NEW_FSM(__NAME, (__ROUTINE)) #else #define NEW_FSM_WITH_ARG(__NAME, __ROUTINE, __ARG_TYPE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ &g_##__NAME##Arg\ )) #define NEW_FSM(__NAME, __ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL\ )) #define NEW_STATIC_FSM(__NAME,__ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL\ )) #define STATIC_FSM(__NAME) #define FSM(__NAME, __STACK_SIZE) #endif #define EXTERN_STATIC_FSM(__NAME) #define EXTERN_FSM(__NAME) #define END_EXTERN_STATIC_FSM #define END_EXTERN_FSM #define DEF_ARG def_class #define END_DEF_ARG(__NAME) end_def_class(__NAME) #define EXTERN_ARG extern_class #define END_EXTERN_ARG(__NAME) end_extern_class(__NAME) #define ARG(__NAME) class(__NAME) #define REF_ARG(__NAME) \ (*((class(__NAME) *)(pArg))) #define CHECK_ARG(__NAME) \ ((NULL == pArg) ? false : true) //! \name macros for finit state machine //! @{ #define END_FSM #define END_STATIC_FSM //! \brief start define a FSM state #define STATE(__NAME) \ fsm_rt_t FSM_##__NAME(void * pArg, void * pTask) //! \brief begin & end #ifndef BEGIN #define BEGIN { #endif #ifndef END #define END } #endif #if SAFE_TASK_THREAD_SYNC == ENABLED # define WAIT_EVENT_BEGIN(__EVENT) { \ if (!SCHEDULER.WaitForSingleObject((__EVENT), pTask)) { \ WAIT_FOR_OBJ; \ } # define CS_WAIT_EVENT(__EVENT) SCHEDULER.WaitForSingleObject((__EVENT), pTask) //! \brief initialize a task event item # define CS_INIT_EVENT(__EVENT,__MANUAL_RESET,__INITIAL_STATE) \ SCHEDULER.CreateEvent((__EVENT),(__MANUAL_RESET), (__INITIAL_STATE)) //! \brief set task event to active state # define CS_SET_EVENT(__EVENT) SCHEDULER.SetEvent((__EVENT)) //! \brief reset task event to inactive state # define CS_RESET_EVENT(__EVENT) SCHEDULER.ResetEvent((__EVENT)) //! @} # if SAFE_TASK_CRITICAL_SECTION == ENABLED //! \name critical section //! @{ //! \brief initialize a specified critical section # define CS_INIT_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.CreateEvent((event_t *)(__CRITICAL), false, true) /*! \brief state modifier which inidicates a specified state to be critical *! section. E.g. *! STATE(DEMO_A) CRITICAL_SECTION_BEGIN(&g_tCritical) *! ... *! TRANSFER_TO_STATE(DEMO_B) *! EXIT_STATE; *! END */ # define CRITICAL_SECTION_BEGIN(__CRITICAL) { \ if (!SCHEDULER.WaitForSingleObject((event_t *)(__CRITICAL), pTask)) {\ WAIT_FOR_OBJ; \ } # define CS_ENTER_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.WaitForSingleObject((event_t *)(__CRITICAL), pTask) # define CS_LEAVE_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.LeaveCriticalSection((__CRITICAL)) # define enter_critical_section(__CRITICAL, __TASK) \ SCHEDULER.WaitForSingleObject((__CRITICAL),(__TASK)) # define create_critical_section(__CRITICAL) \ SCHEDULER.CreateEvent((event_t *)(__CRITICAL), false, true)) //! @} //! \name mutex //! @{ # define CS_INIT_MUTEX(__MUTEX) \ INIT_CRITICAL_SECTION(__MUTEX) # define CS_RELEASE_MUTEX(__MUTEX) \ LEAVE_CRITICAL_SECTION(__MUTEX) # define CS_WAIT_MUTEX(__MUTEX) \ ENTER_CRITICAL_SECTION(__MUTEX) # define release_mutex(__MUTEX) \ LEAVE_CRITICAL_SECTION(__MUTEX) # define create_mutex(__MUTEX) \ INIT_CRITICAL_SECTION(__MUTEX) //! @} # endif #endif #define REGION #define STATIC_ALLOC static #ifndef PUBLIC #define PUBLIC #endif #ifndef public #define public #endif #ifndef PRIVATE #define PRIVATE static #endif #ifndef private #define private static #endif #define REFLEXIVE_STATE return fsm_rt_on_going; #define EXIT_STATE return fsm_rt_cpl; #define WAIT_FOR_OBJ return fsm_rt_wait_for_obj; //! \brief state transfering # define TRANSFER_TO_STATE(__ROUTINE) \ SCHEDULER.Call(pTask, FSM_##__ROUTINE, pArg, false) //! \brief call sub state machine # define CALL_FSM(__ROUTINE, __ARG_ADDR) \ SCHEDULER.Call(pTask, __ROUTINE, __ARG_ADDR, true) //! \brief call sub state machine # define CALL_FSM_EX(__ROUTINE, __ARG_ADDR, __RET_ROUTINE,__RET_ARG_ADDR) \ SCHEDULER.CallEx(pTask, __ROUTINE, __ARG_ADDR, \ __RET_ROUTINE, __RET_ARG_ADDR, true) # define CS_SCHEDULER() SCHEDULER.Scheduler() # define CS_INIT() SCHEDULER.Init() # define CS_HEAP_INIT(__ADDR, __SIZE) SCHEDULER.HeapInit(__ADDR, __SIZE) //# define CS_FINISH() SCHEDULER.Finish() //! \brief a reference to FSM state #define REF_STATE(__NAME) FSM_##__NAME #define THIS_TASK pTask #define EXTERN_STATE(__NAME) \ extern fsm_rt_t FSM_##__NAME(void * pArg, void *pTask) //! @} #define DECLARE #define END_DECLARE #define IMPLEMENT_FSM(__NAME) #define END_IMPLEMENT_FSM /*============================ TYPES =========================================*/ #ifdef RESERVED #undef RESERVED #endif #define __RSV(__N) _##__N #define ___RSV(__N) __RSV(__N) #define RESERVED ___RSV(__LINE__) declare_class(task_t) extern_class(task_t) #if SAFE_TASK_CALL_STACK == ENABLED void *RESERVED; uint8_t : 8; uint8_t : 8; #else void *RESERVED; void *RESERVED; #endif #if SAFE_TASK_THREAD_SYNC == ENABLED uint8_t : 1; uint8_t : 1; uint8_t : 1; void *RESERVED; #else bool RESERVED; #endif const uint8_t *RESERVED; void *RESERVED; end_extern_class(task_t) #undef RESERVED /*! \brief task function prototype * \param pArg start address of a task argument control block * \param (void * volatile) * \retval true current task want to keep running. * \retval false current task completed */ typedef fsm_rt_t safe_task_func_t(void *pArg, void *); declare_class(safe_call_stack_item_t) //! \name call stack item //! @{ extern_class(safe_call_stack_item_t) safe_task_func_t *fnRoutine; //!< routine void *pArg; //!< argument end_extern_class(safe_call_stack_item_t); //! @} #if SAFE_TASK_THREAD_SYNC == ENABLED declare_class(fsm_flag_t) //! \name task event item //! @{ extern_class(fsm_flag_t) bool bSignal; //!< signal volatile void *ptHead; //!< task item volatile void *ptTail; bool bManualReset; //!< manual reset flag locker_t tLocker; //!< thread locker end_extern_class(fsm_flag_t) //! @} //! \name event typedef fsm_flag_t event_t; # if SAFE_TASK_CRITICAL_SECTION == ENABLED //! \name critical section typedef event_t critical_section_t; # endif #endif //! \name co-operation scheduler interface //! @{ DEF_INTERFACE(scheduler_t) void (*Init)(void); //void (*Finish)(void); bool (*HeapInit)(void *, uint16_t); #if SAFE_TASK_CALL_STACK == ENABLED void *(*NewTask)(safe_task_func_t *, void *, volatile safe_call_stack_item_t *, uint8_t ); #else void *(*NewTask)( safe_task_func_t *, void * ); #endif bool (*Scheduler)( void ); bool (*Call)( void *, safe_task_func_t * , void * , bool); bool (*CallEx)( void *, safe_task_func_t *, void *, safe_task_func_t *, void *, bool ); #if SAFE_TASK_THREAD_SYNC == ENABLED event_t *(*CreateEvent)(event_t *, bool , bool ); void (*SetEvent)(event_t *); void (*ResetEvent)(event_t *); bool (*WaitForSingleObject)(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED void (*LeaveCriticalSection)(critical_section_t *); # endif #endif END_DEF_INTERFACE(scheduler_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ extern const scheduler_t SCHEDULER; /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize scheduler * \param none * \return none */ extern void scheduler_init( void ); /*! \brief finish scheduler * \param none * \return none */ extern void scheduler_finish( void ); /*! \brief add tasks to the task pool * \param pHead task heap buffer * \param hwSize heap size * \return access result */ extern bool task_pool_init(void *pHeap, uint16_t hwSize); #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \param pStack a return stack buffer * \param chStackSize return stack size * \return task handle */ extern void *register_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ); #else /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \return task handle */ extern void *register_task( safe_task_func_t *fnRoutine, void *pArg ); #endif /*! \brief scheduler function * \retval true system is busy * \retval false system is idle */ extern bool scheduler( void ); /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ extern bool call_task( void *pT, safe_task_func_t *fnRoutine , void *pArg , bool bSubcall); /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param fnReturnRoutine return to this routine when FSM completed * \param pReturnArg argument for return routine * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ extern bool call_task_ex( void *pT, safe_task_func_t *fnRoutine, void *pArg, safe_task_func_t *fnReturnRoutine, void *pReturnArg, bool bSubcall ) ; #if SAFE_TASK_THREAD_SYNC == ENABLED /*! \brief initialize task event *! \param ptEvent event object *! \param bManualReset flag that indicates whether the event should reset to *! inactived state automatically. *! \param bInitialState event initial state, either set or not. *! \return pointer for event object */ extern event_t *create_event(event_t *, bool bManualReset, bool bInitialState); /*! \brief set task event *! \param ptEvent pointer for task event *! \return none */ extern void set_event(event_t *); /*! \brief reset specified task event *! \param ptEvent task event pointer *! \return none */ extern void reset_event(event_t *); /*! \brief wait for a specified task event *! \param ptEvent target event item *! \param pTask parasitifer task *! \retval true event raised *! \retval false event haven't raised yet. */ extern bool wait_for_single_object(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED /*! \brief try to enter critical section *! \param critical section item *! \return none */ extern void leave_critical_section(critical_section_t *); # endif #endif #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/scheduler_internal.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __SCHEDULER_H__ #define __SCHEDULER_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\task.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ #if SAFE_TASK_CALL_STACK == ENABLED #define NEW_FSM_WITH_ARG(__NAME, __ROUTINE, __ARG) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ &(__ARG),\ g_##__NAME##CallStack,\ UBOUND(g_##__NAME##CallStack)\ )) #define NEW_FSM(__NAME, __ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL,\ g_##__NAME##CallStack,\ UBOUND(g_##__NAME##CallStack)\ )) #define FSM(__NAME, __STACK_SIZE) \ NO_INIT volatile safe_call_stack_item_t g_##__NAME##CallStack[(__STACK_SIZE)+1];\ #define STATIC_FSM(__NAME) FSM(__NAME, 0) #define NEW_STATIC_FSM(__NAME,__ROUTINE) NEW_FSM(__NAME, (__ROUTINE)) #else #define NEW_FSM_WITH_ARG(__NAME, __ROUTINE, __ARG_TYPE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ &g_##__NAME##Arg\ )) #define NEW_FSM(__NAME, __ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL\ )) #define NEW_STATIC_FSM(__NAME,__ROUTINE) \ (NULL != SCHEDULER.NewTask \ (\ __ROUTINE,\ NULL\ )) #define STATIC_FSM(__NAME) #define FSM(__NAME, __STACK_SIZE) #endif #define EXTERN_STATIC_FSM(__NAME) #define EXTERN_FSM(__NAME) #define END_EXTERN_STATIC_FSM #define END_EXTERN_FSM #define DEF_ARG DEF_CLASS #define END_DEF_ARG(__NAME) END_DEF_CLASS(__NAME) #define EXTERN_ARG EXTERN_CLASS #define END_EXTERN_ARG(__NAME) END_EXTERN_CLASS(__NAME) #define ARG(__NAME) CLASS(__NAME) #define REF_ARG(__NAME) \ (*((CLASS(__NAME) *)(pArg))) #define CHECK_ARG(__NAME) \ ((NULL == pArg) ? false : true) //! \name macros for finit state machine //! @{ #define END_FSM #define END_STATIC_FSM //! \brief start define a FSM state #define STATE(__NAME) \ fsm_rt_t FSM_##__NAME(void * pArg, void * pTask) //! \brief begin & end #ifndef BEGIN #define BEGIN { #endif #ifndef END #define END } #endif #if SAFE_TASK_THREAD_SYNC == ENABLED # define WAIT_EVENT_BEGIN(__EVENT) { \ if (!SCHEDULER.WaitForSingleObject((__EVENT), pTask)) { \ WAIT_FOR_OBJ; \ } # define CS_WAIT_EVENT(__EVENT) SCHEDULER.WaitForSingleObject((__EVENT), pTask) //! \brief initialize a task event item # define CS_INIT_EVENT(__EVENT,__MANUAL_RESET,__INITIAL_STATE) \ SCHEDULER.CreateEvent((__EVENT),(__MANUAL_RESET), (__INITIAL_STATE)) //! \brief set task event to active state # define CS_SET_EVENT(__EVENT) SCHEDULER.SetEvent((__EVENT)) //! \brief reset task event to inactive state # define CS_RESET_EVENT(__EVENT) SCHEDULER.ResetEvent((__EVENT)) //! @} # if SAFE_TASK_CRITICAL_SECTION == ENABLED //! \name critical section //! @{ //! \brief initialize a specified critical section # define CS_INIT_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.CreateEvent((event_t *)(__CRITICAL), false, true) /*! \brief state modifier which inidicates a specified state to be critical *! section. E.g. *! STATE(DEMO_A) CRITICAL_SECTION_BEGIN(&g_tCritical) *! ... *! TRANSFER_TO_STATE(DEMO_B) *! EXIT_STATE; *! END */ # define CRITICAL_SECTION_BEGIN(__CRITICAL) { \ if (!SCHEDULER.WaitForSingleObject((event_t *)(__CRITICAL), pTask)) {\ WAIT_FOR_OBJ; \ } # define CS_ENTER_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.WaitForSingleObject((event_t *)(__CRITICAL), pTask) # define CS_LEAVE_CRITICAL_SECTION(__CRITICAL) \ SCHEDULER.LeaveCriticalSection((__CRITICAL)) # define enter_critical_section(__CRITICAL, __TASK) \ SCHEDULER.WaitForSingleObject((__CRITICAL),(__TASK)) # define create_critical_section(__CRITICAL) \ SCHEDULER.CreateEvent((event_t *)(__CRITICAL), false, true)) //! @} //! \name mutex //! @{ # define CS_INIT_MUTEX(__MUTEX) \ INIT_CRITICAL_SECTION(__MUTEX) # define CS_RELEASE_MUTEX(__MUTEX) \ LEAVE_CRITICAL_SECTION(__MUTEX) # define CS_WAIT_MUTEX(__MUTEX) \ ENTER_CRITICAL_SECTION(__MUTEX) # define release_mutex(__MUTEX) \ LEAVE_CRITICAL_SECTION(__MUTEX) # define create_mutex(__MUTEX) \ INIT_CRITICAL_SECTION(__MUTEX) //! @} # endif #endif #define REGION #define STATIC_ALLOC static #ifndef PUBLIC #define PUBLIC #endif #ifndef public #define public #endif #ifndef PRIVATE #define PRIVATE static #endif #ifndef private #define private static #endif #define REFLEXIVE_STATE return fsm_rt_on_going; #define EXIT_STATE return fsm_rt_cpl; #define WAIT_FOR_OBJ return fsm_rt_wait_for_obj; //! \brief state transfering # define TRANSFER_TO_STATE(__ROUTINE) \ SCHEDULER.Call(pTask, FSM_##__ROUTINE, pArg, false) //! \brief call sub state machine # define CALL_FSM(__ROUTINE, __ARG_ADDR) \ SCHEDULER.Call(pTask, __ROUTINE, __ARG_ADDR, true) //! \brief call sub state machine # define CALL_FSM_EX(__ROUTINE, __ARG_ADDR, __RET_ROUTINE,__RET_ARG_ADDR) \ SCHEDULER.CallEx(pTask, __ROUTINE, __ARG_ADDR, \ __RET_ROUTINE, __RET_ARG_ADDR, true) # define CS_SCHEDULER() SCHEDULER.Scheduler() # define CS_INIT() SCHEDULER.Init() # define CS_HEAP_INIT(__ADDR, __SIZE) SCHEDULER.HeapInit(__ADDR, __SIZE) //# define CS_FINISH() SCHEDULER.Finish() //! \brief a reference to FSM state #define REF_STATE(__NAME) FSM_##__NAME #define THIS_TASK pTask #define EXTERN_STATE(__NAME) \ extern fsm_rt_t FSM_##__NAME(void * pArg, void *pTask) //! @} #define DECLARE #define END_DECLARE #define IMPLEMENT_FSM(__NAME) #define END_IMPLEMENT_FSM /*============================ TYPES =========================================*/ #ifdef RESERVED #undef RESERVED #endif #define __RSV(__N) _##__N #define ___RSV(__N) __RSV(__N) #define RESERVED ___RSV(__LINE__) /* EXTERN_CLASS(task_t) #if SAFE_TASK_CALL_STACK == ENABLED void *RESERVED; uint8_t RESERVED; uint8_t RESERVED; #else void *RESERVED; void *RESERVED; #endif #if SAFE_TASK_THREAD_SYNC == ENABLED uint8_t RESERVED : 1; uint8_t RESERVED : 1; uint8_t RESERVED : 1; void *RESERVED; #else bool RESERVED; #endif FLASH uint8_t *RESERVED; void *RESERVED; END_EXTERN_CLASS(task_t) */ #undef RESERVED /*! \brief task function prototype * \param pArg start address of a task argument control block * \param (void * volatile) * \retval true current task want to keep running. * \retval false current task completed */ typedef fsm_rt_t safe_task_func_t(void *pArg, void *); /* //! \name call stack item //! @{ EXTERN_CLASS(safe_call_stack_item_t) safe_task_func_t *fnRoutine; //!< routine void *pArg; //!< argument END_EXTERN_CLASS(safe_call_stack_item_t); //! @} #if SAFE_TASK_THREAD_SYNC == ENABLED //! \name task event item //! @{ EXTERN_CLASS(fsm_flag_t) bool bSignal; //!< signal volatile void *ptHead; //!< task item volatile void *ptTail; bool bManualReset; //!< manual reset flag locker_t tLocker; //!< thread locker END_EXTERN_CLASS(fsm_flag_t) //! @} //! \name event typedef fsm_flag_t event_t; # if SAFE_TASK_CRITICAL_SECTION == ENABLED //! \name critical section typedef event_t critical_section_t; # endif #endif */ //! \name co-operation scheduler interface //! @{ DEF_INTERFACE(scheduler_t) void (*Init)(void); //void (*Finish)(void); bool (*HeapInit)(void *, uint16_t); #if SAFE_TASK_CALL_STACK == ENABLED void *(*NewTask)(safe_task_func_t *, void *, volatile safe_call_stack_item_t *, uint8_t ); #else void *(*NewTask)( safe_task_func_t *, void * ); #endif bool (*Scheduler)( void ); bool (*Call)( void *, safe_task_func_t * , void * , bool); bool (*CallEx)( void *, safe_task_func_t *, void *, safe_task_func_t *, void *, bool ); #if SAFE_TASK_THREAD_SYNC == ENABLED event_t *(*CreateEvent)(event_t *, bool , bool ); void (*SetEvent)(event_t *); void (*ResetEvent)(event_t *); bool (*WaitForSingleObject)(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED void (*LeaveCriticalSection)(critical_section_t *); # endif #endif END_DEF_INTERFACE(scheduler_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ //#if !defined(__LIB_REFERENCE__) ////! \brief ES-scheduler //extern const scheduler_t SCHEDULER; //#else //#define SCHEDULER (*(const scheduler_t *)GSF_SCHEDULER_BASE_ADDRESS) //#endif extern const scheduler_t SCHEDULER; /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \note initialize scheduler * \param none * \return none */ extern void scheduler_init( void ); /*! \brief finish scheduler * \param none * \return none */ extern void scheduler_finish( void ); /*! \brief add tasks to the task pool * \param pHead task heap buffer * \param hwSize heap size * \return access result */ extern bool task_pool_init(void *pHeap, uint16_t hwSize); #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \param pStack a return stack buffer * \param chStackSize return stack size * \return task handle */ extern void *register_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ); #else /*! \brief create a new task control block * \param fnRoutine task routine * \param fnReturnTo a routine which will be called when task routine return * false. * \param pArg a pointer of a argument control block * \return task handle */ extern void *register_task( safe_task_func_t *fnRoutine, void *pArg ); #endif /*! \brief scheduler function * \retval true system is busy * \retval false system is idle */ extern bool scheduler( void ); /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ extern bool call_task( void *pT, safe_task_func_t *fnRoutine , void *pArg , bool bSubcall); /*! \brief call a sub task (routine) * \param pT a pointer of task control block * \param fnRoutine target routine * \param pArg a pointer of argument control block * \param fnReturnRoutine return to this routine when FSM completed * \param pReturnArg argument for return routine * \param bSubcall is sub-task to be called * \retval false failed to add a task control block * \retval true succeeded in add a task */ extern bool call_task_ex( void *pT, safe_task_func_t *fnRoutine, void *pArg, safe_task_func_t *fnReturnRoutine, void *pReturnArg, bool bSubcall ) ; #if SAFE_TASK_THREAD_SYNC == ENABLED /*! \brief initialize task event *! \param ptEvent event object *! \param bManualReset flag that indicates whether the event should reset to *! inactived state automatically. *! \param bInitialState event initial state, either set or not. *! \return pointer for event object */ extern event_t *create_event(event_t *, bool bManualReset, bool bInitialState); /*! \brief set task event *! \param ptEvent pointer for task event *! \return none */ extern void set_event(event_t *); /*! \brief reset specified task event *! \param ptEvent task event pointer *! \return none */ extern void reset_event(event_t *); /*! \brief wait for a specified task event *! \param ptEvent target event item *! \param pTask parasitifer task *! \retval true event raised *! \retval false event haven't raised yet. */ extern bool wait_for_single_object(fsm_flag_t *, void *); # if SAFE_TASK_CRITICAL_SECTION == ENABLED /*! \brief try to enter critical section *! \param critical section item *! \return none */ extern void leave_critical_section(critical_section_t *); # endif #endif #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/shell.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\scheduler.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ WEAK bool ON_ENTERING_IDLE_TASK(void) { return true; } WEAK void TRY_TO_SLEEP(void) { } WEAK void ON_LEAVING_IDLE_TASK(void) { } /*! \note system idle task *! \param none *! \return none */ static void idle_task( void ) { if (ON_ENTERING_IDLE_TASK()) { //! try to enter a max allowed sleep mode TRY_TO_SLEEP(); } ON_LEAVING_IDLE_TASK(); } ROOT void OS_SCHEDULER(void) { if (!CS_SCHEDULER()) { //!< scheduler idle_task(); //!< idle state } } ROOT void SCHEDULER_INIT(void) { //! initialize scheduler CS_INIT(); static NO_INIT task_t s_tTaskPool[SAFE_TASK_POOL_SIZE]; CS_HEAP_INIT(s_tTaskPool, sizeof(s_tTaskPool)); } #endif ================================================ FILE: sources/gmsi/service/scheduler/task.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include "app_cfg.h" #include ".\task.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ //const static uint32_t c_wTaskSize = sizeof(safe_task_t); /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ #if 0 //! \brief task locker #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #endif NO_INIT locker_t s_TaskLocker; #endif #if SAFE_TASK_USE_RESERVED_SYSTEM_RAM == ENABLED # if __IS_COMPILER_IAR__ # pragma location = ".sys_ram" # endif #endif NO_INIT safe_task_t *s_pFreeList; /*============================ LOCAL VARIABLES ===============================*/ //! \brief task key for identifying task control blocks static ROM_FLASH uint8_t s_chTaskKey[] = "Schedule"; /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief try to push a task routine into stack * \param pTask * \param fnRoutine return routine * \param pArg argument for return routine * \retval true succeeded in pushing task routine into common return stack. * \retval false failed to push task routine into common return stack */ bool task_push_ex( safe_task_t *pTask, safe_task_func_t *fnRoutine, void *pArg) { if ( (NULL == pTask) || (NULL == pTask->pStack) || (s_chTaskKey != pTask->pchKey) || (pTask->chSP >= pTask->chStackSize) || (NULL == fnRoutine)) { return false; } do { volatile class(safe_call_stack_item_t) *ptRoutine = pTask->pStack; ptRoutine->fnRoutine = fnRoutine; ptRoutine->pArg = pArg; } while (false); pTask->pStack++; pTask->chSP++; return true; } /*! \brief try to pop a task routine from stack * \param pTask * \param pArg a pointer of a argument control block * \retval true succeeded in pushing task routine into common return stack. * \retval false failed to push task routine into common return stack */ bool task_pop( safe_task_t *pTask ) { /*! check input */ if ( (NULL == pTask) || (NULL == pTask->pStack) || (s_chTaskKey != pTask->pchKey) || (pTask->chSP > pTask->chStackSize)) { return false; } //! is stack empty if (0 == pTask->chSP) { /* nothing to pop */ return false; } pTask->pStack--; pTask->chSP--; return true; } #endif /*! \brief verify task control block * \param pchKey target key of the taget control block * \retval true the control block is legal * \retval false the control block is illegal */ bool check_task_key( const uint8_t *pchKey ) { return (pchKey == s_chTaskKey); } #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief create a new task control block * \param fnRoutine task routine * \param pArg a pointer of a argument control block * \param pStack a return stack buffer * \param chStackSize return stack size * \retval NULL failed to create a new task control block * \retval a pointer for a initialized task control block */ safe_task_t *new_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ) #else /*! \brief create a new task control block * \param fnRoutine task routine * \param pArg a pointer of a argument control block * \retval NULL failed to create a new task control block * \retval a pointer for a initialized task control block */ safe_task_t *new_task( safe_task_func_t *fnRoutine, void *pArg ) #endif { safe_task_t *pTask = NULL; #if SAFE_TASK_CALL_STACK == ENABLED if (( NULL == pStack ) || ( 0 == chStackSize )) { //!< check stack return NULL; } #endif if (NULL == fnRoutine) { //!< check task routine return NULL; } #if SAFE_TASK_CALL_STACK == ENABLED #if 0 LOCK( s_TaskLocker, if (NULL != s_pFreeList) { pTask = s_pFreeList; s_pFreeList = s_pFreeList->pNext; } ) #else __IRQ_SAFE { if (NULL != s_pFreeList) { pTask = s_pFreeList; s_pFreeList = s_pFreeList->pNext; } } #endif if (NULL != pTask) { /* find a task control block */ pTask->pchKey = s_chTaskKey; //!< set task key //!< set stack buffer pTask->pStack = (class(safe_call_stack_item_t) *)pStack; //!< set task routine pTask->pStack->fnRoutine = fnRoutine; //!< set argument pTask->pStack->pArg = (void *)pArg; pTask->chStackSize = chStackSize;//!< set stack size pTask->chSP = 0; pTask->bStateChanged = false; #if SAFE_TASK_THREAD_SYNC == ENABLED pTask->ptFlag = NULL; pTask->bSignalRaised = false; pTask->bThreadBlocked = false; #endif pTask->pNext = NULL; } #else #if 0 LOCK( s_TaskLocker, if (NULL != s_pFreeList) { pTask = s_pFreeList; s_pFreeList = s_pFreeList->pNext; } ) #else SAFE_ATOM_CODE( if (NULL != s_pFreeList) { pTask = s_pFreeList; s_pFreeList = s_pFreeList->pNext; } ) #endif if (NULL != pTask) { /* find a task control block */ pTask->pchKey = s_chTaskKey; //!< set task key pTask->fnProcess = fnRoutine; //!< set task routine pTask->pArg = pArg; //!< set argument pTask->bStateChanged = false; #if SAFE_TASK_THREAD_SYNC == ENABLED pTask->ptFlag = NULL; pTask->bSignalRaised = false; pTask->bThreadBlocked = false; #endif pTask->pNext = NULL; } #endif return pTask; } /*! \brief free a task control blcok * \param pTask a pointer of a task control block * \return none */ void free_task( safe_task_t *pTask ) { if (NULL == pTask) { return ; } else if (pTask->pchKey != s_chTaskKey) { //!< check the key return ; } #if 0 LOCK( s_TaskLocker, pTask->pchKey = NULL; //!< clear task key //! add task item to freelist pTask->pNext = s_pFreeList; s_pFreeList = pTask; ) #else __IRQ_SAFE { pTask->pchKey = NULL; //!< clear task key //! add task item to freelist pTask->pNext = s_pFreeList; s_pFreeList = pTask; } #endif } /*! \brief add tasks to the task pool * \param pHead task heap buffer * \param hwSize heap size * \return access result */ bool task_pool_init(void *pHeap, uint16_t hwSize) { uint_fast8_t n = 0; safe_task_t *pTask = (safe_task_t *)pHeap; if (NULL == pHeap || hwSize < sizeof(safe_task_t)) { return false; } //! add tasks to the free list n = hwSize / sizeof(safe_task_t); do { #if 0 LOCK( s_TaskLocker, pTask->pchKey = NULL; //!< clear task key //! add task item to freelist pTask->pNext = s_pFreeList; s_pFreeList = pTask; ) #else __IRQ_SAFE { pTask->pchKey = NULL; //!< clear task key //! add task item to freelist pTask->pNext = s_pFreeList; s_pFreeList = pTask; } #endif pTask++; } while(--n); return true; } #endif /* EOF */ ================================================ FILE: sources/gmsi/service/scheduler/task.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TASK_H__ #define __TASK_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if TASK_SCHEDULER == ENABLED /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*! \brief task function prototype * \param pArg start address of a task argument control block * \param pTask a pointer of task control block * \retval true current task want to keep running. * \retval false current task completed */ typedef fsm_rt_t safe_task_func_t( void *pArg, void * pTask); declare_class(safe_call_stack_item_t) //! \name call stack item //! @{ def_class(safe_call_stack_item_t) safe_task_func_t *fnRoutine; //!< routine void *pArg; //!< argument end_def_class(safe_call_stack_item_t); //! @} typedef volatile struct _task safe_task_t; #if SAFE_TASK_THREAD_SYNC == ENABLED declare_class(fsm_flag_t) //! \name task event item //! @{ def_class(fsm_flag_t) bool bSignal; //!< signal safe_task_t *ptHead; //!< task item safe_task_t *ptTail; bool bManualReset; //!< manual reset flag #if 0 locker_t tLocker; //!< thread locker #endif end_def_class(fsm_flag_t) //! @} //! \name event typedef fsm_flag_t event_t; # if SAFE_TASK_CRITICAL_SECTION == ENABLED //! \name critical section typedef event_t critical_section_t; # endif #endif //! \name task control block //! @{ struct _task { #if SAFE_TASK_CALL_STACK == ENABLED //! task call stack class(safe_call_stack_item_t) *pStack; //!< return stack uint8_t chStackSize; //!< stack size uint8_t chSP; //!< stack pointer #else safe_task_func_t *fnProcess; //!< task routine void *pArg; //!< task arguments #endif #if SAFE_TASK_THREAD_SYNC == ENABLED uint8_t bStateChanged : 1; //!< state changed flag uint8_t bSignalRaised : 1; //!< signal uint8_t bThreadBlocked: 1; //!< task blocked flag class(fsm_flag_t) *ptFlag; //!< target semaphore #else bool bStateChanged; //!< state changed flag #endif const uint8_t * pchKey; //!< key safe_task_t * pNext; }; //! @} /*============================ GLOBAL VARIABLES ==============================*/ #if 0 //! \brief task locker extern NO_INIT locker_t s_TaskLocker; #endif extern NO_INIT safe_task_t *s_pFreeList; /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief add tasks to the task pool * \param pHead task heap buffer * \param hwSize heap size * \return access result */ extern bool task_pool_init(void *pHeap, uint16_t hwSize); /*! \brief verify task control block * \param pchKey target key of the taget control block * \retval true the control block is legal * \retval false the control block is illegal */ extern bool check_task_key( const uint8_t *pchKey ); #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief create a new task control block * \param fnRoutine task routine * \param pArg a pointer of a argument control block * \param pStack a return stack buffer * \param chStackSize return stack size * \retval NULL failed to create a new task control block * \retval a pointer for a initialized task control block */ extern safe_task_t *new_task( safe_task_func_t *fnRoutine, void *pArg, volatile safe_call_stack_item_t *pStack, uint8_t chStackSize ); #else /*! \brief create a new task control block * \param fnRoutine task routine * \param pArg a pointer of a argument control block * \retval NULL failed to create a new task control block * \retval a pointer for a initialized task control block */ extern safe_task_t *new_task( safe_task_func_t *fnRoutine, void *pArg ); #endif /*! \brief free a task control blcok * \param pTask a pointer of a task control block * \return none */ extern void free_task( safe_task_t *pTask ); #if SAFE_TASK_CALL_STACK == ENABLED /*! \brief try to push a task routine into stack * \param pTask * \param fnRoutine return routine * \param pArg argument for return routine * \retval true succeeded in pushing task routine into common return stack. * \retval false failed to push task routine into common return stack */ extern bool task_push_ex( safe_task_t *pTask, safe_task_func_t *fnRoutine, void *pArg); /*! \brief try to pop a task routine from stack * \param pTask * \param pArg a pointer of a argument control block * \retval true succeeded in pushing task routine into common return stack. * \retval false failed to push task routine into common return stack */ extern bool task_pop( safe_task_t *pTask ); #endif #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/service.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\scheduler\scheduler.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ WEAK void scheduler_init(void) { #if TASK_SCHEDULER == ENABLED //! initialize scheduler static NO_INIT task_t s_tTaskPool[SAFE_TASK_POOL_SIZE]; CS_HEAP_INIT(s_tTaskPool, sizeof(s_tTaskPool)); #endif } //extern void SCHEDULER_INIT(void); /*! \brief initialize all services *! \param none *! \retval TRUE initialize services succeed. *! \retval FALSE initialize services failed. */ bool service_init(void) { scheduler_init(); return true; } ================================================ FILE: sources/gmsi/service/service.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_SERVICE_H__ #define __USE_SERVICE_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\scheduler\scheduler.h" #include ".\communication\communication.h" #include ".\encryption\encryption.h" #include ".\memory\memory.h" #include ".\gui\gui.h" #include ".\time\time.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize all services *! \param none *! \retval TRUE initialize services succeed. *! \retval FALSE initialize services failed. */ extern bool service_init(void); #endif ================================================ FILE: sources/gmsi/service/time/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __SERVICE_TIME_APP_CFG_H__ #define __SERVICE_TIME_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/time/multiple_delay/app_cfg.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //! \note do not move this pre-processor statement to other places #include "..\app_cfg.h" #ifndef __MULTIPLE_DELAY_APP_CFG_H__ #define __MULTIPLE_DELAY_APP_CFG_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/service/time/multiple_delay/multiple_delay.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_MULTIPLE_DELAY == ENABLED #include #include "..\..\memory\epool\epool.h" #include "./multiple_delay.h" /*============================ MACROS ========================================*/ #ifndef this # define this (*ptThis) #endif #ifndef base # define base (*ptBase) #endif #ifndef target # define target (*ptTarget) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #ifndef __MD_ATOM_ACCESS # define __MD_ATOM_ACCESS(...) SAFE_ATOM_CODE(__VA_ARGS__) #endif /*============================ TYPES =========================================*/ //! \name delay task item //! @{ def_class(multiple_delay_item_t, which(implement(__single_list_node_t)), //!< list pointer uint32_t wTargetTime; //!< timeout target time multiple_delay_request_priority_t tPriority; //!< request priority void *pTag; //!< object passed to timeout event handler timeout_event_handler_t *fnHandler; //!< time out event handler ) end_def_class(multiple_delay_item_t) //! @} def_simple_fsm( multiple_delay_task, def_params( multiple_delay_t *ptObj; )) DEF_EPOOL(multiple_delay_item_heap_t, multiple_delay_item_t) END_DEF_EPOOL(multiple_delay_item_heap_t) //! \name multiple delay service control block //! @{ def_class(multiple_delay_t, which ( inherit( fsm(multiple_delay_task)) inherit( EPOOL(multiple_delay_item_heap_t) )), //!< fsm for multiple delay task)) multiple_delay_item_t *ptHighPriorityDelayList; //!< hight priority list multiple_delay_item_t *ptDelayList; //!< normal priority list struct { multiple_delay_item_t *ptHead; //!< timeout list Head multiple_delay_item_t *ptTail; //!< timeout list Tail } LowPriorityEvent; struct { multiple_delay_item_t *ptHead; //!< timeout list Head multiple_delay_item_t *ptTail; //!< timeout list Tail } NormalPriorityEvent; uint32_t wOldCounter; //!< Old tick counter number uint32_t wCounter; //!< Tick Counter uint32_t wSavedCounter; ) end_def_class(multiple_delay_t) //! @} /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ private void insert_timer_tick_event_handler( multiple_delay_t *ptObj); private bool init( multiple_delay_t *ptObj, multiple_delay_cfg_t *ptCFG ); private fsm_rt_t task(multiple_delay_t *ptObj); private multiple_delay_item_t * request_delay( multiple_delay_t *ptObj, uint32_t wDelay, multiple_delay_request_priority_t tPriority, //!< request priority void *pTag, //!< object passed to timeout event handler timeout_event_handler_t *fnHandler); private void cancel_delay(multiple_delay_t *ptObj, multiple_delay_item_t *ptItem); private declare_fsm_implementation(multiple_delay_task); private declare_fsm_initialiser(multiple_delay_task, args( multiple_delay_t *ptObj )); /*============================ GLOBAL VARIABLES ==============================*/ #if defined(LIB_GENERATION) ROOT #endif const i_multiple_delay_t MULTIPLE_DELAY = { .Init = &init, .Task = &task, .RequestDelay = &request_delay, .Cancel = &cancel_delay, .Dependent = { .TimerTickService = &insert_timer_tick_event_handler, }, }; /*============================ IMPLEMENTATION ================================*/ private fsm_rt_t task(multiple_delay_t *ptObj) { class_internal(ptObj, ptThis, multiple_delay_t); if (NULL == ptThis) { return fsm_rt_err; } return call_fsm( multiple_delay_task, ref_obj_as(this, fsm(multiple_delay_task))); } private void add_to_delay_list( multiple_delay_item_t *ptItem, multiple_delay_item_t **ppList) { class_internal(ptItem, ptTarget, multiple_delay_item_t); __MD_ATOM_ACCESS (){ do { class_internal((*ppList), ptListItem, multiple_delay_item_t); if (NULL == ptListItem) { LIST_INSERT_AFTER((*ppList), ptItem); break; } if (target.wTargetTime <= ptListItem->wTargetTime) { LIST_INSERT_AFTER((*ppList), ptItem); break; } ppList = (multiple_delay_item_t **)&(ptListItem->ptNext); } while(true); } } private bool remove_from_delay_list( multiple_delay_item_t *ptItem, multiple_delay_item_t **ppList) { class_internal(ptItem, ptTarget, multiple_delay_item_t); bool bResult = false; __MD_ATOM_ACCESS (){ do { class_internal((*ppList), ptListItem, multiple_delay_item_t); if (NULL == ptListItem) { break; } if (ptListItem == &target) { LIST_REMOVE_AFTER((*ppList), ptItem); bResult = true; break; } ppList = (multiple_delay_item_t **)&(ptListItem->ptNext); } while(true); } return bResult; } private void cancel_delay(multiple_delay_t *ptObj, multiple_delay_item_t *ptItem) { class_internal(ptObj, ptThis, multiple_delay_t); class_internal(ptItem, ptTarget, multiple_delay_item_t); if (NULL == ptThis || NULL == ptItem) { return ; } uint32_t tCount = 2; switch( target.tPriority ) { while(0 != tCount) { case MULTIPLE_DELAY_HIGH_PRIORITY: if (remove_from_delay_list(ptItem, &this.ptHighPriorityDelayList)) { break; } tCount--; case MULTIPLE_DELAY_LOW_PRIORITY: case MULTIPLE_DELAY_NORMAL_PRIORITY: default: if (remove_from_delay_list(ptItem, &this.ptDelayList)) { break; } tCount--; } } if (0 == tCount) { return; } //! raise event handler if (NULL != target.fnHandler) { //! call timeout handler (*target.fnHandler)( MULTIPLE_DELAY_CANCELLED, target.pTag); } //! free obj EPOOL_FREE( multiple_delay_item_heap_t, ref_obj_as(this, EPOOL(multiple_delay_item_heap_t)), ptItem); } private multiple_delay_item_t * request_delay( multiple_delay_t *ptObj, uint32_t wDelay, multiple_delay_request_priority_t tPriority, //!< request priority void *pTag, //!< object passed to timeout event handler timeout_event_handler_t *fnHandler) { class_internal(ptObj, ptThis, multiple_delay_t); multiple_delay_item_t *ptNewItem = NULL; do { uint32_t wCurrentCounter; if (NULL == ptThis || 0 == wDelay || NULL == fnHandler) { break; } //__MD_ATOM_ACCESS(){ wCurrentCounter = this.wCounter; //} if ((uint32_t)(wCurrentCounter + wDelay) < wCurrentCounter) { //! prevent overflow break; } //! allocate an delay item ptNewItem = EPOOL_NEW( multiple_delay_item_heap_t, ref_obj_as(this, EPOOL(multiple_delay_item_heap_t))); if (NULL == ptNewItem) { break; } do { class_internal(ptNewItem, ptTarget, multiple_delay_item_t); target.fnHandler = fnHandler; target.pTag = pTag; target.tPriority = tPriority; target.wTargetTime = wCurrentCounter + wDelay; switch( tPriority ) { case MULTIPLE_DELAY_LOW_PRIORITY: case MULTIPLE_DELAY_NORMAL_PRIORITY: default: add_to_delay_list(ptNewItem, &this.ptDelayList); break; case MULTIPLE_DELAY_HIGH_PRIORITY: add_to_delay_list(ptNewItem, &this.ptHighPriorityDelayList); break; } } while(false); } while(false); return ptNewItem; } private void insert_timer_tick_event_handler(multiple_delay_t *ptObj) { class_internal(ptObj, ptThis, multiple_delay_t); if (NULL == ptThis) { return ; } //! visit each node of High Priority Delay List (sorted list) do { if (NULL == this.ptHighPriorityDelayList) { if (NULL == this.ptDelayList) { this.wCounter = 0; this.wOldCounter = 0; this.wSavedCounter = 0; break; } } else { do { class_internal( this.ptHighPriorityDelayList, ptTarget, multiple_delay_item_t); if (NULL == ptTarget) { break; } if (target.wTargetTime <= this.wCounter) { //! timeout detected LIST_STACK_POP(this.ptHighPriorityDelayList, ptTarget); if (NULL != target.fnHandler) { //! call timeout handler (*target.fnHandler)( MULTIPLE_DELAY_TIMEOUT, target.pTag); } EPOOL_FREE( multiple_delay_item_heap_t, ref_obj_as(this, EPOOL(multiple_delay_item_heap_t)), (multiple_delay_item_t *)&target); } else { break; } } while(true); } //! increase the counter this.wCounter++; } while(false); } private bool init( multiple_delay_t *ptObj, multiple_delay_cfg_t *ptCFG ) { class_internal(ptObj, ptThis, multiple_delay_t); if (NULL == ptThis) { return false; } do { if (NULL == ptThis || NULL == ptCFG) { break; } else if (NULL == ptCFG->pchBuffer) { break; } else if (ptCFG->nSize < sizeof(multiple_delay_item_t)) { break; } memset(ptThis, 0, sizeof(multiple_delay_t)); if (!EPOOL_INIT( multiple_delay_item_heap_t, ref_obj_as(this, EPOOL(multiple_delay_item_heap_t)))) { break; } EPOOL_ADD_HEAP( multiple_delay_item_heap_t, ref_obj_as(this, EPOOL(multiple_delay_item_heap_t)), ptCFG->pchBuffer, ptCFG->nSize); return NULL != init_fsm(multiple_delay_task, &base_obj(fsm(multiple_delay_task)), args(ptObj)); } while(false); return false; } private fsm_initialiser(multiple_delay_task, args( multiple_delay_t *ptObj )) init_body( if (NULL == ptObj) { abort_init(); } this.ptObj = ptObj; ) private fsm_implementation(multiple_delay_task) def_states(CHECK_LIST, RAISE_NORMAL_PRIORITY_EVENT, RAISE_LOW_PRIORITY_EVENT) class_internal(this.ptObj, ptTarget, multiple_delay_t); body( on_start( if (NULL == ptTarget) { fsm_report(GSF_ERR_INVALID_PTR); } //__MD_ATOM_ACCESS(){ target.wSavedCounter = target.wCounter; //} if (target.wOldCounter == target.wSavedCounter) { fsm_on_going(); } target.wOldCounter = target.wSavedCounter; ) state( CHECK_LIST, do { class_internal(target.ptDelayList, ptItem, multiple_delay_item_t); if (NULL == target.ptDelayList) { break; } if (ptItem->wTargetTime <= target.wSavedCounter) { __MD_ATOM_ACCESS (){ //! timeout detected LIST_STACK_POP(target.ptDelayList, ptItem); } if (ptItem->tPriority == MULTIPLE_DELAY_LOW_PRIORITY) { //! add the item to the low priority timeout list LIST_QUEUE_ENQUEUE( target.LowPriorityEvent.ptHead, target.LowPriorityEvent.ptTail, ptItem); } else { //! add the item to the normal priority timeout list LIST_QUEUE_ENQUEUE( target.NormalPriorityEvent.ptHead, target.NormalPriorityEvent.ptTail, ptItem); } } else { break; } } while(true); update_state_to(RAISE_NORMAL_PRIORITY_EVENT); ) privilege_state(RAISE_NORMAL_PRIORITY_EVENT, do { class(multiple_delay_item_t) *ptItem; LIST_QUEUE_DEQUEUE( target.NormalPriorityEvent.ptHead, target.NormalPriorityEvent.ptTail, ptItem); if (NULL == ptItem) { //! no pending list transfer_to(RAISE_LOW_PRIORITY_EVENT); } if (NULL != ptItem->fnHandler) { (*(ptItem->fnHandler))(MULTIPLE_DELAY_TIMEOUT, ptItem->pTag); } EPOOL_FREE( multiple_delay_item_heap_t, ref_obj_as(target, EPOOL(multiple_delay_item_heap_t)), (multiple_delay_item_t *)ptItem); } while(false); ) state(RAISE_LOW_PRIORITY_EVENT, do { class(multiple_delay_item_t) *ptItem; LIST_QUEUE_DEQUEUE( target.LowPriorityEvent.ptHead, target.LowPriorityEvent.ptTail, ptItem); if (NULL == ptItem) { //! no pending list fsm_cpl(); } if (NULL != ptItem->fnHandler) { (*(ptItem->fnHandler))(MULTIPLE_DELAY_TIMEOUT, ptItem->pTag); } EPOOL_FREE( multiple_delay_item_heap_t, ref_obj_as(target, EPOOL(multiple_delay_item_heap_t)), (multiple_delay_item_t *)ptItem); } while(false); ) ) #endif /* EOF */ ================================================ FILE: sources/gmsi/service/time/multiple_delay/multiple_delay.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MULTIPLE_DELAY_H__ #define __MULTIPLE_DELAY_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #if USE_SERVICE_MULTIPLE_DELAY == ENABLED #include "..\..\memory\epool\epool.h" /*============================ MACROS ========================================*/ #define MULTIPLE_DELAY_CFG(__ADDR, ...) \ do { \ multiple_delay_cfg_t tCFG = { \ __VA_ARGS__ \ }; \ \ MULTIPLE_DELAY.Init((__ADDR), &tCFG); \ } while(false) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name delay status //! @{ typedef enum { MULTIPLE_DELAY_TIMEOUT = 0, //!< timout MULTIPLE_DELAY_CANCELLED, //!< delay request is cancelled by user } multiple_delay_report_status_t; //! @} typedef enum { MULTIPLE_DELAY_LOW_PRIORITY, MULTIPLE_DELAY_NORMAL_PRIORITY, MULTIPLE_DELAY_HIGH_PRIORITY, } multiple_delay_request_priority_t; //! \brief delay request timeout event handler prototype (delegate) typedef void timeout_event_handler_t(multiple_delay_report_status_t tStatus, void *pObj); //! \name delay task item //! @{ declare_class(multiple_delay_item_t) extern_class(multiple_delay_item_t, which(implement(__single_list_node_t)), //!< list pointer uint32_t wTargetTime; //!< timeout target time multiple_delay_request_priority_t tPriority; //!< request priority void *pTag; //!< object passed to timeout event handler timeout_event_handler_t *fnHandler; //!< time out event handler ) end_extern_class(multiple_delay_item_t) //! @} declare_class(multiple_delay_t) declare_simple_fsm(multiple_delay_task) extern_simple_fsm( multiple_delay_task, def_params( multiple_delay_t *ptObj; )) EXTERN_EPOOL(multiple_delay_item_heap_t, multiple_delay_item_t) END_EXTERN_EPOOL(multiple_delay_item_heap_t) //! \name multiple delay service control block //! @{ extern_class(multiple_delay_t, which ( inherit( fsm(multiple_delay_task)) inherit( EPOOL(multiple_delay_item_heap_t) )), //!< fsm for multiple delay task)) multiple_delay_item_t *ptHighPriorityDelayList; //!< hight priority list multiple_delay_item_t *ptDelayList; //!< normal priority list struct { multiple_delay_item_t *ptHead; //!< timeout list Head multiple_delay_item_t *ptTail; //!< timeout list Tail } LowPriorityEvent; struct { multiple_delay_item_t *ptHead; //!< timeout list Head multiple_delay_item_t *ptTail; //!< timeout list Tail } NormalPriorityEvent; uint32_t wOldCounter; //!< Old tick counter number uint32_t wCounter; //!< Tick Counter uint32_t wSavedCounter; ) end_extern_class(multiple_delay_t) //! @} typedef struct { union { mem_block_t; mem_block_t tHeapBuffer; }; }multiple_delay_cfg_t; def_interface(i_multiple_delay_t) bool (*Init) (multiple_delay_t *, multiple_delay_cfg_t *); fsm_rt_t (*Task) (multiple_delay_t *); multiple_delay_item_t * (*RequestDelay) (multiple_delay_t * , uint32_t wDelay , multiple_delay_request_priority_t tPriority,//!< request priority void *pTag ,//!< object passed to timeout event handler timeout_event_handler_t *fnHandler); void (*Cancel) (multiple_delay_t *ptObj, multiple_delay_item_t *ptItem); struct { void (*TimerTickService)(multiple_delay_t *); } Dependent; end_def_interface(i_multiple_delay_t) /*============================ PROTOTYPES ====================================*/ /*============================ GLOBAL VARIABLES ==============================*/ extern const i_multiple_delay_t MULTIPLE_DELAY; #endif #endif /* EOF */ ================================================ FILE: sources/gmsi/service/time/time.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /* EOF */ ================================================ FILE: sources/gmsi/service/time/time.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __SERVICE_TIME_H__ #define __SERVICE_TIME_H__ /*============================ INCLUDES ======================================*/ #include ".\app_cfg.h" #include ".\multiple_delay\multiple_delay.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/app_type.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __APP_TYPE_H_INCLUDED__ #define __APP_TYPE_H_INCLUDED__ /*============================ INCLUDES ======================================*/ #include #include #include /*============================ MACROS ========================================*/ //! \name boolean value //! @{ #ifndef false # define false 0x00 #endif #ifdef true #undef true #endif #define true (!false) //! @} #ifndef NULL # define NULL ((void*)0) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define GET_U16_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 8) | \ ((*((uint8_t *)(p) + 1)) << 0)) #define GET_U24_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 16) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 0)) #define GET_U32_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 24) | \ ((*((uint8_t *)(p) + 1)) << 16) | \ ((*((uint8_t *)(p) + 2)) << 8) | \ ((*((uint8_t *)(p) + 3)) << 0)) #define GET_U16_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8)) #define GET_U24_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 16)) #define GET_U32_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 16) | \ ((*((uint8_t *)(p) + 3)) << 24)) #define SET_U16_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint16_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint16_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U24_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U32_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 24) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 3) = (((uint32_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U16_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint16_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint16_t)(v)) >> 8) & 0xFF;\ } while (0) #define SET_U24_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 16) & 0xFF;\ } while (0) #define SET_U32_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 3) = (((uint32_t)(v)) >> 24) & 0xFF;\ } while (0) #define GET_LE_U16(p) GET_U16_LSBFIRST(p) #define GET_LE_U24(p) GET_U24_LSBFIRST(p) #define GET_LE_U32(p) GET_U32_LSBFIRST(p) #define GET_BE_U16(p) GET_U16_MSBFIRST(p) #define GET_BE_U24(p) GET_U24_MSBFIRST(p) #define GET_BE_U32(p) GET_U32_MSBFIRST(p) #define SET_LE_U16(p, v) SET_U16_LSBFIRST(p, v) #define SET_LE_U24(p, v) SET_U24_LSBFIRST(p, v) #define SET_LE_U32(p, v) SET_U32_LSBFIRST(p, v) #define SET_BE_U16(p, v) SET_U16_MSBFIRST(p, v) #define SET_BE_U24(p, v) SET_U24_MSBFIRST(p, v) #define SET_BE_U32(p, v) SET_U32_MSBFIRST(p, v) #define SWAP_U16(v) ((((uint16_t)(v) & 0xFF00) >> 8) | \ (((uint16_t)(v) & 0x00FF) << 8)) #define SWAP_U24(v) ((((uint32_t)(v) & 0x00FF0000) >> 16) | \ (((uint32_t)(v) & 0x0000FF00) << 0) | \ (((uint32_t)(v) & 0x000000FF) << 16)) #define SWAP_U32(v) ((((uint32_t)(v) & 0xFF000000) >> 24) | \ (((uint32_t)(v) & 0x00FF0000) >> 8) | \ (((uint32_t)(v) & 0x0000FF00) << 8) | \ (((uint32_t)(v) & 0x000000FF) << 24)) #if defined(__BIG_ENDIAN__) && (__BIG_ENDIAN__ == 1) # define LE_TO_SYS_U16(v) SWAP_U16(v) # define LE_TO_SYS_U24(v) SWAP_U24(v) # define LE_TO_SYS_U32(v) SWAP_U32(v) # define BE_TO_SYS_U16(v) ((uint16_t)(v)) # define BE_TO_SYS_U24(v) ((uint32_t)(v)) # define BE_TO_SYS_U32(v) ((uint32_t)(v)) # define SYS_TO_LE_U16(v) SWAP_U16(v) # define SYS_TO_LE_U24(v) SWAP_U24(v) # define SYS_TO_LE_U32(v) SWAP_U32(v) # define SYS_TO_BE_U16(v) ((uint16_t)(v)) # define SYS_TO_BE_U24(v) ((uint32_t)(v)) # define SYS_TO_BE_U32(v) ((uint32_t)(v)) # define GET_SYS_U16(p) GET_BE_U16(p) # define GET_SYS_U24(p) GET_BE_U24(p) # define GET_SYS_U32(p) GET_BE_U32(p) #else # define LE_TO_SYS_U16(v) ((uint16_t)(v)) # define LE_TO_SYS_U24(v) ((uint32_t)(v)) # define LE_TO_SYS_U32(v) ((uint32_t)(v)) # define BE_TO_SYS_U16(v) SWAP_U16(v) # define BE_TO_SYS_U24(v) SWAP_U24(v) # define BE_TO_SYS_U32(v) SWAP_U32(v) # define SYS_TO_LE_U16(v) ((uint16_t)(v)) # define SYS_TO_LE_U24(v) ((uint32_t)(v)) # define SYS_TO_LE_U32(v) ((uint32_t)(v)) # define SYS_TO_BE_U16(v) SWAP_U16(v) # define SYS_TO_BE_U24(v) SWAP_U24(v) # define SYS_TO_BE_U32(v) SWAP_U32(v) # define GET_SYS_U16(p) GET_LE_U16(p) # define GET_SYS_U24(p) GET_LE_U24(p) # define GET_SYS_U32(p) GET_LE_U32(p) #endif #define IS_FSM_ERR(__FSM_RT) ((__FSM_RT) < fsm_rt_cpl) #define is_fsm_err(__FSM_RT) IS_FSM_ERR(__FSM_RT) /*============================ TYPES =========================================*/ #ifndef __FSM_RT_TYPE__ #define __FSM_RT_TYPE__ //! \name finit state machine state //! @{ typedef enum { fsm_rt_err = -1, //!< fsm error, error code can be get from other interface fsm_rt_cpl = 0, //!< fsm complete fsm_rt_on_going = 1, //!< fsm on-going fsm_rt_wait_for_obj = 2, //!< fsm wait for object fsm_rt_asyn = 3, //!< fsm asynchronose complete, you can check it later. } fsm_rt_t; //! @} #endif #define __REG_TYPE__ typedef volatile unsigned char reg8_t; typedef volatile unsigned short reg16_t; typedef volatile unsigned int reg32_t; /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif // __APP_TYPE_H_INCLUDED__ ================================================ FILE: sources/gmsi/utilities/arm/arm_compiler.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_ARM_COMPILER_H__ #define __USE_ARM_COMPILER_H__ /*============================ INCLUDES ======================================*/ #include #include #include #include #include #include "cmsis_compiler.h" //! \name The macros to identify the compiler //! @{ //! \note for IAR #ifdef __IS_COMPILER_IAR__ # undef __IS_COMPILER_IAR__ #endif #if defined(__IAR_SYSTEMS_ICC__) # define __IS_COMPILER_IAR__ 1 #endif //! \note for arm compiler 5 #ifdef __IS_COMPILER_ARM_COMPILER_5__ # undef __IS_COMPILER_ARM_COMPILER_5__ #endif #if ((__ARMCC_VERSION >= 5000000) && (__ARMCC_VERSION < 6000000)) # define __IS_COMPILER_ARM_COMPILER_5__ 1 #endif //! @} //! \note for arm compiler 6 #ifdef __IS_COMPILER_ARM_COMPILER_6__ # undef __IS_COMPILER_ARM_COMPILER_6__ #endif #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) # define __IS_COMPILER_ARM_COMPILER_6__ 1 #endif #ifdef __IS_COMPILER_LLVM__ # undef __IS_COMPILER_LLVM__ #endif #if defined(__clang__) && !__IS_COMPILER_ARM_COMPILER_6__ # define __IS_COMPILER_LLVM__ 1 #else //! \note for gcc # ifdef __IS_COMPILER_GCC__ # undef __IS_COMPILER_GCC__ # endif # if defined(__GNUC__) && !( defined(__IS_COMPILER_ARM_COMPILER_5__) \ || defined(__IS_COMPILER_ARM_COMPILER_6__) \ || defined(__IS_COMPILER_LLVM__)) # define __IS_COMPILER_GCC__ 1 # endif //! @} #endif //! @} #if __IS_COMPILER_IAR__ # include #endif /* ----------------- Start of section using anonymous unions -------------- */ #if __IS_COMPILER_ARM_COMPILER_5__ //#pragma push #pragma anon_unions #elif __IS_COMPILER_ARM_COMPILER_6__ #elif __IS_COMPILER_IAR__ #pragma language=extended #elif __IS_COMPILER_GCC__ /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning 586 #else #warning Not supported compiler type #endif /*----------------------------------------------------------------------------* * Warning Mitigation * *----------------------------------------------------------------------------*/ #if defined(__clang__) //__IS_COMPILER_LLVM__ #pragma clang diagnostic ignored "-Wcompound-token-split-by-macro" #pragma clang diagnostic ignored "-Wmissing-declarations" #pragma clang diagnostic ignored "-Wdeprecated-declarations" #pragma clang diagnostic ignored "-Wmicrosoft-anon-tag" #pragma clang diagnostic ignored "-Wmissing-braces" #pragma clang diagnostic ignored "-Wconstant-conversion" #pragma clang diagnostic ignored "-Wmicrosoft-enum-forward-reference" #pragma clang diagnostic ignored "-Wbuiltin-requires-header" #pragma clang diagnostic ignored "-Winitializer-overrides" #pragma clang diagnostic ignored "-Wbraced-scalar-init" #pragma clang diagnostic ignored "-Wempty-body" #pragma clang diagnostic ignored "-Wgnu-empty-struct" #pragma clang diagnostic ignored "-Wint-conversion" #pragma clang diagnostic ignored "-Wint-to-pointer-cast" #pragma clang diagnostic ignored "-Wmicrosoft-include" #pragma clang diagnostic ignored "-Wpragma-pack" #pragma clang diagnostic ignored "-Wunused-function" #pragma clang diagnostic ignored "-Wswitch" #pragma clang diagnostic ignored "-Wembedded-directive" #pragma clang diagnostic ignored "-Wundef" #pragma clang diagnostic ignored "-Wgnu-zero-variadic-macro-arguments" #pragma clang diagnostic ignored "-Wpadded" #pragma clang diagnostic ignored "-Wnewline-eof" #pragma clang diagnostic ignored "-Wduplicate-enum" #pragma clang diagnostic ignored "-Wextra-semi" #pragma clang diagnostic ignored "-Wextra-semi-stmt" #pragma clang diagnostic ignored "-Wzero-length-array" #pragma clang diagnostic ignored "-Wmissing-prototypes" #pragma clang diagnostic ignored "-Wimplicit-int-conversion" #pragma clang diagnostic ignored "-Wnonportable-include-path" #pragma clang diagnostic ignored "-Wmissing-variable-declarations" #pragma clang diagnostic ignored "-Wc++-compat" #pragma clang diagnostic ignored "-Wsign-conversion" #pragma clang diagnostic ignored "-Wimplicit-fallthrough" #pragma clang diagnostic ignored "-Wmissing-noreturn" #pragma clang diagnostic ignored "-Wcast-qual" #pragma clang diagnostic ignored "-Wbad-function-cast" #pragma clang diagnostic ignored "-Wswitch-enum" #pragma clang diagnostic ignored "-Wdisabled-macro-expansion" #pragma clang diagnostic ignored "-Wmissing-field-initializers" #pragma clang diagnostic ignored "-Wtautological-pointer-compare" /*! \NOTE do not ignore following warning unless you take the risk by yourself */ //#pragma clang diagnostic ignored "-Wbitfield-constant-conversion" //#pragma clang diagnostic ignored "-Wpointer-integer-compare" //#pragma clang diagnostic ignored "-Wunused-value" //#pragma clang diagnostic ignored "-Wno-sometimes-uninitialized" //#pragma clang diagnostic ignored "-Wdeprecated-declarations" //#pragma clang diagnostic ignored "-Wunused-variable" #elif __IS_COMPILER_GCC__ // TODO: validate diagnositc ignored for GCC #pragma gcc diagnostic ignored "-Wmissing-declarations" #pragma gcc diagnostic ignored "-Wdeprecated-declarations" #pragma gcc diagnostic ignored "-Wmicrosoft-anon-tag" #pragma gcc diagnostic ignored "-Wmissing-braces" #pragma gcc diagnostic ignored "-Wconstant-conversion" #pragma gcc diagnostic ignored "-Wmicrosoft-enum-forward-reference" #pragma gcc diagnostic ignored "-Wbuiltin-requires-header" #pragma gcc diagnostic ignored "-Winitializer-overrides" #pragma gcc diagnostic ignored "-Wbraced-scalar-init" #pragma gcc diagnostic ignored "-Wempty-body" #pragma gcc diagnostic ignored "-Wgnu-empty-struct" #pragma gcc diagnostic ignored "-Wint-conversion" #pragma gcc diagnostic ignored "-Wint-to-pointer-cast" #pragma gcc diagnostic ignored "-Wmicrosoft-include" #pragma gcc diagnostic ignored "-Wpragma-pack" #pragma gcc diagnostic ignored "-Wunused-function" #pragma gcc diagnostic ignored "-Wswitch" #pragma gcc diagnostic ignored "-Wembedded-directive" #pragma gcc diagnostic ignored "-Wundef" #pragma gcc diagnostic ignored "-Wgnu-zero-variadic-macro-arguments" #pragma gcc diagnostic ignored "-Wpadded" #pragma gcc diagnostic ignored "-Wnewline-eof" #pragma gcc diagnostic ignored "-Wduplicate-enum" #pragma gcc diagnostic ignored "-Wextra-semi" #pragma gcc diagnostic ignored "-Wextra-semi-stmt" #pragma gcc diagnostic ignored "-Wzero-length-array" #pragma gcc diagnostic ignored "-Wmissing-prototypes" #pragma gcc diagnostic ignored "-Wimplicit-int-conversion" #pragma gcc diagnostic ignored "-Wnonportable-include-path" #pragma gcc diagnostic ignored "-Wmissing-variable-declarations" #pragma gcc diagnostic ignored "-Wc++-compat" #pragma gcc diagnostic ignored "-Wsign-conversion" #pragma gcc diagnostic ignored "-Wimplicit-fallthrough" #pragma gcc diagnostic ignored "-Wmissing-noreturn" #pragma gcc diagnostic ignored "-Wcast-qual" #pragma gcc diagnostic ignored "-Wbad-function-cast" #pragma gcc diagnostic ignored "-Wswitch-enum" #pragma gcc diagnostic ignored "-Wdisabled-macro-expansion" #pragma gcc diagnostic ignored "-Wmissing-field-initializers" #pragma gcc diagnostic ignored "-Wtautological-pointer-compare" /*! \NOTE do not ignore following warning unless you take the risk by yourself */ //#pragma gcc diagnostic ignored "-Wbitfield-constant-conversion" //#pragma gcc diagnostic ignored "-Wpointer-integer-compare" //#pragma gcc diagnostic ignored "-Wunused-value" //#pragma gcc diagnostic ignored "-Wno-sometimes-uninitialized" //#pragma gcc diagnostic ignored "-Wdeprecated-declarations" //#pragma gcc diagnostic ignored "-Wunused-variable" #elif __IS_COMPILER_IAR__ //! undefined behavior: the order of volatile accesses is undefined in this statement #pragma diag_suppress=Pa082 //! Typedef name has already been declared (with same type) #pragma diag_suppress=pe301 //! enumerated type mixed with another type #pragma diag_suppress=pe188 //! extra ";" ignored #pragma diag_suppress=pe381 //! enumerated type mixed with another enumerated type #pragma diag_suppress=pa089 //! use of address of unaligned structure member #pragma diag_suppress=pa039 //,Pe186,Pe111,,pe128,,,Pe1866,Pe064,Pa039 #endif #if __IS_COMPILER_ARM_COMPILER_6__ # pragma clang diagnostic ignored "-Wdollar-in-identifier-extension" #endif /*----------------------------------------------------------------------------* * Warning Emphasize * *----------------------------------------------------------------------------*/ #if defined(__clang__) //__IS_COMPILER_LLVM__ #pragma clang diagnostic warning "-Wcast-align" #elif __IS_COMPILER_GCC__ #endif /*============================ MACROS ========================================*/ #ifndef DEF_REG #define DEF_REG \ union { \ struct { #endif #ifndef END_DEF_REG #define END_DEF_REG(__NAME) \ }; \ reg32_t Value; \ }__NAME; #endif #ifndef __REG_MACRO__ #define __REG_MACRO__ #endif #ifndef REG_RSVD_0x10 #define REG_RSVD_0x10 \ reg32_t : 32; \ reg32_t : 32; \ reg32_t : 32; \ reg32_t : 32; #endif #ifndef REG_RSVD_0x80 #define REG_RSVD_0x80 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 \ REG_RSVD_0x10 #endif #ifndef REG_RSVD_0x100 #define REG_RSVD_0x100 \ REG_RSVD_0x80 \ REG_RSVD_0x80 #endif #ifndef REG_RSVD_0x800 #define REG_RSVD_0x800 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 \ REG_RSVD_0x100 #endif //! \brief The mcu memory align mode # define MCU_MEM_ALIGN_SIZE sizeof(int) #ifndef __volatile__ #define __volatile__ volatile #endif //! \brief 1 cycle nop operation #ifndef NOP #define NOP() __asm__ __volatile__ ("nop"); #endif //! \brief none standard memory types #if __IS_COMPILER_IAR__ # define ROM_FLASH _Pragma(__STR(location=".rom.flash")) const # define ROM_EEPROM _Pragma(__STR(location=".rom.eeprom")) const # define NO_INIT __no_init # define ROOT __root # define INLINE inline # define NO_INLINE __attribute__((noinline)) # define ALWAYS_INLINE inline __attribute__((always_inline)) # define WEAK __weak # define RAMFUNC __ramfunc # define __asm__ __asm # define __ALIGN(__N) __attribute__((aligned (__N))) # define __AT_ADDR(__ADDR) @ __ADDR # define __SECTION(__SEC) __attribute__((section (__SEC))) # define __WEAK_ALIAS(__ORIGIN, __ALIAS) \ _Pragma(__STR(weak __ORIGIN=__ALIAS)) # define PACKED __attribute__((packed)) # define UNALIGNED __attribute__((packed)) # define TRANSPARENT_UNION __attribute__((transparent_union)) #elif __IS_COMPILER_ARM_COMPILER_5__ # define ROM_FLASH __attribute__(( section( ".rom.flash"))) const # define ROM_EEPROM __attribute__(( section( ".rom.eeprom"))) const # define NO_INIT __attribute__( ( section( ".bss.noinit"),zero_init) ) # define ROOT __attribute__((used)) # define INLINE __inline # define NO_INLINE __attribute__((noinline)) # define ALWAYS_INLINE __inline __attribute__((always_inline)) # define WEAK __attribute__((weak)) # define RAMFUNC __attribute__((section (".textrw"))) # define __asm__ __asm # define __ALIGN(__N) __attribute__((aligned (__N))) # define __AT_ADDR(__ADDR) __attribute__((at(__ADDR))) # define __SECTION(__SEC) __attribute__((section (__SEC))) # define __WEAK_ALIAS(__ORIGIN, __ALIAS) \ __attribute__((weakref(__STR(__ALIAS)))) # define PACKED __attribute__((packed)) # define UNALIGNED __attribute__((packed)) # define TRANSPARENT_UNION __attribute__((transparent_union)) #elif __IS_COMPILER_ARM_COMPILER_6__ # define ROM_FLASH __attribute__(( section( ".rom.flash"))) const # define ROM_EEPROM __attribute__(( section( ".rom.eeprom"))) const # define NO_INIT __attribute__( ( section( ".bss.noinit")) ) # define ROOT __attribute__((used)) # define INLINE __inline # define NO_INLINE __attribute__((noinline)) # define ALWAYS_INLINE __inline __attribute__((always_inline)) # define WEAK __attribute__((weak)) # define RAMFUNC __attribute__((section (".textrw"))) # define __asm__ __asm # define __ALIGN(__N) __attribute__((aligned (__N))) # define __AT_ADDR(__ADDR) __attribute__((section (".ARM.__at_" #__ADDR))) # define __SECTION(__SEC) __attribute__((section (__SEC))) # define __WEAK_ALIAS(__ORIGIN, __ALIAS) \ __attribute__((weakref(__STR(__ALIAS)))) # define PACKED __attribute__((packed)) # define UNALIGNED __unaligned # define TRANSPARENT_UNION __attribute__((transparent_union)) #elif __IS_COMPILER_LLVM__ # define ROM_FLASH __attribute__(( __section__( ".rom.flash"))) const # define ROM_EEPROM __attribute__(( __section__( ".rom.eeprom"))) const # define NO_INIT __attribute__(( __section__( ".bss.noinit"))) # define ROOT __used # define INLINE inline # define NO_INLINE __noinline # define ALWAYS_INLINE __always_inline # define WEAK __weak_symbol # define RAMFUNC __attribute__((__section__ (".textrw"))) # define __asm__ __asm # define __ALIGN(__N) __aligned(__N) # define __AT_ADDR(__ADDR) __section(".ARM.__at_" #__ADDR) # define __SECTION(__SEC) __section(__SEC) # define __WEAK_ALIAS(__ORIGIN, __ALIAS) \ __weak_reference(__ORIGIN,__ALIAS) # define PACKED __packed # define UNALIGNED __packed # define TRANSPARENT_UNION __attribute__((__transparent_union__)) #else /*__IS_COMPILER_GCC__: Using GCC as default for those GCC compliant compilers*/ # define ROM_FLASH __attribute__(( section( ".rom.flash"))) const # define ROM_EEPROM __attribute__(( section( ".rom.eeprom"))) const # define NO_INIT __attribute__(( section( ".bss.noinit"))) # define ROOT __attribute__((used)) # define INLINE inline # define NO_INLINE __attribute__((noinline)) # define ALWAYS_INLINE inline __attribute__((always_inline)) # define WEAK __attribute__((weak)) # define RAMFUNC __attribute__((section (".textrw"))) # define __asm__ __asm # define __ALIGN(__N) __attribute__((aligned (__N))) # define __AT_ADDR(__ADDR) __section(".ARM.__at_" #__ADDR) # define __SECTION(__SEC) __attribute__((section (__SEC))) # define __WEAK_ALIAS(__ORIGIN, __ALIAS) \ __attribute__((weakref(__STR(__ALIAS)))) # define PACKED __attribute__((packed)) # define UNALIGNED __attribute__((packed)) # define TRANSPARENT_UNION __attribute__((transparent_union)) #endif #define WEAK_ALIAS(__ORIGIN, __ALIAS) \ __WEAK_ALIAS(__ORIGIN, __ALIAS) #define AT_ADDR(__ADDR) __AT_ADDR(__ADDR) #define ALIGN(__N) __ALIGN(__N) #define SECTION(__SEC) __SECTION(__SEC) /*----------------------------------------------------------------------------* * Signal & Interrupt Definition * *----------------------------------------------------------------------------*/ /*!< Macro to enable all interrupts. */ #if __IS_COMPILER_IAR__ # define ENABLE_GLOBAL_INTERRUPT() __enable_interrupt() #else # define ENABLE_GLOBAL_INTERRUPT() __enable_irq() #endif /*!< Macro to disable all interrupts. */ #if __IS_COMPILER_IAR__ # define DISABLE_GLOBAL_INTERRUPT() ____disable_irq() static ALWAYS_INLINE uint32_t ____disable_irq(void) { uint32_t wPRIMASK = __get_interrupt_state(); __disable_irq(); return wPRIMASK & 0x1; } #elif __IS_COMPILER_ARM_COMPILER_5__ # define DISABLE_GLOBAL_INTERRUPT() __disable_irq() #elif __IS_COMPILER_ARM_COMPILER_6__ && !defined(__CMSIS_ARMCC_V6_H) # define DISABLE_GLOBAL_INTERRUPT() __disable_irq() #elif __IS_COMPILER_GCC_ # define DISABLE_GLOBAL_INTERRUPT() __disable_irq() #else /* for other compilers, using gcc assembly syntax to implement */ # define DISABLE_GLOBAL_INTERRUPT() ____disable_irq() static ALWAYS_INLINE uint32_t ____disable_irq(void) { uint32_t cpsr; __asm__ __volatile__("mrs %[cpsr], primask\n" "cpsid i\n" : [cpsr] "=r"(cpsr)); return cpsr & 0x1; } #endif #if __IS_COMPILER_IAR__ # define GET_GLOBAL_INTERRUPT_STATE() __get_interrupt_state() # define SET_GLOBAL_INTERRUPT_STATE(__STATE) __set_interrupt_state(__STATE) typedef __istate_t istate_t; #elif __IS_COMPILER_ARM_COMPILER_5__ || __IS_COMPILER_ARM_COMPILER_6__ # define GET_GLOBAL_INTERRUPT_STATE() __get_PRIMASK() # define SET_GLOBAL_INTERRUPT_STATE(__STATE) __set_PRIMASK(__STATE) typedef int istate_t; #elif __IS_COMPILER_GCC__ # define GET_GLOBAL_INTERRUPT_STATE() __get_PRIMASK() # define SET_GLOBAL_INTERRUPT_STATE(__STATE) __set_PRIMASK(__STATE) typedef uint32_t istate_t; #else typedef uint32_t istate_t; # define GET_GLOBAL_INTERRUPT_STATE() ____get_PRIMASK() /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__((always_inline)) static inline uint32_t ____get_PRIMASK(void) { unsigned int result; __asm__ volatile ("MRS %0, primask" : "=r" (result) ); return(result); } # define SET_GLOBAL_INTERRUPT_STATE(__STATE) ____set_PRIMASK(__STATE) /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__((always_inline)) static inline void ____set_PRIMASK(uint32_t priMask) { __asm__ volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #endif /*----------------------------------------------------------------------------* * Startup Source Code * *----------------------------------------------------------------------------*/ #if __IS_COMPILER_IAR__ #ifndef __VECTOR_TABLE # define __VECTOR_TABLE __vector_table #endif #ifndef __VECTOR_TABLE_ATTRIBUTE # define __VECTOR_TABLE_ATTRIBUTE @".intvec" #endif #ifndef __PROGRAM_START # define __PROGRAM_START __iar_program_start #endif #ifndef __INITIAL_SP # define __INITIAL_SP CSTACK$$Limit #endif #elif __IS_COMPILER_ARM_COMPILER_6__ || __IS_COMPILER_ARM_COMPILER_5__ #ifndef __VECTOR_TABLE # define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE # define __VECTOR_TABLE_ATTRIBUTE ROOT SECTION("RESET") #endif #ifndef __PROGRAM_START # define __PROGRAM_START __main #endif #ifndef __INITIAL_SP # define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #elif //__IS_COMPILER_GCC__ || __IS_COMPILER_LLVM__ # error Unsupported compiler detected. Please contact vsf team for support. #endif #define __GMSI_ARCH_HEADER "arm/cortex-m/arch_cortex-m.h" /*============================ TYPES =========================================*/ /*============================ INCLUDES ======================================*/ //! \brief for interrupt #include "./signal.h" /*============================ PROTOTYPES ====================================*/ #endif ================================================ FILE: sources/gmsi/utilities/arm/signal.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include "../compiler.h" #include "../ooc.h" #include "../app_type.h" #include "signal.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ PROTOTYPES ====================================*/ static void __default_code_region_atom_code_on_enter(void *pObj, void *pLocal); static void __default_code_region_atom_code_on_leave(void *pObj,void *pLocal); static void __default_code_region_none_on_enter(void *pObj, void *pLocal); static void __default_code_region_none_on_leave(void *pObj,void *pLocal); /*============================ LOCAL VARIABLES ===============================*/ /*============================ GLOBAL VARIABLES ==============================*/ static const i_code_region_t i_DefaultCodeRegionAtomCode = { .chLocalObjSize = sizeof(istate_t), .OnEnter = &__default_code_region_atom_code_on_enter, .OnLeave = &__default_code_region_atom_code_on_leave, }; static const i_code_region_t i_DefaultCodeRegionNone = { .chLocalObjSize = 4, .OnEnter = &__default_code_region_none_on_enter, .OnLeave = &__default_code_region_none_on_leave, }; const code_region_t DEFAULT_CODE_REGION_ATOM_CODE = { .pTarget = NULL, .ptMethods = (i_code_region_t *)&i_DefaultCodeRegionAtomCode, }; const code_region_t DEFAULT_CODE_REGION_NONE = { .pTarget = NULL, .ptMethods = (i_code_region_t *)&i_DefaultCodeRegionNone, }; /*============================ IMPLEMENTATION ================================*/ static void __default_code_region_atom_code_on_enter(void *pObj, void *pLocal) { istate_t *ptState = (istate_t *)pLocal; assert(NULL != pLocal); (*ptState) = GET_GLOBAL_INTERRUPT_STATE(); DISABLE_GLOBAL_INTERRUPT(); } static void __default_code_region_atom_code_on_leave(void *pObj,void *pLocal) { istate_t *ptState = (istate_t *)pLocal; assert(NULL != pLocal); SET_GLOBAL_INTERRUPT_STATE(*ptState); } static void __default_code_region_none_on_enter(void *pObj, void *pLocal) { } static void __default_code_region_none_on_leave(void *pObj,void *pLocal) { } /*! \brief initialize a locker *! \param ptLock locker object *! \return none */ void init_lock(locker_t *ptLock) { if (NULL == ptLock) { return ; } (*ptLock) = UNLOCKED; } /*! \brief try to enter a section *! \param ptLock locker object *! \retval lock section is entered *! \retval The section is locked */ bool enter_lock(locker_t *ptLock) { bool bResult = false; if (NULL == ptLock) { return true; } if (UNLOCKED == (*ptLock)) { __IRQ_SAFE { if (UNLOCKED == (*ptLock)) { (*ptLock) = LOCKED; bResult = true; } }; } return bResult; } /*! \brief leave a section *! \param ptLock locker object *! \return none */ void leave_lock(locker_t *ptLock) { if (NULL == ptLock) { return ; } (*ptLock) = UNLOCKED; } /*! \brief get locker status *! \param ptLock locker object *! \return locker status */ bool check_lock(locker_t *ptLock) { if (NULL == ptLock) { return false; } return (*ptLock); } /* EOF */ ================================================ FILE: sources/gmsi/utilities/arm/signal.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_SIGNAL_H_ #define _USE_SIGNAL_H_ /*============================ INCLUDES ======================================*/ #include #include #include "../preprocessor/preprocessor.h" /*! \brief How To Define and Use your own CODE_REGION *! Example: static void __code_region_example_on_enter(void *pObj, void *pLocal) { printf("-------enter-------\r\n"); } static void __code_region_example_on_leave(void *pObj,void *pLocal) { printf("-------leave-------\r\n"); } const static i_code_region_t __example_code_region = { .OnEnter = __code_region_example_on_enter, .OnLeave = __code_region_example_on_leave, }; void main(void) { ... code_region(&__example_code_region, NULL){ printf("\tbody\r\n"); } ... } Output: -------enter------- body -------leave------- *! \note How to use code_region() *! Syntax: *! code_region(
, ) { *! //! put your code here *! } *! *! \note
: this can be NULL, if so, *! DEFAULT_CODE_REGION_NONE will be used. *! *! \note : it is the address of the object you want to pass to *! your OnEnter and OnLeave functions. It can be NULL *! *! \note A local object will be generated from users' stack, the size is specified *! by i_code_region_t.chLocalSize. The address of this local object will *! be passed to your OnEnter and OnLeave functions. You can use it to *! store some local status. *! *! \name List of Default Code Regions *! @{ *! DEFAULT_CODE_REGION_ATOM_CODE //!< interrupt-safe region *! DEFAULT_CODE_REGION_NONE //!< do nothing *! @} */ /*============================ MACROS ========================================*/ #ifndef IAR_PATCH_CODE_REGION_LOCAL_SIZE # define IAR_PATCH_CODE_REGION_LOCAL_SIZE 4 #endif /*============================ MACROFIED FUNCTIONS ===========================*/ //! \brief The safe ATOM code section macro #define SAFE_ATOM_CODE() code_region(&DEFAULT_CODE_REGION_ATOM_CODE) #define __SAFE_ATOM_CODE(...) \ { \ istate_t tState = GET_GLOBAL_INTERRUPT_STATE(); \ DISABLE_GLOBAL_INTERRUPT(); \ __VA_ARGS__; \ SET_GLOBAL_INTERRUPT_STATE(tState); \ } //! \brief Exit from the safe atom operations #define EXIT_SAFE_ATOM_CODE() SET_GLOBAL_INTERRUPT_STATE(tState) #define exit_safe_atom_code() EXIT_SAFE_ATOM_CODE() #define safe_atom_code() SAFE_ATOM_CODE() #define __safe_atom_code(...) __SAFE_ATOM_CODE(__VA_ARGS__) //! \name ES_LOCKER value //! @{ #define LOCKED true //!< locked #define UNLOCKED false //!< unlocked //! @} #define LOCK_INIT(__LOCKER) do {(__LOCKER) = UNLOCKED;}while(false) #define EXIT_LOCK() do {\ (*pLocker) = UNLOCKED;\ SET_GLOBAL_INTERRUPT_STATE(tState);\ } while(false) #define ENTER_LOCK(__LOCKER) enter_lock(__LOCKER) #define LEAVE_LOCK(__LOCKER) leave_lock(__LOCKER) #define GET_LOCK_STATUS(__LOCKER) check_lock(__LOCKER) #define INIT_LOCK(__LOCKER) init_lock(__LOCKER) //! \brief exit lock checker structure #define EXIT_LOCK_CHECKER() EXIT_SAFE_ATOM_CODE() /*! \note check specified locker and run code segment *! \param __LOCKER a ES_LOCKER variable *! \param __CODE target code segment */ #define LOCK_CHECKER(__LOCKER, ...) { \ { \ locker_t *pLocker = &(__LOCKER); \ if (UNLOCKED == (*pLocker)) \ { \ SAFE_ATOM_CODE( \ if (UNLOCKED == (*pLocker)) { \ __VA_ARGS__; \ } \ ) \ } \ } //! \note critical code section protection //! \note LOCKER could be only used among FSMs and there should be no ISR involved. //! \param __LOCKER ES_LOCKER variable //! \param __CODE target code segment #define LOCK(__LOCKER,...) \ LOCK_CHECKER((__LOCKER), \ (*pLocker) = LOCKED; \ ENABLE_GLOBAL_INTERRUPT(); \ __VA_ARGS__; \ (*pLocker) = UNLOCKED; \ ) #if __IS_COMPILER_IAR__ # define __CODE_REGION(__REGION_ADDR) \ for(code_region_t *ptCodeRegion = (code_region_t *)(__REGION_ADDR); \ NULL != ptCodeRegion; \ ptCodeRegion = NULL) \ for(uint8_t chLocal[IAR_PATCH_CODE_REGION_LOCAL_SIZE], \ CONNECT2(__code_region_, __LINE__) = 1; \ CONNECT2(__code_region_, __LINE__)-- ? \ (ptCodeRegion->ptMethods->OnEnter( ptCodeRegion->pTarget, \ chLocal) \ ,1) \ : 0; \ ptCodeRegion->ptMethods->OnLeave(ptCodeRegion->pTarget, chLocal)) #else # define __CODE_REGION(__REGION_ADDR) \ for(code_region_t *ptCodeRegion = (code_region_t *)(__REGION_ADDR); \ NULL != ptCodeRegion; \ ptCodeRegion = NULL) \ for(uint8_t chLocal[ptCodeRegion->ptMethods->chLocalObjSize], \ CONNECT2(__code_region_, __LINE__) = 1; \ CONNECT2(__code_region_, __LINE__)-- ? \ (ptCodeRegion->ptMethods->OnEnter( ptCodeRegion->pTarget, \ chLocal) \ ,1) \ : 0; \ ptCodeRegion->ptMethods->OnLeave(ptCodeRegion->pTarget, chLocal)) #endif #define EXIT_CODE_REGION() \ ptCodeRegion->ptMethods->OnLeave(tCodeRegion.pTarget, chLocal) #define exit_code_region() EXIT_CODE_REGION() #define CODE_REGION(__REGION_ADDR) __CODE_REGION((__REGION_ADDR)) #define code_region(__REGION_ADDR) __CODE_REGION((__REGION_ADDR)) #define CODE_REGION_SIMPLE(__REGION_ADDR, ...) \ __CODE_REGION_SIMPLE((__REGION_ADDR), __VA_ARGS__) #define code_region_simple(__REGION_ADDR, ...) \ __CODE_REGION_SIMPLE((__REGION_ADDR), __VA_ARGS__) #ifndef __IRQ_SAFE # define __IRQ_SAFE \ using( uint32_t CONNECT2(temp,__LINE__) = \ ({uint32_t temp=__get_PRIMASK();__disable_irq();temp;}),\ __set_PRIMASK(CONNECT2(temp,__LINE__))) #endif /*============================ TYPES =========================================*/ typedef volatile bool locker_t; typedef struct { uint_fast8_t chLocalObjSize; void (*OnEnter)(void *pObj, void *pLocal); void (*OnLeave)(void *pObj, void *pLocal); }i_code_region_t; typedef struct { void *pTarget; i_code_region_t *ptMethods; } code_region_t; /*============================ GLOBAL VARIABLES ==============================*/ extern const code_region_t DEFAULT_CODE_REGION_ATOM_CODE; extern const code_region_t DEFAULT_CODE_REGION_NONE; /*============================ PROTOTYPES ====================================*/ /*! \brief try to enter a section *! \param ptLock locker object *! \retval lock section is entered *! \retval The section is locked */ extern bool enter_lock(locker_t *ptLock); /*! \brief leave a section *! \param ptLock locker object *! \return none */ extern void leave_lock(locker_t *ptLock); /*! \brief get locker status *! \param ptLock locker object *! \return locker status */ extern bool check_lock(locker_t *ptLock); /*! \brief initialize a locker *! \param ptLock locker object *! \return none */ extern void init_lock(locker_t *ptLock); #endif ================================================ FILE: sources/gmsi/utilities/avr/app_type.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __APP_TYPE_H_INCLUDED__ #define __APP_TYPE_H_INCLUDED__ /*============================ INCLUDES ======================================*/ #include #include /*============================ MACROS ========================================*/ //! \name boolean value //! @{ #ifndef false # define false 0x00 #endif #ifdef true #undef true #endif #define true (!false) //! @} #ifndef NULL # define NULL ((void*)0) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define GET_U16_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 8) | \ ((*((uint8_t *)(p) + 1)) << 0)) #define GET_U24_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 16) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 0)) #define GET_U32_MSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 24) | \ ((*((uint8_t *)(p) + 1)) << 16) | \ ((*((uint8_t *)(p) + 2)) << 8) | \ ((*((uint8_t *)(p) + 3)) << 0)) #define GET_U16_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8)) #define GET_U24_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 16)) #define GET_U32_LSBFIRST(p) ( ((*((uint8_t *)(p) + 0)) << 0) | \ ((*((uint8_t *)(p) + 1)) << 8) | \ ((*((uint8_t *)(p) + 2)) << 16) | \ ((*((uint8_t *)(p) + 3)) << 24)) #define SET_U16_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint16_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint16_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U24_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U32_MSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 24) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 3) = (((uint32_t)(v)) >> 0) & 0xFF;\ } while (0) #define SET_U16_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint16_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint16_t)(v)) >> 8) & 0xFF;\ } while (0) #define SET_U24_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 16) & 0xFF;\ } while (0) #define SET_U32_LSBFIRST(p, v) \ do{\ *((uint8_t *)(p) + 0) = (((uint32_t)(v)) >> 0) & 0xFF;\ *((uint8_t *)(p) + 1) = (((uint32_t)(v)) >> 8) & 0xFF;\ *((uint8_t *)(p) + 2) = (((uint32_t)(v)) >> 16) & 0xFF;\ *((uint8_t *)(p) + 3) = (((uint32_t)(v)) >> 24) & 0xFF;\ } while (0) #define GET_LE_U16(p) GET_U16_LSBFIRST(p) #define GET_LE_U24(p) GET_U24_LSBFIRST(p) #define GET_LE_U32(p) GET_U32_LSBFIRST(p) #define GET_BE_U16(p) GET_U16_MSBFIRST(p) #define GET_BE_U24(p) GET_U24_MSBFIRST(p) #define GET_BE_U32(p) GET_U32_MSBFIRST(p) #define SET_LE_U16(p, v) SET_U16_LSBFIRST(p, v) #define SET_LE_U24(p, v) SET_U24_LSBFIRST(p, v) #define SET_LE_U32(p, v) SET_U32_LSBFIRST(p, v) #define SET_BE_U16(p, v) SET_U16_MSBFIRST(p, v) #define SET_BE_U24(p, v) SET_U24_MSBFIRST(p, v) #define SET_BE_U32(p, v) SET_U32_MSBFIRST(p, v) #define SWAP_U16(v) ((((uint16_t)(v) & 0xFF00) >> 8) | \ (((uint16_t)(v) & 0x00FF) << 8)) #define SWAP_U24(v) ((((uint32_t)(v) & 0x00FF0000) >> 16) | \ (((uint32_t)(v) & 0x0000FF00) << 0) | \ (((uint32_t)(v) & 0x000000FF) << 16)) #define SWAP_U32(v) ((((uint32_t)(v) & 0xFF000000) >> 24) | \ (((uint32_t)(v) & 0x00FF0000) >> 8) | \ (((uint32_t)(v) & 0x0000FF00) << 8) | \ (((uint32_t)(v) & 0x000000FF) << 24)) # define LE_TO_SYS_U16(v) ((uint16_t)(v)) # define LE_TO_SYS_U24(v) ((uint32_t)(v)) # define LE_TO_SYS_U32(v) ((uint32_t)(v)) # define BE_TO_SYS_U16(v) SWAP_U16(v) # define BE_TO_SYS_U24(v) SWAP_U24(v) # define BE_TO_SYS_U32(v) SWAP_U32(v) # define SYS_TO_LE_U16(v) ((uint16_t)(v)) # define SYS_TO_LE_U24(v) ((uint32_t)(v)) # define SYS_TO_LE_U32(v) ((uint32_t)(v)) # define SYS_TO_BE_U16(v) SWAP_U16(v) # define SYS_TO_BE_U24(v) SWAP_U24(v) # define SYS_TO_BE_U32(v) SWAP_U32(v) # define GET_SYS_U16(p) GET_LE_U16(p) # define GET_SYS_U24(p) GET_LE_U24(p) # define GET_SYS_U32(p) GET_LE_U32(p) #define IS_FSM_ERR(__FSM_RT) ((__FSM_RT) < fsm_rt_cpl) /*============================ TYPES =========================================*/ #ifndef __FSM_RT_TYPE__ #define __FSM_RT_TYPE__ //! \name finit state machine state //! @{ typedef enum { fsm_rt_err = -1, //!< fsm error, error code can be get from other interface fsm_rt_cpl = 0, //!< fsm complete fsm_rt_on_going = 1, //!< fsm on-going fsm_rt_wait_for_obj = 2, //!< fsm wait for object fsm_rt_asyn = 3, //!< fsm asynchronose complete, you can check it later. } fsm_rt_t; //! @} #endif /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif // __APP_TYPE_H_INCLUDED__ ================================================ FILE: sources/gmsi/utilities/avr/avr_compiler.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __USE_AVR_COMPILER_H__ #define __USE_AVR_COMPILER_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ #ifndef NOP #define NOP() __asm__ __volatile__ ("nop"); #endif //! ALU integer width in byte # define ATOM_INT_SIZE 1 //! \brief The mcu memory align mode # define MCU_MEM_ALIGN_SIZE ATOM_INT_SIZE //! \brief The mcu memory endian mode # define __BIG_ENDIAN__ false //! \brief none standard memory types #if __IS_COMPILER_IAR__ # define FLASH __flash # define EEPROM __eeprom # define NO_INIT __no_init # define ROOT __root # define RAM #elif __IS_COMPILER_GCC__ # define FLASH const # define EEPROM const # define NO_INIT # define ROOT # define RAM #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ INCLUDES ======================================*/ //! \brief include I/O head file #if __IS_COMPILER_ICC__ #include #elif __IS_COMPILER_GCC__ #include #include #elif __IS_COMPILER_IAR__ #ifndef _USE_IGNORE_IAR_IOAVR_H_ #ifndef _DEVICE_IO #define _DEVICE_IO #include #endif #include #endif #endif /*! \note using the ANSI-C99 standard type,if the file stdint.h dose not exit *! you should define it all by yourself. *! */ #include ".\app_type.h" //! \brief for interrupt #include "signal.h" #endif ================================================ FILE: sources/gmsi/utilities/avr/signal.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_SIGNAL_H_ #define _USE_SIGNAL_H_ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ //! \brief interrupt / signal #if __IS_COMPILER_GCC__ #include #define REGISTER_ISR(__VECTOR, __ISR) \ extern void __ISR(void);\ ISR(__VECTOR)\ {\ __ISR();\ } #elif __IS_COMPILER_IAR__ #ifndef PRAGMA #define PRAGMA(__STRING) _Pragma(#__STRING) #endif #ifndef ISR #define ISR(num) PRAGMA( vector = num ) __interrupt void isr_##num(void) #endif #define REGISTER_ISR(__VECTOR, __ISR) \ extern __task void __ISR(void);\ PRAGMA( vector = __VECTOR ) __interrupt void isr_##__VECTOR(void)\ {\ __ISR();\ } #endif #define ENABLE_GLOBAL_INTERRUPT() __asm__ __volatile__ ("sei") #define DISABLE_GLOBAL_INTERRUPT() __asm__ __volatile__ ("cli") #define GLOBAL_INTERRUPT_ENABLED() ((0 != (SREG & 0x80)) ? true : false) //! \brief The safe ATOM code section macro # define SAFE_ATOM_CODE(__CODE) {\ volatile uint8_t chSREG = SREG;\ DISABLE_GLOBAL_INTERRUPT();\ __CODE;\ SREG = chSREG;\ } //! \brief Exit from the safe atom operations # define EXIT_SAFE_ATOM_CODE() SREG = chSREG;\ //! \brief ATOM code section macro # define ATOM_CODE(__CODE) {\ DISABLE_GLOBAL_INTERRUPT();\ __CODE;\ ENABLE_GLOBAL_INTERRUPT();\ } //! \brief Exit from the atom operations # define EXIT_ATOM_CODE() ENABLE_GLOBAL_INTERRUPT(); //! \name ES_LOCKER value //! @{ #define LOCKED true //!< locked #define UNLOCKED false //!< unlocked //! @} //! \note critical code section protection //! \param __LOCKER ES_LOCKER variable //! \param __CODE target code segment #define LOCK(__LOCKER, __CODE) \ {\ volatile uint8_t chSREG = SREG;\ locker_t *pLocker = &(__LOCKER);\ DISABLE_GLOBAL_INTERRUPT();\ if (!(*pLocker)) {\ (*pLocker) = LOCKED;\ __CODE;\ (*pLocker) = UNLOCKED;\ }\ SREG = chSREG;\ } #define LOCK_INIT(__LOCKER) do {(__LOCKER) = UNLOCKED;}while(false) #define EXIT_LOCK() do {\ (*pLocker) = UNLOCKED;\ SREG = chSREG;\ } while(false) //! \brief exit lock checker structure #define EXIT_LOCK_CHECKER() EXIT_SAFE_ATOM_CODE() /*! \note check specified locker and run code segment *! \param __LOCKER a ES_LOCKER variable *! \param __CODE target code segment */ #define LOCK_CHECKER(__LOCKER, __CODE) {\ SAFE_ATOM_CODE (\ if (UNLOCKED == (__LOCKER)) {\ __CODE;\ }\ )\ } /*============================ TYPES =========================================*/ typedef volatile bool locker_t; /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif ================================================ FILE: sources/gmsi/utilities/communicate.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __UTILITIES_COMMUNICATE_H__ #define __UTILITIES_COMMUNICATE_H__ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name stream //! @{ typedef struct { union { uint8_t *pchBuffer; //!< stream buffer uint8_t *pchSrc; void *pObj; }; int_fast32_t nSize; //!< stream size } mem_block_t; //! @} //! \name interface: byte pipe //! @{ def_interface(i_byte_pipe_t) //!< read a byte bool (*ReadByte)(uint8_t *pchByte); //!< write a byte bool (*WriteByte)(uint_fast8_t chByte); bool (*Flush)(void); end_def_interface(i_byte_pipe_t) //! @} //! \name interface: pipe //! @{ def_interface(i_pipe_t) implement(i_byte_pipe_t) struct { //! read a block int_fast32_t (*Read)(uint8_t *pchStream, int_fast32_t nSize); //! write a block int_fast32_t (*Write)(uint8_t *pchStream, int_fast32_t nSize); } Stream; end_def_interface(i_pipe_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/compiler.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_COMPILER_H_ #define _USE_COMPILER_H_ /*============================ INCLUDES ======================================*/ #ifdef __STORE_ENVIRONMENT_CFG_IN_HEADER_FILE__ #include "environment_cfg.h" #endif #define __STR(__N) #__N #define STR(__N) __STR(__N) #include ".\error.h" #include ".\preprocessor\preprocessor.h" //! \brief CPU io #if defined(__CPU_AVR__) //!< Atmel AVR series # include ".\avr\avr_compiler.h" #elif defined(__CPU_ARM__) //!< ARM series # include ".\arm\arm_compiler.h" #else //#warning No specified MCU type! use arm as default # include ".\arm\arm_compiler.h" #endif //! \brief system macros #define MAX(__A,__B) (((__A) > (__B)) ? (__A) : (__B)) #define MIN(__A,__B) (((__A) < (__B)) ? (__A) : (__B)) #define UBOUND(__ARRAY) (sizeof(__ARRAY)/sizeof(__ARRAY[0])) #define ABS(__NUM) (((__NUM) < 0)?(-(__NUM)):(__NUM)) #ifndef BIT #define BIT(__N) ((uint32_t)1 << (__N)) #endif #ifndef _BV #define _BV(__N) ((uint32_t)1 << (__N)) #endif #ifndef _BM #define __MASK(__N) (_BV(__N) - 1) #define _BM(__FROM,__TO)\ (__MASK((__TO)+1)-__MASK(__FROM)) #endif #ifndef UNUSED_PARAM # define UNUSED_PARAM(__VAL) (__VAL) = (__VAL) #endif //! \brief This macro convert variable types between different datatypes. #define __TYPE_CONVERT(__ADDR,__TYPE) (*((__TYPE *)(__ADDR))) #define TYPE_CONVERT(__ADDR, __TYPE) __TYPE_CONVERT((__ADDR), __TYPE) #define type_convert(__ADDR, __TYPE) TYPE_CONVERT(__ADDR, __TYPE) //! \brief initialize large object # define OBJECT_INIT_ZERO(__OBJECT) \ do \ { \ memset((void *)&(__OBJECT), 0, sizeof(__OBJECT)); \ } while (0) /*! \note using the ANSI-C99 standard type,if the file stdint.h dose not exit *! you should define it all by yourself. *! */ #include ".\app_type.h" #include ".\ooc.h" #endif ================================================ FILE: sources/gmsi/utilities/delegate.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include ".\compiler.h" #include ".\delegate.h" /*============================ MACROS ========================================*/ /*============================ MACROS ========================================*/ #define EVENT_RT_UNREGISTER 4 #ifndef this # define this (*ptThis) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ typedef fsm_rt_t delegate_handler_func_t(void *pArg, void *pParam); /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ //! \name general event handler //! @{ def_class(delegate_handler_t,, delegate_handler_func_t *fnHandler; //!< event handler void *pArg; //!< Argument class(delegate_handler_t) *ptNext; //!< next ) end_def_class(delegate_handler_t) //! @} //! \name event //! @{ def_class(delegate_t,, delegate_handler_t *ptEvent; delegate_handler_t *ptBlockedList; class(delegate_handler_t) **pptHandler; ) end_def_class(delegate_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ /*! \brief initialize event *! \param ptEvent target event *! \return the address of event item */ delegate_t *delegate_init(delegate_t *ptEvent) { class_internal(ptEvent, ptThis, delegate_t); do { if (NULL == ptThis) { break; } this.ptEvent = NULL; this.ptBlockedList = NULL; this.pptHandler = (class(delegate_handler_t) **)&(this.ptEvent); } while (0); return ptEvent; } /*! \brief initialize event handler item *! \param ptHandler the target event handler item *! \param fnRoutine event handler routine *! \param pArg handler extra arguments *! \return the address of event handler item */ delegate_handler_t *delegate_handler_init( delegate_handler_t *ptHandler, delegate_handler_func_t *fnRoutine, void *pArg) { class_internal(ptHandler, ptThis, delegate_handler_t); if (NULL == ptHandler || NULL == fnRoutine) { return NULL; } this.fnHandler = fnRoutine; this.pArg = pArg; this.ptNext = NULL; return ptHandler; } static class(delegate_handler_t) **search_list( class(delegate_handler_t) **pptHandler, class(delegate_handler_t) *ptHND) { //! search event handler chain while (NULL != (*pptHandler)) { if ((*pptHandler) == ptHND) { return pptHandler; } pptHandler = &((*pptHandler)->ptNext); //!< get next item } return NULL; } /*! \brief register event handler to specified event *! \param ptEvent target event *! \param ptHandler target event handler *! \return access result */ gsf_err_t register_delegate_handler(delegate_t *ptEvent, delegate_handler_t *ptHandler) { class_internal(ptEvent, ptThis, delegate_t); class_internal(ptHandler, ptHND, delegate_handler_t); if ((NULL == ptEvent) || (NULL == ptHandler) || (NULL == ptHND->fnHandler)) { return GSF_ERR_INVALID_PTR; } else if (NULL != ptHND->ptNext) { //! search ready list class(delegate_handler_t) **pptHandler = search_list( (class(delegate_handler_t) **)&(this.ptBlockedList), ptHND ); if (NULL != pptHandler) { //! safe to remove (*pptHandler) = ptHND->ptNext; ptHND->ptNext = NULL; } else { return GSF_ERR_REQ_ALREADY_REGISTERED; } } //! add handler to the ready list ptHND->ptNext = (class(delegate_handler_t) *)(this.ptEvent); this.ptEvent = ptHandler; return GSF_ERR_NONE; } /*! \brief unregister a specified event handler *! \param ptEvent target event *! \param ptHandler target event handler *! \return access result */ gsf_err_t unregister_delegate_handler( delegate_t *ptEvent, delegate_handler_t *ptHandler) { class_internal(ptEvent, ptThis, delegate_t); class_internal(ptHandler, ptHND, delegate_handler_t); class(delegate_handler_t) **pptHandler; if ((NULL == ptEvent) || (NULL == ptHandler)) { return GSF_ERR_INVALID_PTR; } do { //! search ready list pptHandler = search_list( (class(delegate_handler_t) **)&(this.ptEvent), ptHND ); if (NULL != pptHandler) { //! safe to remove (*pptHandler) = ptHND->ptNext; ptHND->ptNext = NULL; if (this.pptHandler == &(ptHND->ptNext)) { this.pptHandler = pptHandler; } break; } //! search ready list pptHandler = search_list( (class(delegate_handler_t) **)&(this.ptBlockedList), ptHND ); if (NULL != pptHandler) { //! safe to remove (*pptHandler) = ptHND->ptNext; ptHND->ptNext = NULL; if (this.pptHandler == &(ptHND->ptNext)) { this.pptHandler = pptHandler; } break; } } while(false); return GSF_ERR_NONE; } static fsm_rt_t __move_to_block_list(class(delegate_t) *ptThis, class(delegate_handler_t) *ptHandler) { class(delegate_handler_t) *ptHND = ptHandler; //! remove handler from ready list (*this.pptHandler) = ptHND->ptNext; //! add handler to block list ptHND->ptNext = (class(delegate_handler_t) *)this.ptBlockedList; this.ptBlockedList = (delegate_handler_t *)ptHND; if (NULL == this.ptEvent) { return fsm_rt_cpl; } return fsm_rt_on_going; } #define RAISE_EVENT_START 0 #define RAISE_EVENT_CHECK_HANDLER 1 #define RAISE_EVENT_RUN_HANDLER 2 #define RAISE_EVENT_RESET_FSM() do { this.chState = 0; } while (0) /*! \brief raise target event *! \param ptEvent the target event *! \param pParam event parameter *! \return access result */ fsm_rt_t invoke_delegate( delegate_t *ptEvent, void *pParam) { class_internal(ptEvent, ptThis, delegate_t); if (NULL == ptThis) { return (fsm_rt_t)GSF_ERR_INVALID_PTR; } if (NULL == this.ptEvent) { if (NULL == this.ptBlockedList) { //! nothing to do return fsm_rt_cpl; } //! initialize state this.ptEvent = this.ptBlockedList; this.ptBlockedList = NULL; this.pptHandler = (class(delegate_handler_t) **)&(this.ptEvent); } if (NULL == (*this.pptHandler)) { //! finish visiting the ready list this.pptHandler = (class(delegate_handler_t) **)&(this.ptEvent); if (NULL == (*this.pptHandler)) { //! complete return fsm_rt_cpl; } } else { class(delegate_handler_t) *ptHandler = (*this.pptHandler); if (NULL != ptHandler->fnHandler) { //! run the event handler fsm_rt_t tFSM = ptHandler->fnHandler(ptHandler->pArg,pParam); if (fsm_rt_on_going == tFSM) { this.pptHandler = &(ptHandler->ptNext); //!< get next item } else if (EVENT_RT_UNREGISTER == tFSM) { //! return EVENT_RT_UNREGISTER means event handler could be removed class(delegate_handler_t) *ptHND = ptHandler; (*this.pptHandler) = ptHND->ptNext; ptHND->ptNext = NULL; } else { return __move_to_block_list(ptThis, ptHandler); } } else { return __move_to_block_list(ptThis, ptHandler); } } return fsm_rt_on_going; } /* EOF */ ================================================ FILE: sources/gmsi/utilities/delegate.h ================================================ /**************************************************************************** * Copyright 2018 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __DELEGATE_H__ #define __DELEGATE_H__ /*============================ INCLUDES ======================================*/ #include ".\ooc.h" #include ".\app_type.h" #include ".\error.h" /*============================ MACROS ========================================*/ #define EVENT_RT_UNREGISTER 4 /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ typedef fsm_rt_t delegate_handler_func_t(void *pArg, void *pParam); declare_class( delegate_handler_t ) //! \name general event handler //! @{ extern_class( delegate_handler_t ,, delegate_handler_func_t *fnHandler; //!< event handler void *pArg; //!< Argument delegate_handler_t *ptNext; //!< next ) end_extern_class(delegate_handler_t) //! @} declare_class( delegate_t ) //! \name event //! @{ extern_class(delegate_t,, delegate_handler_t *ptEvent; delegate_handler_t *ptBlockedList; delegate_handler_t **pptHandler; ) end_extern_class(delegate_t) //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*! \brief initialize event *! \param ptEvent target event *! \return the address of event item */ extern delegate_t *delegate_init(delegate_t *ptEvent); /*! \brief initialize event handler item *! \param ptHandler the target event handler item *! \param fnRoutine event handler routine *! \param pArg handler extra arguments *! \return the address of event handler item */ extern delegate_handler_t *delegate_handler_init( delegate_handler_t *ptHandler, delegate_handler_func_t *fnRoutine, void *pArg); /*! \brief register event handler to specified event *! \param ptEvent target event *! \param ptHandler target event handler *! \return access result */ extern gsf_err_t register_delegate_handler(delegate_t *ptEvent, delegate_handler_t *ptHandler); /*! \brief unregister a specified event handler *! \param ptEvent target event *! \param ptHandler target event handler *! \return access result */ extern gsf_err_t unregister_delegate_handler( delegate_t *ptEvent, delegate_handler_t *ptHandler); /*! \brief raise target event *! \param ptEvent the target event *! \param pArg event argument *! \return access result */ extern fsm_rt_t invoke_delegate( delegate_t *ptEvent, void *pParam); #endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/error.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_ERROR_H_ #define _USE_ERROR_H_ /*============================ INCLUDES ======================================*/ //#include "compiler.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ //! \brief setting error code # define SET_ERROR(__ERROR_ADDR,__CODE,__HANDLER) \ do{(*(__ERROR_ADDR)) = (__CODE);} while(false) //! \brief getting error code # define GET_ERROR(__ERROR_ADDR) (*(__ERROR_ADDR)) /*============================ TYPES =========================================*/ //! \name standard error code //! @{ typedef enum { GSF_ERR_NONE =0, //!< none error GSF_ERR_GENERAL =-1, //!< unspecified error GSF_ERR_NOT_SUPPORT =-2, //!< function not supported GSF_ERR_NOT_READY =-3, //!< service not ready yet GSF_ERR_NOT_AVAILABLE =-4, //!< service not available GSF_ERR_NOT_ACCESSABLE =-5, //!< target not acceesable GSF_ERR_NOT_ENOUGH_RESOURCES =-6, //!< no enough resources GSF_ERR_FAIL =-7, //!< failed GSF_ERR_INVALID_PARAMETER =-8, //!< invalid parameter GSF_ERR_INVALID_RANGE =-9, //!< invalid range GSF_ERR_INVALID_PTR =-10, //!< invalid pointer GSF_ERR_INVALID_KEY =-11, //!< invalid key GSF_ERR_IO =-12, //!< IO error GSF_ERR_REQ_ALREADY_REGISTERED =-13, //!< request all ready exist GSF_ERR_UNKNOWN =-128, //!< unknown error } gsf_err_t; //! @} /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif ================================================ FILE: sources/gmsi/utilities/ooc.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ //#ifndef __OBJECT_ORIENTED_C_H__ //#define __OBJECT_ORIENTED_C_H__ /*============================ INCLUDES ======================================*/ #include #include #undef __PLOOC_CLASS_USE_STRICT_TEMPLATE__ #undef __PLOOC_CLASS_USE_SIMPLE_TEMPLATE__ #undef __PLOOC_CLASS_USE_BLACK_BOX_TEMPLATE__ #ifndef __PLOOC_I_KNOW_BLACK_BOX_IS_INCOMPATIBLE_WITH_OTHER_TEMPLATES__ # define __PLOOC_I_KNOW_BLACK_BOX_IS_INCOMPATIBLE_WITH_OTHER_TEMPLATES__ #endif #if !defined(__PLOOC_CLASS_USE_STRICT_TEMPLATE__) \ && !defined(__PLOOC_CLASS_USE_SIMPLE_TEMPLATE__) #define __PLOOC_CLASS_USE_BLACK_BOX_TEMPLATE__ #endif #include "./3rd-party/PLOOC/plooc_class.h" /*============================ MACROS ========================================*/ #undef this #define this (*ptThis) /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ //#endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/preprocessor/connect.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __CONNECT_H__ #define __CONNECT_H__ #include "../3rd-party/PLOOC/plooc.h" #define __CONNECT2(__A, __B) __A##__B #define __CONNECT3(__A, __B, __C) __A##__B##__C #define __CONNECT4(__A, __B, __C, __D) __A##__B##__C##__D #define __CONNECT5(__A, __B, __C, __D, __E) __A##__B##__C##__D##__E #define __CONNECT6(__A, __B, __C, __D, __E, __F) __A##__B##__C##__D##__E##__F #define __CONNECT7(__A, __B, __C, __D, __E, __F, __G) \ __A##__B##__C##__D##__E##__F##__G #define __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \ __A##__B##__C##__D##__E##__F##__G##__H #define __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \ __A##__B##__C##__D##__E##__F##__G##__H##__I #define ALT_CONNECT2(__A, __B) __CONNECT2(__A, __B) #define CONNECT2(__A, __B) __CONNECT2(__A, __B) #define CONNECT3(__A, __B, __C) __CONNECT3(__A, __B, __C) #define CONNECT4(__A, __B, __C, __D) __CONNECT4(__A, __B, __C, __D) #define CONNECT5(__A, __B, __C, __D, __E) __CONNECT5(__A, __B, __C, __D, __E) #define CONNECT6(__A, __B, __C, __D, __E, __F) \ __CONNECT6(__A, __B, __C, __D, __E, __F) #define CONNECT7(__A, __B, __C, __D, __E, __F, __G) \ __CONNECT7(__A, __B, __C, __D, __E, __F, __G) #define CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \ __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) #define CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \ __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) #define CONNECT(...) \ ALT_CONNECT2(CONNECT, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) #endif ================================================ FILE: sources/gmsi/utilities/preprocessor/language_extension.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __LANGUAGE_EXTENSION_H__ #define __LANGUAGE_EXTENSION_H__ #include "../3rd-party/PLOOC/plooc.h" #include "./connect.h" #undef __using1 #undef __using2 #undef __using3 #undef __using4 #undef using #define __using1(__declare) \ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \ ) #define __using2(__declare, __on_leave_expr) \ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \ (__on_leave_expr) \ ) #define __using3(__declare, __on_enter_expr, __on_leave_expr) \ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \ ((__on_enter_expr),1) : 0; \ (__on_leave_expr) \ ) #define __using4(__dcl1, __dcl2, __on_enter_expr, __on_leave_expr) \ for (__dcl1, __dcl2, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \ ((__on_enter_expr),1) : 0; \ (__on_leave_expr) \ ) #define using(...) \ CONNECT2(__using, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) #undef __with2 #undef __with3 #undef with #define __with2(__type, __addr) \ using(__type *_=(__addr)) #define __with3(__type, __addr, __item) \ using(__type *_=(__addr), *__item = _, _=_,_=_ ) #define with(...) \ CONNECT2(__with, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) #undef _ #undef foreach2 #undef foreach3 #undef foreach #define foreach2(__type, __array) \ using(__type *_ = __array) \ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \ CONNECT2(count,__LINE__) > 0; \ _++, CONNECT2(count,__LINE__)-- \ ) #define foreach3(__type, __array, __item) \ using(__type *_ = __array, *__item = _, _ = _, ) \ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \ CONNECT2(count,__LINE__) > 0; \ _++, __item = _, CONNECT2(count,__LINE__)-- \ ) #define foreach(...) \ CONNECT2(foreach, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) #endif ================================================ FILE: sources/gmsi/utilities/preprocessor/macro_repeat.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __MACRO_REPEAT_H__ #define __MACRO_REPEAT_H__ #include "connect.h" #define MACRO_REPEAT(__IDX, __MACRO, ...) CONNECT2(MACRO_REPEAT, __IDX)(__MACRO, __VA_ARGS__) #define MACRO_REPEAT0( __MACRO, ...) #define MACRO_REPEAT1( __MACRO, ...) MACRO_REPEAT0( __MACRO,## __VA_ARGS__) __MACRO( 0, ##__VA_ARGS__) #define MACRO_REPEAT2( __MACRO, ...) MACRO_REPEAT1( __MACRO,## __VA_ARGS__) __MACRO( 1, ##__VA_ARGS__) #define MACRO_REPEAT3( __MACRO, ...) MACRO_REPEAT2( __MACRO,## __VA_ARGS__) __MACRO( 2, ##__VA_ARGS__) #define MACRO_REPEAT4( __MACRO, ...) MACRO_REPEAT3( __MACRO,## __VA_ARGS__) __MACRO( 3, ##__VA_ARGS__) #define MACRO_REPEAT5( __MACRO, ...) MACRO_REPEAT4( __MACRO,## __VA_ARGS__) __MACRO( 4, ##__VA_ARGS__) #define MACRO_REPEAT6( __MACRO, ...) MACRO_REPEAT5( __MACRO,## __VA_ARGS__) __MACRO( 5, ##__VA_ARGS__) #define MACRO_REPEAT7( __MACRO, ...) MACRO_REPEAT6( __MACRO,## __VA_ARGS__) __MACRO( 6, ##__VA_ARGS__) #define MACRO_REPEAT8( __MACRO, ...) MACRO_REPEAT7( __MACRO,## __VA_ARGS__) __MACRO( 7, ##__VA_ARGS__) #define MACRO_REPEAT9( __MACRO, ...) MACRO_REPEAT8( __MACRO,## __VA_ARGS__) __MACRO( 8, ##__VA_ARGS__) #define MACRO_REPEAT10( __MACRO, ...) MACRO_REPEAT9( __MACRO,## __VA_ARGS__) __MACRO( 9, ##__VA_ARGS__) #define MACRO_REPEAT11( __MACRO, ...) MACRO_REPEAT10( __MACRO,## __VA_ARGS__) __MACRO( 10, ##__VA_ARGS__) #define MACRO_REPEAT12( __MACRO, ...) MACRO_REPEAT11( __MACRO,## __VA_ARGS__) __MACRO( 11, ##__VA_ARGS__) #define MACRO_REPEAT13( __MACRO, ...) MACRO_REPEAT12( __MACRO,## __VA_ARGS__) __MACRO( 12, ##__VA_ARGS__) #define MACRO_REPEAT14( __MACRO, ...) MACRO_REPEAT13( __MACRO,## __VA_ARGS__) __MACRO( 13, ##__VA_ARGS__) #define MACRO_REPEAT15( __MACRO, ...) MACRO_REPEAT14( __MACRO,## __VA_ARGS__) __MACRO( 14, ##__VA_ARGS__) #define MACRO_REPEAT16( __MACRO, ...) MACRO_REPEAT15( __MACRO,## __VA_ARGS__) __MACRO( 15, ##__VA_ARGS__) #define MACRO_REPEAT17( __MACRO, ...) MACRO_REPEAT16( __MACRO,## __VA_ARGS__) __MACRO( 16, ##__VA_ARGS__) #define MACRO_REPEAT18( __MACRO, ...) MACRO_REPEAT17( __MACRO,## __VA_ARGS__) __MACRO( 17, ##__VA_ARGS__) #define MACRO_REPEAT19( __MACRO, ...) MACRO_REPEAT18( __MACRO,## __VA_ARGS__) __MACRO( 18, ##__VA_ARGS__) #define MACRO_REPEAT20( __MACRO, ...) MACRO_REPEAT19( __MACRO,## __VA_ARGS__) __MACRO( 19, ##__VA_ARGS__) #define MACRO_REPEAT21( __MACRO, ...) MACRO_REPEAT20( __MACRO,## __VA_ARGS__) __MACRO( 20, ##__VA_ARGS__) #define MACRO_REPEAT22( __MACRO, ...) MACRO_REPEAT21( __MACRO,## __VA_ARGS__) __MACRO( 21, ##__VA_ARGS__) #define MACRO_REPEAT23( __MACRO, ...) MACRO_REPEAT22( __MACRO,## __VA_ARGS__) __MACRO( 22, ##__VA_ARGS__) #define MACRO_REPEAT24( __MACRO, ...) MACRO_REPEAT23( __MACRO,## __VA_ARGS__) __MACRO( 23, ##__VA_ARGS__) #define MACRO_REPEAT25( __MACRO, ...) MACRO_REPEAT24( __MACRO,## __VA_ARGS__) __MACRO( 24, ##__VA_ARGS__) #define MACRO_REPEAT26( __MACRO, ...) MACRO_REPEAT25( __MACRO,## __VA_ARGS__) __MACRO( 25, ##__VA_ARGS__) #define MACRO_REPEAT27( __MACRO, ...) MACRO_REPEAT26( __MACRO,## __VA_ARGS__) __MACRO( 26, ##__VA_ARGS__) #define MACRO_REPEAT28( __MACRO, ...) MACRO_REPEAT27( __MACRO,## __VA_ARGS__) __MACRO( 27, ##__VA_ARGS__) #define MACRO_REPEAT29( __MACRO, ...) MACRO_REPEAT28( __MACRO,## __VA_ARGS__) __MACRO( 28, ##__VA_ARGS__) #define MACRO_REPEAT30( __MACRO, ...) MACRO_REPEAT29( __MACRO,## __VA_ARGS__) __MACRO( 29, ##__VA_ARGS__) #define MACRO_REPEAT31( __MACRO, ...) MACRO_REPEAT30( __MACRO,## __VA_ARGS__) __MACRO( 30, ##__VA_ARGS__) #define MACRO_REPEAT32( __MACRO, ...) MACRO_REPEAT31( __MACRO,## __VA_ARGS__) __MACRO( 31, ##__VA_ARGS__) #define MACRO_REPEAT33( __MACRO, ...) MACRO_REPEAT32( __MACRO,## __VA_ARGS__) __MACRO( 32, ##__VA_ARGS__) #define MACRO_REPEAT34( __MACRO, ...) MACRO_REPEAT33( __MACRO,## __VA_ARGS__) __MACRO( 33, ##__VA_ARGS__) #define MACRO_REPEAT35( __MACRO, ...) MACRO_REPEAT34( __MACRO,## __VA_ARGS__) __MACRO( 34, ##__VA_ARGS__) #define MACRO_REPEAT36( __MACRO, ...) MACRO_REPEAT35( __MACRO,## __VA_ARGS__) __MACRO( 35, ##__VA_ARGS__) #define MACRO_REPEAT37( __MACRO, ...) MACRO_REPEAT36( __MACRO,## __VA_ARGS__) __MACRO( 36, ##__VA_ARGS__) #define MACRO_REPEAT38( __MACRO, ...) MACRO_REPEAT37( __MACRO,## __VA_ARGS__) __MACRO( 37, ##__VA_ARGS__) #define MACRO_REPEAT39( __MACRO, ...) MACRO_REPEAT38( __MACRO,## __VA_ARGS__) __MACRO( 38, ##__VA_ARGS__) #define MACRO_REPEAT40( __MACRO, ...) MACRO_REPEAT39( __MACRO,## __VA_ARGS__) __MACRO( 39, ##__VA_ARGS__) #define MACRO_REPEAT41( __MACRO, ...) MACRO_REPEAT40( __MACRO,## __VA_ARGS__) __MACRO( 40, ##__VA_ARGS__) #define MACRO_REPEAT42( __MACRO, ...) MACRO_REPEAT41( __MACRO,## __VA_ARGS__) __MACRO( 41, ##__VA_ARGS__) #define MACRO_REPEAT43( __MACRO, ...) MACRO_REPEAT42( __MACRO,## __VA_ARGS__) __MACRO( 42, ##__VA_ARGS__) #define MACRO_REPEAT44( __MACRO, ...) MACRO_REPEAT43( __MACRO,## __VA_ARGS__) __MACRO( 43, ##__VA_ARGS__) #define MACRO_REPEAT45( __MACRO, ...) MACRO_REPEAT44( __MACRO,## __VA_ARGS__) __MACRO( 44, ##__VA_ARGS__) #define MACRO_REPEAT46( __MACRO, ...) MACRO_REPEAT45( __MACRO,## __VA_ARGS__) __MACRO( 45, ##__VA_ARGS__) #define MACRO_REPEAT47( __MACRO, ...) MACRO_REPEAT46( __MACRO,## __VA_ARGS__) __MACRO( 46, ##__VA_ARGS__) #define MACRO_REPEAT48( __MACRO, ...) MACRO_REPEAT47( __MACRO,## __VA_ARGS__) __MACRO( 47, ##__VA_ARGS__) #define MACRO_REPEAT49( __MACRO, ...) MACRO_REPEAT48( __MACRO,## __VA_ARGS__) __MACRO( 48, ##__VA_ARGS__) #define MACRO_REPEAT50( __MACRO, ...) MACRO_REPEAT49( __MACRO,## __VA_ARGS__) __MACRO( 49, ##__VA_ARGS__) #define MACRO_REPEAT51( __MACRO, ...) MACRO_REPEAT50( __MACRO,## __VA_ARGS__) __MACRO( 50, ##__VA_ARGS__) #define MACRO_REPEAT52( __MACRO, ...) MACRO_REPEAT51( __MACRO,## __VA_ARGS__) __MACRO( 51, ##__VA_ARGS__) #define MACRO_REPEAT53( __MACRO, ...) MACRO_REPEAT52( __MACRO,## __VA_ARGS__) __MACRO( 52, ##__VA_ARGS__) #define MACRO_REPEAT54( __MACRO, ...) MACRO_REPEAT53( __MACRO,## __VA_ARGS__) __MACRO( 53, ##__VA_ARGS__) #define MACRO_REPEAT55( __MACRO, ...) MACRO_REPEAT54( __MACRO,## __VA_ARGS__) __MACRO( 54, ##__VA_ARGS__) #define MACRO_REPEAT56( __MACRO, ...) MACRO_REPEAT55( __MACRO,## __VA_ARGS__) __MACRO( 55, ##__VA_ARGS__) #define MACRO_REPEAT57( __MACRO, ...) MACRO_REPEAT56( __MACRO,## __VA_ARGS__) __MACRO( 56, ##__VA_ARGS__) #define MACRO_REPEAT58( __MACRO, ...) MACRO_REPEAT57( __MACRO,## __VA_ARGS__) __MACRO( 57, ##__VA_ARGS__) #define MACRO_REPEAT59( __MACRO, ...) MACRO_REPEAT58( __MACRO,## __VA_ARGS__) __MACRO( 58, ##__VA_ARGS__) #define MACRO_REPEAT60( __MACRO, ...) MACRO_REPEAT59( __MACRO,## __VA_ARGS__) __MACRO( 59, ##__VA_ARGS__) #define MACRO_REPEAT61( __MACRO, ...) MACRO_REPEAT60( __MACRO,## __VA_ARGS__) __MACRO( 60, ##__VA_ARGS__) #define MACRO_REPEAT62( __MACRO, ...) MACRO_REPEAT61( __MACRO,## __VA_ARGS__) __MACRO( 61, ##__VA_ARGS__) #define MACRO_REPEAT63( __MACRO, ...) MACRO_REPEAT62( __MACRO,## __VA_ARGS__) __MACRO( 62, ##__VA_ARGS__) #define MACRO_REPEAT64( __MACRO, ...) MACRO_REPEAT63( __MACRO,## __VA_ARGS__) __MACRO( 63, ##__VA_ARGS__) #define MACRO_REPEAT65( __MACRO, ...) MACRO_REPEAT64( __MACRO,## __VA_ARGS__) __MACRO( 64, ##__VA_ARGS__) #define MACRO_REPEAT66( __MACRO, ...) MACRO_REPEAT65( __MACRO,## __VA_ARGS__) __MACRO( 65, ##__VA_ARGS__) #define MACRO_REPEAT67( __MACRO, ...) MACRO_REPEAT66( __MACRO,## __VA_ARGS__) __MACRO( 66, ##__VA_ARGS__) #define MACRO_REPEAT68( __MACRO, ...) MACRO_REPEAT67( __MACRO,## __VA_ARGS__) __MACRO( 67, ##__VA_ARGS__) #define MACRO_REPEAT69( __MACRO, ...) MACRO_REPEAT68( __MACRO,## __VA_ARGS__) __MACRO( 68, ##__VA_ARGS__) #define MACRO_REPEAT70( __MACRO, ...) MACRO_REPEAT69( __MACRO,## __VA_ARGS__) __MACRO( 69, ##__VA_ARGS__) #define MACRO_REPEAT71( __MACRO, ...) MACRO_REPEAT70( __MACRO,## __VA_ARGS__) __MACRO( 70, ##__VA_ARGS__) #define MACRO_REPEAT72( __MACRO, ...) MACRO_REPEAT71( __MACRO,## __VA_ARGS__) __MACRO( 71, ##__VA_ARGS__) #define MACRO_REPEAT73( __MACRO, ...) MACRO_REPEAT72( __MACRO,## __VA_ARGS__) __MACRO( 72, ##__VA_ARGS__) #define MACRO_REPEAT74( __MACRO, ...) MACRO_REPEAT73( __MACRO,## __VA_ARGS__) __MACRO( 73, ##__VA_ARGS__) #define MACRO_REPEAT75( __MACRO, ...) MACRO_REPEAT74( __MACRO,## __VA_ARGS__) __MACRO( 74, ##__VA_ARGS__) #define MACRO_REPEAT76( __MACRO, ...) MACRO_REPEAT75( __MACRO,## __VA_ARGS__) __MACRO( 75, ##__VA_ARGS__) #define MACRO_REPEAT77( __MACRO, ...) MACRO_REPEAT76( __MACRO,## __VA_ARGS__) __MACRO( 76, ##__VA_ARGS__) #define MACRO_REPEAT78( __MACRO, ...) MACRO_REPEAT77( __MACRO,## __VA_ARGS__) __MACRO( 77, ##__VA_ARGS__) #define MACRO_REPEAT79( __MACRO, ...) MACRO_REPEAT78( __MACRO,## __VA_ARGS__) __MACRO( 78, ##__VA_ARGS__) #define MACRO_REPEAT80( __MACRO, ...) MACRO_REPEAT79( __MACRO,## __VA_ARGS__) __MACRO( 79, ##__VA_ARGS__) #define MACRO_REPEAT81( __MACRO, ...) MACRO_REPEAT80( __MACRO,## __VA_ARGS__) __MACRO( 80, ##__VA_ARGS__) #define MACRO_REPEAT82( __MACRO, ...) MACRO_REPEAT81( __MACRO,## __VA_ARGS__) __MACRO( 81, ##__VA_ARGS__) #define MACRO_REPEAT83( __MACRO, ...) MACRO_REPEAT82( __MACRO,## __VA_ARGS__) __MACRO( 82, ##__VA_ARGS__) #define MACRO_REPEAT84( __MACRO, ...) MACRO_REPEAT83( __MACRO,## __VA_ARGS__) __MACRO( 83, ##__VA_ARGS__) #define MACRO_REPEAT85( __MACRO, ...) MACRO_REPEAT84( __MACRO,## __VA_ARGS__) __MACRO( 84, ##__VA_ARGS__) #define MACRO_REPEAT86( __MACRO, ...) MACRO_REPEAT85( __MACRO,## __VA_ARGS__) __MACRO( 85, ##__VA_ARGS__) #define MACRO_REPEAT87( __MACRO, ...) MACRO_REPEAT86( __MACRO,## __VA_ARGS__) __MACRO( 86, ##__VA_ARGS__) #define MACRO_REPEAT88( __MACRO, ...) MACRO_REPEAT87( __MACRO,## __VA_ARGS__) __MACRO( 87, ##__VA_ARGS__) #define MACRO_REPEAT89( __MACRO, ...) MACRO_REPEAT88( __MACRO,## __VA_ARGS__) __MACRO( 88, ##__VA_ARGS__) #define MACRO_REPEAT90( __MACRO, ...) MACRO_REPEAT89( __MACRO,## __VA_ARGS__) __MACRO( 89, ##__VA_ARGS__) #define MACRO_REPEAT91( __MACRO, ...) MACRO_REPEAT90( __MACRO,## __VA_ARGS__) __MACRO( 90, ##__VA_ARGS__) #define MACRO_REPEAT92( __MACRO, ...) MACRO_REPEAT91( __MACRO,## __VA_ARGS__) __MACRO( 91, ##__VA_ARGS__) #define MACRO_REPEAT93( __MACRO, ...) MACRO_REPEAT92( __MACRO,## __VA_ARGS__) __MACRO( 92, ##__VA_ARGS__) #define MACRO_REPEAT94( __MACRO, ...) MACRO_REPEAT93( __MACRO,## __VA_ARGS__) __MACRO( 93, ##__VA_ARGS__) #define MACRO_REPEAT95( __MACRO, ...) MACRO_REPEAT94( __MACRO,## __VA_ARGS__) __MACRO( 94, ##__VA_ARGS__) #define MACRO_REPEAT96( __MACRO, ...) MACRO_REPEAT95( __MACRO,## __VA_ARGS__) __MACRO( 95, ##__VA_ARGS__) #define MACRO_REPEAT97( __MACRO, ...) MACRO_REPEAT96( __MACRO,## __VA_ARGS__) __MACRO( 96, ##__VA_ARGS__) #define MACRO_REPEAT98( __MACRO, ...) MACRO_REPEAT97( __MACRO,## __VA_ARGS__) __MACRO( 97, ##__VA_ARGS__) #define MACRO_REPEAT99( __MACRO, ...) MACRO_REPEAT98( __MACRO,## __VA_ARGS__) __MACRO( 98, ##__VA_ARGS__) #define MACRO_REPEAT100(__MACRO, ...) MACRO_REPEAT99( __MACRO,## __VA_ARGS__) __MACRO( 99, ##__VA_ARGS__) #define MACRO_REPEAT101(__MACRO, ...) MACRO_REPEAT100(__MACRO,## __VA_ARGS__) __MACRO(100, ##__VA_ARGS__) #define MACRO_REPEAT102(__MACRO, ...) MACRO_REPEAT101(__MACRO,## __VA_ARGS__) __MACRO(101, ##__VA_ARGS__) #define MACRO_REPEAT103(__MACRO, ...) MACRO_REPEAT102(__MACRO,## __VA_ARGS__) __MACRO(102, ##__VA_ARGS__) #define MACRO_REPEAT104(__MACRO, ...) MACRO_REPEAT103(__MACRO,## __VA_ARGS__) __MACRO(103, ##__VA_ARGS__) #define MACRO_REPEAT105(__MACRO, ...) MACRO_REPEAT104(__MACRO,## __VA_ARGS__) __MACRO(104, ##__VA_ARGS__) #define MACRO_REPEAT106(__MACRO, ...) MACRO_REPEAT105(__MACRO,## __VA_ARGS__) __MACRO(105, ##__VA_ARGS__) #define MACRO_REPEAT107(__MACRO, ...) MACRO_REPEAT106(__MACRO,## __VA_ARGS__) __MACRO(106, ##__VA_ARGS__) #define MACRO_REPEAT108(__MACRO, ...) MACRO_REPEAT107(__MACRO,## __VA_ARGS__) __MACRO(107, ##__VA_ARGS__) #define MACRO_REPEAT109(__MACRO, ...) MACRO_REPEAT108(__MACRO,## __VA_ARGS__) __MACRO(108, ##__VA_ARGS__) #define MACRO_REPEAT110(__MACRO, ...) MACRO_REPEAT109(__MACRO,## __VA_ARGS__) __MACRO(109, ##__VA_ARGS__) #define MACRO_REPEAT111(__MACRO, ...) MACRO_REPEAT110(__MACRO,## __VA_ARGS__) __MACRO(110, ##__VA_ARGS__) #define MACRO_REPEAT112(__MACRO, ...) MACRO_REPEAT111(__MACRO,## __VA_ARGS__) __MACRO(111, ##__VA_ARGS__) #define MACRO_REPEAT113(__MACRO, ...) MACRO_REPEAT112(__MACRO,## __VA_ARGS__) __MACRO(112, ##__VA_ARGS__) #define MACRO_REPEAT114(__MACRO, ...) MACRO_REPEAT113(__MACRO,## __VA_ARGS__) __MACRO(113, ##__VA_ARGS__) #define MACRO_REPEAT115(__MACRO, ...) MACRO_REPEAT114(__MACRO,## __VA_ARGS__) __MACRO(114, ##__VA_ARGS__) #define MACRO_REPEAT116(__MACRO, ...) MACRO_REPEAT115(__MACRO,## __VA_ARGS__) __MACRO(115, ##__VA_ARGS__) #define MACRO_REPEAT117(__MACRO, ...) MACRO_REPEAT116(__MACRO,## __VA_ARGS__) __MACRO(116, ##__VA_ARGS__) #define MACRO_REPEAT118(__MACRO, ...) MACRO_REPEAT117(__MACRO,## __VA_ARGS__) __MACRO(117, ##__VA_ARGS__) #define MACRO_REPEAT119(__MACRO, ...) MACRO_REPEAT118(__MACRO,## __VA_ARGS__) __MACRO(118, ##__VA_ARGS__) #define MACRO_REPEAT120(__MACRO, ...) MACRO_REPEAT119(__MACRO,## __VA_ARGS__) __MACRO(119, ##__VA_ARGS__) #define MACRO_REPEAT121(__MACRO, ...) MACRO_REPEAT120(__MACRO,## __VA_ARGS__) __MACRO(120, ##__VA_ARGS__) #define MACRO_REPEAT122(__MACRO, ...) MACRO_REPEAT121(__MACRO,## __VA_ARGS__) __MACRO(121, ##__VA_ARGS__) #define MACRO_REPEAT123(__MACRO, ...) MACRO_REPEAT122(__MACRO,## __VA_ARGS__) __MACRO(122, ##__VA_ARGS__) #define MACRO_REPEAT124(__MACRO, ...) MACRO_REPEAT123(__MACRO,## __VA_ARGS__) __MACRO(123, ##__VA_ARGS__) #define MACRO_REPEAT125(__MACRO, ...) MACRO_REPEAT124(__MACRO,## __VA_ARGS__) __MACRO(124, ##__VA_ARGS__) #define MACRO_REPEAT126(__MACRO, ...) MACRO_REPEAT125(__MACRO,## __VA_ARGS__) __MACRO(125, ##__VA_ARGS__) #define MACRO_REPEAT127(__MACRO, ...) MACRO_REPEAT126(__MACRO,## __VA_ARGS__) __MACRO(126, ##__VA_ARGS__) #define MACRO_REPEAT128(__MACRO, ...) MACRO_REPEAT127(__MACRO,## __VA_ARGS__) __MACRO(127, ##__VA_ARGS__) #define MACRO_REPEAT129(__MACRO, ...) MACRO_REPEAT128(__MACRO,## __VA_ARGS__) __MACRO(128, ##__VA_ARGS__) #define MACRO_REPEAT130(__MACRO, ...) MACRO_REPEAT129(__MACRO,## __VA_ARGS__) __MACRO(129, ##__VA_ARGS__) #define MACRO_REPEAT131(__MACRO, ...) MACRO_REPEAT130(__MACRO,## __VA_ARGS__) __MACRO(130, ##__VA_ARGS__) #define MACRO_REPEAT132(__MACRO, ...) MACRO_REPEAT131(__MACRO,## __VA_ARGS__) __MACRO(131, ##__VA_ARGS__) #define MACRO_REPEAT133(__MACRO, ...) MACRO_REPEAT132(__MACRO,## __VA_ARGS__) __MACRO(132, ##__VA_ARGS__) #define MACRO_REPEAT134(__MACRO, ...) MACRO_REPEAT133(__MACRO,## __VA_ARGS__) __MACRO(133, ##__VA_ARGS__) #define MACRO_REPEAT135(__MACRO, ...) MACRO_REPEAT134(__MACRO,## __VA_ARGS__) __MACRO(134, ##__VA_ARGS__) #define MACRO_REPEAT136(__MACRO, ...) MACRO_REPEAT135(__MACRO,## __VA_ARGS__) __MACRO(135, ##__VA_ARGS__) #define MACRO_REPEAT137(__MACRO, ...) MACRO_REPEAT136(__MACRO,## __VA_ARGS__) __MACRO(136, ##__VA_ARGS__) #define MACRO_REPEAT138(__MACRO, ...) MACRO_REPEAT137(__MACRO,## __VA_ARGS__) __MACRO(137, ##__VA_ARGS__) #define MACRO_REPEAT139(__MACRO, ...) MACRO_REPEAT138(__MACRO,## __VA_ARGS__) __MACRO(138, ##__VA_ARGS__) #define MACRO_REPEAT140(__MACRO, ...) MACRO_REPEAT139(__MACRO,## __VA_ARGS__) __MACRO(139, ##__VA_ARGS__) #define MACRO_REPEAT141(__MACRO, ...) MACRO_REPEAT140(__MACRO,## __VA_ARGS__) __MACRO(140, ##__VA_ARGS__) #define MACRO_REPEAT142(__MACRO, ...) MACRO_REPEAT141(__MACRO,## __VA_ARGS__) __MACRO(141, ##__VA_ARGS__) #define MACRO_REPEAT143(__MACRO, ...) MACRO_REPEAT142(__MACRO,## __VA_ARGS__) __MACRO(142, ##__VA_ARGS__) #define MACRO_REPEAT144(__MACRO, ...) MACRO_REPEAT143(__MACRO,## __VA_ARGS__) __MACRO(143, ##__VA_ARGS__) #define MACRO_REPEAT145(__MACRO, ...) MACRO_REPEAT144(__MACRO,## __VA_ARGS__) __MACRO(144, ##__VA_ARGS__) #define MACRO_REPEAT146(__MACRO, ...) MACRO_REPEAT145(__MACRO,## __VA_ARGS__) __MACRO(145, ##__VA_ARGS__) #define MACRO_REPEAT147(__MACRO, ...) MACRO_REPEAT146(__MACRO,## __VA_ARGS__) __MACRO(146, ##__VA_ARGS__) #define MACRO_REPEAT148(__MACRO, ...) MACRO_REPEAT147(__MACRO,## __VA_ARGS__) __MACRO(147, ##__VA_ARGS__) #define MACRO_REPEAT149(__MACRO, ...) MACRO_REPEAT148(__MACRO,## __VA_ARGS__) __MACRO(148, ##__VA_ARGS__) #define MACRO_REPEAT150(__MACRO, ...) MACRO_REPEAT149(__MACRO,## __VA_ARGS__) __MACRO(149, ##__VA_ARGS__) #define MACRO_REPEAT151(__MACRO, ...) MACRO_REPEAT150(__MACRO,## __VA_ARGS__) __MACRO(150, ##__VA_ARGS__) #define MACRO_REPEAT152(__MACRO, ...) MACRO_REPEAT151(__MACRO,## __VA_ARGS__) __MACRO(151, ##__VA_ARGS__) #define MACRO_REPEAT153(__MACRO, ...) MACRO_REPEAT152(__MACRO,## __VA_ARGS__) __MACRO(152, ##__VA_ARGS__) #define MACRO_REPEAT154(__MACRO, ...) MACRO_REPEAT153(__MACRO,## __VA_ARGS__) __MACRO(153, ##__VA_ARGS__) #define MACRO_REPEAT155(__MACRO, ...) MACRO_REPEAT154(__MACRO,## __VA_ARGS__) __MACRO(154, ##__VA_ARGS__) #define MACRO_REPEAT156(__MACRO, ...) MACRO_REPEAT155(__MACRO,## __VA_ARGS__) __MACRO(155, ##__VA_ARGS__) #define MACRO_REPEAT157(__MACRO, ...) MACRO_REPEAT156(__MACRO,## __VA_ARGS__) __MACRO(156, ##__VA_ARGS__) #define MACRO_REPEAT158(__MACRO, ...) MACRO_REPEAT157(__MACRO,## __VA_ARGS__) __MACRO(157, ##__VA_ARGS__) #define MACRO_REPEAT159(__MACRO, ...) MACRO_REPEAT158(__MACRO,## __VA_ARGS__) __MACRO(158, ##__VA_ARGS__) #define MACRO_REPEAT160(__MACRO, ...) MACRO_REPEAT159(__MACRO,## __VA_ARGS__) __MACRO(159, ##__VA_ARGS__) #define MACRO_REPEAT161(__MACRO, ...) MACRO_REPEAT160(__MACRO,## __VA_ARGS__) __MACRO(160, ##__VA_ARGS__) #define MACRO_REPEAT162(__MACRO, ...) MACRO_REPEAT161(__MACRO,## __VA_ARGS__) __MACRO(161, ##__VA_ARGS__) #define MACRO_REPEAT163(__MACRO, ...) MACRO_REPEAT162(__MACRO,## __VA_ARGS__) __MACRO(162, ##__VA_ARGS__) #define MACRO_REPEAT164(__MACRO, ...) MACRO_REPEAT163(__MACRO,## __VA_ARGS__) __MACRO(163, ##__VA_ARGS__) #define MACRO_REPEAT165(__MACRO, ...) MACRO_REPEAT164(__MACRO,## __VA_ARGS__) __MACRO(164, ##__VA_ARGS__) #define MACRO_REPEAT166(__MACRO, ...) MACRO_REPEAT165(__MACRO,## __VA_ARGS__) __MACRO(165, ##__VA_ARGS__) #define MACRO_REPEAT167(__MACRO, ...) MACRO_REPEAT166(__MACRO,## __VA_ARGS__) __MACRO(166, ##__VA_ARGS__) #define MACRO_REPEAT168(__MACRO, ...) MACRO_REPEAT167(__MACRO,## __VA_ARGS__) __MACRO(167, ##__VA_ARGS__) #define MACRO_REPEAT169(__MACRO, ...) MACRO_REPEAT168(__MACRO,## __VA_ARGS__) __MACRO(168, ##__VA_ARGS__) #define MACRO_REPEAT170(__MACRO, ...) MACRO_REPEAT169(__MACRO,## __VA_ARGS__) __MACRO(169, ##__VA_ARGS__) #define MACRO_REPEAT171(__MACRO, ...) MACRO_REPEAT170(__MACRO,## __VA_ARGS__) __MACRO(170, ##__VA_ARGS__) #define MACRO_REPEAT172(__MACRO, ...) MACRO_REPEAT171(__MACRO,## __VA_ARGS__) __MACRO(171, ##__VA_ARGS__) #define MACRO_REPEAT173(__MACRO, ...) MACRO_REPEAT172(__MACRO,## __VA_ARGS__) __MACRO(172, ##__VA_ARGS__) #define MACRO_REPEAT174(__MACRO, ...) MACRO_REPEAT173(__MACRO,## __VA_ARGS__) __MACRO(173, ##__VA_ARGS__) #define MACRO_REPEAT175(__MACRO, ...) MACRO_REPEAT174(__MACRO,## __VA_ARGS__) __MACRO(174, ##__VA_ARGS__) #define MACRO_REPEAT176(__MACRO, ...) MACRO_REPEAT175(__MACRO,## __VA_ARGS__) __MACRO(175, ##__VA_ARGS__) #define MACRO_REPEAT177(__MACRO, ...) MACRO_REPEAT176(__MACRO,## __VA_ARGS__) __MACRO(176, ##__VA_ARGS__) #define MACRO_REPEAT178(__MACRO, ...) MACRO_REPEAT177(__MACRO,## __VA_ARGS__) __MACRO(177, ##__VA_ARGS__) #define MACRO_REPEAT179(__MACRO, ...) MACRO_REPEAT178(__MACRO,## __VA_ARGS__) __MACRO(178, ##__VA_ARGS__) #define MACRO_REPEAT180(__MACRO, ...) MACRO_REPEAT179(__MACRO,## __VA_ARGS__) __MACRO(179, ##__VA_ARGS__) #define MACRO_REPEAT181(__MACRO, ...) MACRO_REPEAT180(__MACRO,## __VA_ARGS__) __MACRO(180, ##__VA_ARGS__) #define MACRO_REPEAT182(__MACRO, ...) MACRO_REPEAT181(__MACRO,## __VA_ARGS__) __MACRO(181, ##__VA_ARGS__) #define MACRO_REPEAT183(__MACRO, ...) MACRO_REPEAT182(__MACRO,## __VA_ARGS__) __MACRO(182, ##__VA_ARGS__) #define MACRO_REPEAT184(__MACRO, ...) MACRO_REPEAT183(__MACRO,## __VA_ARGS__) __MACRO(183, ##__VA_ARGS__) #define MACRO_REPEAT185(__MACRO, ...) MACRO_REPEAT184(__MACRO,## __VA_ARGS__) __MACRO(184, ##__VA_ARGS__) #define MACRO_REPEAT186(__MACRO, ...) MACRO_REPEAT185(__MACRO,## __VA_ARGS__) __MACRO(185, ##__VA_ARGS__) #define MACRO_REPEAT187(__MACRO, ...) MACRO_REPEAT186(__MACRO,## __VA_ARGS__) __MACRO(186, ##__VA_ARGS__) #define MACRO_REPEAT188(__MACRO, ...) MACRO_REPEAT187(__MACRO,## __VA_ARGS__) __MACRO(187, ##__VA_ARGS__) #define MACRO_REPEAT189(__MACRO, ...) MACRO_REPEAT188(__MACRO,## __VA_ARGS__) __MACRO(188, ##__VA_ARGS__) #define MACRO_REPEAT190(__MACRO, ...) MACRO_REPEAT189(__MACRO,## __VA_ARGS__) __MACRO(189, ##__VA_ARGS__) #define MACRO_REPEAT191(__MACRO, ...) MACRO_REPEAT190(__MACRO,## __VA_ARGS__) __MACRO(190, ##__VA_ARGS__) #define MACRO_REPEAT192(__MACRO, ...) MACRO_REPEAT191(__MACRO,## __VA_ARGS__) __MACRO(191, ##__VA_ARGS__) #define MACRO_REPEAT193(__MACRO, ...) MACRO_REPEAT192(__MACRO,## __VA_ARGS__) __MACRO(192, ##__VA_ARGS__) #define MACRO_REPEAT194(__MACRO, ...) MACRO_REPEAT193(__MACRO,## __VA_ARGS__) __MACRO(193, ##__VA_ARGS__) #define MACRO_REPEAT195(__MACRO, ...) MACRO_REPEAT194(__MACRO,## __VA_ARGS__) __MACRO(194, ##__VA_ARGS__) #define MACRO_REPEAT196(__MACRO, ...) MACRO_REPEAT195(__MACRO,## __VA_ARGS__) __MACRO(195, ##__VA_ARGS__) #define MACRO_REPEAT197(__MACRO, ...) MACRO_REPEAT196(__MACRO,## __VA_ARGS__) __MACRO(196, ##__VA_ARGS__) #define MACRO_REPEAT198(__MACRO, ...) MACRO_REPEAT197(__MACRO,## __VA_ARGS__) __MACRO(197, ##__VA_ARGS__) #define MACRO_REPEAT199(__MACRO, ...) MACRO_REPEAT198(__MACRO,## __VA_ARGS__) __MACRO(198, ##__VA_ARGS__) #define MACRO_REPEAT200(__MACRO, ...) MACRO_REPEAT199(__MACRO,## __VA_ARGS__) __MACRO(199, ##__VA_ARGS__) #define MACRO_REPEAT201(__MACRO, ...) MACRO_REPEAT200(__MACRO,## __VA_ARGS__) __MACRO(200, ##__VA_ARGS__) #define MACRO_REPEAT202(__MACRO, ...) MACRO_REPEAT201(__MACRO,## __VA_ARGS__) __MACRO(201, ##__VA_ARGS__) #define MACRO_REPEAT203(__MACRO, ...) MACRO_REPEAT202(__MACRO,## __VA_ARGS__) __MACRO(202, ##__VA_ARGS__) #define MACRO_REPEAT204(__MACRO, ...) MACRO_REPEAT203(__MACRO,## __VA_ARGS__) __MACRO(203, ##__VA_ARGS__) #define MACRO_REPEAT205(__MACRO, ...) MACRO_REPEAT204(__MACRO,## __VA_ARGS__) __MACRO(204, ##__VA_ARGS__) #define MACRO_REPEAT206(__MACRO, ...) MACRO_REPEAT205(__MACRO,## __VA_ARGS__) __MACRO(205, ##__VA_ARGS__) #define MACRO_REPEAT207(__MACRO, ...) MACRO_REPEAT206(__MACRO,## __VA_ARGS__) __MACRO(206, ##__VA_ARGS__) #define MACRO_REPEAT208(__MACRO, ...) MACRO_REPEAT207(__MACRO,## __VA_ARGS__) __MACRO(207, ##__VA_ARGS__) #define MACRO_REPEAT209(__MACRO, ...) MACRO_REPEAT208(__MACRO,## __VA_ARGS__) __MACRO(208, ##__VA_ARGS__) #define MACRO_REPEAT210(__MACRO, ...) MACRO_REPEAT209(__MACRO,## __VA_ARGS__) __MACRO(209, ##__VA_ARGS__) #define MACRO_REPEAT211(__MACRO, ...) MACRO_REPEAT210(__MACRO,## __VA_ARGS__) __MACRO(210, ##__VA_ARGS__) #define MACRO_REPEAT212(__MACRO, ...) MACRO_REPEAT211(__MACRO,## __VA_ARGS__) __MACRO(211, ##__VA_ARGS__) #define MACRO_REPEAT213(__MACRO, ...) MACRO_REPEAT212(__MACRO,## __VA_ARGS__) __MACRO(212, ##__VA_ARGS__) #define MACRO_REPEAT214(__MACRO, ...) MACRO_REPEAT213(__MACRO,## __VA_ARGS__) __MACRO(213, ##__VA_ARGS__) #define MACRO_REPEAT215(__MACRO, ...) MACRO_REPEAT214(__MACRO,## __VA_ARGS__) __MACRO(214, ##__VA_ARGS__) #define MACRO_REPEAT216(__MACRO, ...) MACRO_REPEAT215(__MACRO,## __VA_ARGS__) __MACRO(215, ##__VA_ARGS__) #define MACRO_REPEAT217(__MACRO, ...) MACRO_REPEAT216(__MACRO,## __VA_ARGS__) __MACRO(216, ##__VA_ARGS__) #define MACRO_REPEAT218(__MACRO, ...) MACRO_REPEAT217(__MACRO,## __VA_ARGS__) __MACRO(217, ##__VA_ARGS__) #define MACRO_REPEAT219(__MACRO, ...) MACRO_REPEAT218(__MACRO,## __VA_ARGS__) __MACRO(218, ##__VA_ARGS__) #define MACRO_REPEAT220(__MACRO, ...) MACRO_REPEAT219(__MACRO,## __VA_ARGS__) __MACRO(219, ##__VA_ARGS__) #define MACRO_REPEAT221(__MACRO, ...) MACRO_REPEAT220(__MACRO,## __VA_ARGS__) __MACRO(220, ##__VA_ARGS__) #define MACRO_REPEAT222(__MACRO, ...) MACRO_REPEAT221(__MACRO,## __VA_ARGS__) __MACRO(221, ##__VA_ARGS__) #define MACRO_REPEAT223(__MACRO, ...) MACRO_REPEAT222(__MACRO,## __VA_ARGS__) __MACRO(222, ##__VA_ARGS__) #define MACRO_REPEAT224(__MACRO, ...) MACRO_REPEAT223(__MACRO,## __VA_ARGS__) __MACRO(223, ##__VA_ARGS__) #define MACRO_REPEAT225(__MACRO, ...) MACRO_REPEAT224(__MACRO,## __VA_ARGS__) __MACRO(224, ##__VA_ARGS__) #define MACRO_REPEAT226(__MACRO, ...) MACRO_REPEAT225(__MACRO,## __VA_ARGS__) __MACRO(225, ##__VA_ARGS__) #define MACRO_REPEAT227(__MACRO, ...) MACRO_REPEAT226(__MACRO,## __VA_ARGS__) __MACRO(226, ##__VA_ARGS__) #define MACRO_REPEAT228(__MACRO, ...) MACRO_REPEAT227(__MACRO,## __VA_ARGS__) __MACRO(227, ##__VA_ARGS__) #define MACRO_REPEAT229(__MACRO, ...) MACRO_REPEAT228(__MACRO,## __VA_ARGS__) __MACRO(228, ##__VA_ARGS__) #define MACRO_REPEAT230(__MACRO, ...) MACRO_REPEAT229(__MACRO,## __VA_ARGS__) __MACRO(229, ##__VA_ARGS__) #define MACRO_REPEAT231(__MACRO, ...) MACRO_REPEAT230(__MACRO,## __VA_ARGS__) __MACRO(230, ##__VA_ARGS__) #define MACRO_REPEAT232(__MACRO, ...) MACRO_REPEAT231(__MACRO,## __VA_ARGS__) __MACRO(231, ##__VA_ARGS__) #define MACRO_REPEAT233(__MACRO, ...) MACRO_REPEAT232(__MACRO,## __VA_ARGS__) __MACRO(232, ##__VA_ARGS__) #define MACRO_REPEAT234(__MACRO, ...) MACRO_REPEAT233(__MACRO,## __VA_ARGS__) __MACRO(233, ##__VA_ARGS__) #define MACRO_REPEAT235(__MACRO, ...) MACRO_REPEAT234(__MACRO,## __VA_ARGS__) __MACRO(234, ##__VA_ARGS__) #define MACRO_REPEAT236(__MACRO, ...) MACRO_REPEAT235(__MACRO,## __VA_ARGS__) __MACRO(235, ##__VA_ARGS__) #define MACRO_REPEAT237(__MACRO, ...) MACRO_REPEAT236(__MACRO,## __VA_ARGS__) __MACRO(236, ##__VA_ARGS__) #define MACRO_REPEAT238(__MACRO, ...) MACRO_REPEAT237(__MACRO,## __VA_ARGS__) __MACRO(237, ##__VA_ARGS__) #define MACRO_REPEAT239(__MACRO, ...) MACRO_REPEAT238(__MACRO,## __VA_ARGS__) __MACRO(238, ##__VA_ARGS__) #define MACRO_REPEAT240(__MACRO, ...) MACRO_REPEAT239(__MACRO,## __VA_ARGS__) __MACRO(239, ##__VA_ARGS__) #define MACRO_REPEAT241(__MACRO, ...) MACRO_REPEAT240(__MACRO,## __VA_ARGS__) __MACRO(240, ##__VA_ARGS__) #define MACRO_REPEAT242(__MACRO, ...) MACRO_REPEAT241(__MACRO,## __VA_ARGS__) __MACRO(241, ##__VA_ARGS__) #define MACRO_REPEAT243(__MACRO, ...) MACRO_REPEAT242(__MACRO,## __VA_ARGS__) __MACRO(242, ##__VA_ARGS__) #define MACRO_REPEAT244(__MACRO, ...) MACRO_REPEAT243(__MACRO,## __VA_ARGS__) __MACRO(243, ##__VA_ARGS__) #define MACRO_REPEAT245(__MACRO, ...) MACRO_REPEAT244(__MACRO,## __VA_ARGS__) __MACRO(244, ##__VA_ARGS__) #define MACRO_REPEAT246(__MACRO, ...) MACRO_REPEAT245(__MACRO,## __VA_ARGS__) __MACRO(245, ##__VA_ARGS__) #define MACRO_REPEAT247(__MACRO, ...) MACRO_REPEAT246(__MACRO,## __VA_ARGS__) __MACRO(246, ##__VA_ARGS__) #define MACRO_REPEAT248(__MACRO, ...) MACRO_REPEAT247(__MACRO,## __VA_ARGS__) __MACRO(247, ##__VA_ARGS__) #define MACRO_REPEAT249(__MACRO, ...) MACRO_REPEAT248(__MACRO,## __VA_ARGS__) __MACRO(248, ##__VA_ARGS__) #define MACRO_REPEAT250(__MACRO, ...) MACRO_REPEAT249(__MACRO,## __VA_ARGS__) __MACRO(249, ##__VA_ARGS__) #define MACRO_REPEAT251(__MACRO, ...) MACRO_REPEAT250(__MACRO,## __VA_ARGS__) __MACRO(250, ##__VA_ARGS__) #define MACRO_REPEAT252(__MACRO, ...) MACRO_REPEAT251(__MACRO,## __VA_ARGS__) __MACRO(251, ##__VA_ARGS__) #define MACRO_REPEAT253(__MACRO, ...) MACRO_REPEAT252(__MACRO,## __VA_ARGS__) __MACRO(252, ##__VA_ARGS__) #define MACRO_REPEAT254(__MACRO, ...) MACRO_REPEAT253(__MACRO,## __VA_ARGS__) __MACRO(253, ##__VA_ARGS__) #define MACRO_REPEAT255(__MACRO, ...) MACRO_REPEAT254(__MACRO,## __VA_ARGS__) __MACRO(254, ##__VA_ARGS__) #define MACRO_REPEAT256(__MACRO, ...) MACRO_REPEAT255(__MACRO,## __VA_ARGS__) __MACRO(255, ##__VA_ARGS__) #endif /* _MACRO_REPEAT_H_ */ ================================================ FILE: sources/gmsi/utilities/preprocessor/mf_u8_dec2str.h ================================================ /**************************************************************************** * Copyright 2020 by Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #include "./connect.h" /*============================ MACROS ========================================*/ #ifdef __cplusplus extern "C" { #endif #ifndef MFUNC_IN_U8_DEC_VALUE # error Please define the MFUNC_IN_U8_DEC_VALUE as the input value. It must be \ a compile-time constant value. #endif #undef __MFUNC_OUT_DEC_DIGIT_TEMP0 #undef __MFUNC_OUT_DEC_DIGIT_TEMP1 #undef __MFUNC_OUT_DEC_DIGIT_TEMP2 #if (MFUNC_IN_U8_DEC_VALUE % 10) == 0 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 0 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 1 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 1 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 2 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 2 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 3 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 3 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 4 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 4 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 5 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 5 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 6 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 6 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 7 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 7 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 8 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 8 #elif (MFUNC_IN_U8_DEC_VALUE % 10) == 9 # define __MFUNC_OUT_DEC_DIGIT_TEMP0 9 #endif #if ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 0 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 0 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 1 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 1 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 2 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 2 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 3 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 3 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 4 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 4 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 5 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 5 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 6 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 6 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 7 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 7 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 8 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 8 #elif ((MFUNC_IN_U8_DEC_VALUE/10) % 10) == 9 # define __MFUNC_OUT_DEC_DIGIT_TEMP1 9 #endif #if ((MFUNC_IN_U8_DEC_VALUE/100) % 10) == 0 # define __MFUNC_OUT_DEC_DIGIT_TEMP2 0 #elif ((MFUNC_IN_U8_DEC_VALUE/100) % 10) == 1 # define __MFUNC_OUT_DEC_DIGIT_TEMP2 1 #elif ((MFUNC_IN_U8_DEC_VALUE/100) % 10) == 2 # define __MFUNC_OUT_DEC_DIGIT_TEMP2 2 #endif #undef __MFUNC_OUT_DEC_DIGIT0 #undef __MFUNC_OUT_DEC_DIGIT1 #undef __MFUNC_OUT_DEC_DIGIT2 #if __MFUNC_OUT_DEC_DIGIT_TEMP0 == 0 # define __MFUNC_OUT_DEC_DIGIT0 0 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 1 # define __MFUNC_OUT_DEC_DIGIT0 1 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 2 # define __MFUNC_OUT_DEC_DIGIT0 2 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 3 # define __MFUNC_OUT_DEC_DIGIT0 3 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 4 # define __MFUNC_OUT_DEC_DIGIT0 4 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 5 # define __MFUNC_OUT_DEC_DIGIT0 5 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 6 # define __MFUNC_OUT_DEC_DIGIT0 6 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 7 # define __MFUNC_OUT_DEC_DIGIT0 7 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 8 # define __MFUNC_OUT_DEC_DIGIT0 8 #elif __MFUNC_OUT_DEC_DIGIT_TEMP0 == 9 # define __MFUNC_OUT_DEC_DIGIT0 9 #endif #if __MFUNC_OUT_DEC_DIGIT_TEMP1 == 0 # define __MFUNC_OUT_DEC_DIGIT1 0 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 1 # define __MFUNC_OUT_DEC_DIGIT1 1 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 2 # define __MFUNC_OUT_DEC_DIGIT1 2 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 3 # define __MFUNC_OUT_DEC_DIGIT1 3 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 4 # define __MFUNC_OUT_DEC_DIGIT1 4 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 5 # define __MFUNC_OUT_DEC_DIGIT1 5 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 6 # define __MFUNC_OUT_DEC_DIGIT1 6 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 7 # define __MFUNC_OUT_DEC_DIGIT1 7 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 8 # define __MFUNC_OUT_DEC_DIGIT1 8 #elif __MFUNC_OUT_DEC_DIGIT_TEMP1 == 9 # define __MFUNC_OUT_DEC_DIGIT1 9 #endif #if __MFUNC_OUT_DEC_DIGIT_TEMP2 == 0 # define __MFUNC_OUT_DEC_DIGIT2 0 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 1 # define __MFUNC_OUT_DEC_DIGIT2 1 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 2 # define __MFUNC_OUT_DEC_DIGIT2 2 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 3 # define __MFUNC_OUT_DEC_DIGIT2 3 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 4 # define __MFUNC_OUT_DEC_DIGIT2 4 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 5 # define __MFUNC_OUT_DEC_DIGIT2 5 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 6 # define __MFUNC_OUT_DEC_DIGIT2 6 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 7 # define __MFUNC_OUT_DEC_DIGIT2 7 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 8 # define __MFUNC_OUT_DEC_DIGIT2 8 #elif __MFUNC_OUT_DEC_DIGIT_TEMP2 == 9 # define __MFUNC_OUT_DEC_DIGIT2 9 #endif #undef MFUNC_OUT_DEC_STR #if __MFUNC_OUT_DEC_DIGIT2 == 0 # if __MFUNC_OUT_DEC_DIGIT1 == 0 # define MFUNC_OUT_DEC_STR __MFUNC_OUT_DEC_DIGIT0 # else # define MFUNC_OUT_DEC_STR CONNECT2( __MFUNC_OUT_DEC_DIGIT1,\ __MFUNC_OUT_DEC_DIGIT0) # endif #else # define MFUNC_OUT_DEC_STR CONNECT3( __MFUNC_OUT_DEC_DIGIT2,\ __MFUNC_OUT_DEC_DIGIT1,\ __MFUNC_OUT_DEC_DIGIT0) #endif #undef MFUNC_IN_U8_DEC_VALUE /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #ifdef __cplusplus } #endif ================================================ FILE: sources/gmsi/utilities/preprocessor/preprocessor.h ================================================ /**************************************************************************** * Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __PREPROCESSOR_H__ #define __PREPROCESSOR_H__ #include "connect.h" #include "macro_repeat.h" #include "language_extension.h" #endif /* __PREPROCESSOR_H__ */ ================================================ FILE: sources/gmsi/utilities/simple_fsm.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #include ".\ooc.h" #ifndef __SIMPLE_FSM_H__ #define __SIMPLE_FSM_H__ /*============================ INCLUDES ======================================*/ #include /*============================ MACROS ========================================*/ #ifndef this # define this (*ptThis) #endif /*============================ MACROFIED FUNCTIONS ===========================*/ #define def_states(...) \ enum { \ START = 0, \ __VA_ARGS__ \ }; #define def_params(...) __VA_ARGS__ #define args(...) ,__VA_ARGS__ #define fsm(__NAME) fsm_##__NAME##_t #define __simple_fsm(__FSM_TYPE, ...) \ def_class(__FSM_TYPE,, \ uint_fast8_t chState; \ __VA_ARGS__ \ ) \ end_def_class(__FSM_TYPE) #define simple_fsm(__NAME, ...) \ declare_simple_fsm(__NAME); \ __simple_fsm(fsm(__NAME), __VA_ARGS__) #define def_simple_fsm(__NAME, ...) \ __simple_fsm(fsm(__NAME), __VA_ARGS__) #define end_def_simple_fsm(...) #define def_fsm(__NAME, ...) \ __simple_fsm(fsm(__NAME), __VA_ARGS__) #define end_def_fsm(...) #define __extern_simple_fsm(__FSM_TYPE, ...) \ declare_class(__FSM_TYPE) \ extern_class(__FSM_TYPE,, \ uint_fast8_t chState; \ __VA_ARGS__ \ ) \ end_extern_class(__FSM_TYPE) #define __declare_simple_fsm(__FSM_TYPE) \ declare_class(__FSM_TYPE) #define declare_simple_fsm(__NAME) __declare_simple_fsm(fsm(__NAME)) #define declare_fsm(__NAME) __declare_simple_fsm(fsm(__NAME)) #define extern_simple_fsm(__NAME, ...) \ __extern_simple_fsm(fsm(__NAME), __VA_ARGS__) /*! \brief extern fsm initialisation function and provide function prototye as <__NAME>_fn, E.g extern_fsm_initialiser( demo_fsm ); we extern a function called: extern fsm_demo_fsm_t *demo_fsm_init( fsm_demo_fsm_t *ptFSM ); and a prototype definition: typedef fsm_demo_fsm_t *demo_fsm_init_fn( fsm_demo_fsm_t *ptFSM ); We can then use demo_fsm_init_fn to define function pointer */ #define __extern_fsm_initialiser(__NAME, ...) \ fsm(__NAME) *__NAME##_init(fsm(__NAME) *ptFSM __VA_ARGS__); \ typedef fsm(__NAME) *__NAME##_init_fn(fsm(__NAME) *ptFSM __VA_ARGS__); #define extern_fsm_initialiser(__NAME, ...) \ __extern_fsm_initialiser(__NAME, __VA_ARGS__) #define declare_fsm_initialiser(__NAME, ...) \ __extern_fsm_initialiser(__NAME, __VA_ARGS__) /*! \brief extern fsm task function and provide function prototye as <__NAME>_fn, E.g extern_fsm_implementation( demo_fsm ); we extern a function called: fsm_rt_t demo_fsm( fsm_demo_fsm_t *ptFSM ) and a prototype definition: typedef fsm_rt_t demo_fsm_fn (fsm_demo_fsm_t *ptFSM); We can then use demo_fsm_fn to define function pointer */ //! @{ #define __extern_fsm_implementation_ex(__NAME,__TYPE, ...) \ fsm_rt_t __NAME( __TYPE *ptFSM __VA_ARGS__ ); \ typedef fsm_rt_t __NAME##_fn( __TYPE *ptFSM __VA_ARGS__ ); #define declare_fsm_implementation_ex(__NAME, __TYPE, ...) \ __extern_fsm_implementation_ex(__NAME, __TYPE, __VA_ARGS__) #define extern_fsm_implementation_ex(__NAME,__TYPE, ...) \ __extern_fsm_implementation_ex(__NAME, __TYPE, __VA_ARGS__) #define extern_fsm_implementation(__NAME, ...) \ __extern_fsm_implementation_ex(__NAME, fsm(__NAME), __VA_ARGS__) #define declare_fsm_implementation(__NAME, ...) \ __extern_fsm_implementation_ex(__NAME, fsm(__NAME), __VA_ARGS__) //! @} #define call_fsm(__NAME, __FSM, ...) \ __NAME((__FSM) __VA_ARGS__) #define call_simple_fsm(__NAME, __FSM, ...) \ __NAME((__FSM) __VA_ARGS__) #define __state(__STATE, ...) \ case __STATE: \ __state_entry_##__STATE:{ \ __VA_ARGS__; \ }; #define state(__STATE, ...) break; __state(__STATE, __VA_ARGS__) #define on_start(...) {__VA_ARGS__;} #define reset_fsm() do { ptThis->chState = 0; } while(0); #define fsm_cpl() do {reset_fsm(); return fsm_rt_cpl;} while(0); #define fsm_report(__ERROR) do {reset_fsm(); return (fsm_rt_t)(__ERROR); } while(0); #define fsm_wait_for_obj() return fsm_rt_wait_for_obj; #define fsm_on_going() return fsm_rt_on_going; //! fsm_continue is deprecated, should not be used anymore //#define fsm_continue() break #define update_state_to(__STATE) \ { ptThis->chState = (__STATE); goto __state_entry_##__STATE;} #define transfer_to(__STATE) \ { ptThis->chState = (__STATE); fsm_on_going() } #define __fsm_initialiser(__NAME, ...) \ fsm(__NAME) *__NAME##_init(fsm(__NAME) *ptFSM __VA_ARGS__) \ { \ class(fsm(__NAME)) *ptThis = ( class(fsm(__NAME)) *)ptFSM; \ if (NULL == ptThis) { \ return NULL; \ } \ ptThis->chState = 0; #define fsm_initialiser(__NAME, ...) \ __fsm_initialiser(__NAME, __VA_ARGS__) #define abort_init() return NULL; #define init_body(...) \ __VA_ARGS__ \ return ptFSM; \ } #define init_fsm(__NAME, __FSM, ...) \ __NAME##_init((__FSM) __VA_ARGS__) #define init_simple_fsm(__NAME, __FSM, ...) \ init_fsm((__FSM) __VA_ARGS__) #define __implement_fsm_ex(__NAME, __TYPE, ...) \ fsm_rt_t __NAME( __TYPE *ptFSM __VA_ARGS__ ) \ { \ class(__TYPE) *ptThis = (class(__TYPE) *)ptFSM; \ if (NULL == ptThis) { \ return fsm_rt_err; \ } #define __body(...) \ switch (ptThis->chState) { \ case 0: \ ptThis->chState++; \ __VA_ARGS__ \ break; \ default: \ return fsm_rt_err; \ } \ \ return fsm_rt_on_going; \ } #define body(...) __body(__VA_ARGS__) #define body_begin() \ switch (ptThis->chState) { \ case 0: \ ptThis->chState++; #define body_end() \ break; \ default: \ return fsm_rt_err; \ } \ } \ return fsm_rt_on_going; /*! \note Debug Support: You can use debug_body() together with debug_state() *! to enable debug specified state. Which means you are ale to set break *! points and single-step into those states. *! *! \note debug_state() must be used in debug_body(). *! *! Example: debug_body() state(xxxxx, //the range no debug is allowed ) state(xxxxx){ //the range you can debug with } end_debug_body() */ #define implement_fsm_ex(__NAME, __TYPE, ...) \ __implement_fsm_ex(__NAME, __TYPE, __VA_ARGS__) #define fsm_implementation(__NAME, ...) \ implement_fsm(__NAME, __VA_ARGS__) #define fsm_implementation_ex(__NAME, __TYPE, ...) \ implement_fsm_ex(__NAME, __TYPE, __VA_ARGS__) #define __implement_fsm(__NAME, ...) \ implement_fsm_ex(__NAME, fsm(__NAME), __VA_ARGS__) #define implement_fsm(__NAME, ...) __implement_fsm(__NAME, __VA_ARGS__) #define __privilege_state(__STATE, ...) \ break;do { \ do { \ __state(__STATE, __VA_ARGS__) \ } while(0); /* add extra while(0) to catch the fsm_continue()*/ \ if (this.chState != (__STATE)) { \ break; \ } \ } while(1); #define privilege_state(__STATE, ...) \ __privilege_state(__STATE, __VA_ARGS__) #define privilege_group(...) { __VA_ARGS__;} #define privilege_body(...) \ do { \ switch (ptThis->chState) { \ case 0: \ ptThis->chState++; \ __VA_ARGS__ \ } \ while(1); \ \ return fsm_rt_on_going; \ } /*============================ TYPES =========================================*/ #ifndef __FSM_RT_TYPE__ #define __FSM_RT_TYPE__ //! \name finit state machine state //! @{ typedef enum { fsm_rt_err = -1, //!< fsm error, error code can be get from other interface fsm_rt_cpl = 0, //!< fsm complete fsm_rt_on_going = 1, //!< fsm on-going fsm_rt_wait_for_obj = 2, //!< fsm wait for object fsm_rt_asyn = 3, //!< fsm asynchronose complete, you can check it later. } fsm_rt_t; //! @} #endif /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/template/t_list.c ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ /*============================ INCLUDES ======================================*/ #ifdef __STORE_ENVIRONMENT_CFG_IN_HEADER_FILE__ #include "environment_cfg.h" #endif #include "..\compiler.h" #include "..\ooc.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ def_structure( __single_list_node_t ) __single_list_node_t *ptNext; end_def_structure( __single_list_note_t ) def_structure( __dual_list_node_t ) __dual_list_node_t *ptNext; __dual_list_node_t *ptPrevious; end_def_structure( __dual_list_note_t ) /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ bool list_find(__single_list_node_t **ppList, __single_list_node_t *ptItem) { bool bResult = false; do { if (NULL == ppList || NULL == ptItem) { break; } else if (NULL == (*ppList)) { break; } do { if ((*ppList) == ptItem) { bResult = true; break; } ppList = &((*ppList)->ptNext); } while(NULL != (*ppList)); } while(false); return bResult; } /*EOF*/ ================================================ FILE: sources/gmsi/utilities/template/t_list.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_TEMPLATE_LIST_H_ #define _USE_TEMPLATE_LIST_H_ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ #define END_DEF_LIST(__NAME) #define END_DEF_SAFE_LIST(__NAME) /*============================ MACROFIED FUNCTIONS ===========================*/ #define __LIST_STACK_PUSH(__P_TOP, __P_NODE) \ do { \ ((__single_list_node_t *)(__P_NODE))->ptNext = \ (__single_list_node_t *)(__P_TOP); \ (*(__single_list_node_t **)&(__P_TOP)) = \ (__single_list_node_t *)(__P_NODE); \ } while(0) #define LIST_STACK_PUSH(__P_TOP, __P_NODE) \ __LIST_STACK_PUSH((__P_TOP), (__P_NODE)) #define LIST_INSERT_AFTER(__P_TARGET, __P_NODE) \ __LIST_STACK_PUSH((__P_TARGET), (__P_NODE)) #define __LIST_STACK_POP(__P_TOP, __P_NODE) \ do { \ (*(__single_list_node_t **)&(__P_NODE)) = \ (__single_list_node_t *)(__P_TOP); \ (*(__single_list_node_t **)&(__P_TOP)) = \ ((__single_list_node_t *)(__P_NODE))->ptNext; \ ((__single_list_node_t *)(__P_NODE))->ptNext = NULL; \ } while(0) #define LIST_STACK_POP(__P_TOP, __P_NODE) __LIST_STACK_POP((__P_TOP), (__P_NODE)) #define LIST_REMOVE_AFTER(__P_TARGET, __P_NODE) \ LIST_STACK_POP((__P_TARGET), (__P_NODE)) #define __LIST_QUEUE_ENQUEUE(__HEAD, __TAIL, __ITEM) \ do { \ if (NULL == (__TAIL)) { \ (*((__single_list_node_t **)&(__TAIL))) = \ (__single_list_node_t *)(__ITEM); \ ((__single_list_node_t *)(__ITEM))->ptNext = NULL; \ (*((__single_list_node_t **)&(__HEAD))) = \ (__single_list_node_t *)(__ITEM); \ } else { \ ((__single_list_node_t *)(__TAIL))->ptNext = \ (__single_list_node_t *)(__ITEM); \ ((__single_list_node_t *)(__ITEM))->ptNext = NULL; \ (*(__single_list_node_t **)&(__TAIL)) = \ (__single_list_node_t *)(__ITEM); \ } \ } while(0) #define LIST_QUEUE_ENQUEUE(__HEAD, __TAIL, __ITEM) \ __LIST_QUEUE_ENQUEUE((__HEAD), (__TAIL), (__ITEM)) #define __LIST_QUEUE_DEQUEUE(__HEAD, __TAIL, __ITEM) \ do { \ (*(__single_list_node_t **)&(__ITEM)) = \ (__single_list_node_t *)(__HEAD); \ if (NULL != (__HEAD)) { \ (*(__single_list_node_t **)&(__HEAD)) = \ ((__single_list_node_t *)(__HEAD))->ptNext; \ if (NULL == (__HEAD)) { \ (__TAIL) = NULL; \ } \ } \ } while(0) #define LIST_QUEUE_DEQUEUE(__HEAD, __TAIL, __ITEM) \ __LIST_QUEUE_DEQUEUE((__HEAD), (__TAIL), (__ITEM)) #define __LIST_QUEUE_REMOVE(__HEAD, __TAIL, __ITEM) \ do { \ __single_list_node_t **ppList = (__single_list_node_t **)&(__HEAD); \ if (list_find(ppList, (__single_list_node_t *)(__ITEM))) { \ LIST_QUEUE_DEQUEUE((*ppList), (__TAIL), (__ITEM)); \ } \ } while(0) #define LIST_QUEUE_REMOVE(__HEAD, __TAIL, __ITEM) \ __LIST_QUEUE_REMOVE((__HEAD), (__TAIL), (__ITEM)) /*============================ TYPES =========================================*/ def_structure( __single_list_node_t ) __single_list_node_t *ptNext; end_def_structure( __single_list_note_t ) def_structure( __dual_list_node_t ) __dual_list_node_t *ptNext; __dual_list_node_t *ptPrevious; end_def_structure( __dual_list_note_t ) /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ extern bool list_find(__single_list_node_t **ppList, __single_list_node_t *ptItem); #endif ================================================ FILE: sources/gmsi/utilities/template/t_pool.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_TEMPLATE_POOL_H_ #define _USE_TEMPLATE_POOL_H_ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ #define END_DEF_POOL(__NAME) #define END_DEF_SAFE_POOL(__NAME) /*============================ MACROFIED FUNCTIONS ===========================*/ #ifndef NONE_ATOM_ACCESS # define NONE_ATOM_ACCESS(...) {__VA_ARGS__;} #endif #define POOL(__NAME) __NAME##_pool_t #define POOL_ITEM(__NAME) __NAME##_pool_item_t #define DEF_SAFE_POOL(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ DEF_POOL_EX(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, SAFE_ATOM_CODE) #define DEF_POOL(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ DEF_POOL_EX(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, NONE_ATOM_ACCESS) #define POOL_MUTEX(__NAME, __POOL) \ __NAME##_pool_mutex((__POOL)) #define POOL_INIT(__NAME, __POOL) \ __NAME##_pool_init((__POOL)) #define POOL_ADD_HEAP(__NAME, __POOL, __BUFFER, __SIZE) \ __NAME##_pool_add_heap((__POOL), (__BUFFER), (__SIZE)) #define POOL_FREE(__NAME, __POOL, __ITEM) \ __NAME##_pool_free((__POOL), (__ITEM)) #define POOL_NEW(__NAME, __POOL) \ __NAME##_pool_new((__POOL)) #define POOL_ITEM_COUNT_ALLOCATED(__NAME, __POOL) \ __NAME##_get_pool_item_count_allocated((__POOL)) #define EXTERN_POOL(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ declare_class(__NAME##_pool_item_t) \ extern_class(__NAME##_pool_item_t) \ union { \ INHERIT(__single_list_node_t) \ __TYPE tObject; \ }; \ EXTERN_DEF_CLASS(__NAME##_pool_item_t) \ \ declare_class(__NAME##_pool_t) \ extern_class(__NAME##_pool_t) \ __single_list_node_t *ptFreeList; \ __MUTEX_TYPE tMutex; \ __PTR_TYPE tCounter; \ end_extern_class(__NAME##_pool_t) \ \ extern __MUTEX_TYPE *__NAME##_pool_mutex(__NAME##_pool_t *ptPool); \ extern bool __NAME##_pool_init(__NAME##_pool_t *ptPool); \ extern __PTR_TYPE __NAME##_get_pool_item_count_allocated( \ __NAME##_pool_t *ptPool); \ extern __TYPE *__NAME##_pool_new(__NAME##_pool_t *ptPool); \ extern void __NAME##_pool_free( \ __NAME##_pool_t *ptPool, __TYPE *ptItem); \ extern bool __NAME##_pool_add_heap( \ __NAME##_pool_t *ptPool, __NAME##_pool_item_t *ptBuffer, __PTR_TYPE tSize); #define DEF_POOL_EX(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, __ATOM_ACCESS) \ declare_class(__NAME##_pool_item_t) \ def_class(__NAME##_pool_item_t) \ union { \ INHERIT(__single_list_node_t) \ __TYPE tObject; \ }; \ end_def_class(__NAME##_pool_item_t) \ \ declare_class(__NAME##_pool_t) \ def_class(__NAME##_pool_t) \ __single_list_node_t *ptFreeList; \ __MUTEX_TYPE tMutex; \ __PTR_TYPE tCounter; \ end_def_class(__NAME##_pool_t) \ \ __MUTEX_TYPE *__NAME##_pool_mutex(__NAME##_pool_t *ptPool) \ { \ if (NULL == ptPool) { \ return NULL; \ } \ \ return &(((class(__NAME##_pool_t) *)ptPool)->tMutex); \ } \ \ bool __NAME##_pool_init(__NAME##_pool_t *ptPool) \ { \ if (NULL == ptPool) { \ return false; \ } \ \ ((class(__NAME##_pool_t) *)ptPool)->ptFreeList = NULL; \ ((class(__NAME##_pool_t) *)ptPool)->tCounter = 0; \ \ return true; \ } \ \ static void __##__NAME##_pool_free_item( \ __NAME##_pool_t *ptPool, __NAME##_pool_item_t *ptItem) \ { \ LIST_STACK_PUSH( \ ((class(__NAME##_pool_t) *)ptPool)->ptFreeList, \ ptItem \ ); \ } \ \ void __NAME##_pool_free( \ __NAME##_pool_t *ptPool, __TYPE *ptItem) \ { \ if ((NULL == ptPool) || (NULL == ptItem) \ ||(NULL != ((class(__NAME##_pool_item_t) *)ptItem)->ptNext)) { \ return ; \ } \ \ __ATOM_ACCESS( \ __##__NAME##_pool_free_item(ptPool, (__NAME##_pool_item_t *)ptItem); \ \ if (((class(__NAME##_pool_t) *)ptPool)->tCounter) { \ ((class(__NAME##_pool_t) *)ptPool)->tCounter--; \ } \ ) \ } \ \ __TYPE *__NAME##_pool_new(__NAME##_pool_t *ptPool) \ { \ __single_list_node_t *ptItem = NULL; \ \ if (NULL == ptPool) { \ return NULL; \ } \ \ __ATOM_ACCESS( \ do { \ if ((NULL == ((class(__NAME##_pool_t) *)ptPool)->ptFreeList)) { \ break; \ } \ \ LIST_STACK_POP( \ ((class(__NAME##_pool_t) *)ptPool)->ptFreeList, \ ptItem \ ); \ \ ((class(__NAME##_pool_t) *)ptPool)->tCounter++; \ \ } while(false); \ ) \ \ if(NULL == ptItem) { \ return NULL: \ } \ \ return &(((class(__NAME##_pool_item_t) *)ptItem)->tObject); \ } \ \ bool __NAME##_pool_add_heap( \ __NAME##_pool_t *ptPool, __NAME##_pool_item_t *ptBuffer, __PTR_TYPE tSize) \ { \ if ((NULL == ptPool) || (NULL == ptBuffer) || (0 == tSize)) { \ return false; \ } \ \ __ATOM_ACCESS( \ do { \ __##__NAME##_pool_free_item(ptPool, ptBuffer++); \ } while(--tSize); \ ) \ \ return true; \ } \ __PTR_TYPE __NAME##_get_pool_item_count_allocated(__NAME##_pool_t *ptPool) \ { \ __PTR_TYPE tResult = 0; \ if (NULL == ptPool) { \ return 0; \ } \ \ __ATOM_ACCESS( \ tResult = ((class(__NAME##_pool_t) *)ptPool)->tCounter; \ ) \ \ return tResult; \ } /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif ================================================ FILE: sources/gmsi/utilities/template/t_queue.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_TEMPLATE_QUEUE_H_ #define _USE_TEMPLATE_QUEUE_H_ /*============================ INCLUDES ======================================*/ /*============================ MACROS ========================================*/ #define END_DEF_QUEUE(__NAME) #define END_DEF_QUEUE_U8(__NAME) #define END_DEF_QUEUE_U16(__NAME) #define END_DEF_QUEUE_U32(__NAME) #define END_DEF_SAFE_QUEUE(__NAME) #define END_DEF_SAFE_QUEUE_U8(__NAME) #define END_DEF_SAFE_QUEUE_U16(__NAME) #define END_DEF_SAFE_QUEUE_U32(__NAME) #define END_EXTERN_QUEUE(__NAME) #define END_EXTERN_QUEUE_U8(__NAME) #define END_EXTERN_QUEUE_U16(__NAME) #define END_EXTERN_QUEUE_U32(__NAME) #define END_EXTERN_SAFE_QUEUE(__NAME) #define END_EXTERN_SAFE_QUEUE_U8(__NAME) #define END_EXTERN_SAFE_QUEUE_U16(__NAME) #define END_EXTERN_SAFE_QUEUE_U32(__NAME) /*============================ MACROFIED FUNCTIONS ===========================*/ #ifndef NONE_ATOM_ACCESS # define NONE_ATOM_ACCESS(...) {__VA_ARGS__;} #endif #define QUEUE_MUTEX(__NAME, __QUEUE) \ __NAME##_queue_mutex(__QUEUE) #define QUEUE_INIT(__NAME, __QUEUE, __BUFFER, __SIZE) \ __NAME##_queue_init((__QUEUE), (__BUFFER), (__SIZE), false) #define QUEUE_SERIALIZE(__NAME, __QUEUE, __BUFFER, __SIZE) \ __NAME##_queue_init((__QUEUE), (__BUFFER), (__SIZE), true) #define QUEUE_INIT_EX(__NAME, __QUEUE, __BUFFER, __SIZE, __SERIALISED) \ __NAME##_queue_init((__QUEUE), (__BUFFER), (__SIZE), (__SERIALISED)) #define QUEUE_DESERIALIZE(__NAME, __QUEUE) \ __NAME##_get_queue_buffer(__QUEUE) #define DEQUEUE(__NAME, __QUEUE, __ADDR) \ __NAME##_dequeue((__QUEUE),(__ADDR)) #define DEQUEUE_BLOCK(__NAME, __QUEUE, __ADDR, __SIZE) \ __NAME##_dequeue_block((__QUEUE),(__ADDR), (__SIZE)) #define DEQUEUE_REF(__NAME, __QUEUE) \ __NAME##_dequeue_ref((__QUEUE)) #define ENQUEUE(__NAME, __QUEUE, __VALUE) \ __NAME##_enqueue((__QUEUE), (__VALUE)) #define ENQUEUE_BLOCK(__NAME, __QUEUE, __ADDR, __SIZE) \ __NAME##_enqueue_block((__QUEUE),(__ADDR), (__SIZE)) #define PEEK_QUEUE(__NAME, __QUEUE, __ADDR) \ __NAME##_queue_peek((__QUEUE),(__ADDR)) #define GET_QUEUE_COUNT(__NAME, __QUEUE) \ __NAME##_get_queue_item_count((__QUEUE)) #define GET_QUEUE_AVAILABLE_COUNT(__NAME, __QUEUE) \ __NAME##_get_queue_item_available_count((__QUEUE)) #define RESET_PEEK(__NAME, __QUEUE) \ __NAME##_reset_peek((__QUEUE)) #define GET_ALL_PEEKED(__NAME, __QUEUE) \ __NAME##_get_all_peeked((__QUEUE)) #define QUEUE(__NAME) __NAME##_queue_t #define EXTERN_QUEUE(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ declare_class(__NAME##_queue_t) \ extern_class(__NAME##_queue_t,, \ __TYPE *ptBuffer; \ __PTR_TYPE tSize; \ __PTR_TYPE tHead; \ __PTR_TYPE tTail; \ __PTR_TYPE tCounter; \ __PTR_TYPE tPeek; \ __PTR_TYPE tPeekCounter; \ __MUTEX_TYPE tMutex; \ ) \ end_extern_class(__NAME##_queue_t) \ \ extern __MUTEX_TYPE *__NAME##_queue_mutex(__NAME##_queue_t *ptQueue); \ extern bool __NAME##_queue_init( \ __NAME##_queue_t *ptQueue, __TYPE *ptBuffer, __PTR_TYPE tSize, bool bFull); \ extern bool __NAME##_enqueue(__NAME##_queue_t *ptQueue, __TYPE tObj); \ extern int_fast32_t __NAME##_enqueue_block( __NAME##_queue_t *ptQueue, \ __TYPE *ptSrc, \ __PTR_TYPE hwSize); \ extern bool __NAME##_queue_peek(__NAME##_queue_t *ptQueue, __TYPE *ptObj); \ extern bool __NAME##_dequeue(__NAME##_queue_t *ptQueue, __TYPE *ptObj); \ extern int_fast32_t __NAME##_dequeue_block( __NAME##_queue_t *ptQueue, \ __TYPE *ptSrc, \ __PTR_TYPE hwSize); \ extern __TYPE * __NAME##_dequeue_ref(__NAME##_queue_t *ptQueue); \ extern void __NAME##_get_all_peeked(__NAME##_queue_t *ptQueue); \ extern void __NAME##_reset_peek(__NAME##_queue_t *ptQueue); \ extern __PTR_TYPE __NAME##_get_queue_item_count(__NAME##_queue_t *ptQueue); \ extern __PTR_TYPE __NAME##_get_queue_item_available_count( \ __NAME##_queue_t *ptQueue); \ extern __TYPE * __NAME##_get_queue_buffer(__NAME##_queue_t *ptQueue); #define DEF_QUEUE_EX( \ __NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, __ATOM_ACCESS) \ declare_class(__NAME##_queue_t) \ def_class(__NAME##_queue_t,, \ __TYPE *ptBuffer; \ __PTR_TYPE tSize; \ __PTR_TYPE tHead; \ __PTR_TYPE tTail; \ __PTR_TYPE tCounter; \ __PTR_TYPE tPeek; \ __PTR_TYPE tPeekCounter; \ __MUTEX_TYPE tMutex; \ ) \ end_def_class(__NAME##_queue_t) \ \ __MUTEX_TYPE *__NAME##_queue_mutex(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if ( NULL == ptQueue) { \ return NULL; \ } \ return &(ptQ->tMutex); \ } \ \ __TYPE * __NAME##_get_queue_buffer(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if ( NULL == ptQueue) { \ return NULL; \ } \ return ptQ->ptBuffer; \ } \ bool __NAME##_queue_init( \ __NAME##_queue_t *ptQueue, __TYPE *ptBuffer, __PTR_TYPE tSize, bool bFull) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQueue || NULL == ptBuffer || 0 == tSize) { \ return false; \ } \ \ ptQ->ptBuffer = ptBuffer; \ ptQ->tSize = tSize; \ ptQ->tHead = 0; \ ptQ->tPeek = 0; \ ptQ->tTail = 0; \ if (bFull) { \ ptQ->tCounter = tSize; \ ptQ->tPeekCounter = tSize; \ } else { \ ptQ->tCounter = 0; \ ptQ->tPeekCounter = 0; \ } \ \ return true; \ } \ \ bool __NAME##_enqueue(__NAME##_queue_t *ptQueue, __TYPE tObj) \ { \ bool bResult = false; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return false; \ } \ \ __ATOM_ACCESS( \ do { \ if ((ptQ->tHead == ptQ->tTail) && (0 != ptQ->tCounter)) { \ break; \ } \ \ ptQ->ptBuffer[ptQ->tTail++] = tObj; \ if (ptQ->tTail >= ptQ->tSize) { \ ptQ->tTail = 0; \ } \ ptQ->tCounter++; \ ptQ->tPeekCounter++; \ bResult = true; \ } while (false); \ ) \ \ return bResult; \ } \ int_fast32_t __NAME##_enqueue_block(__NAME##_queue_t *ptQueue, \ __TYPE *ptSrc, \ __PTR_TYPE wSize) \ { \ int_fast32_t nResult = -1; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ do { \ if (NULL == ptQ || NULL == ptSrc || 0 == wSize) { \ break; \ } \ \ __ATOM_ACCESS( \ do { \ if ((ptQ->tHead == ptQ->tTail) && (0 != ptQ->tCounter)) { \ break; \ } \ __PTR_TYPE wLength; \ if (ptQ->tTail < ptQ->tHead) { \ wLength = ptQ->tHead - ptQ->tTail; \ } else /*if (ptQ->tTail >= ptQ->tHead)*/ { \ wLength = ptQ->tSize - ptQ->tTail; \ } \ wLength = MIN(wLength, wSize); \ memcpy( &(ptQ->ptBuffer[ptQ->tTail]), \ ptSrc, \ wLength * sizeof(__TYPE)); \ ptQ->tTail += wLength; \ if (ptQ->tTail >= ptQ->tSize) { \ ptQ->tTail = 0; \ } \ ptQ->tCounter += wLength; \ ptQ->tPeekCounter += wLength; \ nResult = wLength; \ } while (false); \ ) \ } while(false); \ \ return nResult; \ } \ \ bool __NAME##_queue_peek(__NAME##_queue_t *ptQueue, __TYPE *ptObj) \ { \ bool bResult = false; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return false; \ } \ \ __ATOM_ACCESS( \ do { \ __TYPE tObj; \ if ((ptQ->tPeek == ptQ->tTail) && (!ptQ->tPeekCounter)) { \ break; \ } \ tObj = ptQ->ptBuffer[ptQ->tPeek++]; \ ptQ->tPeekCounter--; \ if (ptQ->tPeek >= ptQ->tSize) { \ ptQ->tPeek = 0; \ } \ if (NULL != ptObj) { \ *ptObj = tObj; \ } \ bResult = true; \ } while (false); \ ) \ \ return bResult; \ } \ bool __NAME##_dequeue(__NAME##_queue_t *ptQueue, __TYPE *ptObj) \ { \ bool bResult = false; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return false; \ } \ \ __ATOM_ACCESS( \ do { \ if ((ptQ->tHead == ptQ->tTail) && (!ptQ->tCounter)) { \ break; \ } \ if (NULL != ptObj) { \ *ptObj = ptQ->ptBuffer[ptQ->tHead]; \ } \ ptQ->tHead++; \ if (ptQ->tHead >= ptQ->tSize) { \ ptQ->tHead = 0; \ } \ ptQ->tCounter--; \ ptQ->tPeek = ptQ->tHead; \ ptQ->tPeekCounter = ptQ->tCounter; \ bResult = true; \ } while (false); \ ) \ \ return bResult; \ } \ int_fast32_t __NAME##_dequeue_block( __NAME##_queue_t *ptQueue, \ __TYPE *ptSrc, \ __PTR_TYPE wSize) \ { \ int_fast32_t nResult = -1; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ do { \ if (NULL == ptQ || NULL == ptSrc || 0 == wSize) { \ break; \ } \ \ __ATOM_ACCESS( \ do { \ if ((ptQ->tHead == ptQ->tTail) && (!(ptQ->tCounter))) { \ break; \ } \ __PTR_TYPE wLength; \ if (ptQ->tHead < ptQ->tTail) { \ wLength = ptQ->tTail - ptQ->tHead; \ } else /*if (ptQ->tHead >= ptQ->tTail)*/ { \ wLength = ptQ->tSize - ptQ->tHead; \ } \ wLength = MIN(wLength, wSize); \ memcpy( ptSrc, \ &(ptQ->ptBuffer[ptQ->tHead]), \ wLength * sizeof(__TYPE)); \ ptQ->tHead += wLength; \ if (ptQ->tHead >= ptQ->tSize) { \ ptQ->tHead = 0; \ } \ ptQ->tCounter -= wLength; \ ptQ->tPeek = ptQ->tHead; \ ptQ->tPeekCounter = ptQ->tCounter; \ nResult = wLength; \ } while (false); \ ) \ } while(false); \ \ return nResult; \ } \ __TYPE * __NAME##_dequeue_ref(__NAME##_queue_t *ptQueue) \ { \ __TYPE *ptObj = NULL; \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return NULL; \ } \ \ __ATOM_ACCESS( \ do { \ if ((ptQ->tHead == ptQ->tTail) && (!ptQ->tCounter)) { \ break; \ } \ ptObj = &(ptQ->ptBuffer[ptQ->tHead]); \ ptQ->tHead++; \ if (ptQ->tHead >= ptQ->tSize) { \ ptQ->tHead = 0; \ } \ ptQ->tCounter--; \ ptQ->tPeek = ptQ->tHead; \ ptQ->tPeekCounter = ptQ->tCounter; \ } while (false); \ ) \ \ return ptObj; \ } \ __PTR_TYPE __NAME##_get_queue_item_count(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ __PTR_TYPE tCount; \ if (NULL == ptQ) { \ return 0; \ } \ \ __ATOM_ACCESS( \ tCount = ptQ->tCounter; \ ) \ return tCount; \ } \ __PTR_TYPE __NAME##_get_queue_item_available_count(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ __PTR_TYPE tSize; \ if (NULL == ptQ) { \ return 0; \ } \ \ __ATOM_ACCESS( \ tSize = ptQ->tSize - ptQ->tCounter; \ ) \ return tSize; \ } \ void __NAME##_get_all_peeked(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return ; \ } \ \ __ATOM_ACCESS( \ ptQ->tHead = ptQ->tPeek; \ ptQ->tCounter = ptQ->tPeekCounter; \ ) \ } \ void __NAME##_reset_peek(__NAME##_queue_t *ptQueue) \ { \ class(__NAME##_queue_t) *ptQ = (class(__NAME##_queue_t) *)ptQueue; \ if (NULL == ptQ) { \ return ; \ } \ \ __ATOM_ACCESS( \ ptQ->tPeek = ptQ->tHead; \ ptQ->tPeekCounter = ptQ->tCounter; \ ) \ } #define DEF_SAFE_QUEUE(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ DEF_QUEUE_EX(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, SAFE_ATOM_CODE) #define DEF_SAFE_QUEUE_U8(__NAME, __PTR_TYPE,__MUTEX_TYPE) \ DEF_SAFE_QUEUE(__NAME, uint8_t, __PTR_TYPE, __MUTEX_TYPE) #define EXTERN_SAFE_QUEUE_U8(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ EXTERN_QUEUE(__NAME, uint8_t, __PTR_TYPE, __MUTEX_TYPE) #define DEF_SAFE_QUEUE_U16(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ DEF_SAFE_QUEUE(__NAME, uint16_t, __PTR_TYPE, __MUTEX_TYPE) #define DEF_SAFE_QUEUE_U32(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ DEF_SAFE_QUEUE(__NAME, uint32_t __PTR_TYPE, __MUTEX_TYPE) #define DEF_QUEUE(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE) \ DEF_QUEUE_EX(__NAME, __TYPE, __PTR_TYPE, __MUTEX_TYPE, NONE_ATOM_ACCESS) #define DEF_QUEUE_U8(__NAME, __PTR_TYPE,__MUTEX_TYPE) \ DEF_QUEUE(__NAME, uint8_t, __PTR_TYPE, __MUTEX_TYPE) #define DEF_QUEUE_U16(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ DEF_QUEUE(__NAME, uint16_t, __PTR_TYPE, __MUTEX_TYPE) #define DEF_QUEUE_U32(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ DEF_QUEUE(__NAME, uint32_t __PTR_TYPE, __MUTEX_TYPE) #define EXTERN_QUEUE_U8(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ EXTERN_QUEUE(__NAME, uint8_t, __PTR_TYPE, __MUTEX_TYPE) #define EXTERN_QUEUE_U16(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ EXTERN_QUEUE(__NAME, uint16_t, __PTR_TYPE, __MUTEX_TYPE) #define EXTERN_QUEUE_U32(__NAME, __PTR_TYPE, __MUTEX_TYPE) \ EXTERN_QUEUE(__NAME, uint32_t, __PTR_TYPE, __MUTEX_TYPE) /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif ================================================ FILE: sources/gmsi/utilities/template/template.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_TEMPLATE_H_ #define _USE_TEMPLATE_H_ /*============================ INCLUDES ======================================*/ #include ".\t_queue.h" #include ".\t_pool.h" #include ".\t_list.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ /*============================ IMPLEMENTATION ================================*/ #endif ================================================ FILE: sources/gmsi/utilities/tiny_fsm.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef __TINY_FSM_H__ #define __TINY_FSM_H__ /*============================ INCLUDES ======================================*/ #include ".\compiler.h" /*============================ MACROS ========================================*/ /*============================ MACROFIED FUNCTIONS ===========================*/ /*! \brief you can use tiny fsm at any where you want with little cost. E.g. / *! \brief function that output a char with none-block manner *! \param chByte target char *! \retval true the target char has been put into the output buffer *! \retval false service is busy * / extern bool serial_out(uint8_t chByte); extern void toggle_led_a(void); extern void toggle_led_b(void); #define SERIAL_OUT(__BYTE) serial_out(__BYTE) DEF_TINY_FSM(Print_String) DEF_PARAM uint8_t *pchString; END_DEF_PARAM PRIVATE bool m_CriticalSection = false; PRIVATE TINY_STATE(Print_String, Print_Init); PRIVATE TINY_STATE(Print_String, Print_Output); END_DEF_TINY_FSM PRIVATE TINY_STATE(Print_String, Print_Init) BEGIN if ((NULL == PARAM) || (NULL == PARAM->pchString)) { TINY_FSM_END; //!< end fsm } else if ('\0' == (*PARAM->pchString)) { TINY_FSM_END; //!< end fsm } else if (m_CriticalSection) { TINY_FSM_TRANSFER_TO(Print_Init); //!< try to enter critical section } m_CriticalSection = true; TINY_FSM_TRANSFER_TO(Print_Output) END PRIVATE TINY_STATE(Print_String, Print_Output) BEGIN if (SERIAL_OUT(*(PARAM->pchString))) { PARAM->pchString++; if ('\0' == (*PARAM->pchString)) { //! complete m_CriticalSection = false; //!< leave critical section TINY_FSM_END; //!< complete } } TINY_FSM_TRANSFER_TO(Print_Output) //!< reflexive END int main(void) { NEW_TINY_FSM(Print_String, DemoStringA) NEW_TINY_FSM(Print_String, DemoStringB) static uint8_t chDemoA[] = "Hello world"; static uint8_t chDemoB[] = "Tiny FSM Demo"; ... while(true) { //! call DemoStringA, the instance of the tiny FSM Print_String CALL_TINY_FSM(Print_String, DemoStringA, Print_Init) PARAM_INIT chDemoA //!< output string "Hello world" END_PARAM_INIT END_CALL_TINY_FSM(Print_String) //! an example of checking whether a sepecified fsm is complete or not if (IS_TINY_FSM_CPL(DemoStringA)) { toggle_led_a(); //!< do something here. E.g. toggle a LED } //! call DemoStringB, the instance of the tiny FSM Print_String CALL_TINY_FSM(Print_String, DemoStringB, Print_Init) PARAM_INIT chDemoB //!< output string "Tiny FSM Demo" END_PARAM_INIT END_CALL_TINY_FSM(Print_String) //! an example of checking whether a sepecified fsm is complete or not if (IS_TINY_FSM_CPL(DemoStringB)) { toggle_led_b(); //!< do something here. E.g. toggle a LED } } return 0; } */ #define DEF_TINY_FSM(__NAME) \ typedef struct tiny_fsm_##__NAME##_arg tiny_fsm_##__NAME##_arg_t;\ typedef void *(*tiny_fsm_##__NAME##_task)(tiny_fsm_##__NAME##_arg_t *pArg);\ struct tiny_fsm_##__NAME##_arg #define DEF_PARAM { #define END_DEF_PARAM }; #define END_DEF_TINY_FSM #define NEW_TINY_FSM(__NAME, __VAR) \ tiny_fsm_##__NAME##_task s_TinyFSM##__VAR = NULL; #define TINY_STATE(__NAME, __STATE_NAME) \ void *tiny_fsm_state_##__STATE_NAME(tiny_fsm_##__NAME##_arg_t *pArg) #define BEGIN { #define END } #define PRIVATE static #define PUBLIC #define INTERNAL static #define PARAM pArg #define TINY_FSM_END return NULL; #define TINY_FSM_TRANSFER_TO(__STATE_NAME) return (void *)&tiny_fsm_state_##__STATE_NAME; #define IS_TINY_FSM_CPL(__VAR) (NULL == s_TinyFSM##__VAR) #define CALL_TINY_FSM(__NAME,__VAR, __START_STATE) do {\ tiny_fsm_##__NAME##_task *s_ptTinyFSMTemp = &s_TinyFSM##__VAR;\ bool bReset = IS_TINY_FSM_CPL(__VAR);\ tiny_fsm_##__NAME##_task s_TinyFSMStart = &(tiny_fsm_state_##__START_STATE);\ static tiny_fsm_##__NAME##_arg_t tParam, tResetParam = #define PARAM_INIT { #define END_PARAM_INIT };\ if (bReset) {\ tParam = tResetParam;\ *s_ptTinyFSMTemp = s_TinyFSMStart;\ } #define NO_PARAM_INIT {0};\ if (bReset) {\ tParam = tResetParam;\ *s_ptTinyFSMTemp = s_TinyFSMStart;\ } #define SET_PARAM(__FIELD,__VALUE) do {tParam.__FIELD = (__VALUE);} while(false); #define END_CALL_TINY_FSM(__NAME) \ *s_ptTinyFSMTemp = (tiny_fsm_##__NAME##_task)(*s_ptTinyFSMTemp)( &tParam );\ } while(false); /*============================ TYPES =========================================*/ /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif /* EOF */ ================================================ FILE: sources/gmsi/utilities/usebits.h ================================================ /**************************************************************************** * Copyright 2017 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * * You may obtain a copy of the License at * * * * http://www.apache.org/licenses/LICENSE-2.0 * * * * Unless required by applicable law or agreed to in writing, software * * distributed under the License is distributed on an "AS IS" BASIS, * * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * * See the License for the specific language governing permissions and * * limitations under the License. * * * ****************************************************************************/ #ifndef _USE_BITS_H_ #define _USE_BITS_H_ /*============================ INCLUDES ======================================*/ #include "compiler.h" /*============================ MACROS ========================================*/ //! \name binary compatibility definition //! @{ # define BIT00 BIT0 //!< bit 0 # define BIT01 BIT1 //!< bit 1 # define BIT02 BIT2 //!< bit 2 # define BIT03 BIT3 //!< bit 3 # define BIT04 BIT4 //!< bit 4 # define BIT05 BIT5 //!< bit 5 # define BIT06 BIT6 //!< bit 6 # define BIT07 BIT7 //!< bit 7 # define BIT08 BIT8 //!< bit 8 # define BIT09 BIT9 //!< bit 9 //! @} /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ typedef union { uint8_t Value; uint8_t Byte; struct { #if __BIG_ENDIAN__ != true unsigned BIT0:1; unsigned BIT1:1; unsigned BIT2:1; unsigned BIT3:1; unsigned BIT4:1; unsigned BIT5:1; unsigned BIT6:1; unsigned BIT7:1; #else unsigned BIT7:1; unsigned BIT6:1; unsigned BIT5:1; unsigned BIT4:1; unsigned BIT3:1; unsigned BIT2:1; unsigned BIT1:1; unsigned BIT0:1; #endif } Bits; }byte_t; typedef union { uint16_t Value; uint8_t Byte[2]; struct { #if !defined(__BIG_ENDIAN) || __BIG_ENDIAN__ != true unsigned BIT0:1; unsigned BIT1:1; unsigned BIT2:1; unsigned BIT3:1; unsigned BIT4:1; unsigned BIT5:1; unsigned BIT6:1; unsigned BIT7:1; unsigned BIT8:1; unsigned BIT9:1; unsigned BIT10:1; unsigned BIT11:1; unsigned BIT12:1; unsigned BIT13:1; unsigned BIT14:1; unsigned BIT15:1; #else unsigned BIT15:1; unsigned BIT14:1; unsigned BIT13:1; unsigned BIT12:1; unsigned BIT11:1; unsigned BIT10:1; unsigned BIT9:1; unsigned BIT8:1; unsigned BIT7:1; unsigned BIT6:1; unsigned BIT5:1; unsigned BIT4:1; unsigned BIT3:1; unsigned BIT2:1; unsigned BIT1:1; unsigned BIT0:1; #endif } Bits; struct { #if !defined(__BIG_ENDIAN) || __BIG_ENDIAN__ != true uint8_t ByteL; uint8_t ByteH; #else uint8_t ByteH; uint8_t ByteL; #endif } HWord; }hword_t; typedef union { uint32_t Value; uint8_t Byte[4]; hword_t HWord[2]; struct { #if !defined(__BIG_ENDIAN) || __BIG_ENDIAN__ != true unsigned BIT0:1; unsigned BIT1:1; unsigned BIT2:1; unsigned BIT3:1; unsigned BIT4:1; unsigned BIT5:1; unsigned BIT6:1; unsigned BIT7:1; unsigned BIT8:1; unsigned BIT9:1; unsigned BIT10:1; unsigned BIT11:1; unsigned BIT12:1; unsigned BIT13:1; unsigned BIT14:1; unsigned BIT15:1; unsigned BIT16:1; unsigned BIT17:1; unsigned BIT18:1; unsigned BIT19:1; unsigned BIT20:1; unsigned BIT21:1; unsigned BIT22:1; unsigned BIT23:1; unsigned BIT24:1; unsigned BIT25:1; unsigned BIT26:1; unsigned BIT27:1; unsigned BIT28:1; unsigned BIT29:1; unsigned BIT30:1; unsigned BIT31:1; #else unsigned BIT31:1; unsigned BIT30:1; unsigned BIT29:1; unsigned BIT28:1; unsigned BIT27:1; unsigned BIT26:1; unsigned BIT25:1; unsigned BIT24:1; unsigned BIT23:1; unsigned BIT22:1; unsigned BIT21:1; unsigned BIT20:1; unsigned BIT19:1; unsigned BIT18:1; unsigned BIT17:1; unsigned BIT16:1; unsigned BIT15:1; unsigned BIT14:1; unsigned BIT13:1; unsigned BIT12:1; unsigned BIT11:1; unsigned BIT10:1; unsigned BIT9:1; unsigned BIT8:1; unsigned BIT7:1; unsigned BIT6:1; unsigned BIT5:1; unsigned BIT4:1; unsigned BIT3:1; unsigned BIT2:1; unsigned BIT1:1; unsigned BIT0:1; #endif } Bits; struct { #if !defined(__BIG_ENDIAN) || __BIG_ENDIAN__ != true uint8_t ByteA; uint8_t ByteB; uint8_t ByteC; uint8_t ByteD; #else uint8_t ByteD; uint8_t ByteC; uint8_t ByteB; uint8_t ByteA; #endif } Word; }word_t; /*============================ GLOBAL VARIABLES ==============================*/ /*============================ LOCAL VARIABLES ===============================*/ /*============================ PROTOTYPES ====================================*/ #endif