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Repository: IAIK/transientfail
Branch: master
Commit: 43947508d8ba
Files: 123
Total size: 486.1 KB
Directory structure:
gitextract_1s0czu4x/
├── LICENSE
├── README.md
├── docs/
│ ├── CNAME
│ ├── bibliography.js
│ ├── css/
│ │ └── style.css
│ ├── dist/
│ │ ├── index.js
│ │ └── typescript/
│ │ ├── d3.d.ts
│ │ ├── draw-links.d.ts
│ │ ├── index.d.ts
│ │ ├── initializeSVG.d.ts
│ │ ├── link-enter.d.ts
│ │ ├── link-exit.d.ts
│ │ ├── link-update.d.ts
│ │ ├── links/
│ │ │ ├── draw-links.d.ts
│ │ │ ├── link-enter.d.ts
│ │ │ ├── link-exit.d.ts
│ │ │ └── link-update.d.ts
│ │ ├── node-enter.d.ts
│ │ ├── node-exit.d.ts
│ │ ├── nodes/
│ │ │ ├── node-enter.d.ts
│ │ │ ├── node-exit.d.ts
│ │ │ └── node-update.d.ts
│ │ ├── prepare-data.d.ts
│ │ ├── services.d.ts
│ │ ├── typings.d.ts
│ │ └── utils.d.ts
│ ├── index.html
│ ├── js/
│ │ ├── export.js
│ │ ├── filter.js
│ │ └── tree.js
│ └── tree.js
└── pocs/
├── Makefile
├── get_hyperthread_pair.sh
├── libcache/
│ ├── Makefile
│ ├── cache.c
│ └── cache.h
├── libpte/
│ ├── .gitignore
│ ├── Makefile
│ ├── module/
│ │ ├── Makefile
│ │ ├── pteditor.c
│ │ └── pteditor.h
│ ├── ptedit.c
│ ├── ptedit.h
│ └── ptedit_header.h
├── meltdown/
│ ├── AC/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── BR/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── DE/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── GP/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── main.c
│ │ └── module/
│ │ ├── Makefile
│ │ └── kernel_module.c
│ ├── NM/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── main.c
│ │ ├── secret.h
│ │ └── victim.c
│ ├── P/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── PK/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── RW/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── SS/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── cacheutils.h
│ │ └── main.c
│ ├── UD/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── US/
│ ├── Makefile
│ ├── README.md
│ └── main.c
└── spectre/
├── BTB/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.cpp
│ ├── ca_oop/
│ │ ├── cacheutils.h
│ │ ├── exploit.sh
│ │ ├── hyper_thread_pair.sh
│ │ ├── main.c
│ │ └── smc_utils.h
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.cpp
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
├── PHT/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── ca_oop/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
├── RSB/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── ca_oop/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
└── STL/
├── Makefile
├── README.md
└── main.c
================================================
FILE CONTENTS
================================================
================================================
FILE: LICENSE
================================================
zlib License
(C) 2020 Graz University of Technology
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
================================================
FILE: README.md
================================================
# Transient Fail
Transient Fail is a project that gathers different proof-of-concept implementations of Transient Execution Attacks. It was originally developed for our Usenix 2019 paper
[A Systematic Evaluation of Transient Execution Attacks and Defenses](http://cc0x1f.net/publications/transient_sytematization.pdf) by Canella, Van Bulck, Schwarz, Lipp, von Berg, Ortner, Piessens, Evtyushkin and Gruss
## Content
This project provides two different things:
* In the docs folder, we provide the source for the content of the [transient.fail](http://transient.fail) website.
* In the pocs folder, we provide our proof-of-concept implementations as well as two libraries required for them. Libcache is a small library that provides all the required functionality for time measurement, flushing and loading values, TSX transactions and so on. Libpte is a fork of [PTEditor](https://github.com/misc0110/PTEditor) developed by Michael Schwarz and allows manipulation of paging structures via a Linux kernel module.
## Status
Transient Fail is under active development as we add new proof-of-concepts that we discover during our research. We invite everybody who wants to contribute to do so via pull requests.
## Compilers and Operating Systems
So far, we only support Linux with gcc on x86 and ARMv8. Therefore, we have only tested them on such platforms, but welcome any feedback and pull requests on other platforms.
## Literature
* [Meltdown](https://meltdownattack.com)
* [Spectre](https://spectreattack.com)
* [Foreshadow](https://foreshadowattack.eu)
* [Systematic Evaluation](https://www.usenix.org/conference/usenixsecurity19/presentation/canella)
* [SpectreReturns](https://www.usenix.org/conference/woot18/presentation/koruyeh)
* [ret2spec](https://arxiv.org/pdf/1807.10364.pdf)
* [LazyFP](https://arxiv.org/pdf/1806.07480.pdf)
================================================
FILE: docs/CNAME
================================================
transient.fail
================================================
FILE: docs/bibliography.js
================================================
var sources = {
"Canella2018": {
"title": "A Systematic Evaluation of Transient Execution Attacks and Defenses",
"author": "Claudio Canella, Jo Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, Daniel Gruss",
"url": "https://arxiv.org/pdf/1811.05441.pdf",
"conference": "USENIX Security 2019"
},
"Kocher2019": {
title: "Spectre Attacks: Exploiting Speculative Execution",
author: "Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, Yuval Yarom",
url: "https://spectreattack.com/spectre.pdf",
conference: "IEEE S&P 2019"
},
"Lipp2018": {
title: "Meltdown: Reading Kernel Memory from User Space",
author: "Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, Mike Hamburg",
url: "https://meltdownattack.com/meltdown.pdf",
conference: "USENIX Security 2018"
},
"Schwarz2019": {
title: "ZombieLoad: Cross-Privilege-Boundary Data Sampling",
author: "Michael Schwarz, Moritz Lipp, Daniel Moghimi, Jo Van Bulck, Julian Stecklina, Thomas Prescher, Daniel Gruss",
url: "https://zombieloadattack.com/zombieload.pdf",
conference: "ACM CCS 2019"
},
"Evtyushkin2018": {
title: "BranchScope: A New Side-Channel Attack on Directional Branch Predictor",
author: "Dmitry Evtyushkin, Ryan Riley, Nael Abu-Ghazaleh, Dmitry Ponomarev",
url: "http://www.cs.ucr.edu/~nael/pubs/asplos18.pdf",
conference: "ASPLOS 2018"
},
"Fog": {
url: "https://www.agner.org/optimize/microarchitecture.pdf",
author: "Agner Fog",
title: "The microarchitecture of Intel, AMD and VIA CPUs"
},
"Maisuradze2018": {
url: "https://arxiv.org/pdf/1807.10364.pdf",
title: "ret2spec: Speculative Execution Using Return Stack Buffers",
author: "Giorgi Maisuradze, Christian Rossow",
conference: "ACM CCS 2018"
},
"Koruyeh2018": {
url: "https://www.usenix.org/system/files/conference/woot18/woot18-paper-koruyeh.pdf",
title: "Spectre Returns! Speculation Attacks using the Return Stack Buffer",
author: "Esmaeil Mohammadian Koruyeh, Khaled N. Khasawneh, Chengyu Song, Nael Abu-Ghazaleh",
conference: "USENIX WOOT 2018"
},
"Horn2018": {
url: "https://bugs.chromium.org/p/project-zero/issues/detail?id=1528",
title: "Speculative execution, variant 4: speculative store bypass",
author: "Jann Horn"
},
"Stecklina2018": {
url: "https://arxiv.org/pdf/1806.07480.pdf",
title: "LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels",
author: "Julian Stecklina, Thomas Prescher"
},
"Intel2018": {
url: "https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf",
author: "Intel",
title: "Speculative Execution Side Channel Mitigations"
},
"ARM2018": {
url: "https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper",
author: "ARM",
title: "Whitepaper Cache Speculation Side-channels"
},
"VanBulck2018": {
title: "Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution",
author: "Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, Raoul Strackx",
url: "https://foreshadowattack.eu/foreshadow.pdf",
conference: "USENIX Security 2018"
},
"Weisse2018": {
title: "Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution",
author: "Ofir Weisse, Jo Van Bulck, Marina Minkin, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Raoul Strackx, Thomas F. Wenisch, Yuval Yarom",
url: "https://foreshadowattack.eu/foreshadow-NG.pdf"
},
"Kiriansky2018": {
url: "https://arxiv.org/pdf/1807.03757.pdf",
title: "Speculative Buffer Overflows: Attacks and Defenses",
author: "Vladimir Kiriansky, Carl Waldspurger"
},
"VanSchaik2019": {
title: "RIDL: Rogue In-flight Data Load",
author: "Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida",
url: "https://mdsattacks.com/files/ridl.pdf",
conference: "IEEE S&P 2019"
},
"RIDLAddendum1": {
title: "Addendum 1 to RIDL: Rogue In-flight Data Load",
author: "Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida",
url: "https://mdsattacks.com/files/ridl-addendum.pdf",
conference: "Addendum to IEEE S&P 2019 paper",
},
"Canella2019": {
title: "Fallout: Leaking Data on Meltdown-Resistant CPUs",
author: "Claudio Canella, Daniel Genkin, Lukas Giner, Daniel Gruss, Moritz Lipp, Marina Minkin, Daniel Moghimi, Frank Piessens, Michael Schwarz, Berk Sunar, Jo Van Bulck, Yuval Yarom",
url: "https://dl.acm.org/doi/abs/10.1145/3319535.3363219",
conference: "ACM CCS 2019"
},
"IntelMDS": {
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling",
author: "Intel",
title: "Deep Dive: Intel Analysis of Microarchitectural Data Sampling"
},
"IntelTAA": {
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort",
author: "Intel",
title: "Deep Dive: Intel Transactional Synchronization Extensions (Intel TSX) Asynchronous Abort"
},
"Chen2019": {
title: "SGXPECTRE: Stealing Intel Secrets from SGX Enclaves via Speculative Execution",
author: "Guoxing Chen, Sanchuan Chen, Yuan Xiao, Yinqian Zhang, Zhiqiang Lin, Ten H. Lai",
conference: "IEEE EuroS&P 2019",
url: "https://arxiv.org/pdf/1802.09085.pdf"
},
"Falk2019": {
author: "Brandon Falk",
title: "CPU Introspection: Intel Load Port Snooping",
url: "https://gamozolabs.github.io/metrology/2019/12/30/load-port-monitor.html",
conference: "Gamozo Labs Blog",
},
};
================================================
FILE: docs/css/style.css
================================================
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cursor: pointer;
display: flex;
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================================================
FILE: docs/dist/index.js
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================================================
FILE: docs/dist/typescript/d3.d.ts
================================================
import { hierarchy, stratify, tree, treemap } from "d3-hierarchy";
import { select, selectAll } from "d3-selection";
import { zoom } from "d3-zoom";
declare const _default: {
hierarchy: typeof hierarchy;
stratify: typeof stratify;
tree: typeof tree;
treemap: typeof treemap;
select: typeof select;
selectAll: typeof selectAll;
event: any;
zoom: typeof zoom;
};
export default _default;
================================================
FILE: docs/dist/typescript/draw-links.d.ts
================================================
import { ITreeConfig } from "./typings";
interface ICoordinates {
x: number;
y: number;
}
export declare const generateLinkLayout: (s: ICoordinates, d: ICoordinates, treeConfig: ITreeConfig) => string;
export {};
================================================
FILE: docs/dist/typescript/index.d.ts
================================================
import { ITreeConfig } from "./typings";
export declare function create(userSettings: Partial<ITreeConfig>): {
refresh: (data: any, newSettings?: Partial<ITreeConfig> | undefined) => void;
clean: (keepConfig: boolean) => void;
};
================================================
FILE: docs/dist/typescript/initializeSVG.d.ts
================================================
import * as d3 from "d3-selection";
import { ITreeConfig } from "./typings";
export declare const initiliazeSVG: (treeConfig: ITreeConfig) => d3.Selection<SVGGElement, unknown, HTMLElement, any>;
================================================
FILE: docs/dist/typescript/link-enter.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ITreeConfig } from "./typings";
export declare const drawLinkEnter: (link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, computedTree: HierarchyPointNode<{}>, settings: ITreeConfig) => Selection<SVGPathElement, HierarchyPointNode<{}>, SVGGElement, {}>;
================================================
FILE: docs/dist/typescript/link-exit.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ITreeConfig } from "./typings";
export declare const drawLinkExit: (link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, settings: ITreeConfig) => void;
================================================
FILE: docs/dist/typescript/link-update.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ITreeConfig } from "./typings";
export declare const drawLinkUpdate: (linkEnter: Selection<SVGPathElement, HierarchyPointNode<{}>, SVGGElement, {}>, link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, settings: ITreeConfig) => void;
================================================
FILE: docs/dist/typescript/links/draw-links.d.ts
================================================
import { ITreeConfig } from "../typings";
interface ICoordinates {
x: number;
y: number;
}
export declare const generateLinkLayout: (s: ICoordinates, d: ICoordinates, treeConfig: ITreeConfig) => string;
export {};
================================================
FILE: docs/dist/typescript/links/link-enter.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "../typings";
export declare const drawLinkEnter: (link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, settings: ITreeConfig, nodes: ExtendedHierarchyPointNode[], oldNodes: ExtendedHierarchyPointNode[]) => Selection<SVGPathElement, HierarchyPointNode<{}>, SVGGElement, {}>;
================================================
FILE: docs/dist/typescript/links/link-exit.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "../typings";
export declare const drawLinkExit: (link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, settings: ITreeConfig, nodes: ExtendedHierarchyPointNode[], oldNodes: ExtendedHierarchyPointNode[]) => void;
================================================
FILE: docs/dist/typescript/links/link-update.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
import { BaseType, Selection } from "d3-selection";
import { ITreeConfig } from "../typings";
export declare const drawLinkUpdate: (linkEnter: Selection<SVGPathElement, HierarchyPointNode<{}>, SVGGElement, {}>, link: Selection<BaseType, HierarchyPointNode<{}>, SVGGElement, {}>, settings: ITreeConfig) => void;
================================================
FILE: docs/dist/typescript/node-enter.d.ts
================================================
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "./typings";
export declare const placeNodeEnter: (node: Selection<BaseType, ExtendedHierarchyPointNode, SVGGElement, {}>, settings: ITreeConfig) => Selection<SVGGElement, ExtendedHierarchyPointNode, SVGGElement, {}>;
================================================
FILE: docs/dist/typescript/node-exit.d.ts
================================================
export declare const placeExit: (node: any, settings: any) => any;
================================================
FILE: docs/dist/typescript/nodes/node-enter.d.ts
================================================
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "../typings";
export declare const drawNodeEnter: (node: Selection<BaseType, ExtendedHierarchyPointNode, SVGGElement, {}>, settings: ITreeConfig, nodes: ExtendedHierarchyPointNode[], oldNodes: ExtendedHierarchyPointNode[]) => Selection<SVGGElement, ExtendedHierarchyPointNode, SVGGElement, {}>;
================================================
FILE: docs/dist/typescript/nodes/node-exit.d.ts
================================================
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "../typings";
export declare const drawNodeExit: (node: Selection<BaseType, ExtendedHierarchyPointNode, SVGGElement, {}>, settings: ITreeConfig, nodes: ExtendedHierarchyPointNode[], oldNodes: ExtendedHierarchyPointNode[]) => void;
================================================
FILE: docs/dist/typescript/nodes/node-update.d.ts
================================================
import { BaseType, Selection } from "d3-selection";
import { ExtendedHierarchyPointNode, ITreeConfig } from "../typings";
export declare const drawNodeUpdate: (nodeEnter: Selection<SVGGElement, ExtendedHierarchyPointNode, SVGGElement, {}>, node: Selection<BaseType, ExtendedHierarchyPointNode, SVGGElement, {}>, settings: ITreeConfig) => void;
================================================
FILE: docs/dist/typescript/prepare-data.d.ts
================================================
import { HierarchyNode } from "d3-hierarchy";
import { ITreeConfig } from "./typings";
export declare const generateNestedData: (data: any, treeConfig: ITreeConfig) => HierarchyNode<any>;
export declare const generateBasicTreemap: (treeConfig: ITreeConfig) => import("d3-hierarchy").TreeLayout<unknown>;
================================================
FILE: docs/dist/typescript/services.d.ts
================================================
export declare const getAreaSize: (htmlId: string) => {
areaWidth: number;
areaHeight: number;
};
================================================
FILE: docs/dist/typescript/typings.d.ts
================================================
import { HierarchyPointNode } from "d3-hierarchy";
export interface ITreeConfig {
htmlId: string;
idKey: string;
relationnalField: string;
hasFlatData: boolean;
nodeWidth: number;
nodeHeight: number;
mainAxisNodeSpacing: number | "auto";
renderNode: (node: any) => string | null;
linkShape?: "quadraticBeziers" | "curve" | "orthogonal" | "";
linkColor: (node: any) => string;
linkWidth: (node: any) => number;
onNodeClick: (node: any) => void;
onNodeMouseEnter: (node: any) => void;
onNodeMouseLeave: (node: any) => void;
isHorizontal: boolean;
hasPanAndZoom: boolean;
duration: number;
marginTop: number;
marginBottom: number;
marginLeft: number;
marginRight: number;
secondaryAxisNodeSpacing: number;
}
export interface ExtendedHierarchyPointNode extends HierarchyPointNode<{}> {
x0?: number;
y0?: number;
}
================================================
FILE: docs/dist/typescript/utils.d.ts
================================================
import { ExtendedHierarchyPointNode, ITreeConfig } from "./typings";
export declare const getAreaSize: (
htmlId: string
) => {
areaWidth: number;
areaHeight: number;
};
declare type Result = ExtendedHierarchyPointNode & {
x0: number;
y0: number;
};
export declare const getFirstDisplayedAncestor: (
ghostNodes: ExtendedHierarchyPointNode[],
viewableNodes: ExtendedHierarchyPointNode[],
id: string
) => Result;
export declare const setNodeLocation: (
xPosition: number,
yPosition: number,
settings: ITreeConfig
) => string;
export {};
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@inproceedings{Canella2019extended,<br>
title = {{A Systematic Evaluation of Transient Execution Attacks and Defenses}},<br>
author = {Canella, Claudio and Van Bulck, Jo and Schwarz, Michael and Lipp, Moritz and von Berg, Benjamin and Ortner, Philipp and Piessens, Frank and Evtyushkin, Dmitry and Gruss, Daniel},<br>
booktitle = {USENIX Security Symposium},<br>
year = {2019},<br>
note = {extended classification tree at https://transient.fail/},<br>
}<br>
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================================================
FILE: docs/js/filter.js
================================================
var index = {};
function buildIndex() {
index = {};
for(let node of data) {
if(index[node.id] !== undefined) {
alert("Duplicate ID " + node.id + ": " + node.title + " and " + index[node.id].title);
}
index[node.id] = node;
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var show_spectre = $("#toggleSpectre").prop("checked");
var show_todo = $("#toggleTodo").prop("checked");
var show_fails = $("#toggleFails").prop("checked");
var show_working = $("#toggleWorking").prop("checked");
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// var show_nopaper = $("#toggleNoPaper").prop("checked");
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================================================
FILE: docs/js/tree.js
================================================
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================================================
FILE: docs/tree.js
================================================
var color = {
root: "#DDDDDD",
group: "#BBBBFF",
works: "#FF5722",
fails: "#8BC34A",
todo: "#FFA500"
}
var data = [{
id: 1,
title: "Transient cause",
father: null,
img: "transient-overview.svg",
description: "We split the tree based on the cause for entering transient execution. If the cause is handling a fault or a microcode assist upon instruction retirement, we have a Meltdown-type attack. If the cause is a control or data flow prediction, we have a Spectre-type attack.",
sources: [
sources["Canella2018"],
sources["Kocher2019"],
sources["Lipp2018"]
],
color: color.root
},
{
id: 2,
title: "Spectre-type",
img: "spectre-root.svg",
text_top: "prediction",
description: "Spectre exploits a performance optimization in modern CPUs. Instead of waiting for the correct resolution of a branch, the CPU tries to predict the most likely outcome of the branch and starts transiently executing along the predicted path. Upon resolving the branch, the CPU discards the results of the transient execution if the prediction was wrong but does not revert changes in the microarchitecture. The prediction is based on events in the past, allowing an attacker to mistrain the predictor to leak data through the microarchitecture that should normally not be accessible to the attacker.",
sources: [
sources["Kocher2019"],
sources["Canella2018"]
],
father: 1,
color: color.group
},
{
id: 3,
title: "Meltdown-type",
img: "meltdown-root.svg",
text_bottom: "fault/assist",
father: 1,
description: "Meltdown exploits the fact that exceptions are only raised (i.e., become architecturally visible) upon the retirement of the faulting instruction. In some microarchitectures, this property allows transient instructions ahead in the pipeline to compute on unauthorized results of the instruction that is about to suffer a fault. The CPU's in-order instruction-retirement mechanism takes care to discard any architectural effects of such computations, but secrets may leak through microarchitectural covert channels.<p/>We further classify Meltdown-type attacks based on the fault condition. A first category of <i>architectural faults</i> iterates over all possible Intel x86 exception types. A second category considers so-called <i>microarchitectural faults</i>, which are never visible at the architectural level, by branching on different conditions that provoke microcode assists.<p/>The resulting unambiguous naming scheme results in Meltdown-type attack leaves of the form “Meltdown-TC-BUF”, where TC denotes the transient cause (specific exception type or microcode assist) and BUF denotes the microarchitectural buffer responsible for the leakage.",
sources: [
sources["Lipp2018"],
sources["VanBulck2018"],
sources["VanSchaik2019"],
sources["Canella2019"],
sources["Schwarz2019"],
sources["Canella2018"],
],
color: color.group
},
{
id: 4,
title: "Spectre-PHT",
alias: "Spectre v1",
img: "spectre.svg",
text_top: "microarchitectural buffer",
father: 2,
description: "Kocher et al. first introduced Spectre-PHT, an attack that poisons the Pattern History Table (PHT) to mispredict the direction (taken or not-taken) of conditional branches. Depending on the underlying microarchitecture, the PHT is accessed based on a combination of virtual address bits of the branch instruction plus a hidden Branch History Buffer (BHB) that accumulates global behavior for the last N branches on the same physical core.",
sources: [
sources["Canella2018"],
sources["Kocher2019"],
sources["Evtyushkin2018"],
sources["Fog"]
],
names: [
{
title: "Spectre variant 1",
url: "https://spectreattack.com/"
},
{
title: "Spectre variant 1.1",
url: "https://arxiv.org/pdf/1807.03757.pdf"
},
{
title: "Bounds Check Bypass (BCB)",
url: "https://software.intel.com/security-software-guidance/api-app/sites/default/files/336983-Intel-Analysis-of-Speculative-Execution-Side-Channels-White-Paper.pdf"
}
],
cve: [{
title: "CVE-2017-5753",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5753"
}],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT"
},
{
title: "https://github.com/google/safeside",
url: "https://github.com/google/safeside/tree/master/demos"
}
],
color: color.group
},
{
id: 5,
title: "Spectre-BTB",
alias: "Spectre v2",
img: "spectre.svg",
father: 2,
description: "In Spectre-BTB, the attacker poisons the Branch Target Buffer (BTB) to steer the transient execution to a mispredicted branch target. For direct branches, the CPU indexes the BTB using a subset of the virtual address bits of the branch instruction to yield the predicted jump target. For indirect branches, CPUs use different mechanisms, which may take into account global branching history accumulated in the BHB when indexing the BTB. We refer to both types as Spectre-BTB.<p>Contrary to Spectre-PHT, where transient instructions execute along a restricted mispredicted path, Spectre-BTB enables redirection of transient control flow to an arbitrary destination. Adopting established techniques from return-oriented programming (ROP) attacks, but abusing BTB poisoning instead of application-level vulnerabilities, selected code “gadgets” found in the victim address space may be chained together to construct arbitrary transient instruction sequences. Hence, while the success of Spectre-PHT critically relies on unintended leakage along the mispredicted code path, ROP-style gadget abuse in Spectre-BTB enables more direct construction of covert channels that expose secrets from the transient domain.",
sources: [
sources["Kocher2019"],
sources["Canella2018"]
],
names: [
{
title: "Spectre variant 2",
url: "https://spectreattack.com/"
},
{
title: "Branch Target Injection (BTI)",
url: "https://software.intel.com/security-software-guidance/api-app/sites/default/files/336983-Intel-Analysis-of-Speculative-Execution-Side-Channels-White-Paper.pdf"
}
],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB"
},
{
title: "https://github.com/google/safeside",
url: "https://github.com/google/safeside/tree/master/demos"
}
],
color: color.group
},
{
id: 6,
title: "Spectre-RSB",
alias: "ret2spec",
img: "spectre.svg",
father: 2,
description: "Maisuradze and Rossow and Koruyeh et al. introduced a Spectre variant that exploits the Return Stack Buffer (RSB). The RSB is a small per-core microarchitectural buffer that stores the virtual addresses following the N most recent <code>call</code> instructions. When encountering a <code>ret</code> instruction, the CPU pops the topmost element from the RSB to predict the return flow.<p>Misspeculation arises whenever the RSB layout diverges from the actual return addresses on the software stack. Such disparity for instance naturally occurs when restoring kernel/enclave/user stack pointers upon protection domain switches.<p>Furthermore, same-address-space adversaries may explicitly overwrite return addresses on the software stack, or transiently execute <code>call</code> instructions which update the RSB without committing architectural effects. This may allow untrusted code executing in a sandbox to transiently divert return control flow to interesting code gadgets outside of the sandboxed environment.<p>Due to the fixed-size nature of the RSB, a special case of misspeculation occurs for deeply nested function calls. Since the RSB can only store return addresses for the N most recent calls, an underfill occurs when the software stack is unrolled. In this case, the RSB can no longer provide accurate predictions. Starting from Skylake, Intel CPUs use the BTB as a fallback, thus allowing Spectre-BTB-style attacks triggered by <code>ret</code> instructions.",
sources: [
sources["Maisuradze2018"],
sources["Koruyeh2018"],
sources["Canella2018"]
],
names: [
{
title: "ret2spec",
url: "https://arxiv.org/pdf/1807.10364.pdf",
},
{
title: "SpectreRSB",
url: "https://www.usenix.org/conference/woot18/presentation/koruyeh",
},
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB"
}],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
color: color.group
},
{
id: 7,
title: "Spectre-STL",
alias: "Spectre v4",
img: "spectre.svg",
father: 2,
description: "Speculation in modern CPUs is not restricted to control flow but also includes predicting dependencies in the data flow. A common type, a Store To Load (STL) dependency, requires that a memory load shall not be executed before all preceding stores writing to the same location have completed. However, even before the addresses of all prior stores in the pipeline are known, the CPU's memory disambiguator may predict which loads can already be executed speculatively. <p>When the disambiguator predicts that a load does not have a dependency on a prior store, the load reads data from the L1 data cache. When the addresses of all prior stores are known, the prediction is verified. If any overlap is found, the load and all following instructions are re-executed. </p><p>Jann Horn (Google Project Zero) showed how mispredictions by the memory disambiguator could be abused to speculatively bypass store instructions. Like previous attacks, Spectre-STL adversaries rely on an appropriate transient instruction sequence to leak unsanitized stale values via a microarchitectural covert channel. Furthermore, operating on stale pointer values may speculatively break type and memory safety guarantees in the transient execution domain. </p>",
sources: [
sources["Horn2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/STL"
},
{
title: "https://github.com/google/safeside",
url: "https://github.com/google/safeside/tree/master/demos"
}
],
names: [
{
title: "Spectre variant 4",
url: "https://software.intel.com/security-software-guidance/software-guidance/speculative-store-bypass"
},
{
title: "Speculative Store Bypass (SSB)",
url: "https://software.intel.com/security-software-guidance/software-guidance/speculative-store-bypass"
},
],
cve: [{
title: "CVE-2018-3639",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3639"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/speculative-store-bypass"
},
{
title: "AMD",
},
{
title: "ARM",
},
],
color: color.works
},
{
id: 8,
title: "Meltdown-NM-REG",
alias: "LazyFP",
father: 3,
description: "During a context switch, the OS has to save all the registers, including the floating point unit (FPU) and SIMD registers. These latter registers are large and saving them would slow down context switches. Therefore, CPUs allow for a lazy state switch, meaning that instead of saving the registers, the FPU is simply marked as “not available”. The first FPU instruction issued after the FPU was marked as “not available” causes a device-not-available (#NM) exception, allowing the OS to save the FPU state of previous execution context before marking the FPU as available again. <p/> Stecklina and Prescher propose an attack on the above lazy state switch mechanism. The attack consists of three steps. In the first step, a victim performs operations loading data into the FPU registers. Then, in the second step, the CPUswitches to the attacker and marks the FPU as “not available”. The attacker now issues an instruction that uses the FPU, which generates an #NM fault. Before the faulting instruction retires, however, the CPU has already transiently executed the following instructions using data from the previous context. As such, analogous to previous Meltdown-type attacks, a malicious transient instruction sequence following the faulting instruction can encode the unauthorized FPU register contents through a microarchitectural covert channel.",
sources: [
sources["Stecklina2018"],
sources["Canella2018"]
],
names: [
{
title: "Lazy FP State Restore (LazyFP)",
url: "https://www.cyberus-technology.de/posts/2018-06-06-intel-lazyfp-vulnerability.html"
},
],
cve: [{
title: "CVE-2018-3665",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3665"
}],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/NM"
}],
affects: [
{
title: "Intel",
url: "https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00145.html"
},
],
color: color.works
},
{
id: 9,
title: "Meltdown-AC",
alias: "",
father: 3,
description: "Upon detecting an unaligned memory operand, the CPU may generate an alignment-check exception (#AC) when the EFLAGS.AC flag is set. In our tests on Intel CPUs, we were unable to transiently encode the results of unaligned memory accesses. We suspect that this is because #AC is generated early in the pipeline, even before the operand’s virtual address is translated to a physical one. However, this appears not to be the case on some AMD and ARM microarchitectures, on which it is possible to transiently leak data after the exception.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/AC"
}],
affects: [
{
title: "AMD",
url: "https://www.amd.com/system/files/documents/security-whitepaper.pdf"
},
{
title: "ARM",
},
],
color: color.group
},
{
id: 67,
title: "Meltdown-AC-LFB",
alias: "RIDL",
img: "mds.svg",
father: 9,
description: "The RIDL addendum explained that misaligned loads due to the AC flag may leak data from line-fill buffers. Interestingly, in contrast to the main RIDL variant Meltdown-P-LFB exploiting page faults, Meltdown-AC-LFB may work even on processors enumerating RDCL_NO silicon mitigations.",
sources: [
sources["RIDLAddendum1"],
sources["VanSchaik2019"],
sources["IntelMDS"],
],
names: [
{
title: "Rogue In-flight Data Load (RIDL) Addendum",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Fill Buffer Data Sampling (MFBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12130",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12130"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
poc: [{
title: "https://github.com/vusec/ridl",
url: "https://github.com/vusec/ridl",
}],
color: color.works
},
{
id: 68,
title: "Meltdown-AC-LP",
alias: "RIDL",
img: "mds.svg",
father: 9,
description: "The RIDL addendum explained that misaligned loads due to the AC flag may leak data from load ports. Interestingly, in contrast to the main RIDL variant Meltdown-P-LFB exploiting page faults, Meltdown-AC-LP may work even on processors enumerating RDCL_NO silicon mitigations.",
sources: [
sources["RIDLAddendum1"],
sources["VanSchaik2019"],
sources["Falk2019"],
sources["IntelMDS"],
],
names: [
{
title: "Rogue In-flight Data Load (RIDL) Addendum",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Load Port Data Sampling (MLPDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12127",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12127"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
poc: [{
title: "https://github.com/vusec/ridl",
url: "https://github.com/vusec/ridl",
}],
color: color.works
},
{
id: 10,
title: "Meltdown-DE",
father: 3,
description: "On the ARM microarchitectures we tested, division by zero produces no exception, merely yielding zero. As there is no fault, we do not count this as a Meltdown variant on ARM. On x86, the division raises a divide-by-zero exception (#DE). On both the AMD and Intel microarchitectures we tested, the CPU continues with transient execution after the exception, using zero as the result of the division. Thus the division itself does not leak a value (for example the numerator) but subsequent transient execution can still be used to leak values.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/DE"
}],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
],
color: color.works
},
{
id: 11,
title: "Meltdown-PF",
img: "pte.svg",
father: 3,
description: "The category of Meltdown attacks caused by a page fault. As there are many possibilities for a page fault, the attacks are further classified by the bit in the page-table entry causing the page fault.",
sources: [
sources["Canella2018"]
],
color: color.group
},
{
id: 12,
title: "Meltdown-UD",
father: 3,
description: "For our original paper we did not succeed in transiently executing instructions following an invalid opcode. Google's Safeside project subsequently achieved this on ARM, and we have updated our PoC accordingly. We suspect that on Intel and AMD CPUs exceptions during instruction fetch or decode are immediately handled by the CPU, without first buffering the offending instruction in the ROB. Hence, invalid opcodes would only leak if the microarchitectural effect is an effect caused by the invalid opcode itself, rather than by subsequent transient instructions.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/UD"
},
{
title: "https://github.com/google/safeside",
url: "https://github.com/google/safeside/blob/master/demos/meltdown_ud.cc"
}],
affects: [{
title: "ARM",
}],
color: color.works
},
{
id: 13,
title: "Meltdown-SS",
father: 3,
description: "We reliably found in our experiments on Intel CPUs that we cannot transiently leak the results of out-of-limit segment accesses. We suspect that, due to the simplistic IA32 segmentation design, segment limits are validated early-on, and immediately raise a #GP or #SS (stack-segment fault) exception, without sending the offending instruction to the ROB. However, we have successfully reproduced Meltdown-SS on some AMD microarchitectures, which is consistent with AMD's documentation that #SS does not suppress speculation.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/SS"
}],
affects: [
{
title: "AMD",
url: "https://www.amd.com/system/files/documents/security-whitepaper.pdf"
}
],
color: color.works
},
{
id: 14,
title: "Meltdown-BR",
father: 3,
description: "A Meltdown-BR attack exploits transient execution following a #BR exception to encode out-of-bounds secrets that are never architecturally visible. As such, Meltdown-BR is an exception-driven alternative for Spectre-PHT. Using such an attack, an attcker can leak data safeguarded by either an IA32 bound instruction (Intel, AMD), or state-of-the-art MPX protection (Intel-only). This is the first experiment demonstrating a Meltdown-type transient execution attack exploiting delayed exception handling on AMD CPUs.",
sources: [
sources["Intel2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/BR"
}],
color: color.group
},
{
id: 15,
title: "Meltdown-GP",
father: 3,
description: "Similar to page faults, x86 general protection faults (#GP) have been abused in multiple Meltdown-type attacks. We hence categorize further based on #GP cause and targeted microarchitectural buffer.",
todo: "While we have done our best to explore all potentially exploitable causes for #GP exceptions in the x86 architecture, we encourage future research to further investigate potential Meltdown-GP variants.",
sources: [
sources["Canella2018"],
sources["ARM2018"],
sources["Intel2018"],
sources["Canella2019"]
],
color: color.group
},
{
id: 16,
title: "Meltdown-US",
img: "pte-us.svg",
father: 11,
description: "Modern CPUs commonly feature a “user/supervisor” (U/S) pagetable attribute to denote a virtual memory page as belonging to the OS kernel. Page faults raised by the U/S attribute can be abused to read cached kernel secrets, as well as to extract data from other microarchitectural buffers. We therefore categorize Meltdown-US further by the leakage source.",
sources: [
sources["Lipp2018"],
sources["Schwarz2019"],
sources["Canella2019"],
sources["Canella2018"]
],
color: color.group
},
{
id: 17,
title: "Meltdown-P",
img: "pte-p.svg",
father: 11,
description: "Meltdown-P exploits transient execution following a page fault when accessing unmapped pages (present bit clear). As with the U/S attribute, page faults caused by the present bit have been abused to extract data from a variety of buffers. We therefore categorize Meltdown-P further by the leakage source.",
sources: [
sources["VanBulck2018"],
sources["VanSchaik2019"],
sources["Canella2019"],
sources["Canella2018"]
],
color: color.group
},
{
id: 18,
title: "Meltdown-RW",
img: "pte-rw.svg",
alias: "v1.2",
father: 11,
description: "Kiriansky and Waldspurger presented the first Meltdown-type attack that bypasses page-table based access rights within the current privilege level. Specifically, they showed that transient execution does not respect the “read/write” page-table attribute. The ability to transiently overwrite read-only data within the current privilege level can bypass software-based sandboxes which rely on hardware enforcement of read-only memory.",
sources: [
sources["Kiriansky2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/RW"
}],
names: [
{
title: "Variant 1.2",
url: "https://arxiv.org/pdf/1807.03757.pdf"
},
],
affects: [
{
title: "Intel",
url: "https://www.intel.com/content/www/us/en/support/articles/000029382/processors.html"
},
{
title: "ARM",
}
],
color: color.works
},
{
id: 19,
title: "Meltdown-PK",
img: "pte-pk.svg",
father: 11,
description: "Intel Skylake-SP server CPUs support memory-protection keys for user space (PKU). This feature allows processes to change the access permissions of a page directly from user space, i.e., without requiring a syscall/hypercall. Thus, with PKU, user-space applications can implement efficient hardware-enforced isolation of trusted parts. A Meltdown-PK attack bypasses both the read and write isolation provided by the PKU. Meltdown-PK works if an attacker has code execution in the containing process, even if the attacker cannot execute the <code>wrpkru</code> instruction (e.g., blacklisting).",
todo: "We encourage exploring the possibility of using Meltdown-PK to leak data from other buffers apart from the L1 cache and store buffer.",
sources: [
sources["Canella2018"]
],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/insights/more-information-transient-execution-findings",
},
],
color: color.group
},
{
id: 70,
title: "Meltdown-PK-L1",
father: 19,
description: "As part of our systematic analysis, we presented a novel Meltdown-PK-L1 variant which bypasses both the read and write isolation provided by PKU to leak unauthorized data from the L1 cache.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/PK"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/insights/more-information-transient-execution-findings",
},
],
color: color.works
},
{
id: 71,
title: "Meltdown-PK-SB",
alias: "Fallout",
img: "mds.svg",
father: 19,
description: "The Fallout paper includes an experiment to leak data from the store buffer using a faulting load from a page marked as unreadable with PKU.",
sources: [
sources["Canella2019"]
],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/insights/more-information-transient-execution-findings",
},
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12126",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
}],
color: color.works
},
{
id: 20,
title: "Meltdown-XD",
img: "pte-x.svg",
father: 11,
description: "On our test systems, we did not succeed in transiently executing instructions residing in non-executable memory.",
sources: [
sources["Canella2018"]
],
color: color.fails
},
{
id: 21,
title: "Meltdown-SM-SB",
alias: "Fallout",
img: "mds.svg",
father: 11,
description: "Although supervisor mode access prevention (SMAP) raises a page fault (#PF) when accessing user-space memory from the kernel, it seems to be free of any Meltdown effect in our experiments. Thus, we were not able to leak user data from kernel space using Meltdown-SM in our experiments.<p/>However, the Fallout paper includes an experiment to leak store buffer data using SMAP exceptions from kernel space.",
sources: [
sources["Canella2018"],
sources["Canella2019"]
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12126",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
}],
affects: [
{
title: "Intel"
}
],
color: color.works
},
{
id: 22,
title: "Meltdown-MPX",
father: 14,
description: "An attacker can leak data safeguarded by state-of-the-art MPX protection (Intel-only).",
sources: [
sources["Intel2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/BR"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/insights/more-information-transient-execution-findings",
},
],
color: color.works
},
{
id: 23,
title: "Meltdown-BND",
father: 14,
description: "An attcker can leak data safeguarded by an IA32 bound instruction (Intel, AMD). This is the first experiment demonstrating a Meltdown-type transient execution attack exploiting delayed exception handling on AMD CPUs.",
sources: [
sources["Intel2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/BR"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/insights/more-information-transient-execution-findings",
},
{
title: "AMD"
}
],
color: color.works
},
{
id: 24,
title: "Cross-address-space",
text_top: "mistraining strategy",
description: "In a cross-address-space scenario, an attacker has two options. In the first, an attacker can mirror the virtual address space layout of the victim on a hyperthread (same physical core) and mistrain at the exact same virtual address as the victim branch. We refer to this as cross-address-space in-place (CA-IP). In the second, the attacker mistrains the PHT on a congruent virtual address in a different address space. We refer to this as cross-address-space out-of-place (CA-OP). Cross-address-space attacks are possible because the PHT is shared between hyperthreads on the same logical core.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT"
}],
father: 4,
color: color.group
},
{
id: 25,
title: "Same-address-space",
father: 4,
description: "In a same-address-space scenario, an attacker has two options. The first option is to mistrain the exact location that is later on attacked. We refer to this as same-address-space in-place (SA-IP), In the second scenario, a congruent address is used for the mistraining. This is possible because only a subset of the virtual address is used for indexing the PHT. We refer to this as same-address-space out-of-place (SA-OP).",
sources: [
sources["Kocher2019"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT"
}],
color: color.group
},
{
id: 26,
title: "Cross-address-space",
father: 5,
description: "In a cross-address-space scenario, an attacker has two options. In the first, an attacker can mirror the virtual address space layout of the victim on a hyperthread (same physical core) and mistrain at the exact same virtual address as the victim branch. We refer to this as cross-address-space in-place (CA-IP). In the second, the attacker mistrains the BTB on a congruent virtual address in a different address space. We refer to this as cross-address-space out-of-place (CA-OP). Cross-address-space attacks are possible because the BTB is shared between hyperthreads on the same logical core.",
sources: [
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB"
}],
color: color.group
},
{
id: 27,
title: "Same-address-space",
father: 5,
description: "In a same-address-space scenario, an attacker has two options. The first option is to mistrain the exact location that is later on attacked. We refer to this as same-address-space in-place (SA-IP), In the second scenario, a congruent address is used for the mistraining. This is possible because only a subset of the virtual address is used for indexing the BTB. We refer to this as same-address-space out-of-place (SA-OP).",
sources: [
sources["Kocher2019"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB"
}],
color: color.group
},
{
id: 28,
title: "Cross-address-space",
father: 6,
description: "In a cross-address-space RSB attack, an attacker cannot simply run on a hyperthread to influence the RSB. This is because the RSB is not shared between hyperthreads. Therefore, an attacker has to interleave the execution of their program with the victim's program to poison the RSB. This is possible in both in-place and out-of-place scenarios.",
sources: [
sources["Maisuradze2018"],
sources["Koruyeh2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB"
}],
color: color.group
},
{
id: 29,
title: "Same-address-space",
father: 6,
description: "In a same-address-space RSB attack, an attacker can explicitly overwrite the return address on the software stack or transiently execute <code>call</code> instructions. Another cause for misspeculation is deeply nested function calls. This is due to the limited size of the RSB. One natural occurrence of RSB misspeculation is when restoring the kernel/enclave/user stack pointer upon switching protection domains. In all those cases, the execution might be diverted to a special code gadget that leaks data.",
sources: [
sources["Maisuradze2018"],
sources["Koruyeh2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB"
}],
color: color.group
},
{
id: 30,
title: "PHT-CA-IP",
img: "spectre.svg",
text_top: "in-place (IP) vs. out-of-place (OP)",
father: 24,
description: "The cross-address-space, in-place variant of Spectre-PHT.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT/ca_ip"
}],
sources: [
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
cve: [{
title: "CVE-2017-5753",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5753"
}],
color: color.works
},
{
id: 31,
title: "PHT-CA-OP",
img: "spectre.svg",
father: 24,
description: "The cross-address-space, out-of-place variant of Spectre-PHT.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT/ca_oop"
}],
sources: [
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
cve: [{
title: "CVE-2017-5753",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5753"
}],
color: color.works
},
{
id: 32,
title: "PHT-SA-IP",
alias: "Spectre v1",
img: "spectre.svg",
father: 25,
description: "The same-address-space, in-place variant of Spectre-PHT. This was one of the first discovered variants. It is the best-known variant of Spectre-PHT.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT/sa_ip"
}],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
sources: [
sources["Kocher2019"],
sources["Kiriansky2018"],
sources["Canella2018"]
],
cve: [{
title: "CVE-2017-5753",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5753"
}],
color: color.works
},
{
id: 33,
title: "PHT-SA-OP",
img: "spectre.svg",
father: 25,
description: "The same-address-space, out-of-place variant of Spectre-PHT.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/PHT/sa_oop"
}],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
sources: [
sources["Canella2018"]
],
cve: [{
title: "CVE-2017-5753",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5753"
}],
color: color.works
},
{
id: 34,
title: "BTB-CA-IP",
alias: "Spectre v2",
img: "spectre.svg",
father: 26,
description: "The cross-address-space, in-place variant of Spectre-BTB. This was one of the first discovered variants.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB/ca_ip"
}],
sources: [
sources["Kocher2019"],
sources["Chen2019"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
color: color.works
},
{
id: 35,
title: "BTB-CA-OP",
alias: "Spectre v2",
img: "spectre.svg",
father: 26,
description: "The cross-address-space, out-of-place variant of Spectre-BTB. This was one of the first discovered variants.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB/ca_oop"
}],
sources: [
sources["Kocher2019"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
color: color.works
},
{
id: 36,
title: "BTB-SA-IP",
img: "spectre.svg",
father: 27,
description: "The same-address-space, in-place variant of Spectre-BTB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB/sa_ip"
}],
sources: [
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}
],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
color: color.works
},
{
id: 37,
title: "BTB-SA-OP",
alias: "Spectre v2",
img: "spectre.svg",
father: 27,
description: "The same-address-space, out-of-place variant of Spectre-BTB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/BTB/sa_oop"
}],
sources: [
sources["Chen2019"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
],
cve: [{
title: "CVE-2017-5715",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5715"
}],
color: color.works
},
{
id: 38,
title: "RSB-CA-IP",
alias: "ret2spec",
img: "spectre.svg",
father: 28,
description: "The cross-address-space, in-place variant of Spectre-RSB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB/ca_ip"
}],
sources: [
sources["Koruyeh2018"],
sources["Maisuradze2018"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
],
color: color.works
},
{
id: 39,
title: "RSB-CA-OP",
img: "spectre.svg",
father: 28,
description: "The cross-address-space, out-of-place variant of Spectre-RSB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB/ca_oop"
}],
sources: [
sources["Koruyeh2018"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
],
color: color.works
},
{
id: 40,
title: "RSB-SA-IP",
alias: "ret2spec",
img: "spectre.svg",
father: 29,
description: "The same-address-space, in-place variant of Spectre-RSB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB/sa_ip"
}],
sources: [
sources["Maisuradze2018"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
},
],
color: color.works
},
{
id: 41,
title: "RSB-SA-OP",
alias: "ret2spec",
img: "spectre.svg",
father: 29,
description: "The same-address-space, out-of-place variant of Spectre-RSB.",
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/spectre/RSB/sa_oop"
}],
sources: [
sources["Koruyeh2018"],
sources["Maisuradze2018"],
sources["Canella2018"]
],
affects: [
{
title: "Intel",
},
{
title: "AMD",
},
{
title: "ARM",
}, ],
color: color.works
},
{
id: 42,
title: "Meltdown-US-L1",
alias: "Meltdown",
img: "meltdown.svg",
father: 16,
description: "The original Meltdown attack reads cached kernel memory from user space on CPUs that do not transiently enforce the user/supervisor flag. In the trigger phase an unauthorized kernel address is dereferenced, which eventually causes a page fault. Before the fault becomes architecturally visible, however, the attacker executes a transient instruction sequence that for instance accesses a cache line based on the privileged data read by the trigger instruction. In the final phase, after the exception has been raised, the privileged data is reconstructed at the receiving end of the covert channel (e.g., Flush+Reload).",
sources: [
sources["Lipp2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/meltdown",
url: "https://github.com/IAIK/meltdown"
},
{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/US"
},
{
title: "https://github.com/google/safeside",
url: "https://github.com/google/safeside/tree/master/demos"
}
],
names: [
{
title: "Meltdown",
url: "https://meltdownattack.com/"
},
{
title: "Rogue Data Cache Load (RDCL)",
url: "https://software.intel.com/security-software-guidance/software-guidance/rogue-data-cache-load"
},
{
title: "Variant 3",
},
],
cve: [{
title: "CVE-2017-5754",
url: "https://nvd.nist.gov/vuln/detail/CVE-2017-5754"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/rogue-data-cache-load"
},
{
title: "ARM",
url: "https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability"
},
{
title: "IBM",
url: "https://www.ibm.com/blogs/psirt/potential-impact-processors-power-family/"
},
],
color: color.works
},
{
id: 43,
title: "Meltdown-US-LFB",
alias: "ZombieLoad v1",
img: "zombieload.svg",
father: 16,
description: "ZombieLoad uses various architectural and microarchitectural faults to leak data from the fill buffers. In contrast to Meltdown-US-L1, only the least-significant 6 bits of the virtual address can be used to address the data, thus giving less control over which data is leaked. However, this allows ZombieLoad to cross all privilege boundaries (user-to-user, kernel, Intel SGX, VM-to-VM, VM-to-hypervisor).",
sources: [
sources["Schwarz2019"],
sources["VanSchaik2019"],
sources["IntelMDS"],
],
names: [
{
title: "ZombieLoad",
url: "https://zombieloadattack.com/"
},
{
title: "Microarchitectural Fill Buffer Data Sampling (MFBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
poc: [{
title: "https://github.com/IAIK/ZombieLoad",
url: "https://github.com/IAIK/ZombieLoad/tree/master/attacker/variant1_linux"
}],
cve: [{
title: "CVE-2018-12130",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12130"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
color: color.works
},
{
id: 44,
title: "Meltdown-US-SB",
alias: "Fallout",
img: "mds.svg",
father: 16,
description: "Fallout exploits the fact that faulting loads can pick up previously stored values from the store buffer if the least-significant 12 bits of the virtual address match.",
sources: [
sources["Canella2019"],
sources["IntelMDS"],
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12126",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
color: color.works
},
{
id: 45,
title: "Meltdown-US-LP",
father: 16,
description: "Intel explains that faulting loads which span a 64-byte cacheline boundary may leak data from the processor's load ports.",
todo: "We encourage experimentation to confirm the possibility of reading CPU load port data through U/S exceptions.",
sources: [
sources["IntelMDS"],
],
names: [
{
title: "Microarchitectural Load Port Data Sampling (MLPDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12127",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12127"
}],
color: color.todo
},
{
id: 46,
title: "Meltdown-P-L1",
alias: "Foreshadow",
img: "foreshadow.svg",
father: 17,
description: "Meltdown-P-L1 exploits an “L1 Terminal Fault” (L1TF) microarchitectural condition when accessing unmapped pages. A terminal page fault occurs when accessing a page-table entry with either the “present” bit cleared or a “reserved” bit set. In such cases, the CPU immediately aborts address translation. However, since the L1 data cache is indexed in parallel to address translation, the page table entry’s physical address field (i.e., frame number) may still be passed to the L1 cache. Any data present in L1 and tagged with that physical address will now be forwarded to the transient execution, regardless of access permissions.</p>Foreshadow was initially demonstrated against Intel SGX technology, and a generalized form of the attack allows an attacker to bypass operating system or hypervisor isolation. This variation allows an untrusted virtual machine, controlling guest-physical addresses, to extract the host machine’s entire L1 data cache (including data belonging to the hypervisor or other virtual machines). The underlying problem is that a terminal fault in the guest page-tables early-outs the address translation process, such that guest-physical addresses are erroneously passed to the L1 data cache, without first being translated into a proper host physical address.</p>",
sources: [
sources["VanBulck2018"],
sources["Weisse2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/P"
},
{
title: "https://github.com/jovanbulck/sgx-step/",
url: "https://github.com/jovanbulck/sgx-step/tree/master/app/foreshadow"
}
],
names: [
{
title: "Foreshadow, Foreshadow-NG",
url: "https://foreshadowattack.eu/"
},
{
title: "L1 Terminal Fault (L1TF)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault",
}
],
cve: [{
title: "CVE-2018-3615",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3615"
},
{
title: "CVE-2018-3620",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3620"
},
{
title: "CVE-2018-3646",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3646"
}
],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/l1-terminal-fault"
},
{
title: "IBM",
url: "https://www.ibm.com/blogs/psirt/potential-impact-processors-power-family/"
},
],
color: color.works
},
{
id: 47,
title: "Meltdown-P-LFB",
alias: "RIDL",
img: "mds.svg",
father: 17,
description: "RIDL leaks in-flight data from the line-fill buffer (LFB) by exploiting faulting loads on non-present addresses. If the least-significant 6 bits of the non-present virtual address match a virtual address of data currently stored in the LFB, then this data can be leaked. Any data travelling between the L1 cache and the remaining memory subsystem has to go through the LFB and can be leaked with RIDL.",
sources: [
sources["VanSchaik2019"],
sources["Schwarz2019"],
sources["IntelMDS"],
],
names: [
{
title: "Rogue In-flight Data Load (RIDL)",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Fill Buffer Data Sampling (MFBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12130",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12130"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
poc: [{
title: "https://github.com/vusec/ridl",
url: "https://github.com/vusec/ridl",
}],
color: color.works
},
{
id: 48,
title: "Meltdown-P-SB",
alias: "Fallout",
img: "mds.svg",
father: 17,
description: "Fallout exploits the fact that faulting loads due to a non-present page fault can pick up previously stored values from the store buffer if the least-significant 12 bits of the virtual addresses match.",
sources: [
sources["Canella2019"],
sources["IntelMDS"],
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12126",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
color: color.works
},
{
id: 49,
title: "Meltdown-P-LP",
alias: "RIDL",
img: "mds.svg",
father: 17,
description: "Intel, the RIDL paper, and Brandon Falk describe that faulting loads which span a 64-byte cacheline boundary may leak data from the processor's load ports.",
sources: [
sources["Falk2019"],
sources["VanSchaik2019"],
sources["IntelMDS"],
],
names: [
{
title: "Rogue In-flight Data Load (RIDL)",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Load Port Data Sampling (MLPDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12127",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12127"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
poc: [{
title: "https://github.com/vusec/ridl",
url: "https://github.com/vusec/ridl",
}],
color: color.works
},
{
id: 50,
title: "Meltdown-CPL-REG",
alias: "v3a",
father: 15,
description: "Meltdown-CPL-REG allows an attacker to read privileged system registers. It was first discovered and published by ARM and subsequently Intel determined that their CPUs are also susceptible to the attack. Accessing privileged system registers (e.g., via <code>rdmsr</code>) raises a general protection fault (#GP) when the current privilege level (CPL) is not zero. Similarly to previous Meltdown-type attacks, however, the attack exploits the fact that the transient execution following the faulting instruction can still compute on the unauthorized data, and leak the system register contents through a microarchitectural covert channel.",
sources: [
sources["ARM2018"],
sources["Intel2018"],
sources["Canella2018"]
],
poc: [{
title: "https://github.com/IAIK/transientfail",
url: "https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/GP"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/rogue-system-register-read"
},
{
title: "ARM",
url: "https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability"
}
],
names: [
{
title: "Variant 3a",
},
{
title: "Rogue System Register Read (RSRR)",
url: "https://software.intel.com/security-software-guidance/api-app/sites/default/files/336983-Intel-Analysis-of-Speculative-Execution-Side-Channels-White-Paper.pdf"
}
],
cve: [{
title: "CVE-2018-3640",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-3640"
}],
color: color.works
},
{
id: 51,
title: "Meltdown-NC-SB",
alias: "Fallout",
img: "mds.svg",
father: 15,
description: "Meltdown-NC-SB abuses #GP exceptions from non-canonical addresses to read data from the store buffer.",
todo: "We encourage investigation of using non-canonical loads to leak data from other buffers.",
sources: [
sources["Canella2019"],
sources["IntelMDS"],
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
],
cve: [{
title: "CVE-2018-12126",
url: "https://nvd.nist.gov/vuln/detail/CVE-2018-12126"
}],
affects: [
{
title: "Intel",
url: "https://software.intel.com/security-software-guidance/software-guidance/microarchitectural-data-sampling"
},
],
color: color.works
},
{
id: 59,
title: "Meltdown-AVX",
father: 15,
description: "Meltdown-AVX abuses #GP exceptions caused by misaligned AVX vector load instructions. According to Intel, faulting or assisting vector SSE/AVX loads that are more than 64 bits in size may leak data.",
color: color.works,
sources: [
sources["IntelMDS"],
sources["Canella2019"],
sources["RIDLAddendum1"],
],
color: color.group
},
{
id: 65,
title: "Meltdown-AVX-SB",
alias: "Fallout",
img: "mds.svg",
father: 59,
description: "Meltdown-AVX-SB abuses #GP exceptions caused by misaligned AVX load instructions to read data from the store buffer.",
sources: [
sources["Canella2019"],
],
names: [
{
title: "Fallout",
url: "https://mdsattacks.com/"
},
{
title: "Microarchitectural Store Buffer Data Sampling (MSBDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling"
},
{
title: "Microarchitectural Data Sampling (MDS)",
url: "https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microar
gitextract_1s0czu4x/
├── LICENSE
├── README.md
├── docs/
│ ├── CNAME
│ ├── bibliography.js
│ ├── css/
│ │ └── style.css
│ ├── dist/
│ │ ├── index.js
│ │ └── typescript/
│ │ ├── d3.d.ts
│ │ ├── draw-links.d.ts
│ │ ├── index.d.ts
│ │ ├── initializeSVG.d.ts
│ │ ├── link-enter.d.ts
│ │ ├── link-exit.d.ts
│ │ ├── link-update.d.ts
│ │ ├── links/
│ │ │ ├── draw-links.d.ts
│ │ │ ├── link-enter.d.ts
│ │ │ ├── link-exit.d.ts
│ │ │ └── link-update.d.ts
│ │ ├── node-enter.d.ts
│ │ ├── node-exit.d.ts
│ │ ├── nodes/
│ │ │ ├── node-enter.d.ts
│ │ │ ├── node-exit.d.ts
│ │ │ └── node-update.d.ts
│ │ ├── prepare-data.d.ts
│ │ ├── services.d.ts
│ │ ├── typings.d.ts
│ │ └── utils.d.ts
│ ├── index.html
│ ├── js/
│ │ ├── export.js
│ │ ├── filter.js
│ │ └── tree.js
│ └── tree.js
└── pocs/
├── Makefile
├── get_hyperthread_pair.sh
├── libcache/
│ ├── Makefile
│ ├── cache.c
│ └── cache.h
├── libpte/
│ ├── .gitignore
│ ├── Makefile
│ ├── module/
│ │ ├── Makefile
│ │ ├── pteditor.c
│ │ └── pteditor.h
│ ├── ptedit.c
│ ├── ptedit.h
│ └── ptedit_header.h
├── meltdown/
│ ├── AC/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── BR/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── DE/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── GP/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── main.c
│ │ └── module/
│ │ ├── Makefile
│ │ └── kernel_module.c
│ ├── NM/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── main.c
│ │ ├── secret.h
│ │ └── victim.c
│ ├── P/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── PK/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── RW/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── SS/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── cacheutils.h
│ │ └── main.c
│ ├── UD/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── US/
│ ├── Makefile
│ ├── README.md
│ └── main.c
└── spectre/
├── BTB/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.cpp
│ ├── ca_oop/
│ │ ├── cacheutils.h
│ │ ├── exploit.sh
│ │ ├── hyper_thread_pair.sh
│ │ ├── main.c
│ │ └── smc_utils.h
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.cpp
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
├── PHT/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── ca_oop/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
├── RSB/
│ ├── ca_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── ca_oop/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ ├── sa_ip/
│ │ ├── Makefile
│ │ ├── README.md
│ │ └── main.c
│ └── sa_oop/
│ ├── Makefile
│ ├── README.md
│ └── main.c
└── STL/
├── Makefile
├── README.md
└── main.c
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function u (line 1) | function u(t){t._.x=t.z+t.parent.m,t.m+=t.parent.m}
function a (line 1) | function a(t){t.x*=n,t.y=t.depth*e}
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function l (line 1) | function l(t){return t.x0=t.y0=0,t.x1=e,t.y1=r,t.eachBefore(h),i=[0],n&&...
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FILE: docs/dist/typescript/draw-links.d.ts
type ICoordinates (line 2) | interface ICoordinates {
FILE: docs/dist/typescript/links/draw-links.d.ts
type ICoordinates (line 2) | interface ICoordinates {
FILE: docs/dist/typescript/typings.d.ts
type ITreeConfig (line 2) | interface ITreeConfig {
type ExtendedHierarchyPointNode (line 26) | interface ExtendedHierarchyPointNode extends HierarchyPointNode<{}> {
FILE: docs/dist/typescript/utils.d.ts
type Result (line 8) | type Result = ExtendedHierarchyPointNode & {
FILE: docs/js/export.js
function getTranslation (line 1) | function getTranslation(obj) {
function exportTikz (line 12) | function exportTikz() {
function exportSVG (line 56) | function exportSVG() {
function exportDOT (line 104) | function exportDOT() {
FILE: docs/js/filter.js
function buildIndex (line 2) | function buildIndex() {
function hasParent (line 12) | function hasParent(node, parent_id) {
function hasChild (line 22) | function hasChild(node, child_id) {
function toggleMeltdownSpectre (line 27) | function toggleMeltdownSpectre(meltdown, spectre, filterInclude) {
function recursiveFlatten (line 60) | function recursiveFlatten(input) {
function filter (line 79) | function filter() {
FILE: pocs/libcache/cache.c
function perf_init (line 4) | void perf_init() {
function rdtsc (line 18) | uint64_t rdtsc() {
function rdtsc_begin (line 32) | uint64_t rdtsc_begin() {
function rdtsc_end (line 48) | uint64_t rdtsc_end() {
function flush (line 64) | void flush(void *p) { asm volatile("clflush 0(%0)\n" : : "c"(p) : "rax"); }
function maccess (line 67) | void maccess(void *p) { asm volatile("movq (%0), %%rax\n" : : "c"(p) : "...
function mfence (line 70) | void mfence() { asm volatile("mfence"); }
function nospec (line 73) | void nospec() { asm volatile("lfence"); }
function xbegin (line 76) | unsigned int xbegin() {
function xend (line 83) | void xend() {
function has_tsx (line 88) | int has_tsx() {
function maccess_tsx (line 99) | void maccess_tsx(void* ptr) {
function rdtsc (line 108) | uint32_t rdtsc() {
function flush (line 121) | void flush(void *p) { asm volatile("clflush 0(%0)\n" : : "c"(p)); }
function maccess (line 124) | void maccess(void *p) { asm volatile("mov (%0), %%eax\n" : : "c"(p) : "e...
function mfence (line 127) | void mfence() { asm volatile("mfence"); }
function nospec (line 130) | void nospec() { asm volatile("lfence"); }
function has_tsx (line 133) | int has_tsx() {
function rdtsc (line 146) | uint64_t rdtsc() {
function rdtsc_begin (line 185) | uint64_t rdtsc_begin() {
function rdtsc_end (line 223) | uint64_t rdtsc_end() {
function flush (line 260) | void flush(void *p) {
function maccess (line 267) | void maccess(void *p) {
function mfence (line 275) | void mfence() { asm volatile("DSB ISH"); }
function nospec (line 278) | void nospec() { asm volatile("DSB SY\nISB"); }
function rdtsc (line 281) | uint64_t rdtsc() {
function rdtsc_begin (line 290) | uint64_t rdtsc_begin() {
function rdtsc_end (line 299) | uint64_t rdtsc_end() {
function flush (line 308) | void flush(void *p) { asm volatile( "dcbf 0, %0\n\t"
function maccess (line 314) | void maccess(void *p) { asm volatile( "ld %%r0, 0(%0)" ::"r"(p): "r0"); }
function mfence (line 317) | void mfence() { asm volatile( "lwsync" ); }
function nospec (line 320) | void nospec() { asm volatile( "hwsync" ); }
function flush_reload (line 324) | int flush_reload(void *ptr) {
function flush_reload_t (line 350) | int flush_reload_t(void *ptr) {
function reload_t (line 373) | int reload_t(void *ptr) {
function detect_flush_reload_threshold (line 395) | size_t detect_flush_reload_threshold() {
function maccess_speculative (line 414) | void maccess_speculative(void* ptr) {
function unblock_signal (line 429) | void unblock_signal(int signum __attribute__((__unused__))) {
function trycatch_segfault_handler (line 437) | void trycatch_segfault_handler(int signum) {
function try_start (line 448) | int try_start() {
function try_end (line 470) | void try_end() {
function try_abort (line 483) | void try_abort() {
function cache_encode (line 495) | void cache_encode(char data) {
function cache_decode_pretty (line 500) | void cache_decode_pretty(char *leaked, int index) {
function flush_shared_memory (line 515) | void flush_shared_memory() {
FILE: pocs/libpte/module/pteditor.c
type pgdval_t (line 35) | typedef pgdval_t p4dval_t;
function set_swapper_pgd (line 38) | void __attribute__((weak)) set_swapper_pgd(pgd_t* pgdp, pgd_t pgd) {}
function pte_t (line 41) | static inline pte_t native_make_pte(pteval_t val)
function pgd_t (line 46) | static inline pgd_t native_make_pgd(pgdval_t val)
function pmd_t (line 51) | static inline pmd_t native_make_pmd(pmdval_t val)
function pud_t (line 56) | static inline pud_t native_make_pud(pudval_t val)
function p4d_t (line 62) | static inline p4d_t native_make_p4d(p4dval_t val)
function pteval_t (line 68) | static inline pteval_t native_pte_val(pte_t pte)
function pud_large (line 73) | static inline int pud_large(pud_t pud) {
function pmd_large (line 81) | static inline int pmd_large(pmd_t pmd) {
function kallsyms_lookup_name (line 104) | unsigned long kallsyms_lookup_name(const char* name) {
type vm_t (line 120) | typedef struct {
type mm_struct (line 138) | struct mm_struct
type mm_struct (line 139) | struct mm_struct
function device_open (line 141) | static int device_open(struct inode *inode, struct file *file) {
function device_release (line 152) | static int device_release(struct inode *inode, struct file *file) {
function _invalidate_tlb (line 159) | static void
function invalidate_tlb_custom (line 206) | static void
function invalidate_tlb_kernel (line 211) | static void
function _set_pat (line 216) | static void _set_pat(void* _pat) {
function set_pat (line 229) | static void set_pat(size_t pat) {
type mm_struct (line 233) | struct mm_struct
type task_struct (line 234) | struct task_struct
type pid (line 235) | struct pid
function resolve_vm (line 253) | static int resolve_vm(size_t addr, vm_t* entry, int lock) {
function update_vm (line 353) | static int update_vm(ptedit_entry_t* new_entry, int lock) {
function vm_to_user (line 411) | static void vm_to_user(ptedit_entry_t* user, vm_t* vm) {
function device_ioctl (line 438) | static long device_ioctl(struct file *file, unsigned int ioctl_num, unsi...
type file_operations (line 590) | struct file_operations
type miscdevice (line 595) | struct miscdevice
type proc_ops (line 603) | struct proc_ops
type file_operations (line 624) | struct file_operations
function open_umem (line 629) | static int open_umem(struct inode *inode, struct file *filp) { return 0; }
function devmem_bypass (line 636) | static int devmem_bypass(struct kretprobe_instance *p, struct pt_regs *r...
type kretprobe (line 643) | struct kretprobe
function init_module (line 646) | int init_module(void) {
function cleanup_module (line 691) | void cleanup_module(void) {
FILE: pocs/libpte/module/pteditor.h
type ptedit_entry_t (line 29) | typedef struct {
type ptedit_page_t (line 65) | typedef struct {
type ptedit_page_t (line 77) | typedef struct {
type ptedit_paging_t (line 88) | typedef struct {
FILE: pocs/libpte/ptedit.c
type ptedit_paging_definition_t (line 39) | typedef struct {
function ptedit_entry_t (line 50) | ptedit_entry_t ptedit_resolve_kernel(void* address, pid_t pid) {
function ptedit_phys_read_map (line 68) | static inline size_t ptedit_phys_read_map(size_t address) {
function ptedit_phys_write_map (line 73) | static inline void ptedit_phys_write_map(size_t address, size_t value) {
function ptedit_phys_read_pread (line 78) | static inline size_t ptedit_phys_read_pread(size_t address) {
function ptedit_phys_write_pwrite (line 92) | static inline void ptedit_phys_write_pwrite(size_t address, size_t value) {
function ptedit_entry_t (line 207) | static ptedit_entry_t ptedit_resolve_user(void* address, pid_t pid) {
function ptedit_entry_t (line 213) | static ptedit_entry_t ptedit_resolve_user_map(void* address, pid_t pid) {
function ptedit_update_kernel (line 219) | void ptedit_update_kernel(void* address, pid_t pid, ptedit_entry_t* vm) {
function ptedit_update_user_ext (line 230) | void ptedit_update_user_ext(void* address, pid_t pid, ptedit_entry_t* vm...
function ptedit_update_user (line 274) | static void ptedit_update_user(void* address, pid_t pid, ptedit_entry_t*...
function ptedit_update_user_map (line 281) | static void ptedit_update_user_map(void* address, pid_t pid, ptedit_entr...
function ptedit_set_pfn (line 298) | size_t ptedit_set_pfn(size_t pte, size_t pfn) {
function ptedit_get_pfn (line 310) | size_t ptedit_get_pfn(size_t pte) {
function ptedit_print_entry_line (line 334) | void ptedit_print_entry_line(size_t entry, int line) {
function ptedit_print_entry (line 387) | void ptedit_print_entry(size_t entry) {
function ptedit_print_entry_t (line 395) | void ptedit_print_entry_t(ptedit_entry_t entry) {
function ptedit_init (line 419) | int ptedit_init() {
function ptedit_cleanup (line 477) | void ptedit_cleanup() {
function ptedit_use_implementation (line 492) | void ptedit_use_implementation(int implementation) {
function ptedit_get_pagesize (line 526) | int ptedit_get_pagesize() {
function ptedit_read_physical_page (line 538) | void ptedit_read_physical_page(size_t pfn, char* buffer) {
function ptedit_write_physical_page (line 560) | void ptedit_write_physical_page(size_t pfn, char* content) {
function ptedit_get_paging_root (line 588) | size_t ptedit_get_paging_root(pid_t pid) {
function ptedit_set_paging_root (line 606) | void ptedit_set_paging_root(pid_t pid, size_t root) {
function ptedit_invalidate_tlb (line 624) | void ptedit_invalidate_tlb(void* address) {
function ptedit_switch_tlb_invalidation (line 635) | int ptedit_switch_tlb_invalidation(int implementation) {
function ptedit_get_mts (line 645) | size_t ptedit_get_mts() {
function ptedit_get_mt (line 658) | char ptedit_get_mt(unsigned char mt) {
function ptedit_set_mts (line 717) | void ptedit_set_mts(size_t mts) {
function ptedit_set_mt (line 728) | void ptedit_set_mt(unsigned char mt, unsigned char value) {
function ptedit_find_mt (line 741) | unsigned char ptedit_find_mt(unsigned char type) {
function ptedit_find_first_mt (line 767) | int ptedit_find_first_mt(unsigned char type) {
function ptedit_apply_mt (line 783) | size_t ptedit_apply_mt(size_t entry, unsigned char mt) {
function ptedit_extract_mt (line 797) | unsigned char ptedit_extract_mt(size_t entry) {
function ptedit_full_serializing_barrier (line 806) | void ptedit_full_serializing_barrier() {
function ptedit_pte_set_bit (line 834) | void ptedit_pte_set_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_clear_bit (line 843) | void ptedit_pte_clear_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_get_bit (line 852) | unsigned char ptedit_pte_get_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_get_pfn (line 858) | size_t ptedit_pte_get_pfn(void* address, pid_t pid) {
function ptedit_pte_set_pfn (line 865) | void ptedit_pte_set_pfn(void* address, pid_t pid, size_t pfn) {
FILE: pocs/libpte/ptedit.h
type pid_t (line 10) | typedef size_t pid_t;
type ptedit_entry_t (line 212) | typedef ptedit_entry_t(*ptedit_resolve_t)(void*, pid_t);
type ptedit_pgd_t (line 298) | typedef struct {
type ptedit_pgd_t (line 319) | typedef ptedit_pgd_t ptedit_p4d_t;
type ptedit_pgd_t (line 325) | typedef ptedit_pgd_t ptedit_pud_t;
type ptedit_pgd_t (line 331) | typedef ptedit_pgd_t ptedit_pmd_t;
type ptedit_pmd_large_t (line 338) | typedef struct {
type ptedit_pte_t (line 362) | typedef struct {
type ptedit_pgd_t (line 387) | typedef struct {
type ptedit_pgd_t (line 403) | typedef ptedit_pgd_t ptedit_p4d_t;
type ptedit_pgd_t (line 409) | typedef ptedit_pgd_t ptedit_pud_t;
type ptedit_pgd_t (line 415) | typedef ptedit_pgd_t ptedit_pmd_t;
type ptedit_pgd_large_t (line 421) | typedef struct {
type ptedit_pmd_large_t (line 443) | typedef struct {
type ptedit_pte_t (line 465) | typedef struct {
FILE: pocs/libpte/ptedit_header.h
type ptedit_entry_t (line 30) | typedef struct {
type ptedit_page_t (line 66) | typedef struct {
type ptedit_page_t (line 78) | typedef struct {
type ptedit_paging_t (line 89) | typedef struct {
type pid_t (line 168) | typedef size_t pid_t;
type ptedit_entry_t (line 370) | typedef ptedit_entry_t(*ptedit_resolve_t)(void*, pid_t);
type ptedit_pgd_t (line 456) | typedef struct {
type ptedit_pgd_t (line 477) | typedef ptedit_pgd_t ptedit_p4d_t;
type ptedit_pgd_t (line 483) | typedef ptedit_pgd_t ptedit_pud_t;
type ptedit_pgd_t (line 489) | typedef ptedit_pgd_t ptedit_pmd_t;
type ptedit_pmd_large_t (line 496) | typedef struct {
type ptedit_pte_t (line 520) | typedef struct {
type ptedit_pgd_t (line 545) | typedef struct {
type ptedit_pgd_t (line 561) | typedef ptedit_pgd_t ptedit_p4d_t;
type ptedit_pgd_t (line 567) | typedef ptedit_pgd_t ptedit_pud_t;
type ptedit_pgd_t (line 573) | typedef ptedit_pgd_t ptedit_pmd_t;
type ptedit_pgd_large_t (line 579) | typedef struct {
type ptedit_pmd_large_t (line 601) | typedef struct {
type ptedit_pte_t (line 623) | typedef struct {
type ptedit_paging_definition_t (line 984) | typedef struct {
function ptedit_entry_t (line 995) | ptedit_entry_t ptedit_resolve_kernel(void* address, pid_t pid) {
function ptedit_phys_read_map (line 1013) | static inline size_t ptedit_phys_read_map(size_t address) {
function ptedit_phys_write_map (line 1018) | static inline void ptedit_phys_write_map(size_t address, size_t value) {
function ptedit_phys_read_pread (line 1023) | static inline size_t ptedit_phys_read_pread(size_t address) {
function ptedit_phys_write_pwrite (line 1037) | static inline void ptedit_phys_write_pwrite(size_t address, size_t value) {
function ptedit_entry_t (line 1152) | static ptedit_entry_t ptedit_resolve_user(void* address, pid_t pid) {
function ptedit_entry_t (line 1158) | static ptedit_entry_t ptedit_resolve_user_map(void* address, pid_t pid) {
function ptedit_update_kernel (line 1164) | void ptedit_update_kernel(void* address, pid_t pid, ptedit_entry_t* vm) {
function ptedit_update_user_ext (line 1175) | void ptedit_update_user_ext(void* address, pid_t pid, ptedit_entry_t* vm...
function ptedit_update_user (line 1219) | static void ptedit_update_user(void* address, pid_t pid, ptedit_entry_t*...
function ptedit_update_user_map (line 1226) | static void ptedit_update_user_map(void* address, pid_t pid, ptedit_entr...
function ptedit_set_pfn (line 1243) | size_t ptedit_set_pfn(size_t pte, size_t pfn) {
function ptedit_get_pfn (line 1255) | size_t ptedit_get_pfn(size_t pte) {
function ptedit_print_entry_line (line 1279) | void ptedit_print_entry_line(size_t entry, int line) {
function ptedit_print_entry (line 1332) | void ptedit_print_entry(size_t entry) {
function ptedit_print_entry_t (line 1340) | void ptedit_print_entry_t(ptedit_entry_t entry) {
function ptedit_init (line 1364) | int ptedit_init() {
function ptedit_cleanup (line 1422) | void ptedit_cleanup() {
function ptedit_use_implementation (line 1437) | void ptedit_use_implementation(int implementation) {
function ptedit_get_pagesize (line 1471) | int ptedit_get_pagesize() {
function ptedit_read_physical_page (line 1483) | void ptedit_read_physical_page(size_t pfn, char* buffer) {
function ptedit_write_physical_page (line 1505) | void ptedit_write_physical_page(size_t pfn, char* content) {
function ptedit_get_paging_root (line 1533) | size_t ptedit_get_paging_root(pid_t pid) {
function ptedit_set_paging_root (line 1551) | void ptedit_set_paging_root(pid_t pid, size_t root) {
function ptedit_invalidate_tlb (line 1569) | void ptedit_invalidate_tlb(void* address) {
function ptedit_switch_tlb_invalidation (line 1580) | int ptedit_switch_tlb_invalidation(int implementation) {
function ptedit_get_mts (line 1590) | size_t ptedit_get_mts() {
function ptedit_get_mt (line 1603) | char ptedit_get_mt(unsigned char mt) {
function ptedit_set_mts (line 1662) | void ptedit_set_mts(size_t mts) {
function ptedit_set_mt (line 1673) | void ptedit_set_mt(unsigned char mt, unsigned char value) {
function ptedit_find_mt (line 1686) | unsigned char ptedit_find_mt(unsigned char type) {
function ptedit_find_first_mt (line 1712) | int ptedit_find_first_mt(unsigned char type) {
function ptedit_apply_mt (line 1728) | size_t ptedit_apply_mt(size_t entry, unsigned char mt) {
function ptedit_extract_mt (line 1742) | unsigned char ptedit_extract_mt(size_t entry) {
function ptedit_full_serializing_barrier (line 1751) | void ptedit_full_serializing_barrier() {
function ptedit_pte_set_bit (line 1779) | void ptedit_pte_set_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_clear_bit (line 1788) | void ptedit_pte_clear_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_get_bit (line 1797) | unsigned char ptedit_pte_get_bit(void* address, pid_t pid, int bit) {
function ptedit_pte_get_pfn (line 1803) | size_t ptedit_pte_get_pfn(void* address, pid_t pid) {
function ptedit_pte_set_pfn (line 1810) | void ptedit_pte_set_pfn(void* address, pid_t pid, size_t pfn) {
FILE: pocs/meltdown/AC/main.c
function main (line 26) | int main(void) {
FILE: pocs/meltdown/BR/main.c
function fault_handler (line 33) | void fault_handler(int no) {
function main (line 56) | int main(void) {
FILE: pocs/meltdown/DE/main.c
function main (line 13) | int main(void) {
FILE: pocs/meltdown/GP/main.c
function main (line 11) | int main(int argc, char **argv) {
FILE: pocs/meltdown/GP/module/kernel_module.c
type mm_struct (line 14) | struct mm_struct
type task_struct (line 15) | struct task_struct
type pid (line 16) | struct pid
function pid_to_cr3 (line 36) | unsigned long pid_to_cr3(size_t pid) {
function my_proc_show (line 52) | static int my_proc_show(struct seq_file *m, void *v) {
function my_proc_write (line 57) | static ssize_t my_proc_write(struct file *file, const char __user *buffer,
function my_proc_open (line 67) | static int my_proc_open(struct inode *inode, struct file *file) {
type proc_ops (line 72) | struct proc_ops
type file_operations (line 78) | struct file_operations
function hello_init (line 86) | static int __init hello_init(void) {
function hello_exit (line 97) | static void __exit hello_exit(void) {
FILE: pocs/meltdown/NM/main.c
function main (line 16) | int main(void) {
FILE: pocs/meltdown/NM/victim.c
function main (line 5) | int main(void) {
FILE: pocs/meltdown/P/main.c
function main (line 20) | int main(void) {
FILE: pocs/meltdown/PK/main.c
function main (line 14) | int main(void) {
FILE: pocs/meltdown/RW/main.c
function function (line 14) | void function() {
function main (line 21) | int main(void) {
FILE: pocs/meltdown/SS/cacheutils.h
function perf_init (line 35) | void perf_init() {
function rdtsc (line 52) | uint64_t rdtsc() {
function rdtsc_begin (line 70) | uint64_t rdtsc_begin() {
function rdtsc_end (line 86) | uint64_t rdtsc_end() {
function flush (line 102) | void flush(void *p) { asm volatile("clflush 0(%0)\n" : : "c"(p) : "rax"); }
function maccess (line 105) | void maccess(void *p) { asm volatile("mov (%0), %%eax\n" : : "c"(p) : "r...
function mfence (line 108) | void mfence() { asm volatile("mfence"); }
function nospec (line 111) | void nospec() { asm volatile("lfence"); }
function xbegin (line 115) | unsigned int xbegin() {
function xend (line 122) | void xend() {
function has_tsx (line 127) | int has_tsx() {
function maccess_tsx (line 138) | void maccess_tsx(void* ptr) {
function rdtsc (line 151) | uint64_t rdtsc() {
function rdtsc_begin (line 190) | uint64_t rdtsc_begin() {
function rdtsc_end (line 228) | uint64_t rdtsc_end() {
function flush (line 265) | void flush(void *p) {
function maccess (line 272) | void maccess(void *p) {
function mfence (line 280) | void mfence() { asm volatile("DSB ISH"); }
function nospec (line 283) | void nospec() { asm volatile("DSB SY\nISB"); }
function flush_reload (line 288) | int flush_reload(void *ptr) {
function flush_reload_t (line 314) | int flush_reload_t(void *ptr) {
function reload_t (line 337) | int reload_t(void *ptr) {
function detect_flush_reload_threshold (line 359) | size_t detect_flush_reload_threshold() {
function maccess_speculative (line 379) | void maccess_speculative(void* ptr) {
function unblock_signal (line 397) | void unblock_signal(int signum __attribute__((__unused__))) {
function trycatch_segfault_handler (line 405) | void trycatch_segfault_handler(int signum) {
function try_start (line 417) | int try_start() {
function try_end (line 439) | void try_end() {
function try_abort (line 452) | void try_abort() {
FILE: pocs/meltdown/SS/main.c
type user_desc (line 21) | struct user_desc
type user_desc (line 33) | struct user_desc
function seg_ok (line 45) | void inline __attribute__((always_inline)) seg_ok(void) {
function seg_fail (line 51) | void inline __attribute__((always_inline)) seg_fail(void) {
function main (line 57) | int main(void) {
FILE: pocs/meltdown/UD/main.c
function main (line 13) | int main(void) {
FILE: pocs/meltdown/US/main.c
function main (line 20) | int main(void) {
FILE: pocs/spectre/BTB/ca_ip/main.cpp
class Animal (line 19) | class Animal {
method move (line 21) | virtual void move() {
class Bird (line 27) | class Bird : public Animal {
method Bird (line 31) | Bird() {
method move (line 34) | void move() {
class Fish (line 40) | class Fish : public Animal {
method Fish (line 44) | Fish() {
method move (line 47) | void move() {
function move_animal (line 55) | void move_animal(Animal* animal) {
function main (line 60) | int main(int argc, char **argv) {
FILE: pocs/spectre/BTB/ca_oop/cacheutils.h
function rdtsc (line 17) | inline __attribute__((always_inline)) uint64_t rdtsc() {
function maccess (line 35) | inline __attribute__((always_inline)) void maccess(volatile void* p)
function flush (line 43) | inline __attribute__((always_inline)) void flush(void* p) {
FILE: pocs/spectre/BTB/ca_oop/main.c
function calibration (line 62) | size_t calibration() {
function main (line 96) | int main(int argc, char **argv) {
FILE: pocs/spectre/BTB/ca_oop/smc_utils.h
function call_addr (line 1) | inline __attribute__((always_inline)) void call_addr(size_t addr)
function inject_code (line 12) | size_t inject_code(size_t dest, char* hex, size_t length)
function inject_jump (line 18) | size_t inject_jump(size_t dest, size_t target)
function inject_maccess (line 27) | size_t inject_maccess(size_t dest, size_t target)
function inject_nop (line 36) | size_t inject_nop(size_t dest, size_t no)
function assemble (line 46) | size_t assemble(char *in, char **out)
function inject_asm (line 80) | size_t inject_asm(size_t dest, char* asm_code)
FILE: pocs/spectre/BTB/sa_ip/main.cpp
class Animal (line 19) | class Animal {
method move (line 21) | virtual void move() {
class Bird (line 26) | class Bird : public Animal {
method Bird (line 30) | Bird() {
method move (line 33) | void move() {
class Fish (line 39) | class Fish : public Animal {
method Fish (line 43) | Fish() {
method move (line 46) | void move() {
function move_animal (line 54) | void move_animal(Animal* animal) {
function main (line 59) | int main(int argc, char **argv) {
FILE: pocs/spectre/BTB/sa_oop/main.c
function segfault_handler (line 18) | static void segfault_handler(int signum) {
function dummy (line 24) | void dummy() {
function dump_secret (line 28) | void dump_secret() {
function main (line 33) | int main(int argc, const char **argv) {
FILE: pocs/spectre/PHT/ca_ip/main.c
function access_array (line 19) | char access_array(int x) {
function main (line 37) | int main(int argc, const char **argv) {
FILE: pocs/spectre/PHT/ca_oop/main.c
function access_array (line 23) | char access_array(int x) {
function oop (line 54) | void oop() {
function main (line 62) | int main(int argc, const char **argv) {
FILE: pocs/spectre/PHT/sa_ip/main.c
function access_array (line 19) | char access_array(int x) {
function main (line 38) | int main(int argc, const char **argv) {
FILE: pocs/spectre/PHT/sa_oop/main.c
function access_array (line 22) | char access_array(int x) {
function oop (line 54) | void oop() {
function main (line 66) | int main(int argc, const char **argv) {
FILE: pocs/spectre/RSB/ca_ip/main.c
function in_place (line 16) | void __attribute__((noinline)) in_place() {
function attacker (line 26) | void __attribute__((noinline)) attacker() {
function victim (line 36) | void __attribute__((noinline)) victim() {
function main (line 58) | int main(int argc, char **argv) {
FILE: pocs/spectre/RSB/ca_oop/main.c
function wrong_return (line 16) | void __attribute__((noinline)) wrong_return() {
function pollute_rsb (line 22) | void __attribute__((noinline)) pollute_rsb() {
function main (line 32) | int main(int argc, char **argv) {
FILE: pocs/spectre/RSB/sa_ip/main.c
function in_place (line 10) | void __attribute__((noinline)) in_place() {
function main (line 44) | int main(int argc, char **argv) {
FILE: pocs/spectre/RSB/sa_oop/main.c
function call_manipulate_stack (line 17) | int __attribute__ ((noinline)) call_manipulate_stack() {
function call_leak (line 26) | int __attribute__ ((noinline)) call_leak() {
function call_start (line 35) | int __attribute__ ((noinline)) call_start() {
function confuse_compiler (line 40) | void confuse_compiler() {
function main (line 48) | int main(int argc, const char **argv) {
FILE: pocs/spectre/STL/main.c
function access_array (line 20) | char access_array(int x) {
function main (line 49) | int main(int argc, const char **argv) {
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"path": "docs/dist/typescript/link-enter.d.ts",
"chars": 381,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { ITreeCon"
},
{
"path": "docs/dist/typescript/link-exit.d.ts",
"chars": 280,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { ITreeCon"
},
{
"path": "docs/dist/typescript/link-update.d.ts",
"chars": 361,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { ITreeCon"
},
{
"path": "docs/dist/typescript/links/draw-links.d.ts",
"chars": 222,
"preview": "import { ITreeConfig } from \"../typings\";\ninterface ICoordinates {\n x: number;\n y: number;\n}\nexport declare const "
},
{
"path": "docs/dist/typescript/links/link-enter.d.ts",
"chars": 449,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { Extended"
},
{
"path": "docs/dist/typescript/links/link-exit.d.ts",
"chars": 386,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { Extended"
},
{
"path": "docs/dist/typescript/links/link-update.d.ts",
"chars": 362,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nimport { BaseType, Selection } from \"d3-selection\";\nimport { ITreeCon"
},
{
"path": "docs/dist/typescript/node-enter.d.ts",
"chars": 326,
"preview": "import { BaseType, Selection } from \"d3-selection\";\nimport { ExtendedHierarchyPointNode, ITreeConfig } from \"./typings\";"
},
{
"path": "docs/dist/typescript/node-exit.d.ts",
"chars": 67,
"preview": "export declare const placeExit: (node: any, settings: any) => any;\n"
},
{
"path": "docs/dist/typescript/nodes/node-enter.d.ts",
"chars": 403,
"preview": "import { BaseType, Selection } from \"d3-selection\";\nimport { ExtendedHierarchyPointNode, ITreeConfig } from \"../typings\""
},
{
"path": "docs/dist/typescript/nodes/node-exit.d.ts",
"chars": 339,
"preview": "import { BaseType, Selection } from \"d3-selection\";\nimport { ExtendedHierarchyPointNode, ITreeConfig } from \"../typings\""
},
{
"path": "docs/dist/typescript/nodes/node-update.d.ts",
"chars": 344,
"preview": "import { BaseType, Selection } from \"d3-selection\";\nimport { ExtendedHierarchyPointNode, ITreeConfig } from \"../typings\""
},
{
"path": "docs/dist/typescript/prepare-data.d.ts",
"chars": 304,
"preview": "import { HierarchyNode } from \"d3-hierarchy\";\nimport { ITreeConfig } from \"./typings\";\nexport declare const generateNest"
},
{
"path": "docs/dist/typescript/services.d.ts",
"chars": 106,
"preview": "export declare const getAreaSize: (htmlId: string) => {\n areaWidth: number;\n areaHeight: number;\n};\n"
},
{
"path": "docs/dist/typescript/typings.d.ts",
"chars": 906,
"preview": "import { HierarchyPointNode } from \"d3-hierarchy\";\nexport interface ITreeConfig {\n htmlId: string;\n idKey: string;"
},
{
"path": "docs/dist/typescript/utils.d.ts",
"chars": 556,
"preview": "import { ExtendedHierarchyPointNode, ITreeConfig } from \"./typings\";\nexport declare const getAreaSize: (\n htmlId: strin"
},
{
"path": "docs/index.html",
"chars": 21546,
"preview": "<!DOCTYPE html>\n<html lang=\"en\">\n <head>\n <meta charset=\"utf-8\">\n <meta http-equiv=\"X-UA-Compatible\" content=\"IE="
},
{
"path": "docs/js/export.js",
"chars": 5329,
"preview": "function getTranslation(obj) {\n if(obj.transform === undefined) return [0,0];\n if(obj.transform.baseVal === undefi"
},
{
"path": "docs/js/filter.js",
"chars": 7232,
"preview": "var index = {};\nfunction buildIndex() {\n index = {};\n for(let node of data) {\n if(index[node.id] !== undefi"
},
{
"path": "docs/js/tree.js",
"chars": 292,
"preview": "$(document).ready(function(e) {\n $('[data-toggle=\"popover\"]').popover();\n $('[data-toggle=\"tooltip\"]').tooltip();\n"
},
{
"path": "docs/tree.js",
"chars": 88215,
"preview": "var color = {\n root: \"#DDDDDD\",\n group: \"#BBBBFF\",\n works: \"#FF5722\",\n fails: \"#8BC34A\",\n todo: \"#FFA500\""
},
{
"path": "pocs/Makefile",
"chars": 3487,
"preview": "all: libcache/cacheutils.h libpte/libpte.a meltdown/US meltdown/P meltdown/RW meltdown/NM meltdown/GP meltdown/PK meltdo"
},
{
"path": "pocs/get_hyperthread_pair.sh",
"chars": 423,
"preview": "#!/bin/zsh\n\nsetopt extendedglob\n\ncd /sys/devices/system/cpu/\n\nfor i in cpu[0-9]##; do\n package=`cat $i/topology/physica"
},
{
"path": "pocs/libcache/Makefile",
"chars": 128,
"preview": "all: header\n\nheader: cache.c cache.h\n\tcat cache.h cache.c | sed 's/#include \".*\"//g' > cacheutils.h\n\nclean:\n\trm -f cache"
},
{
"path": "pocs/libcache/cache.c",
"chars": 13077,
"preview": "#include \"cache.h\"\n\n// ---------------------------------------------------------------------------\nvoid perf_init() {\n "
},
{
"path": "pocs/libcache/cache.h",
"chars": 5838,
"preview": "#ifndef _CACHEUTILS_H_\n#define _CACHEUTILS_H_\n\n#include <assert.h>\n#include <unistd.h>\n#include <sys/syscall.h>\n#include"
},
{
"path": "pocs/libpte/.gitignore",
"chars": 256,
"preview": "# ---> C\n# Object files\n*.o\n*.ko\n*.obj\n*.elf\n\n# Precompiled Headers\n*.gch\n*.pch\n\n# Libraries\n*.lib\n*.a\n*.la\n*.lo\n\n# Shar"
},
{
"path": "pocs/libpte/Makefile",
"chars": 470,
"preview": "all: pteditor ptedit.o header libpte.a\n\nheader: module/pteditor.c module/pteditor.h ptedit.c ptedit.h\n\tcat module/ptedit"
},
{
"path": "pocs/libpte/module/Makefile",
"chars": 189,
"preview": "obj-m += pteditor.o\nccflags-y += -Wno-unused-result\nall:\n\tmake -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules\n"
},
{
"path": "pocs/libpte/module/pteditor.c",
"chars": 17860,
"preview": "#include <linux/mm_types.h>\n#include <asm/tlbflush.h>\n#include <asm/uaccess.h>\n#include <asm/io.h>\n#include <linux/fs.h>"
},
{
"path": "pocs/libpte/module/pteditor.h",
"chars": 4464,
"preview": "/* See LICENSE file for license and copyright information */\n\n#ifndef PTEDITOR_MODULE_H\n#define PTEDITOR_MODULE_H\n\n#if d"
},
{
"path": "pocs/libpte/ptedit.c",
"chars": 31998,
"preview": "#include <stdio.h>\n#include <stdlib.h>\n#include <fcntl.h>\n#include <string.h>\n#include \"module/pteditor.h\"\n#include \"pte"
},
{
"path": "pocs/libpte/ptedit.h",
"chars": 19080,
"preview": "/** @file */\n\n#ifndef _PTEDITOR_H_\n#define _PTEDITOR_H_\n\n#include \"module/pteditor.h\"\n#include <sys/types.h>\n\n#if define"
},
{
"path": "pocs/libpte/ptedit_header.h",
"chars": 55525,
"preview": "// Warning: this file was generated by make. DO NOT EDIT!\n/* See LICENSE file for license and copyright information */\n\n"
},
{
"path": "pocs/meltdown/AC/Makefile",
"chars": 226,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../\n\nmain_arm: main.c\n\taarch64-l"
},
{
"path": "pocs/meltdown/AC/README.md",
"chars": 1869,
"preview": "# Meltdown-AC PoC\n\nThis folder contains a Meltdown-AC proof-of-concept implementation for x86_64.\n\n## Compile\n\nCompile u"
},
{
"path": "pocs/meltdown/AC/main.c",
"chars": 2310,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/BR/Makefile",
"chars": 428,
"preview": "ifndef MPX\n MPX = 1\nendif\n\nifndef TSX\n TSX = 0\nendif\n\nifndef LFENCE\n LFENCE = "
},
{
"path": "pocs/meltdown/BR/README.md",
"chars": 1335,
"preview": "# Meltdown-BR PoC\n\nThis folder contains a Meltdown-BND and Meltdown-MPX proof-of-concept implementation for x86_64.\n\n## "
},
{
"path": "pocs/meltdown/BR/main.c",
"chars": 3274,
"preview": "#define _GNU_SOURCE\n#include \"libcache/cacheutils.h\"\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include"
},
{
"path": "pocs/meltdown/DE/Makefile",
"chars": 226,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../\n\nmain_arm: main.c\n\taarch64-l"
},
{
"path": "pocs/meltdown/DE/README.md",
"chars": 2373,
"preview": "# Meltdown-DE PoC\n\nThis folder contains a Meltdown-DE proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
},
{
"path": "pocs/meltdown/DE/main.c",
"chars": 1311,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/GP/Makefile",
"chars": 218,
"preview": "all: x86\n\nx86: main_x86\n\nmodule/kernel_module.ko: module/kernel_module.c\n\tcd module && make\n\nmain_x86: main.c module/ker"
},
{
"path": "pocs/meltdown/GP/README.md",
"chars": 1190,
"preview": "# Meltdown-GP PoC\n\nThis folder contains a Meltdown-GP proof-of-concept implementation for x86_64.\nFor ARM, we used the P"
},
{
"path": "pocs/meltdown/GP/main.c",
"chars": 1680,
"preview": "#define _GNU_SOURCE\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#"
},
{
"path": "pocs/meltdown/GP/module/Makefile",
"chars": 166,
"preview": "obj-m += kernel_module.o \n\nall:\n\tmake -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules\n\nclean:\n\tmake -C /lib/mod"
},
{
"path": "pocs/meltdown/GP/module/kernel_module.c",
"chars": 2652,
"preview": "#include <linux/fs.h>\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/proc_fs.h>\n#include <linux/sched"
},
{
"path": "pocs/meltdown/NM/Makefile",
"chars": 393,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c victim.c secret.h\n\tgcc main.c -o poc_x86 -Os -I../../\n\tgcc victi"
},
{
"path": "pocs/meltdown/NM/README.md",
"chars": 1802,
"preview": "# Meltdown-NM PoC\n\nThis folder contains a Meltdown-NM proof-of-concept implementation for x86_64.\n\n## Compile\n\nCompile u"
},
{
"path": "pocs/meltdown/NM/main.c",
"chars": 1903,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/NM/secret.h",
"chars": 62,
"preview": "#ifndef SECRET_H\n#define SECRET_H\n\n#define SECRET 'S'\n\n#endif\n"
},
{
"path": "pocs/meltdown/NM/victim.c",
"chars": 271,
"preview": "#define _GNU_SOURCE\n#include <stdio.h>\n#include \"secret.h\"\n\nint main(void) {\n size_t secret = SECRET;\n // Constantly l"
},
{
"path": "pocs/meltdown/P/Makefile",
"chars": 278,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../ -L../../libpte -lpte -lrt\n\nm"
},
{
"path": "pocs/meltdown/P/README.md",
"chars": 2423,
"preview": "# Meltdown-P PoC\n\nThis folder contains a Meltdown-P proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n\nC"
},
{
"path": "pocs/meltdown/P/main.c",
"chars": 2709,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/PK/Makefile",
"chars": 99,
"preview": "all: x86\n\nx86: main_x86\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../\n\nclean:\n\trm -f poc_*\n"
},
{
"path": "pocs/meltdown/PK/README.md",
"chars": 2006,
"preview": "# Meltdown-PK PoC\n\nThis folder contains a Meltdown-PK proof-of-concept implementation for x86_64.\n\n## Compile\n\nCompile u"
},
{
"path": "pocs/meltdown/PK/main.c",
"chars": 2888,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/RW/Makefile",
"chars": 226,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../\n\nmain_arm: main.c\n\taarch64-l"
},
{
"path": "pocs/meltdown/RW/README.md",
"chars": 2103,
"preview": "# Meltdown-RW PoC\n\nThis folder contains a Meltdown-RW proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
},
{
"path": "pocs/meltdown/RW/main.c",
"chars": 1826,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/SS/Makefile",
"chars": 68,
"preview": "all:\n\tgcc -m32 -DM32=1 -o poc_x86 main.c \n\nclean:\n\trm -rf poc_x86\n\t\n"
},
{
"path": "pocs/meltdown/SS/README.md",
"chars": 1648,
"preview": "# Meltdown-SS PoC\n\nThis folder contains a Meltdown-SS proof-of-concept implementation for x86_64.\n\n## Compile\n\nCompile u"
},
{
"path": "pocs/meltdown/SS/cacheutils.h",
"chars": 11146,
"preview": "#ifndef _CACHEUTILS_H_\n#define _CACHEUTILS_H_\n\n#include <assert.h>\n#include <unistd.h>\n#include <sys/syscall.h>\n#include"
},
{
"path": "pocs/meltdown/SS/main.c",
"chars": 2599,
"preview": "#define _GNU_SOURCE\n#include \"cacheutils.h\"\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mma"
},
{
"path": "pocs/meltdown/UD/Makefile",
"chars": 226,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../\n\nmain_arm: main.c\n\taarch64-l"
},
{
"path": "pocs/meltdown/UD/README.md",
"chars": 2235,
"preview": "# Meltdown-UD PoC\n\nThis folder contains a Meltdown-UD proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
},
{
"path": "pocs/meltdown/UD/main.c",
"chars": 1618,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/meltdown/US/Makefile",
"chars": 279,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -O3 -I../../ -L../../libpte -lpte -lrt\n\nm"
},
{
"path": "pocs/meltdown/US/README.md",
"chars": 2551,
"preview": "# Meltdown-US PoC\n\nThis folder contains a Meltdown-US proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
},
{
"path": "pocs/meltdown/US/main.c",
"chars": 2785,
"preview": "#define _GNU_SOURCE\n#include <memory.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/mman.h>\n#include <sys/sysca"
},
{
"path": "pocs/spectre/BTB/ca_ip/Makefile",
"chars": 241,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.cpp\n\tg++ main.cpp -o poc_x86 -Os -I../../../ \n\nmain_arm: main.cpp\n"
},
{
"path": "pocs/spectre/BTB/ca_ip/README.md",
"chars": 1940,
"preview": "# Spectre-BTB PoC \n\nThis folder contains a Spectre-BTB proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
{
"path": "pocs/spectre/BTB/ca_ip/main.cpp",
"chars": 2539,
"preview": "#ifndef _GNU_SOURCE\n#define _GNU_SOURCE\n#endif\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <sche"
},
{
"path": "pocs/spectre/BTB/ca_oop/cacheutils.h",
"chars": 993,
"preview": "#ifndef CACHEUTILS_H\n#define CACHEUTILS_H\n\n#ifndef HIDEMINMAX\n#define MAX(X,Y) (((X) > (Y)) ? (X) : (Y))\n#define MIN(X,Y"
},
{
"path": "pocs/spectre/BTB/ca_oop/exploit.sh",
"chars": 125,
"preview": "#!/bin/zsh\nfile_name=\"main\"\ngcc -g $file_name.c -o $file_name -Wno-format-security\n./$file_name $(./hyper_thread_pair.sh"
},
{
"path": "pocs/spectre/BTB/ca_oop/hyper_thread_pair.sh",
"chars": 423,
"preview": "#!/bin/zsh\n\nsetopt extendedglob\n\ncd /sys/devices/system/cpu/\n\nfor i in cpu[0-9]##; do\n package=`cat $i/topology/physica"
},
{
"path": "pocs/spectre/BTB/ca_oop/main.c",
"chars": 5877,
"preview": "#define _GNU_SOURCE\n\n#include <sys/mman.h>\n#include <stdint.h>\n#include <string.h>\n#include <stdio.h>\n#include <errno.h>"
},
{
"path": "pocs/spectre/BTB/ca_oop/smc_utils.h",
"chars": 2673,
"preview": "inline __attribute__((always_inline)) void call_addr(size_t addr)\n{\n asm volatile(\n \"movq %0, %%rax\\n\\t\"\n \"call *"
},
{
"path": "pocs/spectre/BTB/sa_ip/Makefile",
"chars": 241,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.cpp\n\tg++ main.cpp -o poc_x86 -Os -I../../../ \n\nmain_arm: main.cpp\n"
},
{
"path": "pocs/spectre/BTB/sa_ip/README.md",
"chars": 1929,
"preview": "# Spectre-BTB PoC \n\nThis folder contains a Spectre-BTB proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
{
"path": "pocs/spectre/BTB/sa_ip/main.cpp",
"chars": 2262,
"preview": "#ifndef _GNU_SOURCE\n#define _GNU_SOURCE\n#endif\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <sche"
},
{
"path": "pocs/spectre/BTB/sa_oop/Makefile",
"chars": 233,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -Os -I../../../ \n\nmain_arm: main.c\n\taarch"
},
{
"path": "pocs/spectre/BTB/sa_oop/README.md",
"chars": 1877,
"preview": "# Spectre-BTB PoC \n\nThis folder contains a Spectre-BTB proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
{
"path": "pocs/spectre/BTB/sa_oop/main.c",
"chars": 2382,
"preview": "#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <signal.h>\n#include <setjmp.h>\n#include <sched.h>\n\n#"
},
{
"path": "pocs/spectre/PHT/ca_ip/Makefile",
"chars": 233,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -Os -I../../../ \n\nmain_arm: main.c\n\taarch"
},
{
"path": "pocs/spectre/PHT/ca_ip/README.md",
"chars": 2392,
"preview": "# Spectre-PHT PoC \n\nThis folder contains a Spectre-PHT proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
{
"path": "pocs/spectre/PHT/ca_ip/main.c",
"chars": 2229,
"preview": "#include <pthread.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n"
},
{
"path": "pocs/spectre/PHT/ca_oop/Makefile",
"chars": 233,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -Os -I../../../ \n\nmain_arm: main.c\n\taarch"
},
{
"path": "pocs/spectre/PHT/ca_oop/README.md",
"chars": 2771,
"preview": "# Spectre-PHT PoC \n\nThis folder contains a Spectre-PHT proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
{
"path": "pocs/spectre/PHT/ca_oop/main.c",
"chars": 3058,
"preview": "#include <pthread.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n"
},
{
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"path": "pocs/spectre/PHT/sa_oop/main.c",
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"preview": "# Spectre-RSB PoC\n\nThis folder contains a Spectre RSB proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
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"path": "pocs/spectre/RSB/ca_ip/main.c",
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"preview": "# Spectre-RSB PoC\n\nThis folder contains a Spectre-RSB proof-of-concept implementation for x86_64 and ARMv8.\n\n## Compile\n"
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"path": "pocs/spectre/RSB/ca_oop/main.c",
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"path": "pocs/spectre/RSB/sa_ip/Makefile",
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"path": "pocs/spectre/RSB/sa_ip/main.c",
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"path": "pocs/spectre/STL/Makefile",
"chars": 229,
"preview": "all: x86\n\nx86: main_x86\narm: main_arm\n\nmain_x86: main.c\n\tgcc main.c -o poc_x86 -Os -I../../\n\nmain_arm: main.c\n\taarch64-l"
},
{
"path": "pocs/spectre/STL/README.md",
"chars": 1727,
"preview": "# Spectre-STL PoC \n\nThis folder contains a Spectre-STL proof-of-concept implementation for x86_64 and ARMv8. \n\n## Compil"
},
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"path": "pocs/spectre/STL/main.c",
"chars": 2483,
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]
About this extraction
This page contains the full source code of the IAIK/transientfail GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 123 files (486.1 KB), approximately 143.0k tokens, and a symbol index with 513 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.