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Repository: Nic30/hwt
Branch: master
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Directory structure:
gitextract_3m5zlo_2/
├── .circleci/
│ └── config.yml
├── .coveragerc
├── .gitignore
├── .readthedocs.yml
├── LICENSE
├── MANIFEST.in
├── README.md
├── doc/
│ ├── conf.py
│ ├── gtkwave.rst
│ ├── hwtCircuitNormalForm.rst
│ ├── index.rst
│ ├── requirements.doc.txt
│ └── requirements.txt
├── hwt/
│ ├── __init__.py
│ ├── code.py
│ ├── code_utils.py
│ ├── constants.py
│ ├── constraints.py
│ ├── doc_markers.py
│ ├── hObjList.py
│ ├── hdl/
│ │ ├── __init__.py
│ │ ├── commonConstants.py
│ │ ├── const.py
│ │ ├── constUtils.py
│ │ ├── frameTmpl.py
│ │ ├── frameTmplUtils.py
│ │ ├── hdlObject.py
│ │ ├── operator.py
│ │ ├── operatorDefs.py
│ │ ├── operatorUtils.py
│ │ ├── portItem.py
│ │ ├── sensitivityCtx.py
│ │ ├── statements/
│ │ │ ├── __init__.py
│ │ │ ├── assignmentContainer.py
│ │ │ ├── codeBlockContainer.py
│ │ │ ├── ifContainter.py
│ │ │ ├── statement.py
│ │ │ ├── switchContainer.py
│ │ │ └── utils/
│ │ │ ├── __init__.py
│ │ │ ├── comparison.py
│ │ │ ├── ioDiscovery.py
│ │ │ ├── listOfHdlStatements.py
│ │ │ ├── reduction.py
│ │ │ └── signalCut.py
│ │ ├── transPart.py
│ │ ├── transTmpl.py
│ │ ├── types/
│ │ │ ├── __init__.py
│ │ │ ├── array.py
│ │ │ ├── arrayCast.py
│ │ │ ├── arrayConst.py
│ │ │ ├── bitConstFunctions.py
│ │ │ ├── bitConstFunctionsGetitem.py
│ │ │ ├── bitConst_opReduce.py
│ │ │ ├── bits.py
│ │ │ ├── bitsCast.py
│ │ │ ├── bitsCastUtils.py
│ │ │ ├── bitsConst.py
│ │ │ ├── bitsRtlSignal.py
│ │ │ ├── defs.py
│ │ │ ├── enum.py
│ │ │ ├── enumConst.py
│ │ │ ├── float.py
│ │ │ ├── floatConst.py
│ │ │ ├── function.py
│ │ │ ├── hdlType.py
│ │ │ ├── slice.py
│ │ │ ├── sliceConst.py
│ │ │ ├── sliceUtils.py
│ │ │ ├── stream.py
│ │ │ ├── streamConst.py
│ │ │ ├── string.py
│ │ │ ├── stringConst.py
│ │ │ ├── struct.py
│ │ │ ├── structCast.py
│ │ │ ├── structUtils.py
│ │ │ ├── structValBase.py
│ │ │ ├── typeCast.py
│ │ │ ├── union.py
│ │ │ └── utils.py
│ │ └── variables.py
│ ├── hwIO.py
│ ├── hwIOs/
│ │ ├── __init__.py
│ │ ├── agents/
│ │ │ ├── __init__.py
│ │ │ ├── bramPort.py
│ │ │ ├── fifo.py
│ │ │ ├── rdSync.py
│ │ │ ├── rdVldSync.py
│ │ │ ├── regCntrl.py
│ │ │ ├── signal.py
│ │ │ ├── struct.py
│ │ │ ├── tuleWithCallback.py
│ │ │ ├── union.py
│ │ │ ├── universalComposite.py
│ │ │ └── vldSync.py
│ │ ├── hwIOArray.py
│ │ ├── hwIODifferential.py
│ │ ├── hwIOStruct.py
│ │ ├── hwIOTristate.py
│ │ ├── hwIOUnion.py
│ │ ├── hwIO_map.py
│ │ ├── signalOps.py
│ │ ├── std.py
│ │ ├── std_ip_defs.py
│ │ └── utils.py
│ ├── hwModule.py
│ ├── hwParam.py
│ ├── mainBases.py
│ ├── math.py
│ ├── mathAutoExt.py
│ ├── pyUtils/
│ │ ├── __init__.py
│ │ ├── arrayQuery.py
│ │ ├── fileHelpers.py
│ │ ├── setList.py
│ │ ├── testUtils.py
│ │ └── typingFuture.py
│ ├── serializer/
│ │ ├── __init__.py
│ │ ├── combLoopAnalyzer/
│ │ │ ├── __init__.py
│ │ │ └── tarjan.py
│ │ ├── exceptions.py
│ │ ├── generic/
│ │ │ ├── __init__.py
│ │ │ ├── constant_cache.py
│ │ │ ├── indent.py
│ │ │ ├── ops.py
│ │ │ ├── tmpVarConstructor.py
│ │ │ ├── to_hdl_ast.py
│ │ │ ├── utils.py
│ │ │ └── value.py
│ │ ├── hwt/
│ │ │ ├── __init__.py
│ │ │ ├── context.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ ├── ip_packager.py
│ │ ├── mode.py
│ │ ├── resourceAnalyzer/
│ │ │ ├── __init__.py
│ │ │ ├── analyzer.py
│ │ │ ├── resourceTypes.py
│ │ │ └── utils.py
│ │ ├── serializer_config.py
│ │ ├── serializer_filter.py
│ │ ├── simModel/
│ │ │ ├── __init__.py
│ │ │ ├── serializer.py
│ │ │ ├── tmpVarConstructorConstOnly.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ ├── store_manager.py
│ │ ├── systemC/
│ │ │ ├── __init__.py
│ │ │ ├── expr.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── type.py
│ │ │ └── utils.py
│ │ ├── utils.py
│ │ ├── verilog/
│ │ │ ├── __init__.py
│ │ │ ├── context.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── types.py
│ │ │ ├── utils.py
│ │ │ └── value.py
│ │ ├── vhdl/
│ │ │ ├── __init__.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ └── xdc/
│ │ ├── __init__.py
│ │ └── serializer.py
│ ├── simulator/
│ │ ├── __init__.py
│ │ ├── agentBase.py
│ │ ├── agentConnector.py
│ │ ├── rtlSimulator.py
│ │ ├── rtlSimulatorJson.py
│ │ ├── rtlSimulatorVcd.py
│ │ ├── simTestCase.py
│ │ └── utils.py
│ ├── synth.py
│ └── synthesizer/
│ ├── __init__.py
│ ├── componentPath.py
│ ├── dummyPlatform.py
│ ├── exceptions.py
│ ├── interfaceLevel/
│ │ ├── __init__.py
│ │ ├── directionFns.py
│ │ ├── getDefaultClkRts.py
│ │ ├── hwModuleImplHelpers.py
│ │ ├── implDependent.py
│ │ ├── propDeclrCollector.py
│ │ └── utils.py
│ ├── rtlLevel/
│ │ ├── __init__.py
│ │ ├── exceptions.py
│ │ ├── extract_part_drivers.py
│ │ ├── fill_stm_list_with_enclosure.py
│ │ ├── mark_visibility_of_signals_and_check_drivers.py
│ │ ├── netlist.py
│ │ ├── reduce_processes.py
│ │ ├── remove_unconnected_signals.py
│ │ ├── rtlNetlistPass.py
│ │ ├── rtlSignal.py
│ │ ├── rtlSignalWalkers.py
│ │ └── statements_to_HdlStmCodeBlockContainers.py
│ ├── typePath.py
│ └── vectorUtils.py
├── pyproject.toml
├── setup.cfg
└── tests/
├── __init__.py
└── all.py
================================================
FILE CONTENTS
================================================
================================================
FILE: .circleci/config.yml
================================================
version: 2.1
orbs:
python: circleci/python@3.1.0
py: nic30/python-all-in-1@0.3.1
jobs:
install-test-deploy:
executor:
name: python/default
tag: '3.13.7'
resource_class: small
steps:
- checkout
# - python/load-cache
- py/install-package-git:
cwd: ..
url: https://github.com/Nic30/hwtLib
- py/install-setup-py
# - python/save-cache
- py/test-and-coverage
- py/deploy-pypi-on-tag
workflows:
main:
jobs:
- install-test-deploy:
context:
- pypi
filters:
tags:
only: /.*/
================================================
FILE: .coveragerc
================================================
[run]
branch = True
source =
hwt
[report]
exclude_lines =
pragma: no cover
def __repr__
raise AssertionError
raise NotImplementedError
if __name__ == .__main__.:
================================================
FILE: .gitignore
================================================
*.pyc
*.dill
*.class
# python egg folders
build/
dist/
hwt.egg-info/
# eclipse project files
.project
.pydevproject
.settings/
#log files
*.jou
*.log
================================================
FILE: .readthedocs.yml
================================================
version: 2
build:
os: ubuntu-lts-latest
tools:
python: "3.12"
apt_packages:
- graphviz
python:
install:
- requirements: doc/requirements.doc.txt
sphinx:
configuration: doc/conf.py
================================================
FILE: LICENSE
================================================
The MIT License (MIT)
Copyright (c) 2015 Nic30
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
================================================
FILE: MANIFEST.in
================================================
include README.md
include MANIFEST.in
================================================
FILE: README.md
================================================
# HWToolkit (hwt),
# the library for hardware development in Python
[](https://circleci.com/gh/Nic30/hwt)
[](https://coveralls.io/github/Nic30/hwt?branch=master)
[](https://badge.fury.io/py/hwt)
[](https://hwtoolkit.readthedocs.io/en/latest/?badge=latest)
[](https://github.com/Nic30/hwt)
[](https://img.shields.io/pypi/pyversions/hwt.svg)
[](https://gitter.im/hwt-community/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
## Keywords
* Metaprogramming (Hardware Construction Language HCL, templatization) + HLS.
* Simulator API, UVM
* Buildtool, IP core generator
## How HWT can help you?
* The lower layer (IR, HDL serializers) is a shield against a problems related to VHDL/Verilog. It is checking for correctness and synthetisability and removing specific of HDLs.
* The system level and HLS layer allows you to quickly build desing generators with advance optimisation techniques of your choice.
* Simulator API and it's UVM simulation environment is just python object with C++ binding. This makes it easy to use while not sacrificing performance.
* Rich type system can describe also data locality and packet features. This significantly simplifies configuration of component which are working with packets or any data over remote bus.
* HWT is not compiler nor transpiler but it is actually a core library. It contains only necessary stuff and you can can modify/extend any part any time.
Because the word of HW developement is always full of unexpected situations.
## Features
* Hardware Construction Language (HCL) (example [simple](https://github.com/Nic30/hwtLib/blob/master/hwtLib/examples/simple.py), [showcase](https://github.com/Nic30/hwtLib/blob/master/hwtLib/examples/showcase0.py)). It is somewhere between HLS and HDL. It offers HLS style of coding but at the same time it allows you to manipulate HDL objects. This means it is a little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.
* Digital circuit simulator with UVM like verification environment (example usage [CAM](https://github.com/Nic30/hwtLib/blob/master/hwtLib/mem/cam_test.py), [structWriter_test.py](https://github.com/Nic30/hwtLib/blob/master/hwtLib/structManipulators/structWriter_test.py))
* Tools for static analysis ([resourceAnalyzer](https://github.com/Nic30/hwt/blob/master/hwt/serializer/resourceAnalyzer/analyzer.py), example usage [cntr_test.py](https://github.com/Nic30/hwtLib/blob/master/hwtLib/examples/arithmetic/cntr_test.py))
* Serializers to export HWT designs into multiple target HDLs ([verilog, VHDL, system-c, IP-core packager, hwt itself...](https://github.com/Nic30/hwt/tree/master/hwt/serializer))
HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library.
Also [serialization modes](https://github.com/Nic30/hwt/blob/master/hwt/serializer/mode.py) allows to tweaks how component should behave during serialization.
HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.
HWT designs are objects. No specific compiler execution is required, just run `python3`, import the thing and use `to_rtl` metod or other (take a look at [examples](https://github.com/Nic30/hwtLib/blob/master/hwtLib/)).
## HWT ecosystem
## Installation
This library is a regular python package. You can install it using:
```
# system-wide, use -u for local use only
sudo pip3 install hwt
# or directly from git
pip3 install --upgrade --force-reinstall --no-cache-dir -r https://raw.githubusercontent.com/Nic30/hwt/master/doc/requirements.txt git+https://github.com/Nic30/hwt.git@master#egg=hwt
```
Then you are able to use functions and classes defined in the hwt library from a python console or script.
Installation of [hwtLib](https://github.com/Nic30/hwtLib) is recomended as it contains common interfaces, agents, components etc...
## FAQ
* Where is the entry point of the compiler?
* This is not a compiler, it is library of the objects which can be converted to Verilog/VHDL and back.
* How do I get Verilog/VHDL?
* Use `to_rtl` method [example](https://github.com/Nic30/hwtLib/blob/master/hwtLib/examples/simple.py)
* How do I define my interface type, protocol and simulation agent?
* Derive from any Interface class. [example](https://github.com/Nic30/hwt/blob/master/hwt/interfaces/std.py#L107)
* I do have c structure of UDP header, how do I send/receive UDP packet over AXI-stream interface?
* Define HStruct type composed of eth_header_t, IPv4_header_t and HStream(uint8_t) and use [AxisFrameGen](https://github.com/Nic30/hwtLib/blob/master/hwtLib/amba/axis_comp/frameGen.py). There is and example of [ping responder](https://github.com/Nic30/hwtLib/blob/master/hwtLib/examples/builders/pingResponder.py)
## Similar projects
* [autofpga](https://github.com/ZipCPU/autofpga) - C++, A utility for Composing FPGA designs from Peripherals
* :skull: [baremetal](https://github.com/dawsonjon/baremetal) - Python, simple HCL
* [BinPy](https://github.com/BinPy/BinPy) - Python, An electronic simulation library
* :skull: [pervognsen/Bitwise](https://github.com/pervognsen/bitwise) - Python, HDL which translates python directly
* :skull: [jamesjiang52/Bitwise](https://github.com/jamesjiang52/Bitwise) - Python, simple HCL.
* [blarney](https://github.com/blarney-lang/blarney) - Haskell, HCL
* [bsc](https://github.com/B-Lang-org/bsc) - Haskell, C++, BSV - Bluespec Compiler
* [Cement HDL/CmtHDL](https://github.com/pku-liang/Cement) - Rust, eHDL
* [chisel](https://chisel.eecs.berkeley.edu/) - 2012-?, Scala, HCL
* [Chips-2.0](https://github.com/dawsonjon/Chips-2.0) - , , FPGA Design Suite based on C to Verilog design flow
* [circt](https://github.com/llvm/circt) - 2020-?, C++/LLVM, compiler infrastructure
* [circuitgraph](https://github.com/circuitgraph/circuitgraph) - Tools for working with circuits as graphs in python
* [concat](https://github.com/conal/concat) - 2016-?, Haskell, Haskell to hardware
* [DUH](https://github.com/sifive/duh) - JS, simple convertor between verilog/scala/ipxact
* [DFiant](https://github.com/DFiantHDL/DFiant) 2019-?, Scala, dataflow based HDL
* [edalize](https://github.com/olofk/edalize) - 2018-?, Python, abstraction layer for eda tools
* [garnet](https://github.com/StanfordAHA/garnet) -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
* [hammer](https://github.com/ucb-bar/hammer) - 2017-?, Python, Highly Agile Masks Made Effortlessly from RTL
* [heterocl](https://github.com/cornell-zhang/heterocl) - 2017-?, C++, A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
* [hoodlum](https://github.com/tcr/hoodlum) - 2016-?, Rust, HCL
* [ILAng](https://github.com/Bo-Yuan-Huang/ILAng) - modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.
* :skull: [jhdl](https://github.com/larsjoost/jhdl) - ?-2017, C++ Verilog/VHDL -> systemC, prototype
* [Kactus2](http://funbase.cs.tut.fi) - IP-core packager
* [kratos](https://github.com/Kuree/kratos) - C++/Python, hardware generator/simulator
* [lgraph](https://github.com/masc-ucsc/lgraph) - C, generic graph library
* [llhd](https://github.com/fabianschuiki/llhd) - Rust, HCL
* [livehd](https://github.com/masc-ucsc/livehd) - mainly C++, An infrastructure designed for Live Hardware Development.
* [Lucid HDL in Alchitry-Labs](https://github.com/alchitry/Alchitry-Labs) - Custom language and IDE inspired by Verilog
* [magma](https://github.com/phanrahan/magma/) - 2017-?, Python, HCL
* [amaranth](https://github.com/amaranth-lang/amaranth)/[migen](https://github.com/m-labs/migen) - 2013-?, Python, HCL
* [mockturtle](https://github.com/lsils/mockturtle) - logic network library
* [moore](https://github.com/fabianschuiki/moore) - Rust, HDL -> model compiler
* [msdsl](https://github.com/sgherbst/msdsl) - Python, real number model -> verilog
* [MyHDL](https://github.com/myhdl/myhdl) - 2004-?, Python, Process based HDL
* [Amaranth HDL](https://github.com/amaranth-lang/amaranth) -, Python, (previously nMigen) A refreshed Python toolbox for building complex digital hardware
* [OpenTimer](https://github.com/OpenTimer/OpenTimer) - , C++, A High-Performance Timing Analysis Tool for VLSI Systems
* [percy](https://github.com/whaaswijk/percy) - Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.
* [PyChip-py-hcl](https://github.com/scutdig/PyChip-py-hcl) - , Python, Chisel3 like HCL
* [pygears](https://github.com/bogdanvuk/pygears) - , Python, function style HDL generator
* [PyMTL3](https://github.com/cornell-brg/pymtl3) 2018-?
* [PyMTL](https://github.com/cornell-brg/pymtl) - 2014-?, Python, Process based HDL
* [PipelineC](https://github.com/JulianKemmerer/PipelineC) - 2018-?, Python, C++ HLS-like automatic pipelining as a language construct/compiler
* [PyRTL](https://github.com/UCSBarchlab/PyRTL) - 2015-?, Python, HCL
* [Pyverilog](https://github.com/PyHDI/Pyverilog) - 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDL
* [rogue](https://github.com/slaclab/rogue) , C++/Python - Hardware Abstraction & Data Acquisition System
* [rohd](https://github.com/intel/rohd), 2023-?, dart, HCL
* [sail](https://github.com/rems-project/sail) 2018-?, (OCaml, Standard ML, Isabelle) - architecture definition language
* :skull: [SFGen](https://github.com/dillonhuff/SFGen) - Python, arithmetic function generator
* [spatial](https://github.com/stanford-ppl/spatial) - Scala, an Argon DSL like, high level abstraction
* [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) - 2015-?, Scala, HCL
* [Silice](https://github.com/sylefeb/Silice) - ?, C++, Custom HDL
* :skull: [SyDpy](https://github.com/bogdanvuk/sydpy) - ?-2016, Python, HCL and verif. framework operating on TML/RTL level
* [systemrdl-compiler](https://github.com/SystemRDL/systemrdl-compiler) - Python,c++, register description language compiler
* [UHDM](https://github.com/alainmarcel/UHDM) - C++ SystemVerilog -> C++ model
* :skull: [Verilog.jl](https://github.com/interplanetary-robot/Verilog.jl) - 2017-2017, Julia, simple Julia to Verilog transpiler
* [veriloggen](https://github.com/PyHDI/veriloggen) - 2015-?, Python, Verilog centric HCL with HLS like features
* :skull: [wyre](https://github.com/nickmqb/wyre) - 2020-2020, Mupad, Minimalistic HDL
* [phi](https://github.com/donn/Phi) - 2019-?, custom language, llvm based compiler of custom hdl
* [prga](https://github.com/PrincetonUniversity/prga) - 2019-?. Python, prototyping platform with integrated yosys
* [Hardcaml](https://github.com/janestreet/hardcaml) - OCaml, HCL
* [magia-hdl](https://github.com/magia-hdl/magia) - 2023-?, Python, HCL
* [Metron](https://github.com/aappleby/Metron) - C++, C++ -> SystemVerilog syntax translator
* [librelane](https://github.com/librelane/librelane) - python, ASIC implementation flow infrastructure
### Dictionary
* IR - Internal Representation
* HDL - Hardware Design Languge (Lang. construct maps directly to specific HW part)
* eHDL - Embedded HDL (HDL construct avare source code generator)
* HCL - Hardware Construction Language (User code constructs IR. IR can be directly transipled to HDL)
* HLS - High Level Synthesis (User code is translated to IR. IR is compiled
to HDL IR in multiple complex steps, typically contains scheduling, arch. mapping etc.)
## Related open-source
* [fusesoc](https://github.com/olofk/fusesoc) - package manager and a set of build tools for FPGA/ASIC development
* [OpenSTA](https://github.com/abk-openroad/OpenSTA) - a gate level static timing verifier
* [RePlAce](https://github.com/abk-openroad/RePlAce) - global placement tool
* [verilator](https://www.veripool.org/wiki/verilator) - Verilog -> C/C++ simulator
* [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing)
* [yosys](https://github.com/YosysHQ/yosys) - RTL synthesis framework
* [UHDM](https://github.com/alainmarcel/UHDM) - SV -> C++
## Board support libraries (Potential candidates for public integration)
* [litex](https://github.com/enjoy-digital/litex) - Buildsystem for migen
* [loam](https://github.com/phanrahan/loam) - Buildsystem for magma
* [vivado-boards](https://github.com/Digilent/vivado-boards) - Vivado XML/TCL files with board description
* [nmigen-boards](https://github.com/nmigen/nmigen-boards) - board and connector meta fo nmigen
## Sources of informations in this area
* [computer-engineering-resources](https://github.com/rajesh-s/computer-engineering-resources) - list of conferences and hardware projects
================================================
FILE: doc/conf.py
================================================
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# This file is execfile()d with the current directory set to its
# containing dir.
#
# Note that not all possible configuration values are present in this
# autogenerated file.
#
# All configuration values have a default; values that are commented out
# serve to show the default.
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
from datetime import datetime
import os
import re
import sys
from sphinx.ext.apidoc import main as apidoc_main
import sphinx_bootstrap_theme
sys.path.insert(0, os.path.abspath('../'))
# -- General configuration ------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
'sphinx.ext.autodoc',
'sphinx.ext.todo',
'sphinx.ext.viewcode',
# 'sphinx.ext.napoleon',
'sphinx.ext.graphviz',
'sphinx.ext.intersphinx',
]
intersphinx_mapping = {
'ipCorePackager': ("https://ipcorepackager.readthedocs.io/en/latest/", None),
}
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# General information about the project.
project = 'hwt'
copyright = '2017-%d, Michal Orsak' % datetime.now().year
author = 'Michal Orsak'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
# The short X.Y version.
version = 'latest'
# The full version, including alpha/beta/rc tags.
release = ''
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = 'en'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This patterns also effect to html_static_path and html_extra_path
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True
# -- Options for HTML output ----------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
# html_theme = 'alabaster'
html_theme = 'bootstrap'
html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
# html_theme_options = {}
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# -- Options for HTMLHelp output ------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'hwtdoc'
# -- Options for LaTeX output ---------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'hwt.tex', 'HWToolkit generated documentation',
'Michal Orsak', 'manual'),
]
# -- Options for manual page output ---------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'hwt', 'HWToolikt Documentation',
[author], 1)
]
# -- Options for Texinfo output -------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'hwt', 'HWToolikt Documentation',
author, 'hwt', 'Collection of tools for hardware generation.',
'Miscellaneous'),
]
# -- Options for Epub output ----------------------------------------------
# Bibliographic Dublin Core info.
epub_title = project
epub_author = author
epub_publisher = author
epub_copyright = copyright
# The unique identifier of the text. This can be a ISBN number
# or the project homepage.
#
# epub_identifier = ''
# A unique identification for the text.
#
# epub_uid = ''
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
notskipregex = re.compile("_[^_]+")
def skip(app, what, name, obj, skip, options):
if name == "__init__" or notskipregex.match(name):
return False
return skip
def setup(app):
app.connect("autodoc-skip-member", skip)
# update *.rst pages
apidoc_main(["--module-first", "--full",
"--output-dir", "../doc", "../hwt"])
================================================
FILE: doc/gtkwave.rst
================================================
GTKWave useful tweaks
======================
.. code-block:: text
echo splash_disable 1 >> ~/.gtkwaverc
================================================
FILE: doc/hwtCircuitNormalForm.rst
================================================
HWT Circuit normal form (hwtCircuitNF)
======================================
HWT Circuit normal form (hwtCircuitNF) is a format of the netlist which is meant as a most simple and compact format of netlist
for circuit analysis. It is supposed to be human and programmatically readable.
hwtCircuitNF is not dependent on HWT and it is rather a specification of the code-style in Verilog/VHDL.
It specifies how statements and signals should be used in order to reduce number of possible descriptions of the same thing.
E.g. a multiplexer can be described using assignment with indexed/conditional expr. and also using switch/if statement
among other possibilities.
A typical synthesis tool converts all this to a gates and it performs the further code analysis there.
However if we want to perform circuit analysis on statement level we have to check every possible syntax.
By performing code analysis and optimization in place on syntax level on normalized circuit we can gain these advantages:
* No need for further conversions with nice object traceability.
* All optimizations would be nearly human readable in every step.
* There is probably less objects in the circuit which would also improve the performance of the compiler.
However there are also downsides of this approach:
* Object have a complex internal structure which could cancel out performance gains.
* The properties of hwtCircuitNF have to be maintained during the updates which add another performance hits.
* For an efficient implementation of analysis the object have to
hwtCircuitNF rules
------------------
(A definition of common netlist in EDIF/VHDL/SystemVerilog)
The netlist described in hwtCircuitNF is a set of components, statements and signals connecting them.
The signal can not cross the boundary of the component, instead it has to be connected to IO of component to achieve this functionality.
The components can be nested, each component has only a single parent, same applies to statements.
Statement can not have nested component.
(A hwtCircuitNF addition)
The signal is driven from component IO or from statement. The signal endpoint is a component IO or statement which is using this
signal to drive something else. Each signal has to drive something and has to be driven by something.
This implies:
* hwtCircuitNF does not contain unconnected statements/components.
* Each signal is somehow connected to some output of the top.
In addition there are several additional rules about statement syntax and signal usage.
Multiplexer coding style
^^^^^^^^^^^^^^^^^^^^^^^^
Rationale: To avoid expression analysis during detection of enclosures, muxes and latches.
no
.. code-block:: verilog
x <= y[(i + 1)*8 - 1: i*8];
no
.. code-block:: verilog
x <= i == 0 ? y[8-1:0] : y[16-1:8];
yes
.. code-block:: verilog
if (i == 0)
x <= y[ 8 - 1: 0]
else if (i == 1)
x <= y[16 - 1: 8]
// ...
yes, prefered
.. code-block:: verilog
case (i)
1'b0: x <= y[ 8-1:0];
1'b1: x <= y[16-1:8];
Note that the instanciation of the MUX as a component is not a MUX description.
Const indexed assignment vs assignment of concatenation
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Rationale: Merge all drivers of signal in to a single statement.
no
.. code-block:: verilog
s[1] <= y;
s[0] <= x;
yes - all assignment with a constant part specification converted to an assignment of concatenation of all parts
.. code-block:: verilog
s <= {y, x};
yes - there is only a single part and this is actually a cast
.. code-block:: verilog
wire s[0:0];
s[0] <= y;
Const indexed drives of disjunctive parts of same signal
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Rationale: Split independent parts of signal if possible.
no
.. code-block:: verilog
if (c0)
s[0] <= x;
if (c1)
s[1] <= y;
yes - all separately driven parts of signal extracted as a signal and the original signal is driven from its parts
.. code-block:: verilog
wire s_0_tmp;
wire s_1_tmp;
assign s <= {s_1_tmp, s_0_tmp};
if (c0)
s_0_tmp <= x;
if (c1)
s_1_tmp <= y;
yes - the part specifier is not a constant expression
.. code-block:: verilog
if (c0)
s[i][0] <= x;
if (c1)
s[i][1] <= y;
Enclosure filed
^^^^^^^^^^^^^^^
Rationale: To be able to analyze any statement without the need for an information from its parent.
no
.. code-block:: verilog
s <= x0;
if (c0)
if (c1) begin
s <= x1;
end
else if (c2)
s <= x2;
yes - enclosure filled
.. code-block:: verilog
if (c0)
if (c1) begin
s <= x1;
end else begin
s <= x0;
end
else if (c2)
s <= x2;
else
s <= x0;
Assignment to concatenation
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Rationale: To have assignments with a single output and to be able to separate them from statements easily.
no
.. code-block:: verilog
{a, b} <= {c, d};
yes - assignment only to single destination
.. code-block:: verilog
a <= c;
b <= d;
Concatenations always on top of expression tree
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Rationale: We need to move indexing operators under the concatenations
in order to make structural hashing as efficient as possible. We need to do this also for other
bitwise operators and not just for index operators.
no: The indexing is at the top of operator tree and the concatenation is at bottom.
.. code-block:: verilog
wire[4-1:0] b;
wire c;
~({a, b, c}[2-1:0])
yes: The indexing is at the bottom of operator tree and concatenation is on top.
.. code-block:: verilog
{~b[1-1:0], ~c}
================================================
FILE: doc/index.rst
================================================
Welcome to hwt (HWToolkit) generated documentation!
===================================================
This documentation is automatically generated from actual source code.
What is hwt (HWToolkit)
-----------------------
* Is a Hardware Construction Framework. It is similar to a HCLs like Chisel3 but it is rather set of object with a normal
behavior rather than a new language. The objects represents signals and other RTL components and can be serialized to Verilog/VHDL/SystemC/...
(That means the hwt is not transpiler or compiler and there is also no entry point.)
* HWT internal representation is graph database of statements and signals.
Hwt type system is made of several elemental datatypes templates which can be used for a type of signal:
* HBits - represents bit vector
* HStruct - structure/record datatype
* HUnion - union datatype
* HArray - array datatype
* TransTmpl metatype - transactional template which describes how data can be partitioned to memores, buses, streams etc.
Think of it like a object which tells how to build frames from potentially sparse data structure in memory.
* The type itself drives it's hw representation, that means the typesystem is user extensible.
* HWT is build as abstraction layer over all HDL languages to shield users from tricky features of such a languages.
However nothings is sacrificed and everything can be overridden.
* HWT uses UVM like verification environment implemented in hwtSimApi. hwtSimApi can use verilator or python based simulator
to achieve high-speed simulation or nearly-zero simulator spin-up.
* Most of parts of HWT ecosystem are independent and you can use them separately.
Other useful libraries
-----------------------
.. image:: _static/hwt_ecosystem_packages.png
Where to start
--------------
Tutorial is in hwtLib.examples.*, every file in this module contains user-entry-level comments.
E.g. hwtLib.examples.simple.SimpleHwModule is a good starting point.
Component in HWT is a class which inherits from HwModule class.
Object of such a class can be converted to a vhdl/Verilog by from hwt.synth.to_rtl function.
That said, this library is regular python library without any non-pyhon dependencies,
it does not have any executable file.
You can also download this doc in `PDF
<https://media.readthedocs.org/pdf/hwtoolkit/latest/hwtoolkit.pdf>`_.
.. toctree::
:maxdepth: 4
:caption: Contents:
hwt
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`
================================================
FILE: doc/requirements.doc.txt
================================================
-r requirements.txt
sphinx_bootstrap_theme
================================================
FILE: doc/requirements.txt
================================================
git+https://github.com/Nic30/pyMathBitPrecise.git@master#egg=pyMathBitPrecise
git+https://github.com/Nic30/pyDigitalWaveTools.git@master#egg=pyDigitalWaveTools
git+https://github.com/Nic30/hdlConvertorAst.git@master#egg=hdlConvertorAst
git+https://github.com/Nic30/ipCorePackager.git@master#egg=ipCorePackager
git+https://github.com/Nic30/hwtSimApi.git@master#egg=hwtSimApi
================================================
FILE: hwt/__init__.py
================================================
================================================
FILE: hwt/code.py
================================================
from operator import and_, or_, xor, add, eq
from types import GeneratorType
from typing import Union, Sequence, Optional, Tuple
from hdlConvertorAst.to.hdlUtils import iter_with_last
from hwt.code_utils import _mkOp, _HwIOToRtlSignal
from hwt.hdl.const import HConst
from hwt.hdl.operatorDefs import concatFn
from hwt.hdl.statements.codeBlockContainer import HdlStmCodeBlockContainer
from hwt.hdl.statements.ifContainter import IfContainer
from hwt.hdl.statements.statement import HwtSyntaxError, HdlStatement
from hwt.hdl.statements.switchContainer import SwitchContainer
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.hdl.types.bits import HBits
from hwt.hdl.types.enum import HEnum
from hwt.hdl.types.typeCast import toHVal
from hwt.mainBases import HwIOBase, HwModuleBase
from hwt.mainBases import RtlSignalBase
from hwt.math import log2ceil
from hwt.pyUtils.arrayQuery import arr_any
from hwt.synthesizer.rtlLevel.rtlSignalWalkers import \
discoverEventDependency
class CodeBlock(HdlStmCodeBlockContainer):
"""
Container for list of statements
"""
def __init__(self, *statements: Sequence[HdlStatement]):
super(CodeBlock, self).__init__()
self._register_stements(statements, self.statements)
self.rank = sum(map(lambda s: s.rank, statements))
if self._outputs:
ctx = self._get_rtl_context()
ctx.statements.add(self)
class If(IfContainer):
"""
If statement generator
"""
def __init__(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):
"""
:param cond: condition in if statement
:param statements: list of statements which should be active
if condition is met
"""
cond_sig = _HwIOToRtlSignal(cond)
if not isinstance(cond_sig, RtlSignalBase):
raise HwtSyntaxError("Condition is not signal, it is not certain"
" if this is an error or desire ", cond_sig)
assert cond_sig._dtype.bit_length() == 1, cond_sig
super(If, self).__init__(cond_sig)
self.rank = 1
self._inputs.append(cond_sig)
cond_sig._rtlEndpoints.append(self)
ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)
self._event_dependent_from_branch = 0 if ev_dep else None
self._register_stements(statements, self.ifTrue)
self._get_rtl_context().statements.add(self)
def Elif(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):
assert self.parentStm is None
self.rank += 1
cond_sig = _HwIOToRtlSignal(cond)
assert cond_sig._dtype.bit_length() == 1, cond_sig
ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)
self._event_dependent_from_branch = len(self.elIfs) + 1 if ev_dep else None
self._inputs.append(cond_sig)
cond_sig._rtlEndpoints.append(self)
stms = ListOfHdlStatement()
self.elIfs.append((cond_sig, stms))
self._register_stements(statements, stms)
return self
def Else(self, *statements: Sequence[HdlStatement]):
assert self.parentStm is None
if self.ifFalse is not None:
raise HwtSyntaxError(
"Else on this if-then-else statement was already used")
self.rank += 1
self.ifFalse = ListOfHdlStatement()
self._register_stements(statements, self.ifFalse)
return self
class Switch(SwitchContainer):
"""
Switch statement generator
"""
def __init__(self, switchOn: Union[RtlSignalBase, HwIOBase]):
switchOn = _HwIOToRtlSignal(switchOn)
if not isinstance(switchOn, RtlSignalBase):
raise HwtSyntaxError("Select is not signal, it is not certain"
" if this is an error or desire")
if arr_any(discoverEventDependency(switchOn), lambda x: True):
raise HwtSyntaxError("Can not switch on result of event operator")
super(Switch, self).__init__(switchOn, [])
switchOn._rtlCtx.statements.add(self)
self._inputs.append(switchOn)
switchOn._rtlEndpoints.append(self)
def add_cases(self, tupesValStms: Sequence[Tuple[Union[HConst, int], Sequence[HdlStatement]]]):
"""
Add multiple case statements from iterable of tuples
(caseVal, statements)
"""
s = self
for val, statements in tupesValStms:
s = s.Case(val, statements)
return s
def Case(self, caseVal: Union[HConst, int], *statements: Sequence[HdlStatement]):
"c-like case of switch statement"
assert self.parentStm is None
caseVal = toHVal(caseVal, self.switchOn._dtype)
assert isinstance(caseVal, HConst), caseVal
assert caseVal._is_full_valid(), "Cmp with invalid value"
assert caseVal not in self._case_value_index, (
"Switch statement already has case for value ", caseVal)
self.rank += 1
stms = ListOfHdlStatement()
self._case_value_index[caseVal] = len(self.cases)
self.cases.append((caseVal, stms))
self._register_stements(statements, stms)
return self
def Default(self, *statements: Sequence[HdlStatement]):
"""c-like default of switch statement
"""
assert self.parentStm is None
self.rank += 1
self.default = ListOfHdlStatement()
self._register_stements(statements, self.default)
return self
def SwitchLogic(cases: Sequence[Tuple[Union[RtlSignalBase, HwIOBase, HConst, bool], Sequence[HdlStatement]]],
default: Optional[Sequence[HdlStatement]]=None):
"""
Generate if tree for cases like (syntax sugar for large generated elifs)
..code-block:: python
if cond0:
statements0
elif cond1:
statements1
else:
default
:param case: iterable of tuples (condition, statements)
:param default: default statements
"""
assigTop = None
hasElse = False
for last, (cond, statements) in iter_with_last(cases):
if isinstance(cond, (RtlSignalBase, HwIOBase)):
if assigTop is None:
assigTop = If(cond,
statements
)
else:
assigTop = assigTop.Elif(cond, statements)
else:
if cond:
if assigTop is None:
assigTop = statements
else:
assigTop.Else(statements)
hasElse = True
if last or isinstance(cases, GeneratorType):
# allow True as a condition for default
break
raise HwtSyntaxError("Condition is not a signal, it is not certain"
" if this is an error or desire ", cond, cases)
if assigTop is None:
if default is None:
return []
else:
return default
else:
if hasElse:
return assigTop
elif default is not None:
assigTop = assigTop.Else(default)
return assigTop
def In(sigOrConst: Union[RtlSignalBase, HwIOBase, HConst], iterable: Sequence[Union[RtlSignalBase, HwIOBase, HConst]]):
"""
HDL convertible "in" operator, check if any of items
in "iterable" equals "sigOrConst"
"""
res = None
for i in iterable:
i = toHVal(i)
if res is None:
res = sigOrConst._eq(i)
else:
res = res | sigOrConst._eq(i)
assert res is not None, "argument iterable is empty"
return res
def StaticForEach(parentModule: HwModuleBase, items, bodyFn, name=""):
"""
Generate for loop for static items
:param parentModule: HwModule where this code should be instantiated
:param items: items which this "for" iterating on
:param bodyFn: function which fn(item, index) or fn(item)
returns (statementList, ack).
It's content is performed in every iteration.
When ack is high loop will fall to next iteration
"""
items = list(items)
itemsCnt = len(items)
if itemsCnt == 0:
# if there are no items there is nothing to generate
return []
elif itemsCnt == 1:
# if there is only one item do not generate counter logic generate
return bodyFn(items[0], 0)
else:
# if there is multiple items we have to generate counter logic
index = parentModule._reg(name + "for_index",
HBits(log2ceil(itemsCnt + 1), signed=False),
def_val=0)
ackSig = parentModule._sig(name + "for_ack")
statementLists = []
for i, (statementList, ack) in [(i, bodyFn(item, i))
for i, item in enumerate(items)]:
statementLists.append(statementList + [(ackSig(ack)), ])
If(ackSig,
If(index._eq(itemsCnt - 1),
index(0)
).Else(
index(index + 1)
)
)
return Switch(index)\
.add_cases(
enumerate(statementLists)
).Default(
bodyFn(items[0], 0)[0],
ackSig(True)
)
class FsmBuilder(Switch):
"""
A syntax sugar which automatically construct the state transition switch and state register
:ivar ~.stateReg: register with state
"""
def __init__(self, parentModule: HwModuleBase, stateT, stateRegName="st"):
"""
:param parentModule: parent HwModule where FSM should be builded
:param stateT: enum type of state
:param stateRegName: name of register where sate is stored
"""
if isinstance(stateT, HEnum):
beginVal = stateT.from_py(stateT._allValues[0])
else:
beginVal = 0
self.stateReg = parentModule._reg(stateRegName, stateT, beginVal)
Switch.__init__(self, self.stateReg)
def Trans(self, stateFrom, *condAndNextState):
"""
:param stateFrom: apply when FSM is in this state
:param condAndNextState: tuples (condition, newState),
last does not to have condition
:attention: transitions has priority, first has the biggest
:attention: if stateFrom is None it is evaluated as default
"""
top = []
last = True
for cAndS in reversed(condAndNextState):
if last is True:
last = False
# if this is last trans. it does not have to condition
try:
condition, newvalue = cAndS
except TypeError:
top = self.stateReg(cAndS)
continue
top = []
else:
condition, newvalue = cAndS
# building decision tree
top = \
If(condition,
self.stateReg(newvalue)
).Else(
top
)
if stateFrom is None:
return Switch.Default(self, top)
else:
return Switch.Case(self, stateFrom, top)
def Default(self, *condAndNextState):
d = self.Trans(None, *condAndNextState)
d.stateReg = self.stateReg
return d
# variadic operator functions
And = _mkOp(and_)
Add = _mkOp(add)
Or = _mkOp(or_)
Xor = _mkOp(xor) # :note: xor is bitwise !=
Xnor = _mkOp(eq) # :note: xnor is bitwise ==
Concat = _mkOp(concatFn)
def ror(sig:Union[RtlSignalBase, HConst], howMany: int) -> RtlSignalBase:
"Rotate right"
if sig._dtype.bit_length() == 1:
return sig
if isinstance(howMany, int):
return sig[howMany:]._concat(sig[:howMany])
elif isinstance(howMany, HConst):
return ror(sig, int(howMany))
else:
t = howMany._dtype
if not isinstance(t, HBits) or t.signed:
raise NotImplementedError(t)
res = sig
for i in range(1, t.domain_size() - 1):
res = howMany._eq(i)._ternary(ror(sig, i), res)
return res
def rol(sig:Union[RtlSignalBase, HConst], howMany:Union[RtlSignalBase, int]) -> RtlSignalBase:
"Rotate left"
if isinstance(howMany, int):
width = sig._dtype.bit_length()
if width == 1:
return sig
return sig[(width - howMany):]._concat(sig[:(width - howMany)])
elif isinstance(howMany, HConst):
return rol(sig, int(howMany))
else:
t = howMany._dtype
if not isinstance(t, HBits) or t.signed:
raise NotImplementedError(t)
res = sig
for i in range(1, t.domain_size() - 1):
res = howMany._eq(i)._ternary(rol(sig, i), res)
return res
def replicate(n:int, v:Union[RtlSignalBase, HConst]):
assert n > 0, n
return Concat(*(v for _ in range(n)))
def segment_get(n:Union[RtlSignalBase, HConst],
segmentWidth:int,
segmentIndex:Union[RtlSignalBase, HConst, int]):
"""
This function gets bits from bit vector as if it was an array of items of "segmentWidth" bits
"""
return n[segmentWidth * (segmentIndex + 1): segmentWidth * segmentIndex]
def split_to_segments(n:Union[RtlSignalBase, HConst], maxSegmentWidth:int, allowLastToBeSmaller=False, extendLast=False):
"""
Split bit vector to a segments of up to maxSegmentWidth bits, lower bits first.
"""
offset = 0
segments = []
width = n._dtype.bit_length()
if not allowLastToBeSmaller and not extendLast:
assert width % maxSegmentWidth == 0, (width, maxSegmentWidth)
while True:
end = min(offset + maxSegmentWidth, width)
segments.append(n[end:offset])
if end == width:
if extendLast and end != offset + maxSegmentWidth:
segments[-1] = segments[-1]._ext(maxSegmentWidth)
break
offset = end
return segments
================================================
FILE: hwt/code_utils.py
================================================
from typing import Union
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.types.defs import BIT
from hwt.mainBases import HwIOBase
from hwt.mainBases import RtlSignalBase
from ipCorePackager.constants import DIRECTION
def rename_signal(hwModule: "HwModule",
sig: Union[RtlSignalBase, int, bool],
name: str):
"""
Wrap signal or value in signal of specified name
:attention: output signal is driven by new signal of a specified name
this means that the assigning to a new signal does not drive a original signal
"""
if isinstance(sig, (int, bool)):
t = BIT
else:
t = sig._dtype
if isinstance(sig, (HConst, int, bool)):
s = hwModule._sig(name, t, def_val=sig, nop_val=sig)
else:
s = hwModule._sig(name, t)
s(sig)
return s
def connect_optional(src: HwIOBase, dst: HwIOBase,
check_fn=lambda hwIO0, hwIO1: (True, [])):
"""
Connect interfaces and ignore all missing things
:param check_fn: filter function(hwIO0, hwIO1) which check if interfaces should be connected
returns tuple (do_check, extra_connection_list)
"""
return list(_connect_optional(src, dst, check_fn, False))
@internal
def _connect_optional(src: HwIOBase, dst: HwIOBase, check_fn, dir_reverse):
do_connect, extra_connections = check_fn(src, dst)
yield from extra_connections
if not do_connect:
return
if not src._hwIOs:
assert not dst._hwIOs, (src, dst)
if dir_reverse:
yield src(dst)
else:
yield dst(src)
for _s in src._hwIOs:
_d = getattr(dst, _s._name, None)
if _d is None:
# if the interfaces does not have subinterface of same name
continue
if _d._masterDir == DIRECTION.IN:
rev = not dir_reverse
else:
rev = dir_reverse
yield from _connect_optional(_s, _d, check_fn, rev)
@internal
def _HwIOToRtlSignal(obj):
if isinstance(obj, HwIOBase):
return obj._sig
else:
return obj
@internal
def _mkOp(fn):
"""
Function to create variadic operator function
:param fn: function to perform binary operation
"""
def op(*operands, key=None) -> RtlSignalBase:
"""
:param operands: variadic parameter of input uperands
:param key: optional function applied on every operand
before processing
"""
assert operands, operands
top = None
if key is not None:
operands = map(key, operands)
for s in operands:
if top is None:
top = s
else:
top = fn(top, s)
return top
return op
================================================
FILE: hwt/constants.py
================================================
"""
Commonly used constants during HW development.
"""
# import constants from other packages to have them on one place
from ipCorePackager.constants import INTF_DIRECTION, DIRECTION
from hwtSimApi.constants import Time, CLK_PERIOD
READ = "READ"
WRITE = "WRITE"
READ_WRITE = "RW"
NOP = "NOP"
class NOT_SPECIFIED():
"""
Constant which means that the thing is not specified
Used for optional arguments as a value which marks that the value of this
argument was not specified on the place where we can not just use None
"""
def __init__(self):
raise AssertionError("Use only a class a constant")
================================================
FILE: hwt/constraints.py
================================================
"""
This module contains the objects to store hardware constraints.
Hardware constrains are usually stored in XDC/UCF files and they specify somethings
which can not be described using HDL (SystemVerilog/VHDL) like relation between clock.
Placement of component if FPGA etc.
"""
from copy import copy
from typing import Union, Tuple
from hwt.hwIO import HwIO
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal
from hwt.hwModule import HwModule
from hwt.synthesizer.componentPath import ComponentPath
class iHdlConstrain():
def _get_parent(self) -> HwModule:
raise NotImplementedError(self)
def _copy_with_root_upadate(self, old_path_prefix, new_path_prefix):
raise NotImplementedError()
def register_on_parent(self):
self._get_parent()._constraints.append(self)
def _get_parent_HwModule(path: Tuple[Union[HwModule, HwIO, RtlSignal, iHdlConstrain], ...]) -> HwModule:
"""
Search parent :class:`hwt.hwModule.HwModule` instance in path
"""
if isinstance(path, iHdlConstrain):
return path._get_parent()
for o in reversed(path):
if isinstance(o, HwModule):
return o
raise AssertionError("No parent HwModule in path", path)
def _get_absolute_path(obj) -> Union[Tuple[Union[HwModule, HwIO, RtlSignal, iHdlConstrain], ...], None]:
"""
Get tuple containing a path of objects from top to this object
"""
if obj is None:
return None
elif isinstance(obj, iHdlConstrain):
return obj
return ComponentPath(obj).resolve()
def _apply_path_update(path: ComponentPath, old_path_prefix: ComponentPath, new_path_prefix: ComponentPath):
"""
Update prefix of the path tuple
"""
if isinstance(path, iHdlConstrain):
return path._copy_with_root_upadate(old_path_prefix, new_path_prefix)
return path.update_prefix(old_path_prefix, new_path_prefix)
class set_max_delay(iHdlConstrain):
"""
Object which represents the max_delay constrain
* usually used to set propagation time between two clock domains etc.
:ivar ~.start: start of the signal path
:ivar ~.end: end of the signal path
:ivar ~.time_ns: max delay of the specified path in ns
"""
def __init__(self,
start: Union[HwIO, RtlSignal],
end: Union[HwIO, RtlSignal],
time_ns: float,
datapath_only=True,
ommit_registration=False):
self.start = _get_absolute_path(start)
self.end = _get_absolute_path(end)
self.time_ns = time_ns
self.datapath_only = datapath_only
if not ommit_registration:
self.register_on_parent()
def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_path_prefix: ComponentPath):
new_o = copy(self)
new_o.start = _apply_path_update(
self.start, old_path_prefix, new_path_prefix)
new_o.end = _apply_path_update(
self.end, old_path_prefix, new_path_prefix)
return new_o
def _get_parent(self) -> HwModule:
return _get_parent_HwModule(self.end)
class set_false_path(iHdlConstrain):
def __init__(self, start: Union[None, HwIO, RtlSignal],
end: Union[None, HwIO, RtlSignal],
ommit_registration=False):
self.start = _get_absolute_path(start)
self.end = _get_absolute_path(end)
if not ommit_registration:
self.register_on_parent()
def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_path_prefix: ComponentPath):
return set_max_delay._copy_with_root_upadate(self, old_path_prefix, new_path_prefix)
def _get_parent(self) -> HwModule:
o = self.start
if o is None:
o = self.end
return _get_parent_HwModule(o)
class get_clock_of(iHdlConstrain):
def __init__(self, obj: Union[HwIO, RtlSignal],
ommit_registration=False):
self.obj = _get_absolute_path(obj)
def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_path_prefix: ComponentPath):
new_o = copy(self)
new_o.obj = _apply_path_update(
self.obj, old_path_prefix, new_path_prefix)
return new_o
def _get_parent(self) -> HwModule:
return _get_parent_HwModule(self.obj)
class set_async_reg(iHdlConstrain):
"""
Placement constrain which tell that the register should be put as close as possible to it's src/dst
It should not be placed on the FF on the src domain,
but should be set on FFs (possibly more) on the destination domain.
"""
def __init__(self, sig: RtlSignal,
ommit_registration=False):
self.sig = _get_absolute_path(sig)
if not ommit_registration:
self.register_on_parent()
def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_path_prefix: ComponentPath):
new_o = copy(self)
new_o.sig = _apply_path_update(
self.sig, old_path_prefix, new_path_prefix)
return new_o
def _get_parent(self) -> HwModule:
return _get_parent_HwModule(self.sig)
================================================
FILE: hwt/doc_markers.py
================================================
def internal(fn):
"""
Decorator which does not affect functionality but it is used as marker
which tells that this object is not interesting for users and it is only used internally
"""
return fn
def hwt_expr_producer(fn):
"""
Decorator which does not affect functionality.
For documentation purposes it specifies that the function produces hwt expression.
"""
return fn
================================================
FILE: hwt/hObjList.py
================================================
from typing import TypeVar, Iterable, List, Union, Tuple, Optional, \
Self
from hwt.mainBases import HwIOBase, HwModuleBase
T = TypeVar("T", HwIOBase, HwModuleBase, None)
class HObjList(list[T]):
"""
Regular list with some interface/unit methods delegated on items.
Main purpose of this class it let :class:`hwt.synthesizer.PropDeclrCollector.PropDeclrCollector`
know that this is not an regular python array and that items should be registered as HW objects.
:ivar _name: name of the property on parent
:ivar _parent: parent HwModule/HwIO object
:note: this object may be nested in HObjList instances but the parent and name will always corresponds
to a HwModule/HwIO object, if there is any
:note: :class:`hwt.synthesizer.PropDeclrCollector.PropDeclrCollector` is used by
:class:`hwt.hwIO.Interface` and :class:`hwt.hwModule.HwModule`
"""
def __init__(self, *args, **kwargs):
hdlNameOverride = kwargs.pop("hdlName", None)
list.__init__(self, *args, **kwargs)
self._name: Optional[str] = None
self._parent: Optional[Union["HwModule", "Interface"]] = None
self._hdlNameOverride: Optional[str] = hdlNameOverride
def _on_append(self, self_obj: Self, item: T, index: int):
pass
def append(self, item: T):
if self._on_append is not HObjList._on_append:
self._on_append(self, item, len(self))
return list.append(self, item)
def clear(self, *args, **kwargs):
assert self._parent is None
return list.clear(self, *args, **kwargs)
def extend(self, iterable: Iterable[T]):
if self._on_append is not HObjList._on_append:
offset = len(self)
for i, item in enumerate(iterable):
self._on_append(self, item, offset + i)
return list.extend(self, iterable)
def insert(self, *args, **kwargs):
assert self._parent is None
return list.insert(self, *args, **kwargs)
def pop(self, *args, **kwargs) -> T:
assert self._parent is None
return list.pop(self, *args, **kwargs)
def remove(self, *args, **kwargs):
assert self._parent is None
return list.remove(self, *args, **kwargs)
def reverse(self, *args, **kwargs):
assert self._parent is None
return list.reverse(self, *args, **kwargs)
def sort(self, *args, **kwargs):
assert self._parent is None
return list.sort(self, *args, **kwargs)
def _getHdlName(self):
"""Get name in HDL """
# list of name or tulple (name, separator)
name: List[Union[str, Tuple[str, str]]] = []
tmp = self
while isinstance(tmp, (HwIOBase, HObjList)):
n = tmp._name
if name:
name_sep = getattr(tmp, "_NAME_SEPARATOR", "_")
n = (n, name_sep)
else:
# no need to add separator at the end because this is a last part of the name
n = n
add_name_part_from_this = True
name_override = tmp._hdlNameOverride
if name_override is not None:
# recursively apply renames
if isinstance(name_override, str):
if isinstance(n, tuple) and name_override:
n = (name_override, n[1])
else:
n = name_override
elif isinstance(name_override, dict):
last_name = name[-1]
if isinstance(last_name, tuple):
last_name = last_name[0]
no = name_override.get(last_name, None)
if no is not None:
if isinstance(no, str):
# everything what we resolved so far is overridden on this parent
name = [no, ]
add_name_part_from_this = False
else:
raise NotImplementedError()
else:
raise TypeError(name_override)
if add_name_part_from_this:
name.append(n)
tmp = getattr(tmp, "_parent", None)
_name = []
for n in reversed(name):
if isinstance(n, str):
_name.append(n)
else:
_name.extend(n)
return "".join(_name)
def _getFullName(self) -> str:
"""get all name hierarchy separated by '.' """
name = ""
tmp = self
while isinstance(tmp, (HwIOBase, HObjList)):
n = tmp._name
if name == '':
if n is not None:
assert isinstance(n, str), (name, n)
name = n
else:
if n is None:
n = "<unnamed>"
name = f"{n:s}.{name:s}"
tmp = getattr(tmp, "_parent", None)
return name
def _make_association(self, *args, **kwargs):
"""
Delegate _make_association on items
:note: doc in :func:`~hwt.synthesizer.interfaceLevel.propDeclCollector._make_association`
"""
for o in self:
o._make_association(*args, **kwargs)
return self
def _updateHwParamsFrom(self, *args, **kwargs):
"""
:note: doc in :func:`~hwt.synthesizer.interfaceLevel.propDeclCollector._updateHwParamsFrom`
"""
for o in self:
if isinstance(o, (HwIOBase, HwModuleBase, HObjList)):
o._updateHwParamsFrom(*args, **kwargs)
return self
def _cleanRtlSignals(self, lockNonExternal=True):
for o in self:
if isinstance(o, (HwIOBase, HwModuleBase, HObjList)):
o._cleanRtlSignals(lockNonExternal=lockNonExternal)
================================================
FILE: hwt/hdl/__init__.py
================================================
"""
This package contains classes for representation of HDL
languages (hdl types, RtlSignal, HdlAssignmentContainer, HdlStmCodeBlockContainer etc.).
It also contains classes for representation of complex HW structures
like dense transaction template (TransTmpl, FrameTmpl).
"""
# [TODO] derive from hdlConvertorAst.hdlAst
================================================
FILE: hwt/hdl/commonConstants.py
================================================
from hwt.hdl.types.defs import BIT
b1 = BIT.from_py(1)
b0 = BIT.from_py(0)
================================================
FILE: hwt/hdl/const.py
================================================
from typing import TypeVar, Generic, Self, Set
from hwt.doc_markers import internal
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.mainBases import RtlSignalBase
T = TypeVar("T", bound="HdlType")
class HConst(Generic[T]):
"""
Wrap around hdl value with overloaded operators
operators are overloaded in every type separately
"""
__slots__ = ["_dtype", "val", "vld_mask"]
def __init__(self, dtype: "HdlType", val, vld_mask):
"""
:param val: pythonic value representing this value
:param dtype: data type object from which this value was derived from
:param vld_mask: validity mask for value
"""
self._dtype = dtype
self.val = val
self.vld_mask = vld_mask
def _is_full_valid(self):
return self.vld_mask == self._dtype.all_mask()
def _is_partially_valid(self) -> bool:
return self.vld_mask != 0
def _auto_cast(self, toType: "HdlType"):
"""
Cast value or signal of this type to another compatible type.
:param toType: instance of HdlType to cast into
"""
return self._dtype.auto_cast_HConst(self, toType)
def _reinterpret_cast(self, toType: "HdlType"):
"""
Cast value or signal of this type to another type of same size.
:param toType: instance of HdlType to cast into
"""
return self._dtype.reinterpret_cast_HConst(self, toType)
def staticEval(self) -> Self:
return self.__copy__()
def __copy__(self) -> Self:
return self.__class__(self._dtype, self.val, self.vld_mask)
@internal
def __hash__(self) -> int:
return hash((self._dtype, self.val, self.vld_mask))
def __repr__(self) -> str:
if self._is_full_valid():
vld_mask = ""
else:
vld_mask = ", mask {0:x}".format(self.vld_mask)
return "<{0:s} {1:s}{2:s}>".format(
self.__class__.__name__, repr(self.val), vld_mask)
@classmethod
def _from_py(cls, typeObj, val, vld_mask) -> Self:
"""
from_py without value normalization and type checking
"""
return cls(typeObj, val, vld_mask)
@classmethod
def from_py(cls, typeObj, val, vld_mask=None) -> Self:
raise NotImplementedError(
f"from_py fn is not implemented for", cls)
def __eq__(self, other):
if isinstance(other, HConst):
return self._dtype == other._dtype and \
self.vld_mask == other.vld_mask and\
self.val == other.val
else:
return super().__eq__(other)
def _eq(self, other):
raise TypeError()
def __ne__(self, other):
eq = self._eq(other)
eq.val = not eq.val
return eq
def _walk_sensitivity(self, casualSensitivity: Set[RtlSignalBase], seen: Set[RtlSignalBase], ctx: SensitivityCtx):
"""
:see: :meth:`hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity`
"""
seen.add(self)
def areHConsts(*items):
"""
:return: True if all arguments are instances of HConst class else False
"""
for i in items:
if not isinstance(i, HConst):
return False
return True
================================================
FILE: hwt/hdl/constUtils.py
================================================
from typing import Union, List
from hwt.hdl.const import HConst
def isSameHConst(a: HConst, b: HConst) -> bool:
"""
:return: True if two Value instances are same
:note: not just equal
"""
return a is b or (isinstance(a, HConst)
and isinstance(b, HConst)
and a.val == b.val
and a.vld_mask == b.vld_mask)
def areSameHConsts(a: Union[None, List[HConst]],
b: Union[None, List[HConst]]) -> bool:
"""
:return: True if two vectors of HConst/RtlSignal instances are same
:note: not just equal
"""
if a is b:
return True
if a is None or b is None:
return False
if len(a) == len(b):
for a_, b_ in zip(a, b):
if not isSameHConst(a_, b_):
return False
return True
else:
return False
================================================
FILE: hwt/hdl/frameTmpl.py
================================================
from itertools import zip_longest
from math import ceil, floor, inf
from typing import Union, Generator, List, Tuple
from hwt.doc_markers import internal
from hwt.hdl.frameTmplUtils import TransTmplWordIterator, \
ChoicesOfFrameParts
from hwt.hdl.transPart import TransPart
from hwt.hdl.types.array import HArray
from hwt.hdl.types.bits import HBits
from hwt.hdl.types.hdlType import HdlType
from hwt.hdl.types.struct import HStruct
from hwt.pyUtils.arrayQuery import flatten
from pyMathBitPrecise.bit_utils import mask, get_bit_range, set_bit_range
class FrameTmpl(object):
"""
Frame template is metainfomation about data structure, it's the template
of transaction for specific interface
Usuall flow of frame generatig consists of these steps:
1. Describe format of data by HDL type (HStruct, HUnion ...)
2. Convert it to TransTmpl to resolve addresses of each field in structure
3. Split parts of TransTmpl into words
4. Use parts in words to assembly frames
:ivar ~._fieldToTPart: dictionary {HStructField: TransPart} to resolve
this association, None by default, builded when packData
is called and is not builded
:note: others ivars described in __init__
"""
def __init__(self, origin: HdlType,
wordWidth: int,
startBitAddr: int,
endBitAddr: int,
transParts: List[TransPart]):
"""
:param origin: instance of HType (usually HStruct)
from which this FrameTmpl was generated from
:param wordWidth: width of word on interface
where this template should be used
:param startBitAddr: bit offset where this frame starts
:param endBitAddr: bit offset where this frame ends
(bit index of first bit behind this frame)
:param transParts: instances of TransPart which are parts of this frame
"""
self.origin = origin
self.wordWidth = wordWidth
assert startBitAddr <= endBitAddr
self.startBitAddr = startBitAddr
self.endBitAddr = endBitAddr
self.parts = transParts
self._fieldToTPart = None
for p in self.parts:
p.parent = self
assert p.startOfPart >= startBitAddr, (p, startBitAddr)
assert p.endOfPart <= endBitAddr, (p, endBitAddr)
@staticmethod
def framesFromTransTmpl(transaction: 'TransTmpl',
wordWidth: int,
maxFrameLen: Union[int, float]=inf,
maxPaddingWords: Union[int, float]=inf,
trimPaddingWordsOnStart: bool=False,
trimPaddingWordsOnEnd: bool=False) -> Generator[
'FrameTmpl', None, None]:
"""
Convert transaction template into FrameTmpls
:param transaction: transaction template used which are FrameTmpls
created from
:param wordWidth: width of data signal in target interface
where frames will be used
:param maxFrameLen: maximum length of frame in bits,
if exceeded another frame will be created
:param maxPaddingWords: maximum of continual padding words in frame,
if exceed frame is split and words are cut of
:attention: if maxPaddingWords<inf trimPaddingWordsOnEnd
or trimPaddingWordsOnStart has to be True
to decide where padding should be trimmed
:param trimPaddingWordsOnStart: trim padding from start of frame
at word granularity
:param trimPaddingWordsOnEnd: trim padding from end of frame
at word granularity
"""
isFirstInFrame = True
partsPending = False
startOfThisFrame = 0
assert maxFrameLen > 0
assert maxPaddingWords >= 0
if maxPaddingWords < inf:
assert trimPaddingWordsOnStart or trimPaddingWordsOnEnd, \
"Padding has to be cut off somewhere"
it = TransTmplWordIterator(wordWidth)
lastWordI = 0
endOfThisFrame = maxFrameLen
parts = []
for wordI, word in it.groupByWordIndex(transaction, 0):
if wordI * wordWidth >= endOfThisFrame:
# now in first+ word behind the frame
# cut off padding at end of frame
paddingWords = wordI - lastWordI
if trimPaddingWordsOnEnd and paddingWords > maxPaddingWords:
# cut off padding and align end of frame to word
_endOfThisFrame = (lastWordI + 1) * wordWidth
else:
_endOfThisFrame = wordI * wordWidth
yield FrameTmpl(transaction,
wordWidth,
startOfThisFrame,
_endOfThisFrame,
parts)
# prepare for start of new frame
parts = []
isFirstInFrame = True
partsPending = False
# start on new word
startOfThisFrame = _endOfThisFrame
endOfThisFrame = startOfThisFrame + maxFrameLen
lastWordI = wordI
# check if padding at potential end of frame can be cut off
if (not isFirstInFrame
and trimPaddingWordsOnEnd
and wordI - lastWordI > maxPaddingWords + 1):
# there is too much continual padding,
# cut it out and start new frame
_endOfThisFrame = (lastWordI + 1) * wordWidth
yield FrameTmpl(transaction,
wordWidth,
startOfThisFrame,
_endOfThisFrame,
parts)
# prepare for start of new frame
parts = []
isFirstInFrame = True
partsPending = False
# start on new word
lastWordI = wordI - 1
startOfThisFrame = lastWordI * wordWidth
endOfThisFrame = startOfThisFrame + maxFrameLen
if isFirstInFrame:
partsPending = True
isFirstInFrame = False
# cut off padding at start of frame
paddingWords = wordI - lastWordI
if trimPaddingWordsOnStart and paddingWords > maxPaddingWords:
startOfThisFrame += paddingWords * wordWidth
endOfThisFrame = startOfThisFrame + maxFrameLen
# resolve end of this part
parts.extend(word)
lastWordI = wordI
# reminder in "parts" after last iteration
endOfThisFrame = transaction.bitAddrEnd
withPadding = not (trimPaddingWordsOnEnd or trimPaddingWordsOnStart)
if partsPending or (withPadding
and endOfThisFrame != startOfThisFrame):
# cut off padding at end of frame
endOfLastWord = (lastWordI + 1) * wordWidth
if endOfThisFrame < endOfLastWord:
endOfThisFrame = endOfLastWord
else:
paddingWords = it.fullWordCnt(endOfLastWord, endOfThisFrame)
if trimPaddingWordsOnEnd and paddingWords > maxPaddingWords:
endOfThisFrame -= paddingWords * wordWidth
# align end of frame to word
endOfThisFrame = min(startOfThisFrame +
maxFrameLen, endOfThisFrame)
yield FrameTmpl(transaction,
wordWidth,
startOfThisFrame,
endOfThisFrame,
parts)
parts = []
startOfThisFrame = endOfThisFrame
# final padding on the end
while withPadding and startOfThisFrame < transaction.bitAddrEnd:
endOfThisFrame = min(startOfThisFrame +
maxFrameLen, transaction.bitAddrEnd)
yield FrameTmpl(transaction,
wordWidth,
startOfThisFrame,
endOfThisFrame,
[])
startOfThisFrame = endOfThisFrame
@internal
def _wordIndx(self, addr: int):
"""
convert bit address to index of word where this address is
"""
return floor(addr / self.wordWidth)
def getWordCnt(self):
"""
Get count of words in this frame
"""
return ceil((self.endBitAddr - self.startBitAddr) / self.wordWidth)
def walkWords(self, showPadding: bool=False)\
-> Generator[Tuple[int, List[Union[TransPart, ChoicesOfFrameParts]]], None, None]:
"""
Walk enumerated words in this frame
:attention: not all indexes has to be present, only words
with items will be generated when not showPadding
:param showPadding: padding TransParts are also present
:return: generator of tuples (wordIndex, list of TransParts
in this word)
"""
wIndex = 0
lastEnd = self.startBitAddr
parts: List[TransPart] = []
for p in self.parts:
end = p.startOfPart
if showPadding and end != lastEnd:
# insert padding before data
while end != lastEnd:
assert end >= lastEnd, (end, lastEnd)
endOfWord = ceil(
(lastEnd + 1) / self.wordWidth) * self.wordWidth
endOfPadding = min(endOfWord, end)
_p = TransPart(self, None, False, lastEnd, endOfPadding, 0)
parts.append(_p)
if endOfPadding >= endOfWord:
yield (wIndex, parts)
wIndex += 1
parts = []
lastEnd = endOfPadding
if self._wordIndx(lastEnd) != self._wordIndx(p.startOfPart):
# if input data continues to a next word, yield current word
# and start processing next one
yield (wIndex, parts)
wIndex += 1
parts = []
lastEnd = p.endOfPart
parts.append(p)
lastEnd = p.endOfPart
if lastEnd % self.wordWidth == 0:
# if we can not add anything to this word,
# yield it directly and continue on next word
yield (wIndex, parts)
wIndex += 1
parts = []
if showPadding and (parts
or lastEnd != self.endBitAddr
or lastEnd % self.wordWidth != 0):
# align end to end of last word
end = ceil(self.endBitAddr / self.wordWidth) * self.wordWidth
# padding is non removable if it is part of data
# and it is removable if it was generated by frame alignment
endOfNonRemovablePadding = self.origin.bitAddrEnd
while end != lastEnd:
assert end >= lastEnd, (end, lastEnd)
endOfWord = ((lastEnd // self.wordWidth) + 1) * self.wordWidth
endOfPadding = min(endOfWord, end)
if lastEnd < endOfNonRemovablePadding:
endOfPadding = min(endOfPadding, endOfNonRemovablePadding)
can_be_removed = False
else:
can_be_removed = True
_p = TransPart(self, None, can_be_removed,
lastEnd, endOfPadding, 0)
_p.parent = self
parts.append(_p)
if endOfPadding >= endOfWord:
yield (wIndex, parts)
wIndex += 1
parts = []
lastEnd = endOfPadding
if parts:
# in the case end of frame is not aligned to end of word
yield (wIndex, parts)
@staticmethod
def fieldToDataDict(dtype, data, res):
return FrameTmpl._fieldToDataDict(dtype, (dtype,), data, res)
@staticmethod
def _fieldToDataDict(dtype, path, data, res):
"""
Construct dictionary {StructField:value} for faster lookup of values
for fields
"""
# assert data is None or isinstance(data, dict)
for f in dtype.fields:
try:
fVal = data[f.name]
except KeyError:
fVal = None
new_path = (*path, f)
if isinstance(f.dtype, HBits):
if fVal is not None:
assert isinstance(fVal, int)
res[new_path] = fVal
elif isinstance(f.dtype, HStruct):
if fVal:
FrameTmpl._fieldToDataDict(f.dtype, new_path, fVal, res)
elif isinstance(f.dtype, HArray):
if fVal:
# assert isinstance(fVal, class_or_tuple)
res[new_path] = fVal
return res
def packData(self, data):
"""
Pack data into list of BitsVal of specified dataWidth
:param data: dict of values for struct fields {fieldName: value}
:return: list of BitsVal which are representing values of words
"""
typeOfWord = HBits(self.wordWidth, None)
fieldToVal = self._fieldToTPart
if fieldToVal is None:
fieldToVal = self._fieldToTPart = self.fieldToDataDict(
self.origin.dtype,
data,
{})
for _, transParts in self.walkWords(showPadding=True):
# build a single data word
actualVldMask = 0
actualVal = 0
for tPart in transParts:
high, low = tPart.getBusWordBitRange()
fhigh, flow = tPart.getFieldBitRange()
if not tPart.isPadding:
val = fieldToVal.get(tPart.tmpl.origin, None)
else:
val = None
if val is None:
newBits = 0
vld = 0
else:
newBits = get_bit_range(val, flow, fhigh - flow)
vld = mask(high - low)
actualVal = set_bit_range(actualVal, low, high - low, newBits)
actualVldMask = set_bit_range(actualVldMask, low, high - low, vld)
v = typeOfWord.getConstCls()(typeOfWord, actualVal,
actualVldMask)
yield v
@internal
def __repr__getName(self, transPart: TransPart, fieldWidth: int):
"""
Get name string for a field
"""
if transPart.isPadding:
return "X" * fieldWidth
else:
path = transPart.tmpl.getFieldPath()
names = []
for p in path:
if isinstance(p, int):
names.append(f"[{p:d}]")
else:
if names:
names.append(f".{p:s}")
else:
names.append(p)
return "".join(names)
@internal
def __repr__word(self,
index: int,
width: int,
padding: int,
transParts: List[TransPart]):
buff = [f"{index: <{padding}}|", ]
DW = self.wordWidth
partsWithChoice = []
endAlignment = transParts[-1].endOfPart % DW
if endAlignment:
# -1 for ending |
percentOfWidth = (DW - endAlignment) / DW
# -1 for ending |
fieldWidth = max(0, int(percentOfWidth * width) - 1)
assert fieldWidth >= 0
s = '%s|' % ("^" * fieldWidth)
buff.append(s)
for tp in reversed(transParts):
percentOfWidth = tp.bit_length() / DW
# -1 for ending |
fieldWidth = max(0, int(percentOfWidth * width) - 1)
assert fieldWidth >= 0
# percentOffset = (tp.inFrameBitAddr % DW) / DW
# offset = int(percentOffset * width)
if isinstance(tp, ChoicesOfFrameParts):
name = "<union>"
partsWithChoice.append(tp)
else:
name = self.__repr__getName(tp, fieldWidth)
buff.append(f'{name: ^{fieldWidth}}|')
return ("".join(buff), partsWithChoice)
def __repr__(self, scale=1):
buff = []
s = f"<{self.__class__.__name__:s} start:{self.startBitAddr:d}, end:{self.endBitAddr:d}"
buff.append(s)
padding = 5
DW = self.wordWidth
width = int(DW * scale)
buff.append(
'{0: <{padding}}{1: <{halfLineWidth}}{2: >{halfLineWidth}}'.format(
"", DW - 1, 0, padding=padding, halfLineWidth=width // 2))
line = '{0: <{padding}}{1:-<{lineWidth}}'.format(
"", "", padding=padding, lineWidth=width + 1)
buff.append(line)
for w, transParts in self.walkWords(showPadding=True):
wStr, partsWithChoice = self.__repr__word(
w, width, padding, transParts)
buff.append(wStr)
while partsWithChoice:
for parts in zip_longest(*partsWithChoice):
parts = list(flatten(parts, level=1))
wStr, _partsWithChoice = self.__repr__word(
w, width, padding, parts)
buff.append(wStr)
partsWithChoice = _partsWithChoice
buff.append(line)
buff.append(">")
return "\n".join(buff)
================================================
FILE: hwt/hdl/frameTmplUtils.py
================================================
from typing import Tuple
from hwt.doc_markers import internal
from hwt.hdl.transPart import TransPart
from hwt.hdl.transTmpl import OneOfTransaction
@internal
def iterSort(iterators, cmpFn):
"""
Sort items from iterators(generators) by alwas selecting item
with lowest value (min first)
:return: generator of tuples (origin index, item) where origin index
is index of iterator in "iterators" from where item commes from
"""
actual = []
_iterators = []
for i, it in enumerate(iterators):
try:
a = next(it)
_iterators.append((i, it))
actual.append(a)
except StopIteration:
continue
while True:
if not _iterators:
return
elif len(_iterators) == 1:
originIndex, it = _iterators[0]
yield originIndex, actual[0]
for item in it:
yield originIndex, item
return
# select minimum and iterator from where it comes from
minimum = None
minimumIndex = None
secondMin = None
for i, val in enumerate(actual):
skipSecMinCheck = False
if minimum is None:
minimum = val
minimumIndex = i
elif cmpFn(val, minimum):
secondMin = minimum
minimum = val
minimumIndex = i
skipSecMinCheck = True
elif not skipSecMinCheck and (
secondMin is None or cmpFn(val, secondMin)):
secondMin = val
actualI, actualIt = _iterators[minimumIndex]
while not cmpFn(secondMin, minimum):
yield (actualI, minimum)
try:
minimum = next(actualIt)
except StopIteration:
minimum = None
break
# consume from actual iterator while
if minimum is None:
del _iterators[minimumIndex]
del actual[minimumIndex]
else:
# minimum is not minimum anymore
actual[minimumIndex] = minimum
class TransPartGroup(list):
"""
Abstract parent class for groups of TransParts
"""
def setIsLast(self, val: bool) -> None:
self._isLast = val
def isLastPart(self) -> bool:
"""
:return: True if this part is last in parts derived from original field
else False
"""
return self._isLast
def getBusWordBitRange(self) -> Tuple[int, int]:
"""
:return: bit range which contains data of this part on bus data signal
"""
offset = self.startOfPart % self.parent.wordWidth
return (offset + self.bit_length(), offset)
def bit_length(self):
return self.endOfPart - self.startOfPart
def __repr__(self):
return "<%s %s>" % (self.__class__.__name__, list.__repr__(self))
class ChoicesOfFrameParts(TransPartGroup):
"""
List of ChoiceOfFrameParts
One of ChoiceOfFrameParts is used to represent the word, item depends
on context
:ivar ~.origin: OneOfTransaction instance
:ivar ~.startOfPart: bit addr of start of this group of frame parts
:ivar ~.endOfPart: bit addr of end of this group of frame parts
:ivar ~._isLast: flag which means this is the last part of original union
"""
def __init__(self, startOfPart: int, origin: OneOfTransaction):
self.origin = origin
self.startOfPart = startOfPart
self.endOfPart = None
self._isLast = False
super(ChoicesOfFrameParts, self).__init__()
def resolveEnd(self):
end = self.startOfPart
for items in self:
if items:
end = max(end, max(itm.endOfPart for itm in items))
self.endOfPart = end
class ChoiceOfFrameParts(list):
"""
:ivar ~.origin: ChoicesOfFrameParts instance
:ivar ~.tmpl: TransTmpl which was item generated from
"""
def __init__(self, origin, tmpl):
self.origin = origin
self.tmpl = tmpl
def __repr__(self):
return "<%s %s>" % (self.__class__.__name__, list.__repr__(self))
def groupIntoChoices(splitsOnWord, wordWidth: int, origin: OneOfTransaction):
"""
:param splitsOnWord: list of lists of parts (fields splited on word
boundaries)
:return: generators of ChoicesOfFrameParts for each word
which are not crossing word boundaries
"""
def cmpWordIndex(a, b):
return a.startOfPart // wordWidth < b.startOfPart // wordWidth
actual = None
itCnt = len(splitsOnWord)
for i, item in iterSort(splitsOnWord, cmpWordIndex):
_actualW = item.startOfPart // wordWidth
if actual is None:
# first pass
actual = ChoicesOfFrameParts(item.startOfPart, origin)
actual.extend(
ChoiceOfFrameParts(actual,
origin.possibleTransactions[_i])
for _i in range(itCnt))
actualW = _actualW
elif _actualW > actualW:
actual.resolveEnd()
yield actual
actual = ChoicesOfFrameParts(item.startOfPart, origin)
actual.extend(
ChoiceOfFrameParts(actual,
origin.possibleTransactions[_i])
for _i in range(itCnt))
actualW = _actualW
actual[i].append(item)
if actual is not None:
actual.setIsLast(True)
actual.resolveEnd()
yield actual
class TransTmplWordIterator():
"""
Iterator which reinterprets any structure
as generator of bits of specified width
"""
def __init__(self, wordWidth):
self.wordWidth = wordWidth
def fullWordCnt(self, start: int, end: int):
"""Count of complete words between two addresses
"""
assert end >= start, (start, end)
gap = max(0, (end - start) - (start % self.wordWidth))
return gap // self.wordWidth
def groupByWordIndex(self, transaction: 'TransTmpl', offset: int):
"""
Group transaction parts splited on words to words
:param transaction: TransTmpl instance which parts
should be grupped into words
:return: generator of tuples (wordIndex, list of transaction parts
in this word)
"""
actualW = None
partsInWord = []
wordWidth = self.wordWidth
for item in self.splitOnWords(transaction, offset):
_actualW = item.startOfPart // wordWidth
if actualW is None:
actualW = _actualW
partsInWord.append(item)
elif _actualW > actualW:
yield (actualW, partsInWord)
actualW = _actualW
partsInWord = [item, ]
else:
partsInWord.append(item)
if partsInWord:
yield (actualW, partsInWord)
@internal
def splitOnWords(self, transaction, addrOffset=0):
"""
:return: generator of TransPart instance
"""
wordWidth = self.wordWidth
end = addrOffset
for tmp in transaction.HwIO_walkFlatten(offset=addrOffset):
if isinstance(tmp, OneOfTransaction):
# unions
split = [self.splitOnWords(ch, end)
for ch in tmp.possibleTransactions]
yield from groupIntoChoices(split, wordWidth, tmp)
end = addrOffset + tmp.possibleTransactions[0].bitAddrEnd
else:
# constant size types
(base, end), tmpl = tmp
startOfPart = base
while startOfPart != end:
wordIndex = startOfPart // wordWidth
endOfWord = (wordIndex + 1) * wordWidth
endOfPart = min(endOfWord, end)
inFieldOffset = startOfPart - base
yield TransPart(self, tmpl, False, startOfPart, endOfPart,
inFieldOffset)
startOfPart = endOfPart
================================================
FILE: hwt/hdl/hdlObject.py
================================================
from io import StringIO
from hdlConvertorAst.translate.common.name_scope import NameScope
class HdlObject():
"""
Base Hdl object class for object which can be directly serialized
to target HDL language
"""
def __repr__(self):
from hwt.serializer.hwt import HwtDebugSerializer
name_scope = NameScope(None, "debug", False, debug=True)
to_hdl = HwtDebugSerializer.TO_HDL_AST(name_scope)
to_hdl.debug = True
hdl = to_hdl.as_hdl(self)
buff = StringIO()
# import sys
# buff = sys.stdout
ser = HwtDebugSerializer.TO_HDL(buff)
ser.visit_iHdlObj(hdl)
return buff.getvalue()
================================================
FILE: hwt/hdl/operator.py
================================================
from typing import Generator, Union, Tuple, Optional, Set, Sequence
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.hdlObject import HdlObject
from hwt.hdl.operatorDefs import isEventDependentOp, HOperatorDef
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.hdl.types.hdlType import HdlType
from hwt.pyUtils.arrayQuery import arr_all
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal, RtlSignalBase, \
OperatorCaheKeyType
@internal
def getCtxFromOps(operands: Sequence):
for o in operands:
if isinstance(o, RtlSignalBase):
return o._rtlCtx
return None # case for casts of constants
def isConst(item: Union[HConst, RtlSignalBase]):
"""
:return: True if expression is constant
"""
return isinstance(item, HConst) or item._const
class HOperatorNode(HdlObject):
"""
Class of operator in expression tree
:ivar ~.operands: list of operands
:ivar ~.evalFn: function to evaluate this operator
:ivar ~.operator: HOperatorDef instance
:ivar ~.result: result signal of this operator
"""
def __init__(self, operator: HOperatorDef,
operands: Tuple[Union[RtlSignalBase, HConst]]):
self.operands = tuple(operands)
self.operator = operator
self.result: Optional[RtlSignal] = None
@internal
def staticEval(self):
"""
Recursively statistically evaluate result of this operator
"""
for o in self.operands:
o.staticEval()
self.result._val = self.operator.eval(self, simulator=None)
@internal
def _walk_sensitivity(self, casualSensitivity: Set[RtlSignal], seen: Set[RtlSignal], ctx: SensitivityCtx):
"""
:see: :meth:`hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity`
"""
seen.add(self)
if isEventDependentOp(self.operator):
if ctx.contains_ev_dependency:
assert self in ctx, "has to have only a single clock signal"
ctx.contains_ev_dependency = True
ctx.append(self)
else:
# walk source of signal
for operand in self.operands:
if operand not in seen:
operand._walk_sensitivity(casualSensitivity, seen, ctx)
@internal
def _walk_public_drivers(self, seen: set) -> Generator["RtlSignal", None, None]:
"""
Walk all non hidden signals in an expression
"""
for op in self.operands:
if not isinstance(op, HConst) and op not in seen:
seen.add(op)
yield from op._walk_public_drivers(seen)
@internal
@staticmethod
def withRes(opDef: HOperatorDef, operands: Sequence[Union[RtlSignalBase, HConst]], resT: HdlType):
"""
Create operator with result signal
:ivar ~.resT: data type of result signal
:ivar ~.outputs: iterable of signals which are outputs
from this operator
"""
# try return existing operator result
for i, o in enumerate(operands):
if isinstance(o, RtlSignalBase):
if i == 0:
k = (opDef, i, *operands[1:])
else:
k = (opDef, i, *operands[:i], *operands[i + 1:])
try:
return o._usedOps[k]
except KeyError:
pass
break
# instantiate new HOperatorNode
op = HOperatorNode(opDef, operands)
out: RtlSignal = resT.getRtlSignalCls()(getCtxFromOps(operands), None, resT)
out._const = arr_all(op.operands, isConst)
out._rtlDrivers.append(op)
out._rtlObjectOrigin = op
op.result = out
# Register potential signals to drivers/endpoints
first_signal = True
for i, o in enumerate(op.operands):
if isinstance(o, RtlSignalBase):
o._rtlEndpoints.append(op)
if first_signal:
# register operator in _usedOps operator cache
if i == 0:
k = (opDef, i, *operands[1:])
else:
k = (opDef, i, *operands[:i], *operands[i + 1:])
o._usedOps[k] = out
o._usedOpsAlias[k] = {k, }
first_signal = False
else:
assert isinstance(o, HConst), (
"HOperatorNode operands can be only signal or values got:", o)
# pre-compute constant signal if all used types support it
if out._const:
precompute = resT._PRECOMPUTE_CONSTANT_SIGNALS
for o in operands:
precompute &= o._dtype._PRECOMPUTE_CONSTANT_SIGNALS
if not precompute:
break
if precompute:
# if this signal is constant precompute its value
out.staticEval()
return out
@internal
def _replace_input(self, inp: RtlSignal, replacement: RtlSignal):
"""
Replace operand signal (non-recursively)
:attention: costly operation because all records in operand cache for all inputs may be potentially updated
"""
assert self.result._rtlCtx is replacement._rtlCtx, self
newOperands = []
modified = False
for op in self.operands:
if op is inp:
modified = True
newOperands.append(replacement)
else:
newOperands.append(op)
assert modified, self
res = self.result
for op in self.operands:
if isinstance(op, RtlSignal):
op: RtlSignal
for k, v in tuple(op._usedOps.items()):
k: OperatorCaheKeyType
if v is res:
if op is inp:
# this operand is originally replaced "inp" the cache key must be transfered
# from original operand to a new replacement
op._usedOps.pop(k)
replacement._usedOps[k] = v
aliases = op._usedOpsAlias.pop(k)
aliases.remove(k)
_aliases = None
for a in aliases:
_aliases = replacement._usedOpsAlias.get(a, None)
if _aliases is not None:
break
if _aliases is None:
_aliases = {k, }
else:
_aliases.add(k)
replacement._usedOpsAlias[k] = _aliases
else:
# some other operand is originally replaced "inp" the cache key must be updated
op._usedOps.pop(k)
kNew = (*k[0:2], *(replacement if _op is inp else _op for _op in k[2:]))
op._usedOps[kNew] = v
aliases = op._usedOpsAlias.pop(k)
aliases.remove(k)
aliases.add(kNew)
op._usedOpsAlias[kNew] = aliases
break # _usedOps/_usedOpsAlias is relevant only for the first operand
self.operands = tuple(newOperands)
inp._rtlEndpoints.discard(self)
replacement._rtlEndpoints.append(self)
@internal
def _destroy(self):
self.result._rtlDrivers.remove(self)
operands = self.operands
first_op_sig = True
for i, o in enumerate(operands):
if isinstance(o, RtlSignalBase):
# discard because same signal can be on multiple places in operand list
o._rtlEndpoints.discard(self)
if first_op_sig:
# clean all references on this operator instance from RtlSignal._usedOps operator cache
_k = (self.operator, i, *operands[:i], *operands[i + 1:])
for k in o._usedOpsAlias[_k]:
res = o._usedOps.pop(k)
assert res is self.result, (self.result._rtlCtx.parent, "HOperatorNode was not stored properly in operand cache", res, self.result, o)
first_op_sig = False
self.result._rtlObjectOrigin = None
self.result = None
self.operands = None
self.operator = None
================================================
FILE: hwt/hdl/operatorDefs.py
================================================
from operator import floordiv, add, sub, inv, mul, ne, and_, or_, \
xor, gt, ge, lt, le, getitem, neg
from typing import Optional
from hdlConvertorAst.hdlAst._expr import HdlOpType
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.types.defs import INT, SLICE
def _getVal(v):
while not isinstance(v, HConst):
v = v._val
return v
class HOperatorDef():
"""
Operator definition
:ivar ~.id: name of operator
:ivar ~._evalFn: function which evaluates operands
:ivar ~.hdlConvertoAstOp: an operator which is used for export to hdlConvertoAst library
"""
def __init__(self, evalFn, allowsAssignTo=False, idStr:Optional[str]=None, hdlConvertoAstOp: Optional[HdlOpType]=None):
self.id = idStr # assigned automatically in HwtOps
self._evalFn = evalFn
self.allowsAssignTo = allowsAssignTo
self.hdlConvertoAstOp = hdlConvertoAstOp
def __eq__(self, other):
return type(self) == type(other) and self.id == other.id
@internal
def __hash__(self):
return hash(self.id)
def eval(self, operator, simulator=None):
"""Load all operands and process them by self._evalFn"""
operands = [_getVal(o) for o in operator.operands]
return self._evalFn(*operands)
def __repr__(self):
return f"<{self.__class__.__name__:s} {self.id:s}>"
def isEventDependentOp(operator):
return operator in (HwtOps.RISING_EDGE, HwtOps.FALLING_EDGE)
def onRisingEdgeFn(a):
return a._onRisingEdge()
def onFallingEdgeFn(a):
return a._onFallingEdge()
def dotOpFn(a, name):
return getattr(a, name)
# [TODO] downto / to are relict of vhdl and should be replaced with slice
def downtoFn(a: int, b: int):
return SLICE.from_py(slice(a, b, -1))
def toFn(a: int, b: int):
return SLICE.from_py(slice(a, b, 1))
def concatFn(a: "AnyHBitsValue", b: "AnyHBitsValue") -> "AnyHBitsValue":
return a._concat(b)
def power(base, exp):
return base ** exp
def eqFn(a, b):
return a._eq(b)
def ternaryFn(cond: "AnyHBitsValue", vTrue, vFalse):
return cond._ternary(vTrue, vFalse)
def callFn(fn: "HdlFunctionDef", *operands, **kwargs):
return fn(*operands, **kwargs)
def bitsToIntFn(a: "AnyHBitsValue"):
return a._auto_cast(INT)
def intToBitsFn(a: "AnyHBitsValue", t: "HdlType"):
return a._auto_cast(t)
def bitsAsSignedFn(a: "AnyHBitsValue"):
return a._signed()
def bitsAsUnsignedFn(a: "AnyHBitsValue"):
return a._unsigned()
def bitsAsVec(a: "AnyHBitsValue"):
return a._vec()
def zextFn(a: "AnyHBitsValue", newWidth: int):
return a._zext(newWidth)
def sextFn(a: "AnyHBitsValue", newWidth: int):
return a._sext(newWidth)
def truncFn(a: "AnyHBitsValue", newWidth: int):
return a._trunc(newWidth)
class HwtOps():
"""
:attention: Remember that and operator "and" is & and "or" is \\|, "and"
and "or" can not be used because they can not be overloaded
:attention: These are operators of internal AST,
they are not equal to verilog or vhdl operators
"""
RISING_EDGE = HOperatorDef(onRisingEdgeFn) # unnecessary
FALLING_EDGE = HOperatorDef(onFallingEdgeFn) # unnecessary
MINUS_UNARY = HOperatorDef(neg)
DIV = HOperatorDef(floordiv)
UDIV = HOperatorDef(lambda a, b: a._unsigned() // b._unsigned())
SDIV = HOperatorDef(lambda a, b: a._signed() // b._signed())
ADD = HOperatorDef(add)
SUB = HOperatorDef(sub)
POW = HOperatorDef(power)
# see https://stackoverflow.com/questions/25848879/difference-between-mod-and-rem-operators-in-vhdl
UREM = HOperatorDef(lambda a, b: a._unsigned() % b._unsigned()) # "rem operator"
SREM = HOperatorDef(lambda a, b: a._signed() % b._signed()) # "modulo operator"
# MUL bit_length and sign of src0, src1 and dst is the same
# sign/unsign variant with double result width is recognized from sext/zext of operands in final phases of serialization
MUL = HOperatorDef(mul)
NOT = HOperatorDef(inv, allowsAssignTo=True)
XOR = HOperatorDef(xor)
AND = HOperatorDef(and_)
OR = HOperatorDef(or_)
DOT = HOperatorDef(dotOpFn, allowsAssignTo=True)
DOWNTO = HOperatorDef(downtoFn)
TO = HOperatorDef(toFn)
CONCAT = HOperatorDef(concatFn, allowsAssignTo=True)
# :note: SEXT, ZEXT, TRUNC are redundant as it can be implemented using INDEX/CONCAT however they exist
# from performance reasons as patern match for them would be very common during optimizations and
# specific evaluation functions may be significantly faster
# :note: normalization rules:
# * SEXT, ZEXT is prefered over concatenation
# * sext(a:1b) should be used internally instead of concat(a, a)
# * TRUNC is prefered over index with a single exception
# * x[0] should be used internally instead of trunc(x, 1)
SEXT = HOperatorDef(sextFn) # sign extension of bit vector to larger width
ZEXT = HOperatorDef(zextFn) # zero extension of bit vector to larger width
TRUNC = HOperatorDef(truncFn, allowsAssignTo=True) # truncate width of bit vector
EQ = HOperatorDef(eqFn)
NE = HOperatorDef(ne)
# :note: for compare operands without U/S the info about sign is stored in type of operands
# for U/S variant the signed flag in the type is ignored and signines is forced by operator definition
GT = HOperatorDef(gt)
GE = HOperatorDef(ge)
LT = HOperatorDef(lt)
LE = HOperatorDef(le)
ULE = HOperatorDef(lambda a, b: a._unsigned() <= b._unsigned())
ULT = HOperatorDef(lambda a, b: a._unsigned() < b._unsigned())
UGT = HOperatorDef(lambda a, b: a._unsigned() > b._unsigned())
UGE = HOperatorDef(lambda a, b: a._unsigned() >= b._unsigned())
SLE = HOperatorDef(lambda a, b: a._signed() <= b._signed())
SLT = HOperatorDef(lambda a, b: a._signed() < b._signed())
SGT = HOperatorDef(lambda a, b: a._signed() > b._signed())
SGE = HOperatorDef(lambda a, b: a._signed() >= b._signed())
# :note: INDEX is used for arrays and also for bit vectors
INDEX = HOperatorDef(getitem, allowsAssignTo=True)
TERNARY = HOperatorDef(ternaryFn)
CALL = HOperatorDef(callFn)
BitsAsSigned = HOperatorDef(bitsAsSignedFn, allowsAssignTo=True)
BitsAsUnsigned = HOperatorDef(bitsAsUnsignedFn, allowsAssignTo=True)
BitsAsVec = HOperatorDef(bitsAsVec, allowsAssignTo=True)
for a_name in dir(HwtOps):
o = getattr(HwtOps, a_name)
if isinstance(o, HOperatorDef):
o.id = a_name
CAST_OPS = (HwtOps.BitsAsVec, HwtOps.BitsAsSigned, HwtOps.BitsAsUnsigned)
BITWISE_OPS = (HwtOps.NOT, HwtOps.XOR, HwtOps.AND, HwtOps.OR)
COMPARE_OPS = (
HwtOps.EQ,
HwtOps.NE,
HwtOps.GT,
HwtOps.GE,
HwtOps.LT,
HwtOps.LE,
HwtOps.ULE,
HwtOps.ULT,
HwtOps.UGT,
HwtOps.UGE,
HwtOps.SLE,
HwtOps.SLT,
HwtOps.SGT,
HwtOps.SGE,
)
# change of compare operator on operand order swap
CMP_OP_SWAP = {
HwtOps.EQ: HwtOps.EQ, # (a == b) == (b == a)
HwtOps.NE: HwtOps.NE, # (a != b) == (b != a)
HwtOps.GT: HwtOps.LT, # (a > b) == (b < a)
HwtOps.GE: HwtOps.LE, # (a >= b) == (b <= a)
HwtOps.LT: HwtOps.GT, # (a < b) == (b > a)
HwtOps.LE: HwtOps.GE, # (a <= b) == (b >= a)
HwtOps.UGT: HwtOps.ULT,
HwtOps.UGE: HwtOps.ULE,
HwtOps.ULT: HwtOps.UGT,
HwtOps.ULE: HwtOps.UGE,
HwtOps.SGT: HwtOps.SLT,
HwtOps.SGE: HwtOps.SLE,
HwtOps.SLT: HwtOps.SGT,
HwtOps.SLE: HwtOps.SGE,
}
CMP_OPS_NEG = {
HwtOps.EQ: HwtOps.NE,
HwtOps.NE: HwtOps.EQ,
HwtOps.GT: HwtOps.LE,
HwtOps.GE: HwtOps.LT,
HwtOps.LT: HwtOps.GE,
HwtOps.LE: HwtOps.GT,
HwtOps.UGT: HwtOps.ULE,
HwtOps.UGE: HwtOps.ULT,
HwtOps.ULT: HwtOps.UGE,
HwtOps.ULE: HwtOps.UGT,
HwtOps.SGT: HwtOps.SLE,
HwtOps.SGE: HwtOps.SLT,
HwtOps.SLT: HwtOps.SGE,
HwtOps.SLE: HwtOps.SGT,
}
# always commutative operators for which order of operands does not matter
ALWAYS_COMMUTATIVE_OPS = (HwtOps.EQ, HwtOps.NE, HwtOps.XOR, HwtOps.AND, HwtOps.OR, HwtOps.ADD, HwtOps.MUL)
# always commutative associative operators for which order of operands in expression tree does not matter
ALWAYS_ASSOCIATIVE_COMMUTATIVE_OPS = (HwtOps.XOR, HwtOps.AND, HwtOps.OR, HwtOps.ADD, HwtOps.MUL)
EVENT_OPS = (HwtOps.RISING_EDGE, HwtOps.FALLING_EDGE)
================================================
FILE: hwt/hdl/operatorUtils.py
================================================
from typing import Union, Tuple
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.portItem import HdlPortItem
from hwt.hdl.statements.statement import HdlStatement, SignalReplaceSpecType
from hwt.mainBases import RtlSignalBase
from hwt.synthesizer.rtlLevel.exceptions import SignalDriverErr
# from hwt.hdl.operator import Operator
@internal
def _replace_input_in_expr(expr: Union[RtlSignalBase, HConst], toReplace: SignalReplaceSpecType) -> RtlSignalBase:
"""
:return: newly rewritten expression with the subexpression replaced, True if changed else False
"""
if isinstance(toReplace, dict):
replacement = toReplace.get(expr, None)
else:
_toReplace, replacement = toReplace
if expr is not _toReplace:
replacement = None
if replacement is not None:
return replacement, True
elif isinstance(expr, RtlSignalBase) and expr._isUnnamedExpr:
op = expr._rtlObjectOrigin
if op is None:
try:
op = expr.singleDriver()
except SignalDriverErr:
return expr, False
if isinstance(op, (HdlPortItem, HdlStatement)):
return expr, False
# assert isinstance(op, Operator), op
operandChanged = False
ops = []
for o in op.operands:
_o, _change = _replace_input_in_expr(o, toReplace)
ops.append(_o)
operandChanged |= _change
if operandChanged:
res = op.operator._evalFn(*ops)
return res, True
else:
return expr, False
else:
return expr, False
@internal
def replace_input_in_expr(topStatement: "HdlStatement",
parentStm: "HdlStatement",
expr: Union[RtlSignalBase, HConst],
toReplace: SignalReplaceSpecType,
# maybeDisconnectedSignals: SetList[RtlSignalBase]
) -> Tuple[RtlSignalBase, bool]:
"""
:return: tuple (newExpression, True if expr is toReplace and should be replaced else False)
"""
res, didContainExpr = _replace_input_in_expr(expr, toReplace)
if didContainExpr:
# maybeDisconnectedSignals.append(expr)
if not isinstance(expr, HConst):
expr._rtlEndpoints.discard(topStatement)
if not isinstance(res, HConst):
res._rtlEndpoints.append(topStatement)
return res, True
else:
assert res is expr
return expr, False
================================================
FILE: hwt/hdl/portItem.py
================================================
from hwt.constants import DIRECTION
from hwt.doc_markers import internal
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.hdl.statements.statement import HwtSyntaxError
from hwt.hdl.types.hdlType import HdlType
from hwt.hdl.variables import HdlSignalItem
from hwt.mainBases import RtlSignalBase
class HdlPortItem():
"""
HDL entity/module/component port item
Used to split signal paths on component boundary.
:note: src/dst are named based on input output signal direction
both dst and src can be parent/component signal, it depends on direction
"""
def __init__(self, name: str, direction: DIRECTION, dtype: HdlType, module: "HwModule"):
self.name = name
self.module = module
self._dtype = dtype
self.direction = direction
self.src = None
self.dst = None
@classmethod
def fromSignal(cls, s: HdlSignalItem, component, d: DIRECTION):
return cls(s._name, d, s._dtype, component)
@internal
def connectOuterSig(self, signal: RtlSignalBase):
"""
Connect to port item on submodule
"""
if self.direction == DIRECTION.IN:
if self.src is not None:
raise HwtSyntaxError(
"Port %s is already associated with %r"
% (self.name, self.src))
self.src = signal
signal._rtlEndpoints.append(self)
elif self.direction == DIRECTION.OUT:
if self.dst is not None:
raise HwtSyntaxError(
"Port %s is already associated with %r"
% (self.name, self.dst))
self.dst = signal
signal._rtlDrivers.append(self)
else:
raise NotImplementedError(self)
signal._hidden = False
signal._rtlCtx.subHwModules.add(self.module)
@internal
def connectInternSig(self, signal):
"""
Connect signal from internal side of of this component to this port.
"""
if self.direction == DIRECTION.OUT:
if self.src is not None:
raise HwtSyntaxError(
"Port %s is already associated with signal %s"
% (self.name, str(self.src)))
self.src = signal
self.src._rtlEndpoints.append(self)
elif self.direction == DIRECTION.IN:
if self.dst is not None:
raise HwtSyntaxError(
"Port %s is already associated with signal %s"
% (self.name, str(self.dst)))
self.dst = signal
self.dst._rtlDrivers.append(self)
else:
raise NotImplementedError(self.direction)
@internal
def getInternSig(self):
"""
return signal inside module which has this port
"""
d = self.direction
if d == DIRECTION.IN:
return self.dst
elif d == DIRECTION.OUT:
return self.src
else:
raise NotImplementedError(d)
@internal
def getOuterSig(self):
"""
return signal inside module which has this port
"""
d = self.direction
if d == DIRECTION.OUT:
return self.dst
elif d == DIRECTION.IN:
return self.src
else:
raise NotImplementedError(d)
@internal
def _walk_sensitivity(self, casualSensitivity: set, seen: set, ctx: SensitivityCtx):
"""
:see: :meth:`hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity`
"""
return
yield
def __repr__(self):
return f"<{self.__class__.__name__:s} src:{self.src}, dst:{self.dst}>"
================================================
FILE: hwt/hdl/sensitivityCtx.py
================================================
from hwt.doc_markers import internal
from hwt.pyUtils.setList import SetList
class SensitivityCtx(SetList):
"""
Sensitivity list used for resolution of sensitivity for statement instances
:ivar ~.contains_ev_dependency: True if this contains event dependent
sensitivity
"""
def __init__(self, initSeq=None):
SetList.__init__(self, initSeq=initSeq)
self.contains_ev_dependency = False
@internal
def extend(self, items):
SetList.extend(self, items)
if isinstance(items, SensitivityCtx):
self.contains_ev_dependency |= items.contains_ev_dependency
@internal
def clear(self):
SetList.clear(self)
self.contains_ev_dependency = False
================================================
FILE: hwt/hdl/statements/__init__.py
================================================
================================================
FILE: hwt/hdl/statements/assignmentContainer.py
================================================
from typing import Tuple, List, Dict, Union, Optional, Generator
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.constUtils import isSameHConst, areSameHConsts
from hwt.hdl.operatorUtils import replace_input_in_expr
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.hdl.statements.statement import HdlStatement, SignalReplaceSpecType
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.mainBases import RtlSignalBase
from hwt.pyUtils.setList import SetList
from hwt.pyUtils.typingFuture import override
class HdlAssignmentContainer(HdlStatement):
"""
Assignment container
:ivar ~.src: source
:ivar ~.dst: destination signal
:ivar ~.indexes: description of index selector on dst
(list of Index/Slice objects) (f.e. [0, 1] means dst[0][1])
:cvar __instCntr: counter used for generating instance ids
:ivar ~._instId: internally used only for intuitive sorting of statements
"""
_DEEPCOPY_SKIP = (*HdlStatement._DEEPCOPY_SKIP, 'src', 'dst', 'indexes')
_DEEPCOPY_SHALLOW_ONLY = (*HdlStatement._DEEPCOPY_SHALLOW_ONLY, "indexes")
__instCntr = 0
def __init__(self, src: Union[RtlSignalBase, HConst], dst: RtlSignalBase,
indexes: Optional[List[Union[RtlSignalBase, HConst]]]=None,
virtual_only=False,
parentStm: Optional[HdlStatement]=None,
parentStmList: Optional[ListOfHdlStatement]=None,
sensitivity: Optional[SetList]=None,
event_dependent_from_branch:Optional[int]=None):
"""
:param dst: destination to assign to
:param src: source which is assigned from
:param indexes: description of index selector on dst
(list of Index/Slice objects) (f.e. [[0], [1]] means dst[0][1])
:param virtual_only: flag indicates that this assignments
is only virtual and should not be added into
netlist, because it is only for internal notation
"""
super(HdlAssignmentContainer, self).__init__(
parentStm,
parentStmList,
sensitivity,
event_dependent_from_branch=event_dependent_from_branch)
self._instId = HdlAssignmentContainer._nextInstId()
self.src = src
self.dst = dst
assert isinstance(dst, RtlSignalBase), dst
self.indexes = indexes
self._collect_inputs()
if not virtual_only:
for i in self._inputs:
i._rtlEndpoints.append(self)
dst._rtlDrivers.append(self)
dst._rtlCtx.statements.add(self)
self._outputs.append(dst)
@override
def __deepcopy__(self, memo: dict):
result = super(HdlAssignmentContainer, self).__deepcopy__(memo)
result.src = self.src
result.dst = self.dst
result._instId = self._nextInstId()
return result
@internal
@override
def _collect_inputs(self) -> None:
src = self.src
if isinstance(src, RtlSignalBase):
self._inputs.append(src)
indexes = self.indexes
if indexes:
for i in indexes:
if isinstance(i, RtlSignalBase):
self._inputs.append(i)
@internal
@override
def _cut_off_drivers_of(self, sig: RtlSignalBase):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._cut_off_drivers_of`
"""
if self._try_cut_off_whole_stm(sig):
return self
@internal
@override
def _discover_enclosure(self) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_enclosure`
"""
assert self._enclosed_for is None
self._enclosed_for = set()
self._enclosed_for.update(self._outputs)
@internal
@override
def _discover_sensitivity(self, seen: set) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_sensitivity`
"""
assert self._sensitivity is None
ctx = self._sensitivity = SensitivityCtx()
casualSensitivity = set()
for inp in self._inputs:
if inp not in seen:
seen.add(inp)
inp._walk_sensitivity(casualSensitivity, seen, ctx)
ctx.extend(casualSensitivity)
@internal
@override
def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, HdlStatement]):
"""
The assignment does not have any uncovered code branches
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._fill_enclosure`
"""
pass
@internal
@override
def _iter_stms(self) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms`
"""
return
yield
@internal
@override
def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms_for_output`
"""
return
yield
@internal
@override
def _on_parent_event_dependent(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._on_parent_event_dependent`
"""
self._event_dependent_from_branch = 0
@internal
@override
def _try_reduce(self) -> Tuple[ListOfHdlStatement, bool]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._try_reduce`
"""
return ListOfHdlStatement((self,)), False
@internal
@override
def _is_mergable(self, other: HdlStatement) -> bool:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._is_mergable`
"""
return isinstance(other, self.__class__)
@override
def isSame(self, other):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement.isSame`
"""
if isinstance(other, self.__class__):
if isSameHConst(self.dst, other.dst)\
and isSameHConst(self.src, other.src)\
and areSameHConsts(self.indexes, other.indexes):
return True
return False
@internal
@override
@classmethod
def _nextInstId(cls):
"""
Get next instance id
"""
i = cls.__instCntr
cls.__instCntr += 1
return i
@internal
@override
def _replace_input_nested(self, topStm: HdlStatement, toReplace: SignalReplaceSpecType) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_input`
"""
didUpdate = False
if self.indexes:
new_indexes = []
for ind in self.indexes:
new_i, _didUpdate = replace_input_in_expr(topStm, self, ind, toReplace)
new_indexes.append(new_i)
didUpdate |= _didUpdate
self.indexes = new_indexes
self.src, _didUpdate = replace_input_in_expr(topStm, self, self.src, toReplace)
didUpdate |= _didUpdate
if didUpdate:
self._replace_input_update_sensitivity_and_inputs(toReplace)
return didUpdate
================================================
FILE: hwt/hdl/statements/codeBlockContainer.py
================================================
from itertools import compress
from typing import List, Set, Tuple, Generator
from hwt.doc_markers import internal
from hwt.hdl.statements.statement import HdlStatement
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.hdl.statements.utils.reduction import HdlStatement_try_reduce_list
from hwt.hdl.statements.utils.signalCut import HdlStatement_cut_off_drivers_of_list
from hwt.mainBases import RtlSignalBase
from hwt.pyUtils.setList import SetList
from hwt.pyUtils.typingFuture import override
class HdlStmCodeBlockContainer(HdlStatement):
"""
Hdl block statement used also to represent a HDL process
:ivar ~.name: name used as id in target HDL
:ivar ~.statements: list of statements in body of process
:note: HdlStmCodeBlockContainer do not have to be process in target HDL, for example
simple process which contains only unconditional assignment will
be rendered just as assignment. It depends on capabilities of the target HDL.
"""
def __init__(self):
super(HdlStmCodeBlockContainer, self).__init__()
self.name = None
self.statements = ListOfHdlStatement()
self.rank = 0
@internal
@classmethod
def from_known_io(cls, name: str, statements: ListOfHdlStatement,
sensitivity: Set["RtlSignal"],
inputs: SetList, outputs: SetList) -> 'HdlStmCodeBlockContainer':
self = cls()
self.name = name
self.statements = statements
self._inputs = inputs
self._outputs = outputs
self._sensitivity = sensitivity
self.rank = sum(map(lambda s: s.rank, statements))
return self
@internal
@override
def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._try_reduce`
"""
new_statements, _, io_change = HdlStatement_try_reduce_list(self.statements)
return new_statements, io_change
@internal
@override
def _iter_stms(self) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms`
"""
yield from self.statements
@internal
@override
def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms_for_output`
"""
yield from self.statements.iterStatementsWithOutput(output)
@internal
@override
def _cut_off_drivers_of(self, sig: RtlSignalBase):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._cut_off_drivers_of`
"""
if self._try_cut_off_whole_stm(sig):
return self
# try to cut off all statements which are drivers of specified signal
# in all branches
child_keep_mask = []
newStatements = []
all_cut_off = True
all_cut_off &= HdlStatement_cut_off_drivers_of_list(
sig, self.statements, child_keep_mask, newStatements)
self.statements = list(compress(self.statements, child_keep_mask))
assert not all_cut_off, "everything was cut of but this should be already known at the start"
if newStatements:
# parts were cut off
# generate new statement for them
n = self.__class__(*newStatements)
if self.parentStm is None:
ctx = n._get_rtl_context()
ctx.statements.add(n)
self._cut_off_drivers_of_regenerate_io(sig, n)
return n
@internal
@override
def _replace_child_statement(self, stm:HdlStatement,
replacement:ListOfHdlStatement,
update_io:bool) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_child_statement`
"""
if update_io:
raise NotImplementedError()
statements: ListOfHdlStatement = self.statements
i = statements.index(stm)
statements.replace(self, stm, i, replacement)
# reset IO because it was shared with this statement
stm._destroy()
================================================
FILE: hwt/hdl/statements/ifContainter.py
================================================
from copy import deepcopy
from functools import reduce
from itertools import compress
from operator import and_
from typing import List, Tuple, Dict, Optional, Callable, Set, Generator
from hwt.doc_markers import internal
from hwt.hdl.operatorUtils import replace_input_in_expr
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.hdl.statements.statement import HdlStatement, SignalReplaceSpecType
from hwt.hdl.statements.utils.comparison import statementsAreSame, isSameStatementList
from hwt.hdl.statements.utils.ioDiscovery import HdlStatement_discover_enclosure_for_statements
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.hdl.statements.utils.reduction import HdlStatement_merge_statement_lists, \
HdlStatement_try_reduce_list, is_mergable_statement_list
from hwt.hdl.statements.utils.signalCut import HdlStatement_cut_off_drivers_of_list
from hwt.mainBases import RtlSignalBase
from hwt.pyUtils.typingFuture import override
from hwt.serializer.utils import RtlSignal_sort_key
from hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure import fill_stm_list_with_enclosure
from hwt.synthesizer.rtlLevel.rtlSignalWalkers import discover_sensitivity_of_sig
class IfContainer(HdlStatement):
"""
Structural container of if statement for hdl rendering
:ivar ~._ifTrue_enclosed_for: set of signals for which if ifTrue branch enclosed
(has not branch where signal is not assignment)
:ivar ~._elIfs_enclosed_for: list of sets of enclosed signals for each elif
:ivar ~._ifFalse_enclosed_for: set of enclosed signals for ifFalse branch
"""
_DEEPCOPY_SHALLOW_ONLY = (*HdlStatement._DEEPCOPY_SHALLOW_ONLY, '_ifTrue_enclosed_for', '_elIfs_enclosed_for', '_ifFalse_enclosed_for')
_DEEPCOPY_SKIP = (*HdlStatement._DEEPCOPY_SKIP, 'cond', 'elIfs')
def __init__(self, cond: RtlSignalBase, ifTrue=None, ifFalse=None, elIfs=None,
parentStm=None, event_dependent_from_branch: Optional[int]=None):
"""
:param cond: RtlSignal as conditions for this if
:param ifTrue: list of statements which should be active if cond.
is met
:param elIfs: list of tuples (list of conditions, list of statements)
:param ifFalse: list of statements which should be active if cond.
and any other cond. in elIfs is met
"""
assert isinstance(cond, RtlSignalBase)
self.cond = cond
super(IfContainer, self).__init__(
parentStm,
event_dependent_from_branch=event_dependent_from_branch)
if ifTrue is None:
ifTrue = ListOfHdlStatement()
self.ifTrue: ListOfHdlStatement = ifTrue
if elIfs is None:
elIfs = []
self.elIfs: List[Tuple[RtlSignalBase, ListOfHdlStatement]] = elIfs
self.ifFalse: Optional[ListOfHdlStatement] = ifFalse
self._ifTrue_enclosed_for: Optional[Set[RtlSignalBase]] = None
self._elIfs_enclosed_for: Optional[Set[RtlSignalBase]] = None
self._ifFalse_enclosed_for: Optional[Set[RtlSignalBase]] = None
@override
def __deepcopy__(self, memo: dict):
result = super(IfContainer, self).__deepcopy__(memo)
result.cond = self.cond
result.elIfs = [(c, deepcopy(stms, memo)) for c, stms in self.elIfs]
return result
@internal
@override
def _collect_io(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._collect_io`
"""
if isinstance(self.cond, RtlSignalBase):
self._inputs.append(self.cond)
for c, _ in self.elIfs:
if isinstance(c, RtlSignalBase):
self._inputs.append(c)
super(IfContainer, self)._collect_io()
@internal
@override
def _collect_inputs(self) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._collect_inputs`
"""
if isinstance(self.cond, RtlSignalBase):
self._inputs.append(self.cond)
for c, _ in self.elIfs:
if isinstance(c, RtlSignalBase):
self._inputs.append(c)
super(IfContainer, self)._collect_inputs()
@internal
@override
def _clean_signal_meta(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._clean_signal_meta`
"""
self._sensitivity = None
self._ifTrue_enclosed_for = None
self._elIfs_enclosed_for = None
self._ifFalse_enclosed_for = None
HdlStatement._clean_signal_meta(self)
@internal
@override
def _cut_off_drivers_of(self, sig: RtlSignalBase):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._cut_off_drivers_of`
"""
if self._try_cut_off_whole_stm(sig):
return self
# try to cut off all statements which are drivers of specified signal
# in all branches
child_keep_mask = []
newIfTrue = []
all_cut_off = True
all_cut_off &= HdlStatement_cut_off_drivers_of_list(
sig, self.ifTrue, child_keep_mask, newIfTrue)
self.ifTrue = ListOfHdlStatement(compress(self.ifTrue, child_keep_mask))
newElifs = []
anyElifHit = False
for cond, stms in self.elIfs:
newCase = []
child_keep_mask.clear()
all_cut_off &= HdlStatement_cut_off_drivers_of_list(
sig, stms, child_keep_mask, newCase)
_stms = list(compress(stms, child_keep_mask))
stms.clear()
stms.extend(_stms)
if newCase:
anyElifHit = True
newElifs.append((cond, newCase))
newIfFalse = None
if self.ifFalse:
newIfFalse = []
child_keep_mask.clear()
all_cut_off &= HdlStatement_cut_off_drivers_of_list(
sig, self.ifFalse, child_keep_mask, newIfFalse)
self.ifFalse = ListOfHdlStatement(compress(self.ifFalse, child_keep_mask))
assert not all_cut_off, "everything was cut of but this should be already known at the start"
if newIfTrue or newIfFalse or anyElifHit or newIfFalse:
# parts were cut off
# generate new statement for them
cond_sig = self.cond
n = self.__class__(cond_sig, newIfTrue)
for c_sig, stms in newElifs:
n.Elif(c_sig, stms)
if newIfFalse is not None:
n.Else(newIfFalse)
if self.parentStm is None:
ctx = n._get_rtl_context()
ctx.statements.add(n)
self._cut_off_drivers_of_regenerate_io(sig, n)
return n
@internal
@override
def _discover_enclosure(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_enclosure`
"""
outputs = self._outputs
self._ifTrue_enclosed_for = HdlStatement_discover_enclosure_for_statements(
self.ifTrue, outputs)
elif_encls = self._elIfs_enclosed_for = []
for _, stms in self.elIfs:
e = HdlStatement_discover_enclosure_for_statements(
stms, outputs)
elif_encls.append(e)
self._ifFalse_enclosed_for = HdlStatement_discover_enclosure_for_statements(
self.ifFalse, outputs)
assert self._enclosed_for is None
encl = self._enclosed_for = set()
for s in self._ifTrue_enclosed_for:
enclosed = True
for elif_e in elif_encls:
if s not in elif_e:
enclosed = False
break
if enclosed and s in self._ifFalse_enclosed_for:
encl.add(s)
@internal
@override
def _discover_sensitivity(self, seen: set) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_sensitivity`
"""
assert self._sensitivity is None, self
ctx = self._sensitivity = SensitivityCtx()
discover_sensitivity_of_sig(self.cond, seen, ctx)
if ctx.contains_ev_dependency:
return
for stm in self.ifTrue:
stm._discover_sensitivity(seen)
ctx.extend(stm._sensitivity)
# elifs
for cond, stms in self.elIfs:
if ctx.contains_ev_dependency:
break
discover_sensitivity_of_sig(cond, seen, ctx)
if ctx.contains_ev_dependency:
break
for stm in stms:
if ctx.contains_ev_dependency:
break
stm._discover_sensitivity(seen)
ctx.extend(stm._sensitivity)
if self.ifFalse:
assert not ctx.contains_ev_dependency, "can not negate event"
# else
for stm in self.ifFalse:
stm._discover_sensitivity(seen)
ctx.extend(stm._sensitivity)
@internal
@override
def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], HdlStatement]]) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._fill_enclosure`
"""
enc = []
outputs = self._outputs
for e in sorted(enclosure.keys(), key=RtlSignal_sort_key):
if e in outputs and e not in self._enclosed_for:
enc.append(e)
if not enc:
return
fill_stm_list_with_enclosure(self, self._ifTrue_enclosed_for,
self.ifTrue, enc, enclosure)
for (_, stms), e in zip(self.elIfs, self._elIfs_enclosed_for):
fill_stm_list_with_enclosure(self, e, stms, enc, enclosure)
self.ifFalse = fill_stm_list_with_enclosure(self, self._ifFalse_enclosed_for,
self.ifFalse, enc, enclosure)
self._enclosed_for.update(enc)
@internal
@override
def _iter_stms(self) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms`
"""
yield from self.ifTrue
for _, stms in self.elIfs:
yield from stms
if self.ifFalse is not None:
yield from self.ifFalse
@internal
@override
def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms_for_output`
"""
yield from self.ifTrue.iterStatementsWithOutput(output)
for _, stms in self.elIfs:
yield from stms.iterStatementsWithOutput(output)
if self.ifFalse is not None:
yield from self.ifFalse.iterStatementsWithOutput(output)
@internal
def _iter_all_elifs(self) -> Generator[Tuple[RtlSignalBase, ListOfHdlStatement], None, None]:
yield (self.cond, self.ifTrue)
yield from self.elIfs
@internal
@override
def _try_reduce(self) -> Tuple[bool, ListOfHdlStatement]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._try_reduce`
"""
# flag if IO of statement has changed
io_change = False
self.ifTrue, rank_decrease, _io_change = HdlStatement_try_reduce_list(
self.ifTrue)
self.rank -= rank_decrease
io_change |= _io_change
new_elifs = []
for cond, statements in self.elIfs:
_statements, rank_decrease, _io_change = HdlStatement_try_reduce_list(
statements)
self.rank -= rank_decrease
io_change |= _io_change
new_elifs.append((cond, _statements))
self.elIfs = new_elifs
if self.ifFalse is not None:
self.ifFalse, rank_decrease, _io_update_required = HdlStatement_try_reduce_list(
self.ifFalse)
self.rank -= rank_decrease
io_change |= _io_change
reduce_self = not self._condHasEffect(
self.ifTrue, self.ifFalse, self.elIfs)
if reduce_self:
res = self.ifTrue
else:
res = ListOfHdlStatement((self,))
self._on_reduce(reduce_self, io_change, res)
# try merge nested ifs as elifs
if self.ifFalse is not None and len(self.ifFalse) == 1:
child = self.ifFalse[0]
if isinstance(child, IfContainer):
self._merge_nested_if_from_else(child)
return res, io_change
@internal
def _merge_nested_if_from_else(self, ifStm: "IfContainer"):
"""
Merge nested IfContarner form else branch to this IfContainer
as elif and else branches
"""
self.elIfs.append((ifStm.cond, ifStm.ifTrue))
self.elIfs.extend(ifStm.elIfs)
self.ifFalse = ifStm.ifFalse
@internal
@override
def _is_mergable(self, other: HdlStatement) -> bool:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._is_mergable`
"""
if not isinstance(other, IfContainer):
return False
if (self.cond is not other.cond
or not is_mergable_statement_list(self.ifTrue, other.ifTrue)):
return False
if len(self.elIfs) != len(other.elIfs):
return False
for (a_c, a_stm), (b_c, b_stm) in zip(self.elIfs, other.elIfs):
if a_c is not b_c or not is_mergable_statement_list(a_stm, b_stm):
return False
return is_mergable_statement_list(self.ifFalse, other.ifFalse)
@internal
@override
def _merge_with_other_stm(self, other: "IfContainer") -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._merge_with_other_stm`
"""
merge = HdlStatement_merge_statement_lists
self.ifTrue = merge(self.ifTrue, other.ifTrue)
new_elifs = []
for ((c, elifA), (_, elifB)) in zip(self.elIfs, other.elIfs):
new_elifs.append((c, merge(elifA, elifB)))
self.elIfs = new_elifs
self.ifFalse = merge(self.ifFalse, other.ifFalse)
other.ifTrue = None
other.elIfs = None
other.ifFalse = None
self._on_merge(other)
@internal
@staticmethod
def _condHasEffect(ifTrue, ifFalse, elIfs):
stmCnt = len(ifTrue)
# [TODO] condition in empty if stm
if ifFalse is not None \
and stmCnt == len(ifFalse) \
and reduce(and_,
[len(stm) == stmCnt
for _, stm in elIfs],
True):
for stms in zip(ifTrue, ifFalse, *map(lambda x: x[1], elIfs)):
if not statementsAreSame(stms):
return True
return False
return True
@override
def isSame(self, other: HdlStatement) -> bool:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement.isSame`
"""
if self is other:
return True
if self.rank != other.rank:
return False
if isinstance(other, IfContainer):
if self.cond is other.cond:
if len(self.ifTrue) == len(other.ifTrue) \
and ((self.ifFalse is None and other.ifFalse is None) or
len(self.ifFalse) == len(other.ifFalse)) \
and len(self.elIfs) == len(other.elIfs):
if not isSameStatementList(self.ifTrue,
other.ifTrue) \
or not isSameStatementList(self.ifFalse,
other.ifFalse):
return False
for (ac, astms), (bc, bstms) in zip(self.elIfs,
other.elIfs):
if not (ac == bc) or\
not isSameStatementList(astms, bstms):
return False
return True
return False
@internal
@override
def _replace_input_nested(self, topStm: HdlStatement, toReplace: SignalReplaceSpecType) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_input`
"""
didUpdate = False
self.cond, _didUpdate = replace_input_in_expr(topStm, self, self.cond, toReplace)
didUpdate |= _didUpdate
for stm in self.ifTrue:
didUpdate |= stm._replace_input_nested(topStm, toReplace)
new_elifs = []
for (cond, stms) in self.elIfs:
new_cond, _didUpdate = replace_input_in_expr(topStm, self, cond, toReplace)
didUpdate |= _didUpdate
for stm in stms:
didUpdate |= stm._replace_input_nested(topStm, toReplace)
new_elifs.append((new_cond, stms))
self.elIfs = new_elifs
if self.ifFalse is not None:
for stm in self.ifFalse:
_didUpdate = stm._replace_input_nested(topStm, toReplace)
didUpdate |= _didUpdate
if didUpdate:
self._replace_input_update_sensitivity_and_inputs(toReplace)
return didUpdate
@internal
@override
def _replace_child_statement(self, stm:HdlStatement,
replacement:ListOfHdlStatement,
update_io:bool) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_child_statement`
"""
if update_io:
raise NotImplementedError()
for branch_list in (self.ifTrue, *(elif_stms for _, elif_stms in self.elIfs), self.ifFalse):
if branch_list is None:
continue
try:
i = branch_list.index(stm)
except ValueError:
# not in list
continue
branch_list.replace(self, stm, i, replacement)
# reset IO because it was shared with this statement
stm._destroy()
return
raise ValueError("Statement", stm, "not found in ", self)
================================================
FILE: hwt/hdl/statements/statement.py
================================================
from copy import deepcopy, copy
from itertools import chain
from typing import List, Tuple, Union, Optional, Dict, Callable, Generator
from hwt.doc_markers import internal
from hwt.hdl.hdlObject import HdlObject
from hwt.mainBases import RtlSignalBase
from hwt.pyUtils.arrayQuery import flatten
from hwt.pyUtils.setList import SetList
class HwtSyntaxError(Exception):
pass
SignalReplaceSpecType = Union[Tuple[RtlSignalBase, RtlSignalBase], Dict[RtlSignalBase, RtlSignalBase]]
class HdlStatement(HdlObject):
"""
:ivar ~._event_dependent_from_branch: index of code branch if statement is event (clk) dependent else None
:ivar ~.parentStm: parent instance of HdlStatement or None
:ivar ~.parentStmList: list in parent statement where this statement is stored
:ivar ~._inputs: SetList of input signals for this statement
(All input signals which are directly used in any statement. Note that the expression is also the signal.)
:ivar ~._outputs: SetList of output signals for this statement
:ivar ~._sensitivity: SetList of input signals
or (rising/falling) operator
:ivar ~._enclosed_for: set of outputs for which this statement is enclosed
(for which there is not any unused branch)
:ivar ~.rank: number of used branches in statement, used as pre-filter
for statement comparing
"""
_DEEPCOPY_SKIP = ('parentStm', 'parentStmList')
_DEEPCOPY_SHALLOW_ONLY = ("_inputs", "_outputs", "_enclosed_for", "_sensitivity")
def __init__(self, parentStm:Optional["HdlStatement"]=None,
parentStmList: Optional["ListOfHdlStatement"]=None,
sensitivity:Optional[SetList]=None,
event_dependent_from_branch:Optional[int]=None):
assert event_dependent_from_branch is None or isinstance(event_dependent_from_branch, int), event_dependent_from_branch
self._event_dependent_from_branch = event_dependent_from_branch
self.parentStm = parentStm
self.parentStmList = parentStmList
self._inputs = SetList()
self._outputs = SetList()
self._enclosed_for = None
self._sensitivity = sensitivity
self.rank = 0
def __deepcopy__(self, memo: dict):
cls = self.__class__
result = cls.__new__(cls)
memo[id(self)] = result
for k, v in self.__dict__.items():
if v is None:
new_v = None
elif k in self._DEEPCOPY_SKIP:
new_v = None
elif k in self._DEEPCOPY_SHALLOW_ONLY:
new_v = copy(v)
else:
new_v = deepcopy(v, memo)
setattr(result, k, new_v)
return result
@internal
def _clean_signal_meta(self):
"""
Clean informations about enclosure for outputs and sensitivity
of this statement
"""
self._enclosed_for = None
self._sensitivity = None
for stm in self._iter_stms():
stm._clean_signal_meta()
@internal
def _collect_io(self) -> None:
"""
Collect inputs/outputs from all child statements
to :py:attr:`~_input` / :py:attr:`_output` attribute on this object
"""
in_add = self._inputs.extend
out_add = self._outputs.extend
for stm in self._iter_stms():
in_add(stm._inputs)
out_add(stm._outputs)
if self.parentStmList is not None:
for o in self._outputs:
self.parentStmList._registerOutput(o, self)
@internal
def _collect_inputs(self) -> None:
"""
Collect inputs from all child statements
to :py:attr:`~_input` attribute on this object
"""
in_add = self._inputs.extend
for stm in self._iter_stms():
in_add(stm._inputs)
@internal
def _collect_outputs(self) -> None:
"""
Collect inputs from all child statements
to :py:attr:`_output` attribute on this object
"""
out_add = self._outputs.extend
for stm in self._iter_stms():
out_add(stm._outputs)
if self.parentStmList is not None:
for o in self._outputs:
self.parentStmList._registerOutput(o, self)
@internal
def _try_cut_off_whole_stm(self, sig: RtlSignalBase) -> bool:
"""
Try cut of output from statement and if this is only output of statement cut off whole statement.
Otherwise prepare for cutting of the signal from this statement.
:param sig: signal which drivers should be removed
:return: true if was removed or False if pruning of sig from this statement is required
"""
if self._sensitivity is not None or self._enclosed_for is not None:
raise NotImplementedError(
"Sensitivity and enclosure has to be cleaned first")
if self.parentStmList is not None:
self.parentStmList._unregisterOutput(sig, self)
if len(self._outputs) == 1 and sig is self._outputs[0]:
# this statement has only this output, eject this statement from its parent
self.parentStm = None # because new parent will be asigned immediately after cutting of
self.parentStmList = None
return True
sig._rtlDrivers.discard(self)
return False
@internal
def _cut_off_drivers_of(self, sig: RtlSignalBase) -> Union[None, "HdlStatement", List["HdlStatement"]]:
"""
Cut all logic from statements which drives signal sig.
:param sig: signal which drivers should be removed
:return: A statement or statement list which was cut off from the original statement
"""
raise NotImplementedError("This is an abstract method and it should be implemented in child class",
self.__class__)
@internal
def _cut_off_drivers_of_regenerate_io(self, cut_off_sig: RtlSignalBase, cut_of_smt: "HdlStatement"):
"""
Update _inputs/_outputs after some part of statement was cut of
:param cut_off_sig: a signal which driver is a cut_of_stm
:param cut_of_smt: the statement wich was cut off from original statement (selected by cut_off_sig)
"""
# update io of this
self._outputs.remove(cut_off_sig)
if cut_of_smt._inputs:
# update inputs on this
self._inputs.clear()
self._collect_inputs()
if self.parentStm is None:
for i in cut_of_smt._inputs:
if i not in self._inputs:
i._rtlEndpoints.remove(self)
if self.parentStm is None:
cut_off_sig._rtlDrivers.append(cut_of_smt)
if self.parentStmList is not None:
self.parentStmList._unregisterOutput(cut_off_sig, self)
@internal
def _discover_enclosure(self) -> None:
"""
Discover all outputs for which is this statement enclosed _enclosed_for property
(has driver in all code branches)
"""
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__, self)
@internal
def _discover_sensitivity(self, seen: set) -> None:
"""
discover all sensitivity signals and store them to _sensitivity property
"""
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__, self)
@internal
def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], 'HdlStatement']]) -> None:
"""
Add assignments to a default values to a code branches which are not assigning to specified output signal.
:attention: enclosure has to be discoverd first use _discover_enclosure() method
"""
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__, self)
@internal
def _get_rtl_context(self) -> 'RtlNetlist':
"""
get RtlNetlist context from signals
"""
for sig in chain(self._inputs, self._outputs):
if sig._rtlCtx:
return sig._rtlCtx
else:
# Param instances does not have context
continue
raise HwtSyntaxError(
"Statement does not have any signal in any context,"
" it should have at least some output or should be alreary optimized out", self)
@internal
def _iter_stms(self):
"""
:return: iterator over all children statements
"""
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__,
self)
@internal
def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator["HdlStatement", None, None]:
"""
:return: iterator of sub statements which have specified output as an output
"""
return
yield
@internal
def _merge_with_other_stm(self, other: "HdlStatement") -> None:
"""
:attention: statements has to be mergable (to check use _is_mergable method)
"""
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__,
self)
@internal
def _on_reduce(self, self_reduced: bool, io_changed: bool,
result_statements: List["HdlStatement"]) -> None:
"""
Update signal IO after reduce attempt
:param self_reduced: if True this object was reduced
:param io_changed: if True IO of this object may changed
and has to be updated
:param result_statements: list of statements which are result
of reduce operation on this statement
"""
parentStm = self.parentStm
parentStmList = self.parentStmList
if self_reduced:
was_top = parentStm is None
# update signal drivers/endpoints
if was_top:
# disconnect self from signals
ctx = self._get_rtl_context()
ctx.statements.remove(self)
ctx.statements.update(result_statements)
for i in self._inputs:
i._rtlEndpoints.discard(self)
for o in self._outputs:
o._rtlDrivers.remove(self)
for stm in result_statements:
stm.parentStm = parentStm
stm.parentStmList = parentStmList
if was_top:
# connect signals to child statements
for inp in stm._inputs:
inp._rtlEndpoints.append(stm)
for outp in stm._outputs:
outp._rtlDrivers.append(stm)
else:
for outp in stm._outputs:
if parentStmList is not None:
parentStmList._registerOutput(outp, stm)
else:
# parent has to update it's inputs/outputs
if io_changed:
if parentStmList is not None:
for o in self._outputs:
parentStmList._unregisterOutput(o, self)
self._inputs = SetList()
self._outputs = SetList()
self._collect_io()
@internal
def _on_merge(self, other: "HdlStatement"):
"""
After merging statements update IO, sensitivity and context
:attention: rank is not updated
"""
self._inputs.extend(other._inputs)
if self.parentStmList is not None:
for o in other._outputs:
if o not in self._outputs:
self._outputs.append(o)
self.parentStmList._registerOutput(o, self)
else:
self._outputs.extend(other._outputs)
if self._sensitivity is not None:
self._sensitivity.extend(other._sensitivity)
else:
assert other._sensitivity is None
if self._enclosed_for is not None:
self._enclosed_for.update(other._enclosed_for)
else:
assert other._enclosed_for is None
other_was_top = other.parentStm is None
if other_was_top:
other._get_rtl_context().statements.remove(other)
for s in other._inputs:
s._rtlEndpoints.discard(other)
s._rtlEndpoints.append(self)
for s in other._outputs:
s._rtlDrivers.discard(other)
s._rtlDrivers.append(self)
@internal
def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__,
self)
def _is_enclosed(self) -> bool:
"""
:return: True if every branch in statement assignas to all output signals else False
"""
return len(self._outputs) == len(self._enclosed_for)
@internal
def _is_mergable(self, other: "HdlStatement") -> bool:
if self is other:
raise ValueError("Can not merge statement with itself")
else:
raise NotImplementedError("This method should be implemented"
" on class of statement", self.__class__,
self)
@internal
def _on_parent_event_dependent(self):
"""
After parent statement become event dependent
propagate event dependency flag to child statements
"""
if self._event_dependent_from_branch != 0:
self._event_dependent_from_branch = 0
for stm in self._iter_stms():
stm._on_parent_event_dependent()
@internal
def _set_parent_stm(self, parentStm: "HdlStatement", parentStmList: "ListOfHdlStatements"):
"""
Assign parent statement and propagate dependency flags if necessary
"""
assert parentStm is not self.parentStm
was_top = self.parentStm is None
self.parentStm = parentStm
if self._event_dependent_from_branch is None\
and parentStm._event_dependent_from_branch is not None:
self._on_parent_event_dependent()
topStatement = parentStm
parents = []
while True:
parents.append(topStatement)
if topStatement.parentStm is None:
break
topStatement = topStatement.parentStm
if was_top:
for inp in self._inputs:
inp._rtlEndpoints.discard(self)
inp._rtlEndpoints.append(topStatement)
for p in parents:
p._inputs.append(inp)
for outp in self._outputs:
outp._rtlDrivers.discard(self)
outp._rtlDrivers.append(topStatement)
for p in parents:
p._outputs.append(outp)
ctx = self._get_rtl_context()
ctx.statements.discard(self)
parentStm.rank += self.rank
self.parentStmList = parentStmList
for o in self._outputs:
parentStmList._registerOutput(o, self)
@internal
def _register_stements(self, statements: List["HdlStatement"],
target: "ListOfHdlStatements"):
"""
Append statements to this container
"""
for stm in flatten(statements):
assert stm.parentStm is None, (
"HdlStatement instance has to have only a single parent", stm)
stm._set_parent_stm(self, target)
target.append(stm)
def isSame(self, other: "HdlStatement") -> bool:
"""
:return: True if other has same meaning as self
"""
raise NotImplementedError("This method should be implemented in child class", self.__class__, self)
@internal
def _destroy(self):
"""
Disconnect this statement from signals and delete it from RtlNetlist context
:attention: signal endpoints/drivers will be altered
that means they can not be used for iteration
"""
for i in self._inputs:
i._rtlEndpoints.discard(self)
if self.parentStm is None:
ctx = self._get_rtl_context()
for o in self._outputs:
o._rtlDrivers.remove(self)
ctx.statements.remove(self)
self.parentStm = None
if self.parentStmList is not None:
self.parentStmList = None
for o in self._outputs:
self.parentStmList._unregisterOutput(o, self)
@internal
def _replace_input_nested(self, topStm: "HdlStatement", toReplace: SignalReplaceSpecType) -> None:
raise NotImplementedError("This method should be implemented in child class", self.__class__, self)
@internal
def _replace_input(self, toReplace: SignalReplaceSpecType) -> bool:
"""
Replace input signal with another
:return: True if the expression was present in this statement (and was replaced)
:note: sensitivity/endpoints are actualized
:note: calling on children does not update parent's _inputs, _sensitivity or _enclosed_for
"""
assert self.parentStm is None, self
return self._replace_input_nested(self, toReplace)
@internal
def _replace_input_update_sensitivity_and_inputs(
self,
toReplace: SignalReplaceSpecType):
"""
This function updates _sensitivity and _inputs containers after the input was replaced in this statement.
:attention: it does not perform the replace of the input. It should be called after the replace.
"""
# if we replace something some input expression may be altered thus full re-computation is required
self._inputs.clear()
self._collect_inputs()
if self._sensitivity is not None:
self._sensitivity = None
self._discover_sensitivity(set())
@internal
def _replace_child_statement(self, stm: "HdlStatement",
replacement: List["HdlStatement"],
update_io: bool) -> None:
"""
Replace a child statement with a list of other statements
:attention: original statement is destroyed and entirely removed from circuit
:note: sensitivity/endoints are actualized
"""
raise NotImplementedError("This method should be implemented in child class", self.__class__, self)
================================================
FILE: hwt/hdl/statements/switchContainer.py
================================================
from copy import deepcopy, copy
from functools import reduce
from itertools import compress
from operator import and_
from typing import List, Tuple, Dict, Optional, Callable, Set, Generator
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.constUtils import isSameHConst
from hwt.hdl.operatorUtils import replace_input_in_expr
from hwt.hdl.sensitivityCtx import SensitivityCtx
from hwt.hdl.statements.statement import HdlStatement, HwtSyntaxError, SignalReplaceSpecType
from hwt.hdl.statements.utils.comparison import isSameStatementList, statementsAreSame
from hwt.hdl.statements.utils.ioDiscovery import HdlStatement_discover_enclosure_for_statements
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.hdl.statements.utils.reduction import HdlStatement_merge_statement_lists, \
HdlStatement_try_reduce_list, is_mergable_statement_list
from hwt.hdl.statements.utils.signalCut import HdlStatement_cut_off_drivers_of_list
from hwt.hdl.types.enum import HEnum
from hwt.mainBases import RtlSignalBase
from hwt.pyUtils.typingFuture import override
from hwt.serializer.utils import RtlSignal_sort_key
from hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure import fill_stm_list_with_enclosure
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal
class SwitchContainer(HdlStatement):
"""
Structural container for switch statement for hdl rendering
:ivar ~.switchOn: select signal of switch
:ivar ~.cases: list of tuples (value, statements)
:ivar ~.default: list of statements (for branch "default")
:ivar ~._case_value_index: dictionary {value:index} for every case in cases
:ivar ~._case_enclosed_for: list of sets of enclosed signal for each case branch
:ivar ~._default_enclosed_for: set of enclosed signals for branch default
"""
_DEEPCOPY_SKIP = (*HdlStatement._DEEPCOPY_SKIP, 'switchOn', 'cases')
_DEEPCOPY_SHALLOW_ONLY = (*HdlStatement._DEEPCOPY_SHALLOW_ONLY, '_case_value_index', '_case_enclosed_for', '_default_enclosed_for')
def __init__(self, switchOn: RtlSignal,
cases: List[Tuple[HConst, ListOfHdlStatement]],
default: Optional[ListOfHdlStatement]=None,
parentStm: HdlStatement=None,
event_dependent_from_branch: Optional[int]=None):
super(SwitchContainer, self).__init__(
parentStm=parentStm,
event_dependent_from_branch=event_dependent_from_branch)
self.switchOn = switchOn
self.cases = cases
self.default = default
self._case_value_index = {}
for i, (v, _) in enumerate(cases):
assert v not in self._case_value_index, v
self._case_value_index[v] = i
self._case_enclosed_for: Optional[List[Set[RtlSignal]]] = None
self._default_enclosed_for: Optional[Set[RtlSignal]] = None
@override
def __deepcopy__(self, memo: dict):
result = super(SwitchContainer, self).__deepcopy__(memo)
result.switchOn = self.switchOn
result.cases = [(c, deepcopy(stms, memo)) for c, stms in self.cases]
result._case_value_index = copy(self._case_value_index)
result._case_enclosed_for = copy(self._case_enclosed_for)
result._default_enclosed_for = copy(self._default_enclosed_for)
return result
@internal
@override
def _cut_off_drivers_of(self, sig: RtlSignalBase):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._cut_off_drivers_of`
"""
if self._try_cut_off_whole_stm(sig):
return self
# try to cut off all statements which are drivers of specified signal
# in all branches
child_keep_mask = []
all_cut_off = True
new_default = None
if self.default:
new_default = ListOfHdlStatement()
child_keep_mask.clear()
case_eliminated = HdlStatement_cut_off_drivers_of_list(
sig, self.default, child_keep_mask, new_default)
all_cut_off &= case_eliminated
if case_eliminated:
self.rank -= 1
self.default = None
else:
self.default = list(compress(self.default, child_keep_mask))
new_cases = []
case_keepmask = []
for val, stms in self.cases:
new_case = ListOfHdlStatement()
child_keep_mask.clear()
case_eliminated = HdlStatement_cut_off_drivers_of_list(
sig, stms, child_keep_mask, new_case)
if case_eliminated:
self.rank -= 1
all_cut_off &= case_eliminated
case_keepmask.append(not case_eliminated)
_stms = list(compress(stms, child_keep_mask))
stms.clear()
stms.extend(_stms)
if new_case or new_default:
# if there is a default we need to add case even in empty
# to prevent falling to default
new_cases.append((val, new_case))
self.cases = list(compress(self.cases, case_keepmask))
assert not all_cut_off, "everything was cut of but this should be already known at start"
if new_cases or new_default:
# parts were cut off
# generate new statement for them
sel_sig = self.switchOn
n = self.__class__(sel_sig)
n.add_cases(new_cases)
if new_default:
n.Default(*new_default)
if self.parentStm is None:
ctx = n._get_rtl_context()
ctx.statements.add(n)
self._cut_off_drivers_of_regenerate_io(sig, n)
return n
@internal
@override
def _clean_signal_meta(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._clean_signal_meta`
"""
self._case_enclosed_for = None
self._default_enclosed_for = None
HdlStatement._clean_signal_meta(self)
@internal
@override
def _collect_io(self):
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._collect_io`
"""
if isinstance(self.switchOn, RtlSignalBase):
self._inputs.append(self.switchOn)
for c, _ in self.cases:
if isinstance(c, RtlSignalBase):
self._inputs.append(c)
super(SwitchContainer, self)._collect_io()
@internal
@override
def _collect_inputs(self) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._collect_inputs`
"""
if isinstance(self.switchOn, RtlSignalBase):
self._inputs.append(self.switchOn)
for c, _ in self.cases:
if isinstance(c, RtlSignalBase):
self._inputs.append(c)
super(SwitchContainer, self)._collect_inputs()
@internal
@override
def _discover_enclosure(self) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_enclosure`
"""
assert self._enclosed_for is None
enclosure = self._enclosed_for = set()
case_enclosures = self._case_enclosed_for = []
outputs = self._outputs
for _, stms in self.cases:
c_e = HdlStatement_discover_enclosure_for_statements(stms, outputs)
case_enclosures.append(c_e)
self._default_enclosed_for = HdlStatement_discover_enclosure_for_statements(
self.default, outputs)
t = self.switchOn._dtype
if not self.default and len(self.cases) < t.domain_size():
# cases does not cover all branches
return
for s in outputs:
enclosed = True
for e in case_enclosures:
if s not in e:
enclosed = False
break
if enclosed and (not self.default or s in self._default_enclosed_for):
enclosure.add(s)
@internal
@override
def _discover_sensitivity(self, seen) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._discover_sensitivity`
"""
assert self._sensitivity is None, self
ctx = self._sensitivity = SensitivityCtx()
casual_sensitivity = set()
self.switchOn._walk_sensitivity(casual_sensitivity, seen, ctx)
if ctx.contains_ev_dependency:
raise HwtSyntaxError(
"Can not switch on event operator result", self.switchOn)
ctx.extend(casual_sensitivity)
for stm in self._iter_stms():
stm._discover_sensitivity(seen)
ctx.extend(stm._sensitivity)
@internal
@override
def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], HdlStatement]]) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._fill_enclosure`
"""
select = []
outputs = self._outputs
for e in sorted(enclosure.keys(), key=RtlSignal_sort_key):
if e in outputs:
select.append(e)
for (_, stms), e in zip(self.cases, self._case_enclosed_for):
fill_stm_list_with_enclosure(self, e, stms, select, enclosure)
e.update(select)
t = self.switchOn._dtype
default_required = len(self.cases) < t.domain_size()
if self.default is not None or default_required:
self.default = fill_stm_list_with_enclosure(
self, self._default_enclosed_for, self.default, select, enclosure)
self._default_enclosed_for.update(select)
self._enclosed_for.update(select)
@internal
@override
def _iter_stms(self) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms`
"""
for _, stms in self.cases:
yield from stms
if self.default is not None:
yield from self.default
@internal
@override
def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[HdlStatement, None, None]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._iter_stms_for_output`
"""
for _, stms in self.cases:
yield from stms.iterStatementsWithOutput(output)
if self.default is not None:
yield from self.default.iterStatementsWithOutput(output)
@internal
@override
def _is_mergable(self, other) -> bool:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._is_mergable`
"""
if not isinstance(other, SwitchContainer):
return False
if not (self.switchOn is other.switchOn and
len(self.cases) == len(other.cases) and
is_mergable_statement_list(self.default, other.default)):
return False
for (vA, caseA), (vB, caseB) in zip(self.cases, other.cases):
if vA != vB or not is_mergable_statement_list(caseA, caseB):
return False
return True
@internal
@override
def _merge_with_other_stm(self, other: "SwitchContainer") -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._merge_with_other_stm`
"""
merge = HdlStatement_merge_statement_lists
newCases = []
for (c, caseA), (_, caseB) in zip(self.cases, other.cases):
newCases.append((c, merge(caseA, caseB)))
self.cases = newCases
other.cases = None
self.default = merge(self.default, other.default)
other.default = None
self._on_merge(other)
@internal
@override
def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._try_reduce`
"""
io_change = False
# try reduce the content of the case branches
new_cases = []
for val, statements in self.cases:
_statements, rank_decrease, _io_change = HdlStatement_try_reduce_list(
statements)
io_change |= _io_change
self.rank -= rank_decrease
new_cases.append((val, _statements))
self.cases = new_cases
# try reduce content of the defult branch
if self.default is not None:
self.default, rank_decrease, _io_change = HdlStatement_try_reduce_list(
self.default)
self.rank -= rank_decrease
io_change |= _io_change
# try reduce self
reduce_self = not self._condHasEffect()
if reduce_self:
if self.cases:
res = self.cases[0][1]
elif self.default is not None:
res = self.default
else:
res = []
else:
res = [self, ]
self._on_reduce(reduce_self, io_change, res)
if not self.default:
t = self.switchOn._dtype
if isinstance(t, HEnum):
dom_size = t.domain_size()
val_cnt = len(t._allValues)
if len(self.cases) == val_cnt and val_cnt < dom_size:
# bit representation is not fully matching enum description
# need to set last case as default to prevent latches
_, stms = self.cases.pop()
self.default = stms
return res, io_change
@internal
def _condHasEffect(self) -> bool:
"""
:return: True if statements in branches has different effect
"""
if not self.cases:
return False
# [TODO]
type_domain_covered = bool(self.default) or len(
self.cases) == self.switchOn._dtype.domain_size()
stmCnt = len(self.cases[0][1])
if type_domain_covered and reduce(
and_,
[len(stm) == stmCnt
for _, stm in self.cases],
True) and (self.default is None
or len(self.default) == stmCnt):
stms = list(self._iter_stms())
if statementsAreSame(stms):
return False
else:
return True
return True
@internal
@override
def _replace_input_nested(self, topStm: "HdlStatement", toReplace: SignalReplaceSpecType) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_input`
"""
didUpdate = False
self.switchOn, _didUpdate = replace_input_in_expr(topStm, self, self.switchOn, toReplace)
didUpdate |= _didUpdate
for (_, stms) in self.cases:
for stm in stms:
stm: HdlStatement
didUpdate |= stm._replace_input_nested(topStm, toReplace)
if self.default is not None:
for stm in self.default:
didUpdate |= stm._replace_input_nested(topStm, toReplace)
if didUpdate:
self._replace_input_update_sensitivity_and_inputs(toReplace)
return didUpdate
@internal
@override
def _replace_child_statement(self, stm: HdlStatement,
replacement:ListOfHdlStatement,
update_io:bool) -> None:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement._replace_child_statement`
"""
if update_io:
raise NotImplementedError()
for branch_list in (*(case_stms for _, case_stms in self.cases), self.default):
if branch_list is None:
continue
try:
i = branch_list.index(stm)
except ValueError:
# not in list
continue
branch_list.replace(self, stm, i, replacement)
# reset IO because it was shared with this statement
stm._destroy()
return
raise ValueError("Statement", stm, "not found in ", self)
@override
def isSame(self, other: HdlStatement) -> bool:
"""
:see: :meth:`hwt.hdl.statements.statement.HdlStatement.isSame`
"""
if self is other:
return True
if self.rank != other.rank:
return False
if isinstance(other, SwitchContainer) \
and isSameHConst(self.switchOn, other.switchOn)\
and len(self.cases) == len(other.cases)\
and isSameStatementList(self.default, other.default):
for (ac, astm), (bc, bstm) in zip(self.cases, other.cases):
if not isSameHConst(ac, bc)\
or not isSameStatementList(astm, bstm):
return False
return True
return False
================================================
FILE: hwt/hdl/statements/utils/__init__.py
================================================
================================================
FILE: hwt/hdl/statements/utils/comparison.py
================================================
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
def isSameStatementList(stmListA: ListOfHdlStatement,
stmListB: ListOfHdlStatement) -> bool:
"""
:return: True if two lists of HdlStatement instances are same
"""
if stmListA is stmListB:
return True
if stmListA is None or stmListB is None:
return False
for a, b in zip(stmListA, stmListB):
if not a.isSame(b):
return False
return True
def statementsAreSame(statements: ListOfHdlStatement) -> bool:
"""
:return: True if all statements are same
"""
iterator = iter(statements)
try:
first = next(iterator)
except StopIteration:
return True
return all(first.isSame(rest) for rest in iterator)
================================================
FILE: hwt/hdl/statements/utils/ioDiscovery.py
================================================
from typing import List, Set
from hwt.doc_markers import internal
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.mainBases import RtlSignalBase
@internal
def HdlStatement_discover_enclosure_for_statements(
statements: ListOfHdlStatement,
outputs: List[RtlSignalBase]) -> Set[RtlSignalBase]:
"""
Discover enclosure for list of statements
:param statements: list of statements in one code branch
:param outputs: list of outputs which should be driven from this statement list
:return: set of signals for which this statement list have always some driver
(is enclosed)
"""
result = set()
if not statements:
return result
for stm in statements:
stm._discover_enclosure()
for o in outputs:
has_driver = False
for stm in statements.iterStatementsWithOutput(o):
assert not has_driver
has_driver = False
result.update(stm._enclosed_for)
return result
================================================
FILE: hwt/hdl/statements/utils/listOfHdlStatements.py
================================================
from copy import deepcopy
from itertools import islice
from typing import Sequence, Dict, List, Union
from hwt.doc_markers import internal
from hwt.hdl.statements.statement import HdlStatement
from hwt.constants import NOT_SPECIFIED
from hwt.mainBases import RtlSignalBase
class ListOfHdlStatement(list):
"""
A list of hdl statements used in statements to keep track of children
"""
def __init__(self, *args):
list.__init__(self)
self.firstStmWithBranchesI = None
self._outputToStatementList: Dict[RtlSignalBase, List[HdlStatement]] = {}
if args:
assert len(args) == 1, ("expected at most 1 argument", args)
self.extend(args[0])
def append(self, v: HdlStatement):
if self.firstStmWithBranchesI is None and v.rank > 0:
self.firstStmWithBranchesI = len(self)
for o in v._outputs:
self._registerOutput(o, v)
return list.append(self, v)
def extend(self, stms: Sequence[HdlStatement]):
for v in stms:
self.append(v)
def insert(self, i: int, v: HdlStatement):
assert isinstance(i, int), i
res = list.insert(self, i, v)
self.firstStmWithBranchesI = NOT_SPECIFIED
for o in v._outputs:
self._registerOutput(o, v)
return res
def pop(self):
raise NotImplementedError()
def remove(self, item):
raise NotImplementedError()
def discard(self, item):
raise NotImplementedError()
def iterStatementsWithOutput(self, out: RtlSignalBase):
yield from self._outputToStatementList.get(out, ())
def _unregisterOutput(self, o: RtlSignalBase, stm: HdlStatement):
self._outputToStatementList[o].remove(stm)
def _registerOutput(self, o: RtlSignalBase, stm: HdlStatement):
self._outputToStatementList.setdefault(o, []).append(stm)
def __setitem__(self, index:Union[int, slice], value:Union["ListOfHdlStatement", HdlStatement]):
cur = self[index]
if isinstance(index, int):
for o in cur._outputs:
self._outputToStatementList[o].remove(cur)
else:
for _cur in cur:
for o in _cur._outputs:
self._outputToStatementList[o].remove(_cur)
res = list.__setitem__(self, index, value)
self.firstStmWithBranchesI = NOT_SPECIFIED
if isinstance(index, int):
for o in value._outputs:
self._registerOutput(o, value)
else:
for v in value:
for o in v._outputs:
self._registerOutput(o, v)
return res
@internal
def _iter_stms_with_branches(self):
"""
:return: iterate statement with rank > 0
"""
startI = self.firstStmWithBranchesI
if startI is None:
return
elif startI is NOT_SPECIFIED:
# recompute firstStmWithBranchesI
startI = None
for i, stm in enumerate(self):
if stm.rank == 0:
continue
if startI is None:
startI = i
self.firstStmWithBranchesI = startI
else:
# use known firstStmWithBranchesI to skip not interesting
for stm in islice(self, startI, None):
if stm.rank == 0:
continue
yield stm
def sort(self, *args, **kwargs):
res = list.sort(self, *args, **kwargs)
self.firstStmWithBranchesI = None
return res
def replace(self, parentStm: HdlStatement, toReplaceStm: HdlStatement, index: int, replacement: List[HdlStatement]):
"""
Replace a single statement in this list with the list of statements while updating all cached values.
"""
parentStm.rank -= toReplaceStm.rank
self[index:index + 1] = replacement
for o in toReplaceStm._outputs:
self._unregisterOutput(o, toReplaceStm)
for rstm in replacement:
for o in rstm._outputs:
self._registerOutput(o, rstm)
rstm._set_parent_stm(parentStm, self)
def __deepcopy__(self, memo: dict):
cls = self.__class__
result = cls(deepcopy(i, memo) for i in self)
memo[id(self)] = result
return result
================================================
FILE: hwt/hdl/statements/utils/reduction.py
================================================
from itertools import islice, zip_longest
from typing import Tuple
from hwt.doc_markers import internal
from hwt.hdl.statements.assignmentContainer import HdlAssignmentContainer
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.pyUtils.arrayQuery import groupedby
from hwt.constants import NOT_SPECIFIED
@internal
def HdlStatement_merge_statement_lists(stmsA: ListOfHdlStatement, stmsB: ListOfHdlStatement)\
->ListOfHdlStatement:
"""
Merge two lists of statements into one
:return: list of merged statements
"""
if stmsA is None and stmsB is None:
return None
elif stmsA is None:
return stmsB
elif stmsB is None:
return stmsA
tmp = ListOfHdlStatement()
# copy all with already known not to merge
if stmsA.firstStmWithBranchesI is NOT_SPECIFIED:
# we need to check items ourselfs
a_it = iter(stmsA)
elif stmsA.firstStmWithBranchesI is not None:
# we know the first item which requires extra care, we can copy all predecessors
tmp.extend(islice(stmsA, 0, stmsA.firstStmWithBranchesI))
a_it = islice(stmsA, stmsA.firstStmWithBranchesI, None)
else:
# items do no require any care, we can copy them all, but instead we use original list
# to avoid copy
tmp = stmsA
a_it = iter(tuple())
if stmsB.firstStmWithBranchesI is not None:
tmp.extend(islice(stmsB, 0, stmsB.firstStmWithBranchesI))
b_it = islice(stmsB, stmsB.firstStmWithBranchesI, None)
else:
b_it = iter(stmsB)
a = None
b = None
a_empty = False
b_empty = False
while not a_empty and not b_empty:
while not a_empty:
a = next(a_it, None)
if a is None:
a_empty = True
break
elif a.rank == 0:
# simple statement does not require merging
tmp.append(a)
a = None
else:
break
while not b_empty:
b = next(b_it, None)
if b is None:
b_empty = True
break
elif b.rank == 0:
# simple statement does not require merging
tmp.append(b)
b = None
else:
break
if a is not None or b is not None:
if a is None:
a = b
b = None
if a is not None and b is not None:
a._merge_with_other_stm(b)
tmp.append(a)
a = None
b = None
return tmp
@internal
def HdlStatement_try_reduce_list(statements: ListOfHdlStatement)\
->Tuple[ListOfHdlStatement, int, bool]:
"""
Simplify statements in the list
"""
io_change = False
new_statements = ListOfHdlStatement()
for stm in statements:
reduced, _io_change = stm._try_reduce()
new_statements.extend(reduced)
io_change |= _io_change
new_statements, rank_decrease = HdlStatement_merge_statements(
new_statements)
new_statements, io_change, _rank_decrease = HdlStatement_reduce_overridden_assignments(new_statements)
rank_decrease += _rank_decrease
return new_statements, rank_decrease, io_change
@internal
def HdlStatement_reduce_overridden_assignments(statements: ListOfHdlStatement)\
->Tuple[ListOfHdlStatement, bool, int]:
io_change = False
new_statements = []
rank_decrease = 0
fully_driven_outputs = set()
for stm in reversed(statements):
if fully_driven_outputs.issuperset(stm._outputs):
rank_decrease += stm.rank
io_change = True
continue
if isinstance(stm, HdlAssignmentContainer):
fully_driven_outputs.update(stm._outputs)
new_statements.append(stm)
return ListOfHdlStatement(reversed(new_statements)), io_change, rank_decrease
@internal
def HdlStatement_merge_statements(statements: ListOfHdlStatement)\
->Tuple[ListOfHdlStatement, int]:
"""
Merge statements in list to remove duplicated if-then-else trees
:return: tuple (list of merged statements, rank decrease due merging)
:note: rank decrease is sum of ranks of reduced statements
:attention: statement list has to me mergable
"""
order = {}
for i, stm in enumerate(statements):
order[stm] = i
new_statements = ListOfHdlStatement()
rank_decrease = 0
for rank, stms in groupedby(statements, lambda s: s.rank):
if rank == 0:
new_statements.extend(stms)
else:
if len(stms) == 1:
new_statements.extend(stms)
continue
# try to merge statements if they are same condition tree
for iA, stmA in enumerate(stms):
if stmA is None:
continue
for iB, stmB in enumerate(islice(stms, iA + 1, None)):
if stmB is None:
continue
if stmA._is_mergable(stmB):
rank_decrease += stmB.rank
stmA._merge_with_other_stm(stmB)
stms[iA + 1 + iB] = None
new_statements.append(stmA)
new_statements.sort(key=lambda stm: order[stm])
return new_statements, rank_decrease
@internal
def is_mergable_statement_list(stmsA: ListOfHdlStatement, stmsB: ListOfHdlStatement):
"""
Walk statements and compare if they can be merged into one statement list
"""
if stmsA is None and stmsB is None:
return True
elif stmsA is None or stmsB is None:
return False
# [todo] there is a performance error when the list has no statements with rank != 0
# all items needs to be checked everytime, for "rtl register if (clk)" statements
# this is a problem as this list can grow large (100K+ items) and needs to be compared with every
# not yet merged statement
for (a, b) in zip_longest(stmsA._iter_stms_with_branches(),
stmsB._iter_stms_with_branches()):
if a is None or b is None or not a._is_mergable(b):
return False
# lists are empty
return True
================================================
FILE: hwt/hdl/statements/utils/signalCut.py
================================================
from typing import List
from hwt.doc_markers import internal
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.mainBases import RtlSignalBase
@internal
def HdlStatement_cut_off_drivers_of_list(sig: RtlSignalBase,
statements: ListOfHdlStatement,
keep_mask: List[bool],
new_statements: ListOfHdlStatement) -> bool:
"""
Cut all logic from statements which drives signal sig.
:param sig: signal which drivers should be removed
:param statements: list of statements to filter
:param keep_mask: list of flags if True statements was driver only of sig
:param new_statements: output list of filtered statements
:return: True if all input statements were reduced
"""
all_cut_off = True
for stm in statements:
if sig in stm._outputs:
newStm = stm._cut_off_drivers_of(sig)
keep = True
if newStm is None:
# statement is des not have drivers of sig
all_cut_off = False
elif newStm is stm:
# statement drives only sig
keep = False
new_statements.append(newStm)
else:
# statement was splited on multiple statements
all_cut_
gitextract_3m5zlo_2/
├── .circleci/
│ └── config.yml
├── .coveragerc
├── .gitignore
├── .readthedocs.yml
├── LICENSE
├── MANIFEST.in
├── README.md
├── doc/
│ ├── conf.py
│ ├── gtkwave.rst
│ ├── hwtCircuitNormalForm.rst
│ ├── index.rst
│ ├── requirements.doc.txt
│ └── requirements.txt
├── hwt/
│ ├── __init__.py
│ ├── code.py
│ ├── code_utils.py
│ ├── constants.py
│ ├── constraints.py
│ ├── doc_markers.py
│ ├── hObjList.py
│ ├── hdl/
│ │ ├── __init__.py
│ │ ├── commonConstants.py
│ │ ├── const.py
│ │ ├── constUtils.py
│ │ ├── frameTmpl.py
│ │ ├── frameTmplUtils.py
│ │ ├── hdlObject.py
│ │ ├── operator.py
│ │ ├── operatorDefs.py
│ │ ├── operatorUtils.py
│ │ ├── portItem.py
│ │ ├── sensitivityCtx.py
│ │ ├── statements/
│ │ │ ├── __init__.py
│ │ │ ├── assignmentContainer.py
│ │ │ ├── codeBlockContainer.py
│ │ │ ├── ifContainter.py
│ │ │ ├── statement.py
│ │ │ ├── switchContainer.py
│ │ │ └── utils/
│ │ │ ├── __init__.py
│ │ │ ├── comparison.py
│ │ │ ├── ioDiscovery.py
│ │ │ ├── listOfHdlStatements.py
│ │ │ ├── reduction.py
│ │ │ └── signalCut.py
│ │ ├── transPart.py
│ │ ├── transTmpl.py
│ │ ├── types/
│ │ │ ├── __init__.py
│ │ │ ├── array.py
│ │ │ ├── arrayCast.py
│ │ │ ├── arrayConst.py
│ │ │ ├── bitConstFunctions.py
│ │ │ ├── bitConstFunctionsGetitem.py
│ │ │ ├── bitConst_opReduce.py
│ │ │ ├── bits.py
│ │ │ ├── bitsCast.py
│ │ │ ├── bitsCastUtils.py
│ │ │ ├── bitsConst.py
│ │ │ ├── bitsRtlSignal.py
│ │ │ ├── defs.py
│ │ │ ├── enum.py
│ │ │ ├── enumConst.py
│ │ │ ├── float.py
│ │ │ ├── floatConst.py
│ │ │ ├── function.py
│ │ │ ├── hdlType.py
│ │ │ ├── slice.py
│ │ │ ├── sliceConst.py
│ │ │ ├── sliceUtils.py
│ │ │ ├── stream.py
│ │ │ ├── streamConst.py
│ │ │ ├── string.py
│ │ │ ├── stringConst.py
│ │ │ ├── struct.py
│ │ │ ├── structCast.py
│ │ │ ├── structUtils.py
│ │ │ ├── structValBase.py
│ │ │ ├── typeCast.py
│ │ │ ├── union.py
│ │ │ └── utils.py
│ │ └── variables.py
│ ├── hwIO.py
│ ├── hwIOs/
│ │ ├── __init__.py
│ │ ├── agents/
│ │ │ ├── __init__.py
│ │ │ ├── bramPort.py
│ │ │ ├── fifo.py
│ │ │ ├── rdSync.py
│ │ │ ├── rdVldSync.py
│ │ │ ├── regCntrl.py
│ │ │ ├── signal.py
│ │ │ ├── struct.py
│ │ │ ├── tuleWithCallback.py
│ │ │ ├── union.py
│ │ │ ├── universalComposite.py
│ │ │ └── vldSync.py
│ │ ├── hwIOArray.py
│ │ ├── hwIODifferential.py
│ │ ├── hwIOStruct.py
│ │ ├── hwIOTristate.py
│ │ ├── hwIOUnion.py
│ │ ├── hwIO_map.py
│ │ ├── signalOps.py
│ │ ├── std.py
│ │ ├── std_ip_defs.py
│ │ └── utils.py
│ ├── hwModule.py
│ ├── hwParam.py
│ ├── mainBases.py
│ ├── math.py
│ ├── mathAutoExt.py
│ ├── pyUtils/
│ │ ├── __init__.py
│ │ ├── arrayQuery.py
│ │ ├── fileHelpers.py
│ │ ├── setList.py
│ │ ├── testUtils.py
│ │ └── typingFuture.py
│ ├── serializer/
│ │ ├── __init__.py
│ │ ├── combLoopAnalyzer/
│ │ │ ├── __init__.py
│ │ │ └── tarjan.py
│ │ ├── exceptions.py
│ │ ├── generic/
│ │ │ ├── __init__.py
│ │ │ ├── constant_cache.py
│ │ │ ├── indent.py
│ │ │ ├── ops.py
│ │ │ ├── tmpVarConstructor.py
│ │ │ ├── to_hdl_ast.py
│ │ │ ├── utils.py
│ │ │ └── value.py
│ │ ├── hwt/
│ │ │ ├── __init__.py
│ │ │ ├── context.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ ├── ip_packager.py
│ │ ├── mode.py
│ │ ├── resourceAnalyzer/
│ │ │ ├── __init__.py
│ │ │ ├── analyzer.py
│ │ │ ├── resourceTypes.py
│ │ │ └── utils.py
│ │ ├── serializer_config.py
│ │ ├── serializer_filter.py
│ │ ├── simModel/
│ │ │ ├── __init__.py
│ │ │ ├── serializer.py
│ │ │ ├── tmpVarConstructorConstOnly.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ ├── store_manager.py
│ │ ├── systemC/
│ │ │ ├── __init__.py
│ │ │ ├── expr.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── type.py
│ │ │ └── utils.py
│ │ ├── utils.py
│ │ ├── verilog/
│ │ │ ├── __init__.py
│ │ │ ├── context.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── types.py
│ │ │ ├── utils.py
│ │ │ └── value.py
│ │ ├── vhdl/
│ │ │ ├── __init__.py
│ │ │ ├── ops.py
│ │ │ ├── serializer.py
│ │ │ ├── statements.py
│ │ │ ├── types.py
│ │ │ └── value.py
│ │ └── xdc/
│ │ ├── __init__.py
│ │ └── serializer.py
│ ├── simulator/
│ │ ├── __init__.py
│ │ ├── agentBase.py
│ │ ├── agentConnector.py
│ │ ├── rtlSimulator.py
│ │ ├── rtlSimulatorJson.py
│ │ ├── rtlSimulatorVcd.py
│ │ ├── simTestCase.py
│ │ └── utils.py
│ ├── synth.py
│ └── synthesizer/
│ ├── __init__.py
│ ├── componentPath.py
│ ├── dummyPlatform.py
│ ├── exceptions.py
│ ├── interfaceLevel/
│ │ ├── __init__.py
│ │ ├── directionFns.py
│ │ ├── getDefaultClkRts.py
│ │ ├── hwModuleImplHelpers.py
│ │ ├── implDependent.py
│ │ ├── propDeclrCollector.py
│ │ └── utils.py
│ ├── rtlLevel/
│ │ ├── __init__.py
│ │ ├── exceptions.py
│ │ ├── extract_part_drivers.py
│ │ ├── fill_stm_list_with_enclosure.py
│ │ ├── mark_visibility_of_signals_and_check_drivers.py
│ │ ├── netlist.py
│ │ ├── reduce_processes.py
│ │ ├── remove_unconnected_signals.py
│ │ ├── rtlNetlistPass.py
│ │ ├── rtlSignal.py
│ │ ├── rtlSignalWalkers.py
│ │ └── statements_to_HdlStmCodeBlockContainers.py
│ ├── typePath.py
│ └── vectorUtils.py
├── pyproject.toml
├── setup.cfg
└── tests/
├── __init__.py
└── all.py
SYMBOL INDEX (1669 symbols across 173 files)
FILE: doc/conf.py
function skip (line 191) | def skip(app, what, name, obj, skip, options):
function setup (line 197) | def setup(app):
FILE: hwt/code.py
class CodeBlock (line 25) | class CodeBlock(HdlStmCodeBlockContainer):
method __init__ (line 30) | def __init__(self, *statements: Sequence[HdlStatement]):
class If (line 40) | class If(IfContainer):
method __init__ (line 45) | def __init__(self, cond: Union[RtlSignalBase, HwIOBase], *statements: ...
method Elif (line 68) | def Elif(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequ...
method Else (line 86) | def Else(self, *statements: Sequence[HdlStatement]):
class Switch (line 99) | class Switch(SwitchContainer):
method __init__ (line 104) | def __init__(self, switchOn: Union[RtlSignalBase, HwIOBase]):
method add_cases (line 117) | def add_cases(self, tupesValStms: Sequence[Tuple[Union[HConst, int], S...
method Case (line 127) | def Case(self, caseVal: Union[HConst, int], *statements: Sequence[HdlS...
method Default (line 145) | def Default(self, *statements: Sequence[HdlStatement]):
function SwitchLogic (line 155) | def SwitchLogic(cases: Sequence[Tuple[Union[RtlSignalBase, HwIOBase, HCo...
function In (line 210) | def In(sigOrConst: Union[RtlSignalBase, HwIOBase, HConst], iterable: Seq...
function StaticForEach (line 227) | def StaticForEach(parentModule: HwModuleBase, items, bodyFn, name=""):
class FsmBuilder (line 276) | class FsmBuilder(Switch):
method __init__ (line 283) | def __init__(self, parentModule: HwModuleBase, stateT, stateRegName="s...
method Trans (line 297) | def Trans(self, stateFrom, *condAndNextState):
method Default (line 335) | def Default(self, *condAndNextState):
function ror (line 350) | def ror(sig:Union[RtlSignalBase, HConst], howMany: int) -> RtlSignalBase:
function rol (line 369) | def rol(sig:Union[RtlSignalBase, HConst], howMany:Union[RtlSignalBase, i...
function replicate (line 388) | def replicate(n:int, v:Union[RtlSignalBase, HConst]):
function segment_get (line 393) | def segment_get(n:Union[RtlSignalBase, HConst],
function split_to_segments (line 402) | def split_to_segments(n:Union[RtlSignalBase, HConst], maxSegmentWidth:in...
FILE: hwt/code_utils.py
function rename_signal (line 11) | def rename_signal(hwModule: "HwModule",
function connect_optional (line 35) | def connect_optional(src: HwIOBase, dst: HwIOBase,
function _connect_optional (line 47) | def _connect_optional(src: HwIOBase, dst: HwIOBase, check_fn, dir_reverse):
function _HwIOToRtlSignal (line 75) | def _HwIOToRtlSignal(obj):
function _mkOp (line 83) | def _mkOp(fn):
FILE: hwt/constants.py
class NOT_SPECIFIED (line 15) | class NOT_SPECIFIED():
method __init__ (line 23) | def __init__(self):
FILE: hwt/constraints.py
class iHdlConstrain (line 17) | class iHdlConstrain():
method _get_parent (line 19) | def _get_parent(self) -> HwModule:
method _copy_with_root_upadate (line 22) | def _copy_with_root_upadate(self, old_path_prefix, new_path_prefix):
method register_on_parent (line 25) | def register_on_parent(self):
function _get_parent_HwModule (line 29) | def _get_parent_HwModule(path: Tuple[Union[HwModule, HwIO, RtlSignal, iH...
function _get_absolute_path (line 43) | def _get_absolute_path(obj) -> Union[Tuple[Union[HwModule, HwIO, RtlSign...
function _apply_path_update (line 55) | def _apply_path_update(path: ComponentPath, old_path_prefix: ComponentPa...
class set_max_delay (line 64) | class set_max_delay(iHdlConstrain):
method __init__ (line 75) | def __init__(self,
method _copy_with_root_upadate (line 88) | def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_...
method _get_parent (line 96) | def _get_parent(self) -> HwModule:
class set_false_path (line 100) | class set_false_path(iHdlConstrain):
method __init__ (line 102) | def __init__(self, start: Union[None, HwIO, RtlSignal],
method _copy_with_root_upadate (line 110) | def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_...
method _get_parent (line 113) | def _get_parent(self) -> HwModule:
class get_clock_of (line 120) | class get_clock_of(iHdlConstrain):
method __init__ (line 122) | def __init__(self, obj: Union[HwIO, RtlSignal],
method _copy_with_root_upadate (line 126) | def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_...
method _get_parent (line 132) | def _get_parent(self) -> HwModule:
class set_async_reg (line 136) | class set_async_reg(iHdlConstrain):
method __init__ (line 144) | def __init__(self, sig: RtlSignal,
method _copy_with_root_upadate (line 150) | def _copy_with_root_upadate(self, old_path_prefix: ComponentPath, new_...
method _get_parent (line 156) | def _get_parent(self) -> HwModule:
FILE: hwt/doc_markers.py
function internal (line 3) | def internal(fn):
function hwt_expr_producer (line 10) | def hwt_expr_producer(fn):
FILE: hwt/hObjList.py
class HObjList (line 10) | class HObjList(list[T]):
method __init__ (line 26) | def __init__(self, *args, **kwargs):
method _on_append (line 33) | def _on_append(self, self_obj: Self, item: T, index: int):
method append (line 36) | def append(self, item: T):
method clear (line 41) | def clear(self, *args, **kwargs):
method extend (line 45) | def extend(self, iterable: Iterable[T]):
method insert (line 52) | def insert(self, *args, **kwargs):
method pop (line 56) | def pop(self, *args, **kwargs) -> T:
method remove (line 60) | def remove(self, *args, **kwargs):
method reverse (line 64) | def reverse(self, *args, **kwargs):
method sort (line 68) | def sort(self, *args, **kwargs):
method _getHdlName (line 72) | def _getHdlName(self):
method _getFullName (line 126) | def _getFullName(self) -> str:
method _make_association (line 145) | def _make_association(self, *args, **kwargs):
method _updateHwParamsFrom (line 155) | def _updateHwParamsFrom(self, *args, **kwargs):
method _cleanRtlSignals (line 164) | def _cleanRtlSignals(self, lockNonExternal=True):
FILE: hwt/hdl/const.py
class HConst (line 11) | class HConst(Generic[T]):
method __init__ (line 19) | def __init__(self, dtype: "HdlType", val, vld_mask):
method _is_full_valid (line 29) | def _is_full_valid(self):
method _is_partially_valid (line 32) | def _is_partially_valid(self) -> bool:
method _auto_cast (line 35) | def _auto_cast(self, toType: "HdlType"):
method _reinterpret_cast (line 43) | def _reinterpret_cast(self, toType: "HdlType"):
method staticEval (line 51) | def staticEval(self) -> Self:
method __copy__ (line 54) | def __copy__(self) -> Self:
method __hash__ (line 58) | def __hash__(self) -> int:
method __repr__ (line 61) | def __repr__(self) -> str:
method _from_py (line 70) | def _from_py(cls, typeObj, val, vld_mask) -> Self:
method from_py (line 77) | def from_py(cls, typeObj, val, vld_mask=None) -> Self:
method __eq__ (line 81) | def __eq__(self, other):
method _eq (line 89) | def _eq(self, other):
method __ne__ (line 92) | def __ne__(self, other):
method _walk_sensitivity (line 97) | def _walk_sensitivity(self, casualSensitivity: Set[RtlSignalBase], see...
function areHConsts (line 104) | def areHConsts(*items):
FILE: hwt/hdl/constUtils.py
function isSameHConst (line 6) | def isSameHConst(a: HConst, b: HConst) -> bool:
function areSameHConsts (line 17) | def areSameHConsts(a: Union[None, List[HConst]],
FILE: hwt/hdl/frameTmpl.py
class FrameTmpl (line 17) | class FrameTmpl(object):
method __init__ (line 38) | def __init__(self, origin: HdlType,
method framesFromTransTmpl (line 68) | def framesFromTransTmpl(transaction: 'TransTmpl',
method _wordIndx (line 209) | def _wordIndx(self, addr: int):
method getWordCnt (line 215) | def getWordCnt(self):
method walkWords (line 221) | def walkWords(self, showPadding: bool=False)\
method fieldToDataDict (line 307) | def fieldToDataDict(dtype, data, res):
method _fieldToDataDict (line 311) | def _fieldToDataDict(dtype, path, data, res):
method packData (line 338) | def packData(self, data):
method __repr__getName (line 381) | def __repr__getName(self, transPart: TransPart, fieldWidth: int):
method __repr__word (line 402) | def __repr__word(self,
method __repr__ (line 437) | def __repr__(self, scale=1):
FILE: hwt/hdl/frameTmplUtils.py
function iterSort (line 9) | def iterSort(iterators, cmpFn):
class TransPartGroup (line 73) | class TransPartGroup(list):
method setIsLast (line 77) | def setIsLast(self, val: bool) -> None:
method isLastPart (line 80) | def isLastPart(self) -> bool:
method getBusWordBitRange (line 87) | def getBusWordBitRange(self) -> Tuple[int, int]:
method bit_length (line 94) | def bit_length(self):
method __repr__ (line 97) | def __repr__(self):
class ChoicesOfFrameParts (line 101) | class ChoicesOfFrameParts(TransPartGroup):
method __init__ (line 113) | def __init__(self, startOfPart: int, origin: OneOfTransaction):
method resolveEnd (line 120) | def resolveEnd(self):
class ChoiceOfFrameParts (line 128) | class ChoiceOfFrameParts(list):
method __init__ (line 134) | def __init__(self, origin, tmpl):
method __repr__ (line 138) | def __repr__(self):
function groupIntoChoices (line 142) | def groupIntoChoices(splitsOnWord, wordWidth: int, origin: OneOfTransact...
class TransTmplWordIterator (line 181) | class TransTmplWordIterator():
method __init__ (line 186) | def __init__(self, wordWidth):
method fullWordCnt (line 189) | def fullWordCnt(self, start: int, end: int):
method groupByWordIndex (line 196) | def groupByWordIndex(self, transaction: 'TransTmpl', offset: int):
method splitOnWords (line 224) | def splitOnWords(self, transaction, addrOffset=0):
FILE: hwt/hdl/hdlObject.py
class HdlObject (line 6) | class HdlObject():
method __repr__ (line 12) | def __repr__(self):
FILE: hwt/hdl/operator.py
function getCtxFromOps (line 15) | def getCtxFromOps(operands: Sequence):
function isConst (line 22) | def isConst(item: Union[HConst, RtlSignalBase]):
class HOperatorNode (line 29) | class HOperatorNode(HdlObject):
method __init__ (line 39) | def __init__(self, operator: HOperatorDef,
method staticEval (line 46) | def staticEval(self):
method _walk_sensitivity (line 55) | def _walk_sensitivity(self, casualSensitivity: Set[RtlSignal], seen: S...
method _walk_public_drivers (line 73) | def _walk_public_drivers(self, seen: set) -> Generator["RtlSignal", No...
method withRes (line 84) | def withRes(opDef: HOperatorDef, operands: Sequence[Union[RtlSignalBas...
method _replace_input (line 146) | def _replace_input(self, inp: RtlSignal, replacement: RtlSignal):
method _destroy (line 204) | def _destroy(self):
FILE: hwt/hdl/operatorDefs.py
function _getVal (line 11) | def _getVal(v):
class HOperatorDef (line 18) | class HOperatorDef():
method __init__ (line 27) | def __init__(self, evalFn, allowsAssignTo=False, idStr:Optional[str]=N...
method __eq__ (line 33) | def __eq__(self, other):
method __hash__ (line 37) | def __hash__(self):
method eval (line 40) | def eval(self, operator, simulator=None):
method __repr__ (line 46) | def __repr__(self):
function isEventDependentOp (line 50) | def isEventDependentOp(operator):
function onRisingEdgeFn (line 54) | def onRisingEdgeFn(a):
function onFallingEdgeFn (line 58) | def onFallingEdgeFn(a):
function dotOpFn (line 62) | def dotOpFn(a, name):
function downtoFn (line 67) | def downtoFn(a: int, b: int):
function toFn (line 71) | def toFn(a: int, b: int):
function concatFn (line 75) | def concatFn(a: "AnyHBitsValue", b: "AnyHBitsValue") -> "AnyHBitsValue":
function power (line 79) | def power(base, exp):
function eqFn (line 83) | def eqFn(a, b):
function ternaryFn (line 87) | def ternaryFn(cond: "AnyHBitsValue", vTrue, vFalse):
function callFn (line 91) | def callFn(fn: "HdlFunctionDef", *operands, **kwargs):
function bitsToIntFn (line 95) | def bitsToIntFn(a: "AnyHBitsValue"):
function intToBitsFn (line 99) | def intToBitsFn(a: "AnyHBitsValue", t: "HdlType"):
function bitsAsSignedFn (line 103) | def bitsAsSignedFn(a: "AnyHBitsValue"):
function bitsAsUnsignedFn (line 107) | def bitsAsUnsignedFn(a: "AnyHBitsValue"):
function bitsAsVec (line 111) | def bitsAsVec(a: "AnyHBitsValue"):
function zextFn (line 115) | def zextFn(a: "AnyHBitsValue", newWidth: int):
function sextFn (line 119) | def sextFn(a: "AnyHBitsValue", newWidth: int):
function truncFn (line 123) | def truncFn(a: "AnyHBitsValue", newWidth: int):
class HwtOps (line 127) | class HwtOps():
FILE: hwt/hdl/operatorUtils.py
function _replace_input_in_expr (line 13) | def _replace_input_in_expr(expr: Union[RtlSignalBase, HConst], toReplace...
function replace_input_in_expr (line 56) | def replace_input_in_expr(topStatement: "HdlStatement",
FILE: hwt/hdl/portItem.py
class HdlPortItem (line 10) | class HdlPortItem():
method __init__ (line 19) | def __init__(self, name: str, direction: DIRECTION, dtype: HdlType, mo...
method fromSignal (line 28) | def fromSignal(cls, s: HdlSignalItem, component, d: DIRECTION):
method connectOuterSig (line 32) | def connectOuterSig(self, signal: RtlSignalBase):
method connectInternSig (line 59) | def connectInternSig(self, signal):
method getInternSig (line 82) | def getInternSig(self):
method getOuterSig (line 95) | def getOuterSig(self):
method _walk_sensitivity (line 108) | def _walk_sensitivity(self, casualSensitivity: set, seen: set, ctx: Se...
method __repr__ (line 115) | def __repr__(self):
FILE: hwt/hdl/sensitivityCtx.py
class SensitivityCtx (line 5) | class SensitivityCtx(SetList):
method __init__ (line 13) | def __init__(self, initSeq=None):
method extend (line 18) | def extend(self, items):
method clear (line 24) | def clear(self):
FILE: hwt/hdl/statements/assignmentContainer.py
class HdlAssignmentContainer (line 15) | class HdlAssignmentContainer(HdlStatement):
method __init__ (line 33) | def __init__(self, src: Union[RtlSignalBase, HConst], dst: RtlSignalBase,
method __deepcopy__ (line 72) | def __deepcopy__(self, memo: dict):
method _collect_inputs (line 81) | def _collect_inputs(self) -> None:
method _cut_off_drivers_of (line 94) | def _cut_off_drivers_of(self, sig: RtlSignalBase):
method _discover_enclosure (line 103) | def _discover_enclosure(self) -> None:
method _discover_sensitivity (line 113) | def _discover_sensitivity(self, seen: set) -> None:
method _fill_enclosure (line 129) | def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, HdlStatement]):
method _iter_stms (line 139) | def _iter_stms(self) -> Generator[HdlStatement, None, None]:
method _iter_stms_for_output (line 148) | def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[Hd...
method _on_parent_event_dependent (line 157) | def _on_parent_event_dependent(self):
method _try_reduce (line 165) | def _try_reduce(self) -> Tuple[ListOfHdlStatement, bool]:
method _is_mergable (line 173) | def _is_mergable(self, other: HdlStatement) -> bool:
method isSame (line 180) | def isSame(self, other):
method _nextInstId (line 194) | def _nextInstId(cls):
method _replace_input_nested (line 204) | def _replace_input_nested(self, topStm: HdlStatement, toReplace: Signa...
FILE: hwt/hdl/statements/codeBlockContainer.py
class HdlStmCodeBlockContainer (line 14) | class HdlStmCodeBlockContainer(HdlStatement):
method __init__ (line 26) | def __init__(self):
method from_known_io (line 34) | def from_known_io(cls, name: str, statements: ListOfHdlStatement,
method _try_reduce (line 48) | def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
method _iter_stms (line 57) | def _iter_stms(self) -> Generator[HdlStatement, None, None]:
method _iter_stms_for_output (line 65) | def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[Hd...
method _cut_off_drivers_of (line 73) | def _cut_off_drivers_of(self, sig: RtlSignalBase):
method _replace_child_statement (line 107) | def _replace_child_statement(self, stm:HdlStatement,
FILE: hwt/hdl/statements/ifContainter.py
class IfContainer (line 26) | class IfContainer(HdlStatement):
method __init__ (line 38) | def __init__(self, cond: RtlSignalBase, ifTrue=None, ifFalse=None, elI...
method __deepcopy__ (line 68) | def __deepcopy__(self, memo: dict):
method _collect_io (line 76) | def _collect_io(self):
method _collect_inputs (line 89) | def _collect_inputs(self) -> None:
method _clean_signal_meta (line 102) | def _clean_signal_meta(self):
method _cut_off_drivers_of (line 114) | def _cut_off_drivers_of(self, sig: RtlSignalBase):
method _discover_enclosure (line 177) | def _discover_enclosure(self):
method _discover_sensitivity (line 210) | def _discover_sensitivity(self, seen: set) -> None:
method _fill_enclosure (line 250) | def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], ...
method _iter_stms (line 275) | def _iter_stms(self) -> Generator[HdlStatement, None, None]:
method _iter_stms_for_output (line 287) | def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[Hd...
method _iter_all_elifs (line 298) | def _iter_all_elifs(self) -> Generator[Tuple[RtlSignalBase, ListOfHdlS...
method _try_reduce (line 304) | def _try_reduce(self) -> Tuple[bool, ListOfHdlStatement]:
method _merge_nested_if_from_else (line 350) | def _merge_nested_if_from_else(self, ifStm: "IfContainer"):
method _is_mergable (line 362) | def _is_mergable(self, other: HdlStatement) -> bool:
method _merge_with_other_stm (line 384) | def _merge_with_other_stm(self, other: "IfContainer") -> None:
method _condHasEffect (line 406) | def _condHasEffect(ifTrue, ifFalse, elIfs):
method isSame (line 422) | def isSame(self, other: HdlStatement) -> bool:
method _replace_input_nested (line 453) | def _replace_input_nested(self, topStm: HdlStatement, toReplace: Signa...
method _replace_child_statement (line 484) | def _replace_child_statement(self, stm:HdlStatement,
FILE: hwt/hdl/statements/statement.py
class HwtSyntaxError (line 12) | class HwtSyntaxError(Exception):
class HdlStatement (line 18) | class HdlStatement(HdlObject):
method __init__ (line 36) | def __init__(self, parentStm:Optional["HdlStatement"]=None,
method __deepcopy__ (line 51) | def __deepcopy__(self, memo: dict):
method _clean_signal_meta (line 70) | def _clean_signal_meta(self):
method _collect_io (line 81) | def _collect_io(self) -> None:
method _collect_inputs (line 98) | def _collect_inputs(self) -> None:
method _collect_outputs (line 109) | def _collect_outputs(self) -> None:
method _try_cut_off_whole_stm (line 125) | def _try_cut_off_whole_stm(self, sig: RtlSignalBase) -> bool:
method _cut_off_drivers_of (line 150) | def _cut_off_drivers_of(self, sig: RtlSignalBase) -> Union[None, "HdlS...
method _cut_off_drivers_of_regenerate_io (line 161) | def _cut_off_drivers_of_regenerate_io(self, cut_off_sig: RtlSignalBase...
method _discover_enclosure (line 186) | def _discover_enclosure(self) -> None:
method _discover_sensitivity (line 195) | def _discover_sensitivity(self, seen: set) -> None:
method _fill_enclosure (line 203) | def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], ...
method _get_rtl_context (line 213) | def _get_rtl_context(self) -> 'RtlNetlist':
method _iter_stms (line 228) | def _iter_stms(self):
method _iter_stms_for_output (line 237) | def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator["H...
method _merge_with_other_stm (line 245) | def _merge_with_other_stm(self, other: "HdlStatement") -> None:
method _on_reduce (line 254) | def _on_reduce(self, self_reduced: bool, io_changed: bool,
method _on_merge (line 307) | def _on_merge(self, other: "HdlStatement"):
method _try_reduce (line 344) | def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
method _is_enclosed (line 349) | def _is_enclosed(self) -> bool:
method _is_mergable (line 356) | def _is_mergable(self, other: "HdlStatement") -> bool:
method _on_parent_event_dependent (line 365) | def _on_parent_event_dependent(self):
method _set_parent_stm (line 376) | def _set_parent_stm(self, parentStm: "HdlStatement", parentStmList: "L...
method _register_stements (line 417) | def _register_stements(self, statements: List["HdlStatement"],
method isSame (line 428) | def isSame(self, other: "HdlStatement") -> bool:
method _destroy (line 435) | def _destroy(self):
method _replace_input_nested (line 459) | def _replace_input_nested(self, topStm: "HdlStatement", toReplace: Sig...
method _replace_input (line 463) | def _replace_input(self, toReplace: SignalReplaceSpecType) -> bool:
method _replace_input_update_sensitivity_and_inputs (line 474) | def _replace_input_update_sensitivity_and_inputs(
method _replace_child_statement (line 491) | def _replace_child_statement(self, stm: "HdlStatement",
FILE: hwt/hdl/statements/switchContainer.py
class SwitchContainer (line 27) | class SwitchContainer(HdlStatement):
method __init__ (line 41) | def __init__(self, switchOn: RtlSignal,
method __deepcopy__ (line 63) | def __deepcopy__(self, memo: dict):
method _cut_off_drivers_of (line 74) | def _cut_off_drivers_of(self, sig: RtlSignalBase):
method _clean_signal_meta (line 144) | def _clean_signal_meta(self):
method _collect_io (line 154) | def _collect_io(self):
method _collect_inputs (line 167) | def _collect_inputs(self) -> None:
method _discover_enclosure (line 180) | def _discover_enclosure(self) -> None:
method _discover_sensitivity (line 213) | def _discover_sensitivity(self, seen) -> None:
method _fill_enclosure (line 233) | def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, Callable[[], ...
method _iter_stms (line 259) | def _iter_stms(self) -> Generator[HdlStatement, None, None]:
method _iter_stms_for_output (line 271) | def _iter_stms_for_output(self, output: RtlSignalBase) -> Generator[Hd...
method _is_mergable (line 283) | def _is_mergable(self, other) -> bool:
method _merge_with_other_stm (line 303) | def _merge_with_other_stm(self, other: "SwitchContainer") -> None:
method _try_reduce (line 321) | def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
method _condHasEffect (line 372) | def _condHasEffect(self) -> bool:
method _replace_input_nested (line 399) | def _replace_input_nested(self, topStm: "HdlStatement", toReplace: Sig...
method _replace_child_statement (line 422) | def _replace_child_statement(self, stm: HdlStatement,
method isSame (line 449) | def isSame(self, other: HdlStatement) -> bool:
FILE: hwt/hdl/statements/utils/comparison.py
function isSameStatementList (line 4) | def isSameStatementList(stmListA: ListOfHdlStatement,
function statementsAreSame (line 21) | def statementsAreSame(statements: ListOfHdlStatement) -> bool:
FILE: hwt/hdl/statements/utils/ioDiscovery.py
function HdlStatement_discover_enclosure_for_statements (line 9) | def HdlStatement_discover_enclosure_for_statements(
FILE: hwt/hdl/statements/utils/listOfHdlStatements.py
class ListOfHdlStatement (line 11) | class ListOfHdlStatement(list):
method __init__ (line 16) | def __init__(self, *args):
method append (line 24) | def append(self, v: HdlStatement):
method extend (line 33) | def extend(self, stms: Sequence[HdlStatement]):
method insert (line 37) | def insert(self, i: int, v: HdlStatement):
method pop (line 46) | def pop(self):
method remove (line 49) | def remove(self, item):
method discard (line 52) | def discard(self, item):
method iterStatementsWithOutput (line 55) | def iterStatementsWithOutput(self, out: RtlSignalBase):
method _unregisterOutput (line 58) | def _unregisterOutput(self, o: RtlSignalBase, stm: HdlStatement):
method _registerOutput (line 61) | def _registerOutput(self, o: RtlSignalBase, stm: HdlStatement):
method __setitem__ (line 64) | def __setitem__(self, index:Union[int, slice], value:Union["ListOfHdlS...
method _iter_stms_with_branches (line 87) | def _iter_stms_with_branches(self):
method sort (line 113) | def sort(self, *args, **kwargs):
method replace (line 118) | def replace(self, parentStm: HdlStatement, toReplaceStm: HdlStatement,...
method __deepcopy__ (line 132) | def __deepcopy__(self, memo: dict):
FILE: hwt/hdl/statements/utils/reduction.py
function HdlStatement_merge_statement_lists (line 12) | def HdlStatement_merge_statement_lists(stmsA: ListOfHdlStatement, stmsB:...
function HdlStatement_try_reduce_list (line 94) | def HdlStatement_try_reduce_list(statements: ListOfHdlStatement)\
function HdlStatement_reduce_overridden_assignments (line 116) | def HdlStatement_reduce_overridden_assignments(statements: ListOfHdlStat...
function HdlStatement_merge_statements (line 138) | def HdlStatement_merge_statements(statements: ListOfHdlStatement)\
function is_mergable_statement_list (line 183) | def is_mergable_statement_list(stmsA: ListOfHdlStatement, stmsB: ListOfH...
FILE: hwt/hdl/statements/utils/signalCut.py
function HdlStatement_cut_off_drivers_of_list (line 9) | def HdlStatement_cut_off_drivers_of_list(sig: RtlSignalBase,
FILE: hwt/hdl/transPart.py
class TransPart (line 6) | class TransPart(object):
method __init__ (line 22) | def __init__(self, parent: 'FrameTmpl',
method bit_length (line 37) | def bit_length(self) -> int:
method getBusWordBitRange (line 43) | def getBusWordBitRange(self) -> Tuple[int, int]:
method getFieldBitRange (line 50) | def getFieldBitRange(self) -> Tuple[int, int]:
method isLastPart (line 58) | def isLastPart(self) -> bool:
method __repr__ (line 65) | def __repr__(self):
FILE: hwt/hdl/transTmpl.py
function _default_shouldEnterFn (line 16) | def _default_shouldEnterFn(transTmpl: 'TransTmpl') -> Tuple[bool, bool]:
class TransTmpl (line 20) | class TransTmpl(object):
method __init__ (line 44) | def __init__(self, dtype: HdlType, bitAddr: int=0,
method _loadFromBits (line 64) | def _loadFromBits(self, dtype: HdlType, bitAddr: int):
method _loadFromHStruct (line 73) | def _loadFromHStruct(self, dtype: HdlType, bitAddr: int):
method _loadFromUnion (line 101) | def _loadFromUnion(self, dtype: HdlType, bitAddr: int) -> int:
method _loadFromArray (line 116) | def _loadFromArray(self, dtype: HdlType, bitAddr: int) -> int:
method _loadFromHStream (line 131) | def _loadFromHStream(self, dtype: HStream, bitAddr: int) -> int:
method _loadFromHType (line 148) | def _loadFromHType(self, dtype: HdlType, bitAddr: int) -> None:
method bit_length (line 171) | def bit_length(self) -> int:
method HwIO_walkFlatten (line 177) | def HwIO_walkFlatten(self, offset: int=0,
method getFieldPath (line 235) | def getFieldPath(self):
method __deepcopy__ (line 246) | def __deepcopy__(self, memo):
method __repr__ (line 261) | def __repr__(self, offset: int=0):
class OneOfTransaction (line 295) | class OneOfTransaction(object):
method __init__ (line 311) | def __init__(self, parent: TransTmpl,
method walkFlattenChilds (line 320) | def walkFlattenChilds(self) -> Generator[
FILE: hwt/hdl/types/array.py
class HArray (line 7) | class HArray(HdlType):
method __init__ (line 15) | def __init__(self, element_t, size, const=False):
method __eq__ (line 20) | def __eq__(self, other):
method __hash__ (line 28) | def __hash__(self):
method bit_length (line 31) | def bit_length(self):
method get_reinterpret_cast_HConst_fn (line 52) | def get_reinterpret_cast_HConst_fn(cls):
method get_reinterpret_cast_RtlSignal_fn (line 59) | def get_reinterpret_cast_RtlSignal_fn(cls):
method getConstCls (line 66) | def getConstCls(cls):
method getRtlSignalCls (line 77) | def getRtlSignalCls(cls):
method isScalar (line 86) | def isScalar(self):
method __repr__ (line 89) | def __repr__(self, indent=0, withAddr=None, expandStructs=False):
FILE: hwt/hdl/types/arrayCast.py
function getBits_from_array (line 17) | def getBits_from_array(array: HArrayAnyValue, wordWidth: int, start: int...
function reinterptet_HArray_to_HBits (line 57) | def reinterptet_HArray_to_HBits(typeFrom: HArray, sigOrConst: HArrayAnyV...
function reinterpret_HArray_to_HArray (line 75) | def reinterpret_HArray_to_HArray(typeFrom: HArray, sigOrConst: HArrayAny...
function reinterpret_HArray_to_HStruct (line 103) | def reinterpret_HArray_to_HStruct(typeFrom: HArray, sigOrConst: HArrayAn...
function reinterpret_cast_HArray (line 109) | def reinterpret_cast_HArray(typeFrom: HArray, sigOrConst: HArrayAnyValue...
FILE: hwt/hdl/types/arrayConst.py
function _HArrayGetitem (line 19) | def _HArrayGetitem(self: Union["HArrayRtlSignal", "HArrayConst"], iamVal...
class HArrayRtlSignal (line 37) | class HArrayRtlSignal(RtlSignal):
method __getitem__ (line 39) | def __getitem__(self, key):
method __iter__ (line 47) | def __iter__(self):
method __call__ (line 53) | def __call__(self, source,
method __len__ (line 68) | def __len__(self):
class HArrayConst (line 72) | class HArrayConst(HConst):
method from_py (line 78) | def from_py(cls, typeObj, val, vld_mask=None):
method to_py (line 130) | def to_py(self):
method __hash__ (line 137) | def __hash__(self):
method _is_full_valid (line 141) | def _is_full_valid(self):
method _is_partially_valid (line 144) | def _is_partially_valid(self) -> bool:
method _getitem__const (line 148) | def _getitem__const(self, key):
method __getitem__ (line 165) | def __getitem__(self, key):
method __setitem__ (line 173) | def __setitem__(self, index: HBitsAnyIndexCompatibleValue, value) -> S...
method __iter__ (line 206) | def __iter__(self):
method __len__ (line 212) | def __len__(self):
method _eq (line 215) | def _eq(self, other):
FILE: hwt/hdl/types/bitConstFunctions.py
function bitsCmp_detect_useless_cmp (line 26) | def bitsCmp_detect_useless_cmp(op0: "HBitsRtlSignal", op1: "HBitsConst",...
function bitsCmp (line 61) | def bitsCmp(self: AnyHBitsValue, selfIsHConst: bool, other: HBitsAnyComp...
function extractNegation (line 165) | def extractNegation(sig: RtlSignalBase) -> tuple[AnyHBitsValue, bool]:
function bitsBitOp (line 180) | def bitsBitOp(self: Union[RtlSignalBase, HConst],
function bitsArithOp (line 272) | def bitsArithOp(self: AnyHBitsValue, selfIsHConst: bool, other: HBitsAny...
function bitsFloordiv (line 319) | def bitsFloordiv(self: AnyHBitsValue, selfIsHConst: bool, other: HBitsAn...
function _bitsMulModGetResultType (line 333) | def _bitsMulModGetResultType(myT: "HBits", otherT: "HBits"):
function bitsMul (line 359) | def bitsMul(self: AnyHBitsValue, selfIsHConst: bool, other: HBitsAnyComp...
function bitsRem (line 402) | def bitsRem(self: AnyHBitsValue, selfIsHConst: bool, other: HBitsAnyComp...
function bitsLshift (line 451) | def bitsLshift(self: AnyHBitsValue, shiftAmount: HBitsAnyCompatibleValue...
function bitsRshift (line 472) | def bitsRshift(self: AnyHBitsValue, shiftAmount: HBitsAnyCompatibleValue...
FILE: hwt/hdl/types/bitConstFunctionsGetitem.py
function _match_msb_get (line 19) | def _match_msb_get(v: "HBitsRtlSignal"):
function _fold_concat_of_msb_using_sext (line 37) | def _fold_concat_of_msb_using_sext(v: "HBitsRtlSignal", vReplicatinCount...
function _get_operator_i_am_the_result_of (line 69) | def _get_operator_i_am_the_result_of(const_or_sig: Union[RtlSignalBase, ...
function bitsGetitem_foldSliceOnCONCAT (line 77) | def bitsGetitem_foldSliceOnCONCAT(v: AnyHBitsValue, start:int, stop: int...
function bitsGetitem_foldSliceOnEXT (line 115) | def bitsGetitem_foldSliceOnEXT(v: AnyHBitsValue,
function bitsGetitem_foldBitGetOnEXT (line 145) | def bitsGetitem_foldBitGetOnEXT(v: AnyHBitsValue,
function bitsGetitem_foldBitGetOnConcat (line 165) | def bitsGetitem_foldBitGetOnConcat(v: AnyHBitsValue, key: HBitsAnyIndexC...
function bitsGetitem (line 188) | def bitsGetitem(v: AnyHBitsValue, iamConst:bool, key: HBitsAnyIndexCompa...
FILE: hwt/hdl/types/bitConst_opReduce.py
function tryReduceAnd (line 10) | def tryReduceAnd(sig:RtlSignalBase, val: HConst):
function tryReduceOr (line 25) | def tryReduceOr(sig:RtlSignalBase, val: HConst):
function tryReduceXor (line 43) | def tryReduceXor(sig:RtlSignalBase, val: HConst):
function reduceSigCheckFnAnd (line 60) | def reduceSigCheckFnAnd(op0Original:RtlSignalBase, op0Negated: bool, op1...
function reduceSigCheckFnOr (line 71) | def reduceSigCheckFnOr(op0Original:RtlSignalBase, op0Negated: bool, op1N...
function reduceSigCheckFnXor (line 83) | def reduceSigCheckFnXor(op0Original:RtlSignalBase, op0Negated: bool, op1...
FILE: hwt/hdl/types/bits.py
class HBits (line 15) | class HBits(HdlType, Bits3t):
method __init__ (line 20) | def __init__(self, bit_length: Union[int, "AnyHBitsValue"],
method _createMutated (line 38) | def _createMutated(self,
method domain_size (line 80) | def domain_size(self):
method get_auto_cast_HConst_fn (line 88) | def get_auto_cast_HConst_fn(cls):
method get_reinterpret_cast_HConst_fn (line 95) | def get_reinterpret_cast_HConst_fn(cls):
method get_auto_cast_RtlSignal_fn (line 101) | def get_auto_cast_RtlSignal_fn(cls):
method get_reinterpret_cast_RtlSignal_fn (line 108) | def get_reinterpret_cast_RtlSignal_fn(cls):
method getConstCls (line 115) | def getConstCls(cls):
method getRtlSignalCls (line 126) | def getRtlSignalCls(cls):
method getAllOnesValue (line 134) | def getAllOnesValue(self):
method __hash__ (line 137) | def __hash__(self):
method __eq__ (line 140) | def __eq__(self, other):
method __repr__ (line 145) | def __repr__(self, indent=0, withAddr=None, expandStructs=False):
FILE: hwt/hdl/types/bitsCast.py
function convertBits__HConst (line 26) | def convertBits__HConst(curType: HBits, val: "HBitsConst", toType: HdlTy...
function convertBits__RtlSignal (line 65) | def convertBits__RtlSignal(curType: HBits, sig: RtlSignal, toType: HdlTy...
function reinterpret_bits_to_hstruct__HConst (line 97) | def reinterpret_bits_to_hstruct__HConst(val: HConst, hStructT: HStruct):
function transfer_signals (line 120) | def transfer_signals(src: Union[HwIOBase, HObjList], dst: Union[HwIOBase...
function reinterpret_bits_to_hstruct__RtlSignal (line 141) | def reinterpret_bits_to_hstruct__RtlSignal(val: RtlSignal, hStructT: HSt...
function reinterpret_bits_to_harray (line 168) | def reinterpret_bits_to_harray(sigOrConst: Union[RtlSignal, HConst], hAr...
function reinterpretBits__HConst (line 187) | def reinterpretBits__HConst(curType: HBits, val: HConst, toType: HdlType):
function reinterpretBits__RtlSignal (line 207) | def reinterpretBits__RtlSignal(curType: HBits, sig: RtlSignal, toType: H...
FILE: hwt/hdl/types/bitsCastUtils.py
class BitWidthErr (line 6) | class BitWidthErr(Exception):
function fitTo_t (line 12) | def fitTo_t(what: Union["HBitsRtlSignal", "HBitsConst"], where_t: HBits,
function fitTo (line 46) | def fitTo(what: Union["HBitsRtlSignal", "HBitsConst"], where: Union["HBi...
FILE: hwt/hdl/types/bitsConst.py
class HBitsConst (line 26) | class HBitsConst(HConst, Bits3val):
method from_py (line 35) | def from_py(cls, typeObj, val, vld_mask=None) -> Self:
method _cast_sign (line 40) | def _cast_sign(self, signed:Union[bool, None]) -> Self:
method _signed (line 57) | def _signed(self) -> Self:
method _unsigned (line 60) | def _unsigned(self) -> Self:
method _vec (line 63) | def _vec(self) -> Self:
method _concat (line 67) | def _concat(self, other: Union[Self, "HBitsRtlSignal"]) -> Union[Self,...
method __getitem__ (line 84) | def __getitem__(self, key: HBitsAnyIndexCompatibleValue) -> Self:
method __setitem__ (line 92) | def __setitem__(self, index: HBitsAnyIndexCompatibleValue, value: Unio...
method __invert__ (line 126) | def __invert__(self) -> Self:
method __hash__ (line 134) | def __hash__(self):
method _isOn (line 138) | def _isOn(self):
method _eq (line 141) | def _eq(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBitsRtl...
method __ne__ (line 149) | def __ne__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __lt__ (line 157) | def __lt__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __gt__ (line 165) | def __gt__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __ge__ (line 173) | def __ge__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __le__ (line 181) | def __le__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __xor__ (line 190) | def __xor__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method __and__ (line 199) | def __and__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method __or__ (line 208) | def __or__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBits...
method __lshift__ (line 217) | def __lshift__(self, other: Union[int, Self]) -> Union[Self, "HBitsRtl...
method __rshift__ (line 225) | def __rshift__(self, other: Union[int, Self]) -> Union[Self, "HBitsRtl...
method __neg__ (line 233) | def __neg__(self) -> Self:
method __sub__ (line 242) | def __sub__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method __add__ (line 250) | def __add__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method __floordiv__ (line 258) | def __floordiv__(self, other: HBitsAnyCompatibleValue) -> Union[Self, ...
method __mul__ (line 266) | def __mul__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method __mod__ (line 274) | def __mod__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method _ternary (line 282) | def _ternary(self, vTrue: Union[Self, "HBitsRtlSignal"], vFalse: Union...
method __abs__ (line 298) | def __abs__(self):
method getMsb (line 303) | def getMsb(self) -> Self:
method __len__ (line 306) | def __len__(self) -> int:
method __eq__ (line 309) | def __eq__(self, other):
method prettyRepr (line 328) | def prettyRepr(self) -> str:
method __repr__ (line 353) | def __repr__(self) -> str:
FILE: hwt/hdl/types/bitsRtlSignal.py
class HBitsRtlSignal (line 29) | class HBitsRtlSignal(RtlSignal):
method _cast_sign (line 32) | def _cast_sign(self, signed: Optional[bool]) -> Self:
method _signed (line 57) | def _signed(self) -> Self:
method _unsigned (line 60) | def _unsigned(self) -> Self:
method _vec (line 63) | def _vec(self) -> Self:
method _concat (line 66) | def _concat(self, other: Union["HBitsConst", Self]) -> Self:
method _ext (line 126) | def _ext(self, newWidth: Union[int, "HBitsConst"], signed: Union[bool,...
method _sext (line 181) | def _sext(self, newWidth: Union[int, "HBitsConst"]) -> Self:
method _zext (line 188) | def _zext(self, newWidth: Union[int, "HBitsConst"]) -> Self:
method _trunc (line 195) | def _trunc(self, newWidth: Union[int, "HBitsConst"]):
method _extOrTrunc (line 242) | def _extOrTrunc(self, newWidth: int, signed: Union[bool, None, Literal...
method __getitem__ (line 245) | def __getitem__(self, key: HBitsAnyIndexCompatibleValue) -> Union["HBi...
method __setitem__ (line 256) | def __setitem__(self, index, value):
method __invert__ (line 259) | def __invert__(self) -> Self:
method __hash__ (line 269) | def __hash__(self) -> int:
method _isOn (line 273) | def _isOn(self) -> Self:
method _eq (line 276) | def _eq(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst", S...
method __ne__ (line 284) | def __ne__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __lt__ (line 292) | def __lt__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __gt__ (line 300) | def __gt__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __ge__ (line 308) | def __ge__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __le__ (line 316) | def __le__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __xor__ (line 325) | def __xor__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst...
method __and__ (line 334) | def __and__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst...
method __or__ (line 343) | def __or__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst"...
method __lshift__ (line 352) | def __lshift__(self, other: Union[int, "HBitsConst"]) -> Union[Self, "...
method __rshift__ (line 360) | def __rshift__(self, other: Union[int, "HBitsConst"]) -> Union[Self, "...
method __neg__ (line 368) | def __neg__(self) -> Self:
method __sub__ (line 378) | def __sub__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst...
method __add__ (line 386) | def __add__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst...
method __floordiv__ (line 394) | def __floordiv__(self, other: HBitsAnyCompatibleValue) -> Union["HBits...
method __mul__ (line 402) | def __mul__(self, other: HBitsAnyCompatibleValue) -> Union["HBitsConst...
method __mod__ (line 410) | def __mod__(self, other: HBitsAnyCompatibleValue) -> Union[Self, "HBit...
method _ternary (line 418) | def _ternary(self, vTrue: Union["HBitsConst", Self], vFalse: Union["HB...
method __abs__ (line 462) | def __abs__(self):
method getMsb (line 467) | def getMsb(self) -> Self:
method _onFallingEdge (line 470) | def _onFallingEdge(self) -> Self:
method _onRisingEdge (line 473) | def _onRisingEdge(self) -> Self:
method __len__ (line 476) | def __len__(self) -> int:
FILE: hwt/hdl/types/enum.py
class HEnum (line 7) | class HEnum(HdlType):
method __init__ (line 16) | def __init__(self, name, valueNames, const=False):
method all_mask (line 30) | def all_mask(self):
method bit_length (line 33) | def bit_length(self):
method domain_size (line 37) | def domain_size(self):
method getRtlSignalCls (line 46) | def getRtlSignalCls(cls):
method getConstCls (line 57) | def getConstCls(cls):
FILE: hwt/hdl/types/enumConst.py
class HEnumRtlSignal (line 13) | class HEnumRtlSignal(RtlSignal):
method _eq (line 15) | def _eq(self, other: Union[Self, "HEnumConst"]) -> "HBitsConst":
method __ne__ (line 19) | def __ne__(self, other: Union[Self, "HEnumConst"]) -> "HBitsConst":
class HEnumConst (line 24) | class HEnumConst(HConst):
method from_py (line 27) | def from_py(cls, typeObj, val, vld_mask=None):
method _eq (line 49) | def _eq(self, other: Union[HEnumRtlSignal, Self]) -> "HBitsConst":
method __ne__ (line 60) | def __ne__(self, other: Union[HEnumRtlSignal, Self]) -> "HBitsConst":
FILE: hwt/hdl/types/float.py
class HFloat (line 7) | class HFloat(HdlType, Floatt):
method __init__ (line 14) | def __init__(self, exponent_w, mantisa_w,
method getConstCls (line 28) | def getConstCls(cls):
method getRtlSignalCls (line 35) | def getRtlSignalCls(cls):
FILE: hwt/hdl/types/floatConst.py
function _HFloatEq (line 18) | def _HFloatEq(self, self_is_val: bool, other):
class HFloatRtlSignal (line 29) | class HFloatRtlSignal(RtlSignal):
method _eq (line 31) | def _eq(self, other):
class HFloatConst (line 35) | class HFloatConst(HConst, FloattVal):
method from_py (line 41) | def from_py(cls, typeObj, val, vld_mask=None):
method _is_full_valid (line 70) | def _is_full_valid(self):
method to_py (line 73) | def to_py(self):
method _eq (line 79) | def _eq(self, other):
method __copy__ (line 82) | def __copy__(self):
method __hash__ (line 88) | def __hash__(self):
FILE: hwt/hdl/types/function.py
class HFunction (line 7) | class HFunction(HdlType):
method all_mask (line 15) | def all_mask(self):
method getConstCls (line 21) | def getConstCls(cls):
class HFunctionConst (line 25) | class HFunctionConst(HConst):
FILE: hwt/hdl/types/hdlType.py
class MethodNotOverloaded (line 8) | class MethodNotOverloaded(NotImplementedError):
class HdlType (line 15) | class HdlType():
method __init__ (line 30) | def __init__(self, const=False):
method _from_py (line 33) | def _from_py(self, v, vld_mask) -> "HConst":
method from_py (line 39) | def from_py(self, v, vld_mask=None) -> "HConst":
method auto_cast_HConst (line 48) | def auto_cast_HConst(self, v: "HConst", toType: Self) -> "HConst":
method auto_cast_RtlSignal (line 72) | def auto_cast_RtlSignal(self, v: "RtlSignal", toType: Self) -> "RtlSig...
method reinterpret_cast_HConst (line 91) | def reinterpret_cast_HConst(self, v: "HConst", toType: Self) -> "HConst":
method reinterpret_cast_RtlSignal (line 113) | def reinterpret_cast_RtlSignal(self, v: "RtlSignal", toType: Self) -> ...
method _reverse_auto_cast_HConst (line 140) | def _reverse_auto_cast_HConst(self, v: "HConst", fromType: Self) -> "H...
method _reverse_auto_cast_RtlSignal (line 149) | def _reverse_auto_cast_RtlSignal(self, v: "RtlSignal", fromType: Self)...
method _reverse_reinterpret_cast_HConst (line 158) | def _reverse_reinterpret_cast_HConst(self, v: "HConst", fromType: Self...
method _reverse_reinterpret_cast_RtlSignal (line 167) | def _reverse_reinterpret_cast_RtlSignal(self, v: "RtlSignal", fromType...
method get_auto_cast_HConst_fn (line 180) | def get_auto_cast_HConst_fn(cls):
method get_auto_cast_RtlSignal_fn (line 185) | def get_auto_cast_RtlSignal_fn(cls):
method get_reverse_auto_cast_RtlSignal_fn (line 190) | def get_reverse_auto_cast_RtlSignal_fn(cls):
method get_reverse_auto_cast_HConst_fn (line 195) | def get_reverse_auto_cast_HConst_fn(cls):
method get_reinterpret_cast_HConst_fn (line 200) | def get_reinterpret_cast_HConst_fn(cls):
method get_reverse_reinterpret_cast_HConst_fn (line 205) | def get_reverse_reinterpret_cast_HConst_fn(cls):
method get_reinterpret_cast_RtlSignal_fn (line 210) | def get_reinterpret_cast_RtlSignal_fn(cls):
method get_reverse_reinterpret_cast_RtlSignal_fn (line 215) | def get_reverse_reinterpret_cast_RtlSignal_fn(cls):
method getConstCls (line 220) | def getConstCls(cls) -> Type["HConst"]:
method getRtlSignalCls (line 230) | def getRtlSignalCls(cls) -> Type["RtlSignal"]:
method _as_hdl (line 238) | def _as_hdl(self, to_Hdl: "ToHdlAst", declaration:bool):
method _as_hdl_requires_def (line 241) | def _as_hdl_requires_def(self, to_Hdl: "ToHdlAst", other_types: list):
method isScalar (line 244) | def isScalar(self):
method __getitem__ (line 247) | def __getitem__(self, key):
method __repr__ (line 255) | def __repr__(self, indent:int=0, withAddr:Optional[int]=None, expandSt...
function default_auto_cast_fn (line 270) | def default_auto_cast_fn(typeFrom: HdlType, sigOrConst: Union["RtlSignal...
function default_reverse_auto_cast_fn (line 275) | def default_reverse_auto_cast_fn(toType: HdlType, sigOrConst: Union["Rtl...
function default_reinterpret_cast_fn (line 280) | def default_reinterpret_cast_fn(fromType: HdlType, sigOrConst: Union["Rt...
function default_reverse_reinterpret_cast_fn (line 285) | def default_reverse_reinterpret_cast_fn(toType: HdlType, sigOrConst: Uni...
FILE: hwt/hdl/types/slice.py
class HSlice (line 6) | class HSlice(HdlType):
method getConstCls (line 13) | def getConstCls(cls):
method getRtlSignalCls (line 24) | def getRtlSignalCls(cls):
FILE: hwt/hdl/types/sliceConst.py
function slice_member_to_HConst (line 12) | def slice_member_to_HConst(v):
class HSliceRtlSignal (line 25) | class HSliceRtlSignal(RtlSignal):
class HSliceConst (line 29) | class HSliceConst(HConst):
method from_py (line 35) | def from_py(cls, typeObj, val, vld_mask=None):
method _is_full_valid (line 48) | def _is_full_valid(self) -> bool:
method _is_partially_valid (line 52) | def _is_partially_valid(self) -> bool:
method to_py (line 56) | def to_py(self):
method _size (line 63) | def _size(self):
method _eq (line 75) | def _eq(self, other):
method __lt__ (line 78) | def __lt__(self, other):
method __copy__ (line 86) | def __copy__(self):
method staticEval (line 91) | def staticEval(self):
method __hash__ (line 101) | def __hash__(self):
method __repr__ (line 105) | def __repr__(self):
FILE: hwt/hdl/types/sliceUtils.py
function slice_to_HSlice (line 8) | def slice_to_HSlice(sliceVals: slice, widthOfSlicedVec: int):
FILE: hwt/hdl/types/stream.py
class HStream (line 10) | class HStream(HdlType):
method __init__ (line 24) | def __init__(self, element_t,
method bit_length (line 39) | def bit_length(self):
method __eq__ (line 46) | def __eq__(self, other: HdlType):
method __hash__ (line 56) | def __hash__(self):
method getConstCls (line 62) | def getConstCls(cls):
method __repr__ (line 70) | def __repr__(self, indent=0, withAddr=None, expandStructs=False):
FILE: hwt/hdl/types/streamConst.py
class HStreamConst (line 10) | class HStreamConst(HConst):
method from_py (line 16) | def from_py(cls, typeObj, val, vld_mask=None):
method to_py (line 50) | def to_py(self):
method __hash__ (line 56) | def __hash__(self):
method _is_full_valid (line 59) | def _is_full_valid(self):
method _getitem__const (line 63) | def _getitem__const(self, key):
method __getitem__ (line 74) | def __getitem__(self, key):
method __setitem__ (line 92) | def __setitem__(self, index, value):
method __iter__ (line 116) | def __iter__(self):
method __len__ (line 119) | def __len__(self):
method _eq (line 122) | def _eq(self, other):
FILE: hwt/hdl/types/string.py
class HString (line 6) | class HString(HdlType):
method all_mask (line 11) | def all_mask(self):
method getConstCls (line 17) | def getConstCls(cls):
method getRtlSignalCls (line 28) | def getRtlSignalCls(cls):
FILE: hwt/hdl/types/stringConst.py
class HStringRtlSignal (line 9) | class HStringRtlSignal(RtlSignal):
method _eq (line 11) | def _eq(self, other):
class HStringConst (line 17) | class HStringConst(HConst):
method from_py (line 23) | def from_py(cls, typeObj, val, vld_mask=None):
method to_py (line 43) | def to_py(self):
method _eq (line 48) | def _eq(self, other):
FILE: hwt/hdl/types/struct.py
class HStructFieldMeta (line 13) | class HStructFieldMeta():
method __init__ (line 22) | def __init__(self, split=False):
method __eq__ (line 25) | def __eq__(self, other):
method __hash__ (line 31) | def __hash__(self):
class HStructField (line 35) | class HStructField(object):
method __init__ (line 40) | def __init__(self, typ: HdlType, name: str, meta=None):
method __eq__ (line 47) | def __eq__(self, other):
method __hash__ (line 52) | def __hash__(self):
method __repr__ (line 55) | def __repr__(self):
class HStruct (line 89) | class HStruct(HdlType):
method __init__ (line 135) | def __init__(self, *template, name=None, const=False):
method bit_length (line 191) | def bit_length(self) -> int:
method getConstCls (line 201) | def getConstCls(self):
method getRtlSignalCls (line 206) | def getRtlSignalCls(self):
method get_reinterpret_cast_HConst_fn (line 216) | def get_reinterpret_cast_HConst_fn(cls):
method get_reinterpret_cast_RtlSignal_fn (line 222) | def get_reinterpret_cast_RtlSignal_fn(cls):
method __fields__eq__ (line 227) | def __fields__eq__(self, other: Self) -> bool:
method __eq__ (line 237) | def __eq__(self, other: HdlType) -> bool:
method __hash__ (line 256) | def __hash__(self):
method __add__ (line 259) | def __add__(self, other):
method isScalar (line 267) | def isScalar(self):
method __repr__ (line 270) | def __repr__(self, indent=0, withAddr=None, expandStructs=False):
function offsetof (line 310) | def offsetof(structTy: HStruct, field: HStructField):
FILE: hwt/hdl/types/structCast.py
function hstruct_reinterpret_to_bits (line 17) | def hstruct_reinterpret_to_bits(self: HStruct, sigOrConst: Union[RtlSign...
function hstruct_reinterpret_using_bits (line 48) | def hstruct_reinterpret_using_bits(self: HStruct, sigOrConst: Union[RtlS...
function hstruct_reinterpret (line 54) | def hstruct_reinterpret(self: HStruct, sigOrConst: Union[RtlSignalBase, ...
FILE: hwt/hdl/types/structUtils.py
function HdlType_select (line 15) | def HdlType_select(t: HStruct, fieldsToUse: filed_filter_t):
function field_path_get_type (line 73) | def field_path_get_type(root: HdlType, field_path: TypePath):
function HStruct_tuple_to_dict (line 87) | def HStruct_tuple_to_dict(v: tuple, t: HdlType, call_to_py_on_scalars=Tr...
FILE: hwt/hdl/types/structValBase.py
class HStructRtlSignalBase (line 14) | class HStructRtlSignalBase(RtlSignal):
method __len__ (line 17) | def __len__(self):
method __iter__ (line 20) | def __iter__(self):
method __getattr__ (line 27) | def __getattr__(self, name:str) -> RtlSignal:
method __call__ (line 35) | def __call__(self, source,
method __repr__ (line 54) | def __repr__(self, indent=0):
class HStructConstBase (line 58) | class HStructConstBase(HConst):
method __init__ (line 65) | def __init__(self, typeObj: "HStruct", val: Optional[Union[dict, tuple...
method __len__ (line 112) | def __len__(self):
method __iter__ (line 115) | def __iter__(self):
method __copy__ (line 122) | def __copy__(self):
method from_py (line 136) | def from_py(cls, typeObj, val, vld_mask=None):
method _is_full_valid (line 148) | def _is_full_valid(self):
method _is_partially_valid (line 156) | def _is_partially_valid(self) -> bool:
method to_py (line 164) | def to_py(self):
method __ne__ (line 172) | def __ne__(self, other):
method _eq (line 188) | def _eq(self, other):
method __eq__ (line 191) | def __eq__(self, other):
method __repr__ (line 207) | def __repr__(self, indent=0):
FILE: hwt/hdl/types/typeCast.py
function toHVal (line 19) | def toHVal(op: Any, suggestedType: Optional[HdlType]=None) -> Union[HCon...
FILE: hwt/hdl/types/union.py
class HUnionConstBase (line 16) | class HUnionConstBase(HConst):
method __init__ (line 27) | def __init__(self, typeObj: "HUnion", val: Optional[Tuple[str, Any]]):
method from_py (line 49) | def from_py(cls, typeObj, val, vld_mask=None):
method __repr__ (line 61) | def __repr__(self, indent=0):
class HUnionRtlSignalBase (line 79) | class HUnionRtlSignalBase(RtlSignal):
method __repr__ (line 83) | def __repr__(self, indent=0):
class HUnionMemberHandler (line 88) | class HUnionMemberHandler(object):
method __init__ (line 93) | def __init__(self, field):
method set (line 96) | def set(self, parent, v):
method get (line 106) | def get(self, parent):
class HUnion (line 119) | class HUnion(HdlType):
method __init__ (line 129) | def __init__(self, *template, name=None, const=False):
method bit_length (line 188) | def bit_length(self):
method getConstCls (line 198) | def getConstCls(self):
method __fields__eq__ (line 202) | def __fields__eq__(self, other):
method __eq__ (line 218) | def __eq__(self, other):
method __hash__ (line 225) | def __hash__(self):
method isScalar (line 229) | def isScalar(self):
method __repr__ (line 232) | def __repr__(self, indent=0, withAddr=None, expandStructs=False):
FILE: hwt/hdl/types/utils.py
function walkFlattenFields (line 14) | def walkFlattenFields(sigOrConst: Union[RtlSignalBase, HConst], skipPadd...
function HConst_from_words (line 45) | def HConst_from_words(t: HdlType,
function is_only_padding (line 118) | def is_only_padding(t: HdlType) -> bool:
FILE: hwt/hdl/variables.py
class HdlSignalItem (line 6) | class HdlSignalItem(HdlObject):
method __init__ (line 17) | def __init__(self, name: str, dtype: "HdlType", def_val=None, virtual_...
method _set_def_val (line 37) | def _set_def_val(self):
FILE: hwt/hwIO.py
function _default_param_updater (line 30) | def _default_param_updater(self, myP, parentPval):
class HwIO (line 34) | class HwIO(HwIOBase, HwIOImplDependentFns,
method __init__ (line 76) | def __init__(self, masterDir=DIRECTION.OUT,
method _m (line 110) | def _m(self) -> Self:
method __call__ (line 122) | def __call__(self, other: Union[Self, HConst, object], exclude:Optiona...
method _loadHwDeclarations (line 137) | def _loadHwDeclarations(self):
method _cleanRtlSignals (line 159) | def _cleanRtlSignals(self, lockNonExternal=True):
method _connectTo (line 169) | def _connectTo(self, master: Union[Self, HConst, object], exclude:Opti...
method _connectToIter (line 178) | def _connectToIter(self, master: Union[Self, HConst, object], exclude:...
method _signalsForHwIO (line 280) | def _signalsForHwIO(self,
method _getHdlName (line 344) | def _getHdlName(self) -> str:
method _getFullName (line 348) | def _getFullName(self) -> str:
method _updateHwParamsFrom (line 352) | def _updateHwParamsFrom(self, otherObj, updater=_default_param_updater,
method _bit_length (line 361) | def _bit_length(self) -> int:
method __repr__ (line 382) | def __repr__(self) -> str:
FILE: hwt/hwIOs/agents/bramPort.py
function storeToRamMaskedByIndex (line 16) | def storeToRamMaskedByIndex(ram:dict[int, Union[tuple[int, int], HBitsCo...
function storeToRamMaskedByAddress (line 48) | def storeToRamMaskedByAddress(ram: dict[int, Union[tuple[int, int], HBit...
class HwIOBramPort_noClkAgent (line 102) | class HwIOBramPort_noClkAgent(SyncAgentBase):
method __init__ (line 115) | def __init__(self, sim: HdlSimulator, hwIO: "HwIOBramPort_noClk"):
method doReq (line 129) | def doReq(self, req: HwIOBramPort_noClkAgent_requestTy):
method onReadReq (line 166) | def onReadReq(self, addr: HBitsConst):
method onWriteReq (line 172) | def onWriteReq(self, addr: HBitsConst, data: HBitsConst, mask: Union[H...
method monitor (line 178) | def monitor(self):
method driver (line 244) | def driver(self):
class HwIOBramPortAgent (line 286) | class HwIOBramPortAgent(HwIOBramPort_noClkAgent):
method getDrivers (line 288) | def getDrivers(self):
FILE: hwt/hwIOs/agents/fifo.py
class HwIOFifoReaderAgent (line 11) | class HwIOFifoReaderAgent(SyncAgentBase):
method __init__ (line 16) | def __init__(self, sim: HdlSimulator, hwIO: "HwIOFifoReader", allowNoR...
method setEnable_asDriver (line 28) | def setEnable_asDriver(self, en: bool):
method setEnable_asMonitor (line 36) | def setEnable_asMonitor(self, en: bool):
method driver_init (line 45) | def driver_init(self):
method monitor_init (line 49) | def monitor_init(self):
method get_data (line 53) | def get_data(self):
method dataReader (line 56) | def dataReader(self):
method getMonitors (line 68) | def getMonitors(self):
method monitor (line 76) | def monitor(self):
method getDrivers (line 108) | def getDrivers(self):
method set_data (line 116) | def set_data(self, d):
method dataWriter (line 119) | def dataWriter(self):
method driver (line 132) | def driver(self):
class HwIOFifoWriterAgent (line 165) | class HwIOFifoWriterAgent(SyncAgentBase):
method __init__ (line 170) | def __init__(self, sim: HdlSimulator, hwIO: "HwIOFifoWriter", allowNoR...
method driver_init (line 177) | def driver_init(self):
method monitor_init (line 181) | def monitor_init(self):
method setEnable_asDriver (line 185) | def setEnable_asDriver(self, en: bool):
method setEnable_asMonitor (line 189) | def setEnable_asMonitor(self, en: bool):
method get_data (line 193) | def get_data(self):
method set_data (line 196) | def set_data(self, d):
method monitor (line 199) | def monitor(self):
method driver (line 221) | def driver(self):
method getDrivers (line 245) | def getDrivers(self):
method getMonitors (line 249) | def getMonitors(self):
FILE: hwt/hwIOs/agents/rdSync.py
class HwIODataRdAgent (line 9) | class HwIODataRdAgent(SyncAgentBase):
method __init__ (line 13) | def __init__(self, sim: HdlSimulator, hwIO: "HwIODataRd", allowNoReset...
method get_ready_signal (line 20) | def get_ready_signal(cls, hwIO: "HwIODataRd"):
method get_ready (line 23) | def get_ready(self):
method set_ready (line 26) | def set_ready(self, val):
method setEnable_asMonitor (line 29) | def setEnable_asMonitor(self, en: bool):
method monitor (line 34) | def monitor(self):
method get_data (line 48) | def get_data(self):
method set_data (line 52) | def set_data(self, data):
method driver (line 56) | def driver(self):
FILE: hwt/hwIOs/agents/rdVldSync.py
class HwIODataRdVldAgent (line 6) | class HwIODataRdVldAgent(SyncAgentBase, DataRdVldAgent):
method __init__ (line 20) | def __init__(self, sim: HdlSimulator, hwIO: "HwIODataRdVld", allowNoRe...
method get_ready_signal (line 28) | def get_ready_signal(cls, hwIO: "HwIODataRdVld"):
method get_ready (line 31) | def get_ready(self):
method set_ready (line 34) | def set_ready(self, val):
method get_valid_signal (line 38) | def get_valid_signal(cls, hwIO: "HwIODataRdVld"):
method get_valid (line 41) | def get_valid(self):
method set_valid (line 45) | def set_valid(self, val):
method get_data (line 48) | def get_data(self):
method set_data (line 52) | def set_data(self, data):
class UniversalRdVldSyncAgent (line 57) | class UniversalRdVldSyncAgent(HwIODataRdVldAgent):
method __init__ (line 67) | def __init__(self, sim: HdlSimulator, hwIO: "HwIODataRdVld", allowNoRe...
method get_data (line 79) | def get_data(self):
method set_data (line 85) | def set_data(self, data):
class HwIORdVldSyncAgent (line 105) | class HwIORdVldSyncAgent(HwIODataRdVldAgent):
method set_data (line 115) | def set_data(self, data):
method get_data (line 118) | def get_data(self):
class RdVldSyncReadListener (line 122) | class RdVldSyncReadListener():
method __init__ (line 124) | def __init__(self, hsAgent: HwIODataRdVldAgent):
method _afterReadWrap (line 130) | def _afterReadWrap(self):
method register (line 139) | def register(self, transCnt, callback):
FILE: hwt/hwIOs/agents/regCntrl.py
class HwIORegCntrlAgent (line 7) | class HwIORegCntrlAgent(SyncAgentBase):
method __init__ (line 12) | def __init__(self, sim, hwIO: "HwIORegCntrl"):
method setEnable_asDriver (line 18) | def setEnable_asDriver(self, en: bool):
method setEnable_asMonitor (line 23) | def setEnable_asMonitor(self, en: bool):
method din_getter (line 28) | def din_getter(self):
method din_setter (line 31) | def din_setter(self, newVal):
method dout_getter (line 36) | def dout_getter(self):
method dout_setter (line 39) | def dout_setter(self, newVal):
method getDrivers (line 44) | def getDrivers(self):
method getMonitors (line 48) | def getMonitors(self):
FILE: hwt/hwIOs/agents/signal.py
class HwIOSignalAgent (line 11) | class HwIOSignalAgent(SyncAgentBase):
method __init__ (line 19) | def __init__(self, sim: HdlSimulator, hwIO: "HwIOSignal", delay=None):
method getDrivers (line 48) | def getDrivers(self):
method getMonitors (line 64) | def getMonitors(self):
method driverInit (line 79) | def driverInit(self):
method get_data (line 90) | def get_data(self):
method set_data (line 93) | def set_data(self, data):
method driverWithClk (line 96) | def driverWithClk(self):
method driverWithTimer (line 109) | def driverWithTimer(self):
method monitorWithTimer (line 126) | def monitorWithTimer(self):
method monitorWithClk (line 139) | def monitorWithClk(self):
FILE: hwt/hwIOs/agents/struct.py
class HwIOStructAgent (line 8) | class HwIOStructAgent(AgentBase):
method __init__ (line 15) | def __init__(self, sim: HdlSimulator, hwIO: "HwIOStruct"):
method set_data (line 20) | def set_data(self, d: Union[HStructConstBase, list]):
method get_data (line 34) | def get_data(self):
method getMonitors (line 38) | def getMonitors(self):
method getDrivers (line 42) | def getDrivers(self):
FILE: hwt/hwIOs/agents/tuleWithCallback.py
class TupleWithCallback (line 2) | class TupleWithCallback(tuple):
method __new__ (line 4) | def __new__(cls, *args, onDone=None):
FILE: hwt/hwIOs/agents/union.py
class HwIOUnionSourceAgent (line 4) | class HwIOUnionSourceAgent(HwIOStructAgent):
method getMonitors (line 6) | def getMonitors(self):
method getDrivers (line 14) | def getDrivers(self):
FILE: hwt/hwIOs/agents/universalComposite.py
class UniversalCompositeAgent (line 7) | class UniversalCompositeAgent(AgentBase):
method __init__ (line 12) | def __init__(self, sim: HdlSimulator, hwIO: HwIO):
method getEnable (line 18) | def getEnable(self):
method setEnable (line 21) | def setEnable(self, v: bool):
method getDrivers (line 29) | def getDrivers(self):
method getMonitors (line 36) | def getMonitors(self):
FILE: hwt/hwIOs/agents/vldSync.py
class HwIODataVldAgent (line 10) | class HwIODataVldAgent(SyncAgentBase):
method __init__ (line 12) | def __init__(self, sim: HdlSimulator, hwIO: "HwIODataVld", allowNoRese...
method get_data (line 20) | def get_data(self):
method set_data (line 23) | def set_data(self, data):
method get_valid_signal (line 27) | def get_valid_signal(cls, hwIO):
method get_valid (line 30) | def get_valid(self):
method set_valid (line 33) | def set_valid(self, val):
method setEnable_asDriver (line 37) | def setEnable_asDriver(self, en):
method monitor (line 42) | def monitor(self):
method driver (line 60) | def driver(self):
FILE: hwt/hwIOs/hwIOArray.py
class HwIOArray (line 17) | class HwIOArray(HObjList[Optional[HwIO]], HwIO):
method __init__ (line 24) | def __init__(self, items: Sequence[HwIO]=(), masterDir=DIRECTION.OUT,
method hwDeclr (line 32) | def hwDeclr(self):
method __hash__ (line 38) | def __hash__(self):
method __eq__ (line 43) | def __eq__(self, other:object) -> bool:
method __copy__ (line 50) | def __copy__(self):
method _registerSubmodule (line 57) | def _registerSubmodule(self, mName:str, submodule:"HwModule", onParent...
method __call__ (line 61) | def __call__(self, other: Self, exclude=None, fit=False):
method _initSimAgent (line 82) | def _initSimAgent(self, sim: HdlSimulator):
method __repr__ (line 86) | def __repr__(self, *args, **kwargs) -> str:
class HwIOArrayAgent (line 90) | class HwIOArrayAgent(AgentBase):
method __init__ (line 97) | def __init__(self, sim: HdlSimulator, hwIO: HwIOArray):
method extendDataFromTuples (line 102) | def extendDataFromTuples(self, dataTuples: Sequence[tuple]):
method getDataAsTuples (line 110) | def getDataAsTuples(self):
method set_data (line 113) | def set_data(self, d: Union[HStructConstBase, list]):
method get_data (line 123) | def get_data(self):
method getMonitors (line 127) | def getMonitors(self):
method getDrivers (line 131) | def getDrivers(self):
FILE: hwt/hwIOs/hwIODifferential.py
class HwIODifferentialSig (line 7) | class HwIODifferentialSig(HwIO):
method hwDeclr (line 13) | def hwDeclr(self):
FILE: hwt/hwIOs/hwIOStruct.py
class BoundedMethodProxy (line 27) | class BoundedMethodProxy():
method __init__ (line 29) | def __init__(self, newInstance, method):
method __call__ (line 33) | def __call__(self, *args, **kwargs):
method __repr__ (line 36) | def __repr__(self):
class HwIOStruct (line 40) | class HwIOStruct(HwIO):
method __init__ (line 53) | def __init__(self, structT: HStruct,
method hwDeclr (line 73) | def hwDeclr(self):
method _initSimAgent (line 95) | def _initSimAgent(self, sim: HdlSimulator):
method _raiseBinOperatorError (line 98) | def _raiseBinOperatorError(self, opStr, other):
method _eq (line 105) | def _eq(self, other: Union["HwIOStruct", HStructConstBase]):
method __add__ (line 113) | def __add__(self, other):
method __sub__ (line 122) | def __sub__(self, other):
method __mul__ (line 131) | def __mul__(self, other):
method __truediv__ (line 140) | def __truediv__(self, other):
method __floordiv__ (line 149) | def __floordiv__(self, other):
method __ne__ (line 158) | def __ne__(self, other: Union["HwIOStruct", HStructConstBase]):
method _reinterpret_cast (line 166) | def _reinterpret_cast(self, toT: HdlType):
method __iter__ (line 169) | def __iter__(self):
method __len__ (line 172) | def __len__(self):
method __getattr__ (line 175) | def __getattr__(self, name:str):
method __copy__ (line 187) | def __copy__(self):
class HdlType_to_HwIO (line 200) | class HdlType_to_HwIO():
method apply (line 209) | def apply(self, dtype: HdlType, field_path: Optional[TypePath]=None, m...
method instantiateFieldFn (line 226) | def instantiateFieldFn(self, hwIO, fieldInfo) -> HwIO:
class HwIO_to_HdlType (line 237) | class HwIO_to_HdlType():
method apply (line 244) | def apply(self, hwIO: Union[HwIO, RtlSignal], const=False, exclude: Op...
class HwIOStructRd (line 266) | class HwIOStructRd(HwIODataRd):
method hwConfig (line 272) | def hwConfig(self):
method hwDeclr (line 276) | def hwDeclr(self):
method _initSimAgent (line 283) | def _initSimAgent(self, sim:HdlSimulator):
class HwIOStructRdAgent (line 287) | class HwIOStructRdAgent(HwIODataRdAgent):
method __init__ (line 289) | def __init__(self, sim:HdlSimulator, hwIO:HwIOStructRd, allowNoReset=F...
method set_data (line 295) | def set_data(self, data):
method get_data (line 299) | def get_data(self):
class HwIOStructVld (line 303) | class HwIOStructVld(HwIODataVld):
method hwConfig (line 308) | def hwConfig(self):
method hwDeclr (line 312) | def hwDeclr(self):
method _initSimAgent (line 319) | def _initSimAgent(self, sim:HdlSimulator):
class HwIOStructVldAgent (line 323) | class HwIOStructVldAgent(HwIODataVldAgent):
method __init__ (line 325) | def __init__(self, sim:HdlSimulator, hwIO:HwIOStructVld, allowNoReset=...
method set_data (line 331) | def set_data(self, data):
method get_data (line 335) | def get_data(self):
class HwIOStructRdVld (line 339) | class HwIOStructRdVld(HwIORdVldSync):
method hwConfig (line 345) | def hwConfig(self):
method hwDeclr (line 349) | def hwDeclr(self):
method _initSimAgent (line 356) | def _initSimAgent(self, sim:HdlSimulator):
class HwIOStructRdVldAgent (line 360) | class HwIOStructRdVldAgent(HwIODataRdVldAgent):
method __init__ (line 362) | def __init__(self, sim:HdlSimulator, hwIO:HwIOStructRdVld, allowNoRese...
method set_data (line 368) | def set_data(self, data):
method get_data (line 372) | def get_data(self):
FILE: hwt/hwIOs/hwIOTristate.py
class HwIOTristateSig (line 12) | class HwIOTristateSig(HwIO):
method hwConfig (line 21) | def hwConfig(self):
method hwDeclr (line 26) | def hwDeclr(self):
method _initSimAgent (line 37) | def _initSimAgent(self, sim: HdlSimulator):
class HwIOTristateClk (line 42) | class HwIOTristateClk(HwIOClk, HwIOTristateSig):
method hwConfig (line 45) | def hwConfig(self):
method _getIpCoreIntfClass (line 50) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 54) | def _initSimAgent(self, sim: HdlSimulator):
FILE: hwt/hwIOs/hwIOUnion.py
class HwIOUnionSink (line 10) | class HwIOUnionSink(HwIOStruct):
method hwDeclr (line 18) | def hwDeclr(self):
class HwIOUnionSource (line 24) | class HwIOUnionSource(HwIOUnionSink):
method hwDeclr (line 31) | def hwDeclr(self):
method _initSimAgent (line 37) | def _initSimAgent(self, sim: HdlSimulator):
FILE: hwt/hwIOs/hwIO_map.py
class HwIOObjMap (line 18) | class HwIOObjMap(List["HwIoMapItem"]):
function _HTypeFromHwIOObjMap (line 47) | def _HTypeFromHwIOObjMap(hwIO: HwIoMapCompatibleHwIO):
function HTypeFromHwIOObjMapItem (line 64) | def HTypeFromHwIOObjMapItem(hwIOMapItem: HwIOMapItem):
function HTypeFromHwIOObjMap (line 119) | def HTypeFromHwIOObjMap(hwIOMap: HwIOObjMap) -> HStruct:
function isPaddingInHwIOObjMap (line 142) | def isPaddingInHwIOObjMap(item: Union[HdlType, Tuple[object, Optional[st...
function _walkHwIOStructAndHwIOObjMap_unpack (line 157) | def _walkHwIOStructAndHwIOObjMap_unpack(io: Union[HObjList, HwIOStruct, ...
function walkHwIOStructAndHwIOObjMap (line 182) | def walkHwIOStructAndHwIOObjMap(io: Union[HObjList, HwIOStruct, HwIOUnio...
function HwIOObjMapItem_find_by_name (line 221) | def HwIOObjMapItem_find_by_name(hwIOMapItem, name: str):
function HwIOObjMap_get_by_field_path (line 246) | def HwIOObjMap_get_by_field_path(root: HwIOObjMap, field_path: TypePath):
FILE: hwt/hwIOs/signalOps.py
class SignalOps (line 4) | class SignalOps(object):
method _auto_cast (line 10) | def _auto_cast(self, toT):
method _cast_sign (line 14) | def _cast_sign(self, signed):
method _signed (line 17) | def _signed(self):
method _unsigned (line 20) | def _unsigned(self):
method _vec (line 23) | def _vec(self):
method _reinterpret_cast (line 26) | def _reinterpret_cast(self, toT):
method _onRisingEdge (line 30) | def _onRisingEdge(self):
method _onFallingEdge (line 33) | def _onFallingEdge(self):
method _isOn (line 37) | def _isOn(self):
method getMsb (line 43) | def getMsb(self):
method _eq (line 46) | def _eq(self, other):
method __ne__ (line 53) | def __ne__(self, other):
method __gt__ (line 57) | def __gt__(self, other):
method __lt__ (line 61) | def __lt__(self, other):
method __ge__ (line 65) | def __ge__(self, other):
method __le__ (line 69) | def __le__(self, other):
method __invert__ (line 74) | def __invert__(self):
method __and__ (line 79) | def __and__(self, other):
method __xor__ (line 86) | def __xor__(self, other):
method __or__ (line 93) | def __or__(self, other):
method __neg__ (line 101) | def __neg__(self):
method __add__ (line 105) | def __add__(self, other):
method __sub__ (line 109) | def __sub__(self, other):
method __mul__ (line 113) | def __mul__(self, other):
method __pow__ (line 117) | def __pow__(self, other):
method __mod__ (line 121) | def __mod__(self, other):
method __truediv__ (line 125) | def __truediv__(self, other):
method __floordiv__ (line 129) | def __floordiv__(self, other):
method __lshift__ (line 133) | def __lshift__(self, other):
method __rshift__ (line 137) | def __rshift__(self, other):
method _reversed (line 142) | def _reversed(self):
method _concat (line 149) | def _concat(self, *others):
method __getitem__ (line 155) | def __getitem__(self, key):
method _ternary (line 161) | def _ternary(self, ifTrue, ifFalse):
method __call__ (line 164) | def __call__(self, source, exclude=None, fit=False):
method __getattr__ (line 174) | def __getattr__(self, name:str):
FILE: hwt/hwIOs/std.py
class HwIOSignal (line 30) | class HwIOSignal(SignalOps, HwIO, Generic[T]):
method __init__ (line 44) | def __init__(self,
method _cleanRtlSignals (line 58) | def _cleanRtlSignals(self, lockNonExternal=True):
method __copy__ (line 70) | def __copy__(self):
method _initSimAgent (line 80) | def _initSimAgent(self, sim: HdlSimulator):
function HwIOVectSignal (line 84) | def HwIOVectSignal(width: int,
class HwIOClk (line 98) | class HwIOClk(HwIOSignal):
method hwConfig (line 105) | def hwConfig(self):
method _getIpCoreIntfClass (line 109) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 114) | def _initSimAgent(self, sim: HdlSimulator):
class HwIORst (line 118) | class HwIORst(HwIOSignal[HBits]):
method _getIpCoreIntfClass (line 124) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 129) | def _initSimAgent(self, sim: HdlSimulator):
class HwIORst_n (line 135) | class HwIORst_n(HwIOSignal[HBits]):
method __init__ (line 141) | def __init__(self,
method _getIpCoreIntfClass (line 152) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 157) | def _initSimAgent(self, sim: HdlSimulator):
class HwIOVldSync (line 163) | class HwIOVldSync(HwIO):
method hwDeclr (line 166) | def hwDeclr(self):
class HwIODataVld (line 170) | class HwIODataVld(HwIOVldSync):
method hwConfig (line 177) | def hwConfig(self):
method hwDeclr (line 181) | def hwDeclr(self):
method _initSimAgent (line 186) | def _initSimAgent(self, sim: HdlSimulator):
class HwIORdSync (line 190) | class HwIORdSync(HwIO):
method hwDeclr (line 193) | def hwDeclr(self) -> None:
class HwIODataRd (line 197) | class HwIODataRd(HwIORdSync):
method hwConfig (line 204) | def hwConfig(self):
method hwDeclr (line 208) | def hwDeclr(self):
method _initSimAgent (line 213) | def _initSimAgent(self, sim: HdlSimulator):
class HwIORdVldSync (line 217) | class HwIORdVldSync(HwIO):
method hwDeclr (line 229) | def hwDeclr(self):
method _initSimAgent (line 234) | def _initSimAgent(self, sim: HdlSimulator):
class HwIODataRdVld (line 238) | class HwIODataRdVld(HwIORdVldSync):
method hwConfig (line 249) | def hwConfig(self):
method hwDeclr (line 253) | def hwDeclr(self):
method _initSimAgent (line 258) | def _initSimAgent(self, sim: HdlSimulator):
class HwIOReqDoneSync (line 262) | class HwIOReqDoneSync(HwIO):
method hwConfig (line 271) | def hwConfig(self) -> None:
method hwDeclr (line 275) | def hwDeclr(self):
class HwIOBramPort_noClk (line 280) | class HwIOBramPort_noClk(HwIO):
method hwConfig (line 286) | def hwConfig(self):
method hwDeclr (line 294) | def hwDeclr(self):
method _getWordAddrStep (line 314) | def _getWordAddrStep(self):
method _getAddrStep (line 320) | def _getAddrStep(self):
method _getIpCoreIntfClass (line 328) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 333) | def _initSimAgent(self, sim: HdlSimulator):
class HwIOBramPort (line 337) | class HwIOBramPort(HwIOBramPort_noClk):
method hwDeclr (line 343) | def hwDeclr(self):
method _initSimAgent (line 351) | def _initSimAgent(self, sim: HdlSimulator):
class HwIOFifoWriter (line 355) | class HwIOFifoWriter(HwIO):
method hwConfig (line 361) | def hwConfig(self):
method hwDeclr (line 365) | def hwDeclr(self):
method _initSimAgent (line 372) | def _initSimAgent(self, sim: HdlSimulator):
method _getIpCoreIntfClass (line 376) | def _getIpCoreIntfClass(self):
class HwIOFifoReader (line 381) | class HwIOFifoReader(HwIO):
method hwConfig (line 387) | def hwConfig(self):
method hwDeclr (line 391) | def hwDeclr(self):
method _initSimAgent (line 397) | def _initSimAgent(self, sim: HdlSimulator):
method _getIpCoreIntfClass (line 401) | def _getIpCoreIntfClass(self):
class HwIORegCntrl (line 406) | class HwIORegCntrl(HwIO):
method hwConfig (line 413) | def hwConfig(self):
method hwDeclr (line 419) | def hwDeclr(self):
method _initSimAgent (line 427) | def _initSimAgent(self, sim: HdlSimulator):
FILE: hwt/hwIOs/std_ip_defs.py
class IP_Clk (line 12) | class IP_Clk(IntfIpMeta):
method __init__ (line 14) | def __init__(self):
method postProcess (line 22) | def postProcess(self, component: Component,
method asQuartusTcl (line 57) | def asQuartusTcl(self, buff: List[str], version: str, component: Compo...
class IP_Rst (line 65) | class IP_Rst(IntfIpMeta):
method __init__ (line 67) | def __init__(self):
method postProcess (line 75) | def postProcess(self, component: Component, packager: IpPackager, this...
method asQuartusTcl (line 78) | def asQuartusTcl(self, buff: List[str], version: str, component: Compo...
class IP_Rst_n (line 92) | class IP_Rst_n(IP_Rst):
method postProcess (line 94) | def postProcess(self, component: Component, packager: IpPackager, this...
method asQuartusTcl (line 98) | def asQuartusTcl(self, buff: List[str], version: str, component: Compo...
class IP_Handshake (line 113) | class IP_Handshake(IntfIpMeta):
method __init__ (line 115) | def __init__(self):
class IP_BlockRamPort (line 128) | class IP_BlockRamPort(IntfIpMeta):
method __init__ (line 130) | def __init__(self):
class IP_FifoReader (line 146) | class IP_FifoReader(IntfIpMeta):
method __init__ (line 148) | def __init__(self):
class IP_FifoWriter (line 161) | class IP_FifoWriter(IntfIpMeta):
method __init__ (line 163) | def __init__(self):
FILE: hwt/hwIOs/utils.py
function addClkRstn (line 6) | def addClkRstn(obj: HwModuleOrHwIOBase):
function addClkRst (line 18) | def addClkRst(obj: HwModuleOrHwIOBase):
function _tryConnect (line 30) | def _tryConnect(src: HwIOBase, module: HwModuleBase, hwIOName: str):
function propagateClk (line 44) | def propagateClk(obj: HwModuleOrHwIOBase):
function propagateClkRstn (line 55) | def propagateClkRstn(obj: HwModuleOrHwIOBase):
function propagateClkRst (line 69) | def propagateClkRst(obj: HwModuleOrHwIOBase):
function propagateRstn (line 85) | def propagateRstn(obj: HwModuleOrHwIOBase):
function propagateRst (line 97) | def propagateRst(obj: HwModuleOrHwIOBase):
FILE: hwt/hwModule.py
class HdlConstraintList (line 21) | class HdlConstraintList(list):
class HwModule (line 28) | class HwModule(PropDeclrCollector, HwModuleImplHelpers):
method __init__ (line 79) | def __init__(self, hdlName:Optional[str]=None):
method _loadHwIODeclarations (line 93) | def _loadHwIODeclarations(self, hwIO: HwIOBase, isExtern: bool):
method _loadHwDeclarations (line 98) | def _loadHwDeclarations(self):
method _registerHwIOInHwImpl (line 120) | def _registerHwIOInHwImpl(self, hwIOName: str, hwIO: HwIOBase, onParen...
method _getDefaultName (line 129) | def _getDefaultName(self) -> str:
method _get_hdl_doc (line 132) | def _get_hdl_doc(self) -> Optional[str]:
method _to_rtl (line 137) | def _to_rtl(self, target_platform: DummyPlatform,
method _updateHwParamsFrom (line 253) | def _updateHwParamsFrom(self, otherObj: PropDeclrCollector,
method _checkCompInstances (line 265) | def _checkCompInstances(self):
function copy_HdlModuleDec_HwIO (line 287) | def copy_HdlModuleDec_HwIO(orig_io: HwIOBase, new_io: HwIOBase,
function copy_HdlModuleDec (line 316) | def copy_HdlModuleDec(orig_m: HwModule, new_m: HwModule):
function _sharedCompBuildHwIOMapList (line 354) | def _sharedCompBuildHwIOMapList(replacement: list[HwIOBase],
function sharedCompBuildHwIOMap (line 366) | def sharedCompBuildHwIOMap(replacement_m: HwModule, substituted_m: HwMod...
FILE: hwt/hwParam.py
class HwParam (line 7) | class HwParam():
method __init__ (line 22) | def __init__(self, initval):
method get_hdl_type (line 28) | def get_hdl_type(self):
method get_hdl_value (line 46) | def get_hdl_value(self):
method get_value (line 57) | def get_value(self):
method set_value (line 60) | def set_value(self, v):
method __repr__ (line 63) | def __repr__(self):
FILE: hwt/mainBases.py
class RtlSignalBase (line 8) | class RtlSignalBase(Generic[T]):
class HwIOBase (line 15) | class HwIOBase():
class HwModuleBase (line 22) | class HwModuleBase():
FILE: hwt/math.py
function inRange (line 16) | def inRange(n: Union[int, AnyHValue], start: Union[int, AnyHValue], end:...
function toPow2Ceil (line 28) | def toPow2Ceil(x: int):
function toPow2Floor (line 38) | def toPow2Floor(n: int):
function addressAlignBestEffort (line 48) | def addressAlignBestEffort(record_width: int, bus_data_width: int):
function log2ceil (line 70) | def log2ceil(x: Union[int, float]):
function isPow2 (line 87) | def isPow2(num: Union[int, float]) -> bool:
function sizeof (line 96) | def sizeof(_type: HdlType) -> int:
function shiftIntArray (line 102) | def shiftIntArray(values: List[Union[int, "HBitsConst"]], item_width: in...
function hMin (line 157) | def hMin(a: AnyHValue, b: AnyHValue):
function hMax (line 166) | def hMax(a: AnyHValue, b: AnyHValue):
FILE: hwt/mathAutoExt.py
function extendForNoOverflowAddSub (line 10) | def extendForNoOverflowAddSub(a: AnyHBitsValue, b: AnyHBitsValue):
function addAutoExt (line 32) | def addAutoExt(a: AnyHBitsValue, b: AnyHBitsValue):
function addAutoExtMany (line 38) | def addAutoExtMany(*ops: tuple[AnyHBitsValue, ...]):
function subAutoExt (line 47) | def subAutoExt(a: AnyHBitsValue, b: AnyHBitsValue):
function addShifted (line 53) | def addShifted(a: AnyHBitsValue, b: AnyHBitsValue, bShift: int, maxResul...
function subShifted (line 117) | def subShifted(a: AnyHBitsValue, b: AnyHBitsValue, bShift: int, maxResul...
function addShiftedMany (line 122) | def addShiftedMany(ops:tuple[tuple[AnyHBitsValue, int]], maxResultWidth:...
function mulFullWidth (line 131) | def mulFullWidth(a: AnyHBitsValue, b: AnyHBitsValue) -> AnyHBitsValue:
FILE: hwt/pyUtils/arrayQuery.py
class DuplicitValueExc (line 12) | class DuplicitValueExc(Exception):
class NoValueExc (line 19) | class NoValueExc(Exception):
function single (line 25) | def single(iterable, fn):
function arr_any (line 49) | def arr_any(iterable, fn):
function arr_all (line 59) | def arr_all(iterable, fn):
function take (line 70) | def take(iterrable, howMay):
function where (line 86) | def where(iterable, fn):
function groupedby (line 95) | def groupedby(collection, fn):
function flatten (line 116) | def flatten(iterables, level=inf):
function grouper (line 131) | def grouper(n: int, iterable: Sequence, padvalue=None):
function areSetsIntersets (line 138) | def areSetsIntersets(setA: set, setB: set):
function balanced_reduce (line 145) | def balanced_reduce(arr: Sequence, opFn):
FILE: hwt/pyUtils/fileHelpers.py
function find_files (line 5) | def find_files(directory, pattern, recursive=True):
FILE: hwt/pyUtils/setList.py
class SetList (line 6) | class SetList(Generic[T], list):
method __init__ (line 12) | def __init__(self, initSeq: Optional[Sequence[T]]=None):
method append (line 19) | def append(self, item: T) -> bool:
method extend (line 30) | def extend(self, items: Sequence[T]):
method insert (line 36) | def insert(self, i: int, x: T):
method _get_set (line 40) | def _get_set(self) -> Set[T]:
method intersection_set (line 43) | def intersection_set(self, other: Set[T]):
method discard (line 46) | def discard(self, item: T) -> bool:
method remove (line 56) | def remove(self, item: T):
method pop (line 60) | def pop(self, *args, **kwargs) -> T:
method clear (line 65) | def clear(self):
method copy (line 69) | def copy(self):
method __setitem__ (line 74) | def __setitem__(self, i: Union[int, slice], v: Union[T, Sequence[T]]):
method __copy__ (line 93) | def __copy__(self):
method __contains__ (line 96) | def __contains__(self, key) -> bool:
FILE: hwt/pyUtils/testUtils.py
class TestMatrix (line 4) | class TestMatrix():
method __init__ (line 10) | def __init__(self, *args, **kwargs):
method split_args_kwargs (line 21) | def split_args_kwargs(self, args):
method __call__ (line 31) | def __call__(self, test_fn):
FILE: hwt/pyUtils/typingFuture.py
function override (line 7) | def override(method):
FILE: hwt/serializer/combLoopAnalyzer/__init__.py
function collect_comb_inputs (line 20) | def collect_comb_inputs(ctx, seen, input_signal, comb_inputs):
function collect_comb_drivers (line 26) | def collect_comb_drivers(path_prefix: Tuple[HwModule, ...],
class CombLoopAnalyzer (line 87) | class CombLoopAnalyzer():
method __init__ (line 92) | def __init__(self):
method visit_HwModule (line 99) | def visit_HwModule(self, m: HwModule):
method visit_HdlModuleDef (line 109) | def visit_HdlModuleDef(self, m: HdlModuleDef) -> None:
method visit_HdlStmCodeBlockContainer (line 112) | def visit_HdlStmCodeBlockContainer(self, proc: HdlStmCodeBlockContaine...
method visit_HdlCompInst (line 115) | def visit_HdlCompInst(self, o: HdlCompInst) -> None:
method report (line 140) | def report(self):
FILE: hwt/serializer/combLoopAnalyzer/tarjan.py
function _tarjan_head (line 4) | def _tarjan_head(index, lowlink, S, S_set, T, g, v):
class StronglyConnectedComponentSearchTarjan (line 12) | class StronglyConnectedComponentSearchTarjan():
method __init__ (line 19) | def __init__(self, g: dict):
method search_strongly_connected_components (line 26) | def search_strongly_connected_components(self) -> Generator:
FILE: hwt/serializer/exceptions.py
class SerializerException (line 2) | class SerializerException(Exception):
class UnsupportedEventOpErr (line 6) | class UnsupportedEventOpErr(SerializerException):
FILE: hwt/serializer/generic/constant_cache.py
class ConstantCache (line 6) | class ConstantCache(object):
method __init__ (line 12) | def __init__(self, toHdlAst, tmpVars: TmpVarConstructor):
method extract_const_val_as_const_var (line 19) | def extract_const_val_as_const_var(self, val: HConst) -> RtlSignalBase:
FILE: hwt/serializer/generic/indent.py
function getIndent (line 5) | def getIndent(indentNum: int):
FILE: hwt/serializer/generic/tmpVarConstructor.py
class TmpVarConstructor (line 12) | class TmpVarConstructor():
method __init__ (line 14) | def __init__(self, toHdlAst, name_scope: NameScope):
method create_var_cached (line 20) | def create_var_cached(self, suggestedName: str, dtype: HdlType,
method create_var (line 34) | def create_var(self,
method finish_var_init (line 56) | def finish_var_init(self, var: RtlSignal):
method sort_hdl_declarations_first (line 72) | def sort_hdl_declarations_first(self):
class TmpVarNotConstructableError (line 76) | class TmpVarNotConstructableError(NotImplementedError):
class NoTmpVars (line 80) | class NoTmpVars():
method create_var_cached (line 82) | def create_var_cached(self, suggestedName, dtype, *args, **kwargs):
method create_cached (line 86) | def create_cached(self, suggestedName, dtype, *args, **kwargs):
FILE: hwt/serializer/generic/to_hdl_ast.py
class ToHdlAst (line 40) | class ToHdlAst():
method getBaseNameScope (line 58) | def getBaseNameScope(cls):
method __init__ (line 66) | def __init__(self, name_scope: Optional[NameScope]=None):
method as_hdl (line 73) | def as_hdl(self, obj) -> iHdlObj:
method as_hdl_HdlType (line 89) | def as_hdl_HdlType(self, typ: HdlType, declaration=False):
method as_hdl_HdlType_array (line 117) | def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
method as_hdl_HdlType_enum (line 136) | def as_hdl_HdlType_enum(self, typ: HEnum, declaration=False):
method as_hdl_HdlType_slice (line 153) | def as_hdl_HdlType_slice(self, typ: HSlice, declaration=False):
method as_hdl_HdlType_float (line 156) | def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
method as_hdl_HdlType_struct (line 159) | def as_hdl_HdlType_struct(self, typ: HStruct, declaration=False):
method as_hdl_If (line 162) | def as_hdl_If(self, *args, **kwargs) -> HdlStmIf:
method as_hdl_cond (line 165) | def as_hdl_cond(self, v, force_bool) -> iHdlExpr:
method as_hdl_statements (line 170) | def as_hdl_statements(self, stm_list) -> iHdlStatement:
method _as_hdl_HdlAssignmentContainer_auto_conversions (line 180) | def _as_hdl_HdlAssignmentContainer_auto_conversions(self, a: HdlAssign...
method as_hdl_HdlAssignmentContainer (line 215) | def as_hdl_HdlAssignmentContainer(self, a: HdlAssignmentContainer):
method as_hdl_IfContainer (line 224) | def as_hdl_IfContainer(self, ifc: IfContainer) -> HdlStmIf:
method as_hdl_Switch (line 258) | def as_hdl_Switch(self, *args, **kwargs) -> HdlStmCase:
method as_hdl_FsmBuilder (line 261) | def as_hdl_FsmBuilder(self, *args, **kwargs) -> HdlStmCase:
method as_hdl_SwitchContainer (line 264) | def as_hdl_SwitchContainer(self, sw: SwitchContainer) -> HdlStmCase:
method as_hdl_PortConnection (line 275) | def as_hdl_PortConnection(self, o: HdlPortItem):
method as_hdl_HdlCompInst (line 290) | def as_hdl_HdlCompInst(self, o: HdlCompInst) -> HdlCompInst:
method as_hdl_GenericItem (line 308) | def as_hdl_GenericItem(self, o: HdlIdDef):
method as_hdl_HdlPortItem (line 312) | def as_hdl_HdlPortItem(self, o: HdlPortItem):
method as_hdl_HdlModuleDec (line 321) | def as_hdl_HdlModuleDec(self, o: HdlModuleDec):
method does_type_requires_extra_def (line 333) | def does_type_requires_extra_def(self, t: HdlType, other_types: list):
method as_hdl_HdlModuleDef_variable (line 340) | def as_hdl_HdlModuleDef_variable(
method _as_hdl_HdlModuleDef (line 352) | def _as_hdl_HdlModuleDef(self, new_m: HdlModuleDef) -> HdlModuleDef:
method _as_hdl_HdlModuleDef_body (line 373) | def _as_hdl_HdlModuleDef_body(
method as_hdl_HdlModuleDef (line 395) | def as_hdl_HdlModuleDef(self, o: HdlModuleDef) -> HdlModuleDef:
method has_to_be_process (line 402) | def has_to_be_process(self, proc: iHdlStatement):
method can_pop_process_wrap (line 406) | def can_pop_process_wrap(self, statements, hasToBeVhdlProcess):
method as_hdl_HdlStmCodeBlockContainer (line 410) | def as_hdl_HdlStmCodeBlockContainer(self, proc: HdlStmCodeBlockContain...
method _static_assert_false (line 454) | def _static_assert_false(self, msg:str):
method _static_assert_symbol_eq (line 457) | def _static_assert_symbol_eq(self, symbol_name:str, v):
method _as_hdl_HdlModuleDef_param_asserts (line 460) | def _as_hdl_HdlModuleDef_param_asserts(self, new_m: HdlModuleDec) -> L...
method _as_hdl_HdlModuleDef_param_asserts_real (line 463) | def _as_hdl_HdlModuleDef_param_asserts_real(self, new_m: HdlModuleDec)...
FILE: hwt/serializer/generic/utils.py
class TmpVarsSwap (line 13) | class TmpVarsSwap():
method __init__ (line 18) | def __init__(self, ctx, tmpVars):
method __enter__ (line 22) | def __enter__(self):
method __exit__ (line 26) | def __exit__(self, exc_type, exc_val, exc_tb):
FILE: hwt/serializer/generic/value.py
class ToHdlAst_Value (line 26) | class ToHdlAst_Value():
method is_suitable_for_const_extract (line 28) | def is_suitable_for_const_extract(self, val: HConst):
method as_hdl_Value (line 34) | def as_hdl_Value(self, val):
method as_hdl_int (line 70) | def as_hdl_int(self, val: int):
method Value_try_extract_as_const (line 74) | def Value_try_extract_as_const(self, val):
method as_hdl_IntegerVal (line 77) | def as_hdl_IntegerVal(self, val: HBitsConst):
method as_hdl_HBitsConst (line 80) | def as_hdl_HBitsConst(self, val: HBitsConst):
method as_hdl_HStringConst (line 92) | def as_hdl_HStringConst(self, val: HStringConst):
method as_hdl_HFunctionConst (line 95) | def as_hdl_HFunctionConst(self, val: HFunctionConst):
method as_hdl_HFloatConst (line 98) | def as_hdl_HFloatConst(self, val):
method as_hdl_HdlSignalItem (line 103) | def as_hdl_HdlSignalItem(self, si: Union[HdlSignalItem, HdlIdDef],
FILE: hwt/serializer/hwt/__init__.py
class HwtSerializer (line 11) | class HwtSerializer(DummySerializerConfig):
class ToHdlAstDebugHwt (line 17) | class ToHdlAstDebugHwt(ToHdlAstHwt):
method as_hdl (line 20) | def as_hdl(self, obj) -> iHdlObj:
class HwtDebugSerializer (line 27) | class HwtDebugSerializer(DummySerializerConfig):
FILE: hwt/serializer/hwt/context.py
class ValueWidthRequirementScope (line 1) | class ValueWidthRequirementScope():
method __init__ (line 11) | def __init__(self, ctx, val):
method __enter__ (line 15) | def __enter__(self):
method __exit__ (line 19) | def __exit__(self, exc_type, exc_val, exc_tb):
FILE: hwt/serializer/hwt/ops.py
class ToHdlAstHwt_ops (line 11) | class ToHdlAstHwt_ops():
method as_hdl_HOperatorNode (line 17) | def as_hdl_HOperatorNode(self, op: HOperatorNode):
FILE: hwt/serializer/hwt/serializer.py
class ToHdlAstHwt (line 20) | class ToHdlAstHwt(ToHdlAstHwt_value, ToHdlAstHwt_ops,
method __init__ (line 31) | def __init__(self, name_scope: Optional[NameScope]=None):
method has_to_be_process (line 37) | def has_to_be_process(self, proc):
method can_pop_process_wrap (line 40) | def can_pop_process_wrap(self, statements, hasToBeVhdlProcess: bool):
method _as_hdl_HdlModuleDef (line 43) | def _as_hdl_HdlModuleDef(self, new_m: HdlModuleDef) -> HdlModuleDef:
method sensitivityListItem (line 46) | def sensitivityListItem(self, item: Union[HdlSignalItem, HOperatorNode...
method as_hdl_CodeBlock (line 55) | def as_hdl_CodeBlock(self, o: CodeBlock):
FILE: hwt/serializer/hwt/types.py
class ToHdlAstHwt_types (line 13) | class ToHdlAstHwt_types():
method does_type_requires_extra_def (line 22) | def does_type_requires_extra_def(self, t, other_types):
method as_hdl_HdlType_str (line 29) | def as_hdl_HdlType_str(self, typ, declaration=False):
method as_hdl_HdlType_array (line 33) | def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
method as_hdl_HdlType_bits (line 38) | def as_hdl_HdlType_bits(self, typ: HBits, declaration=False):
method as_hdl_HdlType_float (line 64) | def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
FILE: hwt/serializer/hwt/value.py
class ToHdlAstHwt_value (line 22) | class ToHdlAstHwt_value(ToHdlAst_Value):
method is_suitable_for_const_extract (line 26) | def is_suitable_for_const_extract(self, val: HConst):
method as_hdl_HBitsConst (line 31) | def as_hdl_HBitsConst(self, val: HBitsConst):
method as_hdl_HdlSignalItem (line 47) | def as_hdl_HdlSignalItem(self, si: Union[HdlSignalItem, HdlIdDef], dec...
method as_hdl_HDictConst (line 66) | def as_hdl_HDictConst(self, val):
method as_hdl_HArrayConst (line 69) | def as_hdl_HArrayConst(self, val: HArrayConst):
method as_hdl_HSliceConst (line 92) | def as_hdl_HSliceConst(self, val: HSliceConst):
method as_hdl_HEnumConst (line 107) | def as_hdl_HEnumConst(self, val: HEnumConst):
FILE: hwt/serializer/ip_packager.py
class ToHdlAstVivadoTclExpr (line 29) | class ToHdlAstVivadoTclExpr(ToHdlAstVhdl2008):
method as_hdl_HdlSignalItem (line 33) | def as_hdl_HdlSignalItem(self, si: HdlSignalItem, declaration=False):
class IpPackager (line 43) | class IpPackager(IpCorePackager):
method __init__ (line 52) | def __init__(self, topHwModule: HwModule, name: str=None,
method toHdlConversion (line 74) | def toHdlConversion(self, top, topName: str, saveTo: str) -> List[str]:
method paramToIpValue (line 89) | def paramToIpValue(self, idPrefix: str, g: HdlIdDef, resolve) -> Value:
method getParamPhysicalName (line 126) | def getParamPhysicalName(self, p: HdlIdDef):
method getParamType (line 130) | def getParamType(self, p: HdlIdDef) -> HdlType:
method iterParams (line 135) | def iterParams(self, module: HwModule):
method iterInterfaces (line 139) | def iterInterfaces(self, top: HwModule):
method serializeType (line 143) | def serializeType(self, hdlType: HdlType) -> str:
method getVectorFromType (line 155) | def getVectorFromType(self, dtype) -> Union[bool, None, Tuple[int, int]]:
method getInterfaceType (line 165) | def getInterfaceType(self, hwIO: HwIO) -> HdlType:
method getInterfaceLogicalName (line 172) | def getInterfaceLogicalName(self, hwIO: HwIO):
method getInterfacePhysicalName (line 179) | def getInterfacePhysicalName(self, hwIO: HwIO):
method getInterfaceDirection (line 186) | def getInterfaceDirection(self, thisHwIO: HwIO):
method getTypeWidth (line 193) | def getTypeWidth(self, dtype: HdlType, do_eval=False)\
method getObjDebugName (line 203) | def getObjDebugName(self, obj: Union[HwIO, HwModule, HwParam]) -> str:
method serialzeValueToTCL (line 210) | def serialzeValueToTCL(self, val, do_eval=False) -> Tuple[str, str, bo...
FILE: hwt/serializer/mode.py
function freeze_dict (line 23) | def freeze_dict(data):
function hwParamsToValTuple (line 33) | def hwParamsToValTuple(module: "HwModule"):
function serializeExclude (line 42) | def serializeExclude(cls: Type["HwModule"]):
function serializeOnce (line 50) | def serializeOnce(cls: Type["HwModule"]):
function serializeParamsUniq (line 58) | def serializeParamsUniq(cls: Type["HwModule"]):
function _serializeExclude_eval (line 67) | def _serializeExclude_eval(parentModule: "HwModule", priv):
function _serializeOnce_eval (line 86) | def _serializeOnce_eval(parentModule: "HwModule", priv):
function _serializeParamsUniq_eval (line 111) | def _serializeParamsUniq_eval(parentModule: "HwModule", priv):
FILE: hwt/serializer/resourceAnalyzer/analyzer.py
function _count_mux_inputs_for_outputs (line 22) | def _count_mux_inputs_for_outputs(stm: HdlStatement, cnt):
function count_mux_inputs_for_outputs (line 34) | def count_mux_inputs_for_outputs(stm):
class ResourceAnalyzer (line 50) | class ResourceAnalyzer():
method __init__ (line 59) | def __init__(self):
method visit_HdlStmCodeBlockContainer_operators (line 63) | def visit_HdlStmCodeBlockContainer_operators(self, sig: RtlSignal, syn...
method visit_HdlStmCodeBlockContainer (line 114) | def visit_HdlStmCodeBlockContainer(self, proc: HdlStmCodeBlockContaine...
method visit_HdlModuleDef (line 167) | def visit_HdlModuleDef(self, m: HdlModuleDef) -> None:
method visit_HdlCompInst (line 176) | def visit_HdlCompInst(self, o: HdlCompInst) -> None:
method visit_HwModule (line 180) | def visit_HwModule(self, m: HwModule):
method report (line 183) | def report(self):
FILE: hwt/serializer/resourceAnalyzer/resourceTypes.py
class ResourceError (line 3) | class ResourceError(Exception):
class RtlResourceType (line 10) | class RtlResourceType():
class ResourceMUX (line 16) | class ResourceMUX(RtlResourceType):
method __init__ (line 18) | def __init__(self, bitWidth, inputs):
method __repr__ (line 22) | def __repr__(self):
class ResourceFF (line 26) | class ResourceFF(RtlResourceType):
class ResourceLatch (line 30) | class ResourceLatch(RtlResourceType):
class ResourceRAM (line 34) | class ResourceRAM(RtlResourceType):
method __init__ (line 39) | def __init__(self, width, items,
method __hash__ (line 65) | def __hash__(self):
method __eq__ (line 73) | def __eq__(self, other):
method __repr__ (line 87) | def __repr__(self):
FILE: hwt/serializer/resourceAnalyzer/utils.py
class ResourceContext (line 11) | class ResourceContext():
method __init__ (line 22) | def __init__(self, module: HwModule):
method registerOperator (line 31) | def registerOperator(self, op: HOperatorNode):
method registerMUX (line 39) | def registerMUX(self, stm: Union[HdlStatement, HOperatorNode], sig: Rt...
method registerFF (line 54) | def registerFF(self, ff):
method registerLatch (line 62) | def registerLatch(self, latch: RtlSignal):
method registerRAM_write_port (line 70) | def registerRAM_write_port(self, mem: RtlSignal, addr: RtlSignal,
method registerRAM_read_port (line 84) | def registerRAM_read_port(self, mem: RtlSignal, addr: RtlSignal,
method finalize (line 98) | def finalize(self):
FILE: hwt/serializer/serializer_config.py
class DummySerializerConfig (line 4) | class DummySerializerConfig():
FILE: hwt/serializer/serializer_filter.py
class SerializerFilter (line 7) | class SerializerFilter(object):
method __init__ (line 19) | def __init__(self):
method do_serialize (line 25) | def do_serialize(self, module: HwModule) -> Tuple[bool, Optional[HwMod...
class SerializerFilterAll (line 45) | class SerializerFilterAll(SerializerFilter):
method do_serialize (line 49) | def do_serialize(self, module: HwModule) -> bool:
class SerializerFilterDoNotExclude (line 53) | class SerializerFilterDoNotExclude(SerializerFilter):
method do_serialize (line 58) | def do_serialize(self, module: HwModule) -> bool:
FILE: hwt/serializer/simModel/__init__.py
class SimModelSerializer (line 10) | class SimModelSerializer(DummySerializerConfig):
FILE: hwt/serializer/simModel/serializer.py
class ToHdlAstSimModel (line 29) | class ToHdlAstSimModel(ToHdlAstSimModel_value, ToHdlAstSimModel_types,
method __init__ (line 40) | def __init__(self, name_scope: Optional[NameScope]=None):
method as_hdl_HdlModuleDec (line 45) | def as_hdl_HdlModuleDec(self, o: HdlModuleDec):
method as_hdl_PortConnection (line 54) | def as_hdl_PortConnection(self, o: HdlPortItem):
method as_hdl_HdlAssignmentContainer (line 64) | def as_hdl_HdlAssignmentContainer(self, a: HdlAssignmentContainer):
method as_hdl_IfContainer_out_invalidate_section (line 76) | def as_hdl_IfContainer_out_invalidate_section(self,
method as_hdl_IfContainer_cond_eval (line 96) | def as_hdl_IfContainer_cond_eval(self, cond):
method as_hdl_IfContainer (line 108) | def as_hdl_IfContainer(self, ifc: IfContainer) -> HdlStmIf:
method as_hdl_SwitchContainer (line 159) | def as_hdl_SwitchContainer(self, sw: SwitchContainer) -> HdlStmIf:
method sensitivityListItem (line 184) | def sensitivityListItem(self, item, anyEventDependent):
method has_to_be_process (line 198) | def has_to_be_process(self, proc):
method can_pop_process_wrap (line 201) | def can_pop_process_wrap(self, statements, hasToBeVhdlProcess):
method as_hdl_HdlStmCodeBlockContainer (line 204) | def as_hdl_HdlStmCodeBlockContainer(self, proc: HdlStmCodeBlockContain...
method as_hdl_extraVarsInit (line 212) | def as_hdl_extraVarsInit(self, extraVars):
method _as_hdl_HdlModuleDef_body (line 215) | def _as_hdl_HdlModuleDef_body(self, *args) -> HdlModuleDef:
FILE: hwt/serializer/simModel/tmpVarConstructorConstOnly.py
class TmpVarConstructorConstOnly (line 5) | class TmpVarConstructorConstOnly(TmpVarConstructor):
method finish_var_init (line 7) | def finish_var_init(self, var: RtlSignal):
method sort_hdl_declarations_first (line 12) | def sort_hdl_declarations_first(self):
FILE: hwt/serializer/simModel/types.py
class ToHdlAstSimModel_types (line 10) | class ToHdlAstSimModel_types():
method as_hdl_HdlType_bits (line 18) | def as_hdl_HdlType_bits(self, typ: HBits, declaration=False):
method as_hdl_HdlType_slice (line 29) | def as_hdl_HdlType_slice(self, typ: HSlice, declaration=False):
method as_hdl_HdlType_array (line 35) | def as_hdl_HdlType_array(self, typ, declaration=False):
method as_hdl_HdlType_enum (line 42) | def as_hdl_HdlType_enum(self, typ, declaration=False):
FILE: hwt/serializer/simModel/value.py
class ToHdlAstSimModel_value (line 28) | class ToHdlAstSimModel_value(ToHdlAst_Value):
method is_suitable_for_const_extract (line 55) | def is_suitable_for_const_extract(self, val: HConst):
method as_hdl_HdlSignalItem (line 59) | def as_hdl_HdlSignalItem(self, si: Union[HdlSignalItem, HdlIdDef],
method as_hdl_HBitsConst (line 71) | def as_hdl_HBitsConst(self, val: HBitsConst):
method as_hdl_HDictConst (line 80) | def as_hdl_HDictConst(self, val):
method as_hdl_HArrayConst (line 87) | def as_hdl_HArrayConst(self, val):
method as_hdl_HSliceConst (line 95) | def as_hdl_HSliceConst(self, val):
method as_hdl_HEnumConst (line 104) | def as_hdl_HEnumConst(self, val: HEnumConst):
method as_hdl_HOperatorNode (line 114) | def as_hdl_HOperatorNode(self, op: HOperatorNode):
FILE: hwt/serializer/store_manager.py
class StoreManager (line 15) | class StoreManager(object):
method __init__ (line 21) | def __init__(self,
method hierarchy_push (line 32) | def hierarchy_push(self, obj: Union[HdlModuleDec, HdlModuleDef]) -> Na...
method hierarchy_pop (line 37) | def hierarchy_pop(self, obj: Union[HdlModuleDec, HdlModuleDef]) -> Nam...
method write (line 43) | def write(self, obj: Union[iHdlObj, HdlConstraintList]):
class SaveToStream (line 47) | class SaveToStream(StoreManager):
method __init__ (line 52) | def __init__(self,
method write (line 64) | def write(self, obj: Union[iHdlObj, HdlConstraintList]):
class SaveToFilesFlat (line 75) | class SaveToFilesFlat(StoreManager):
method __init__ (line 80) | def __init__(self,
method write (line 92) | def write(self, obj: Union[iHdlObj, HdlConstraintList]):
class SaveToSingleFiles (line 116) | class SaveToSingleFiles(StoreManager):
method __init__ (line 122) | def __init__(self,
method write (line 138) | def write(self, obj: Union[iHdlObj, HdlConstraintList]):
FILE: hwt/serializer/systemC/__init__.py
class SystemCSerializer (line 10) | class SystemCSerializer(DummySerializerConfig):
FILE: hwt/serializer/systemC/expr.py
class ToHdlAstSystemC_expr (line 27) | class ToHdlAstSystemC_expr(ToHdlAst_Value):
method as_hdl_Value (line 31) | def as_hdl_Value(self, v):
method as_hdl_operand (line 36) | def as_hdl_operand(self, operand: Union[RtlSignal, HConst], i: int,
method as_hdl_HOperatorNode_INDEX (line 40) | def as_hdl_HOperatorNode_INDEX(self, op: HOperatorNode):
method as_hdl_HOperatorNode_BITSCAST (line 70) | def as_hdl_HOperatorNode_BITSCAST(self, op: HOperatorNode):
method as_hdl_HOperatorNode_TERNARY (line 82) | def as_hdl_HOperatorNode_TERNARY(self, op: HOperatorNode, ops: list[An...
method as_hdl_HOperatorNode (line 85) | def as_hdl_HOperatorNode(self, op: HOperatorNode):
method as_hdl_HdlSignalItem (line 128) | def as_hdl_HdlSignalItem(self, si: HdlSignalItem, declaration=False):
method as_hdl_HBitsConst (line 144) | def as_hdl_HBitsConst(self, val):
method as_hdl_HEnumConst (line 151) | def as_hdl_HEnumConst(self, val: HEnumConst):
method as_hdl_HArrayConst (line 156) | def as_hdl_HArrayConst(self, val):
FILE: hwt/serializer/systemC/serializer.py
class ToHdlAstSystemC (line 20) | class ToHdlAstSystemC(ToHdlAstSystemC_expr, ToHdlAstSystemC_type,
method __init__ (line 34) | def __init__(self, name_scope: Optional[NameScope]=None):
method as_hdl_HdlModuleDec (line 40) | def as_hdl_HdlModuleDec(self, o: HdlModuleDec):
method as_hdl_HdlPortItem (line 43) | def as_hdl_HdlPortItem(self, o: HdlPortItem):
method as_hdl_HdlCompInst (line 76) | def as_hdl_HdlCompInst(self, o: HdlCompInst) -> HdlCompInst:
FILE: hwt/serializer/systemC/statements.py
class ToHdlAstSystemC_statements (line 20) | class ToHdlAstSystemC_statements():
method has_to_be_process (line 22) | def has_to_be_process(self, proc: iHdlStatement):
method can_pop_process_wrap (line 25) | def can_pop_process_wrap(self, statements, hasToBeVhdlProcess):
method sensitivityListItem (line 28) | def sensitivityListItem(self, item, anyIsEventDependent):
method as_hdl_SwitchContainer (line 37) | def as_hdl_SwitchContainer(self, sw: SwitchContainer) -> HdlStmCase:
method _as_hdl_HdlAssignmentContainer (line 55) | def _as_hdl_HdlAssignmentContainer(self, dst, typeOfDst, src):
method as_hdl_HdlAssignmentContainer (line 70) | def as_hdl_HdlAssignmentContainer(self, a: HdlAssignmentContainer):
FILE: hwt/serializer/systemC/type.py
class ToHdlAstSystemC_type (line 14) | class ToHdlAstSystemC_type():
method does_type_requires_extra_def (line 22) | def does_type_requires_extra_def(self, t, other_types):
method as_hdl_HdlType_str (line 29) | def as_hdl_HdlType_str(self, typ, declaration=False):
method as_hdl_HdlType_bits (line 33) | def as_hdl_HdlType_bits(self, typ: HBits, declaration=False):
method as_hdl_HdlType_array (line 56) | def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
method as_hdl_HdlType_enum (line 65) | def as_hdl_HdlType_enum(self, typ: HEnum, declaration=False):
method as_hdl_HdlType_float (line 69) | def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
FILE: hwt/serializer/systemC/utils.py
function systemCTypeOfSig (line 10) | def systemCTypeOfSig(s):
FILE: hwt/serializer/utils.py
function getMaxStmIdForStm (line 11) | def getMaxStmIdForStm(stm: HdlStatement):
function RtlSignal_sort_key (line 28) | def RtlSignal_sort_key(s: RtlSignalBase):
function HdlStatement_sort_key (line 32) | def HdlStatement_sort_key(stm: HdlStatement):
FILE: hwt/serializer/verilog/__init__.py
class VerilogSerializer (line 10) | class VerilogSerializer(DummySerializerConfig):
FILE: hwt/serializer/verilog/context.py
class SignalTypeSwap (line 4) | class SignalTypeSwap():
method __init__ (line 10) | def __init__(self, ctx, signalType: SIGNAL_TYPE):
method __enter__ (line 14) | def __enter__(self):
method __exit__ (line 18) | def __exit__(self, exc_type, exc_val, exc_tb):
FILE: hwt/serializer/verilog/ops.py
class ToHdlAstVerilog_ops (line 21) | class ToHdlAstVerilog_ops():
method _operandIsAnotherOperand (line 29) | def _operandIsAnotherOperand(self, operand):
method as_hdl_operand (line 33) | def as_hdl_operand(self, operand: Union[RtlSignal, HConst], i: int,
method as_hdl_HOperatorNode_TERNARY (line 85) | def as_hdl_HOperatorNode_TERNARY(self, op: HOperatorNode, ops: list[An...
method as_hdl_HOperatorNode_BITSCAST (line 95) | def as_hdl_HOperatorNode_BITSCAST(self, op: HOperatorNode):
method as_hdl_HOperatorNode_TRUNC (line 109) | def as_hdl_HOperatorNode_TRUNC(self, op: HOperatorNode):
method as_hdl_HOperatorNode_SEXT_ZEXT (line 122) | def as_hdl_HOperatorNode_SEXT_ZEXT(self, op: HOperatorNode):
method as_hdl_HOperatorNode_INDEX (line 162) | def as_hdl_HOperatorNode_INDEX(self, op: HOperatorNode):
method as_hdl_HOperatorNode (line 180) | def as_hdl_HOperatorNode(self, op: HOperatorNode):
FILE: hwt/serializer/verilog/serializer.py
class ToHdlAstVerilog (line 25) | class ToHdlAstVerilog(ToHdlAstVerilog_types,
method __init__ (line 30) | def __init__(self, name_scope: Optional[NameScope]=None):
method as_hdl_HdlModuleDef_variable (line 34) | def as_hdl_HdlModuleDef_variable(
method _static_assert_false (line 76) | def _static_assert_false(self, msg:str):
method _static_assert_symbol_eq (line 79) | def _static_assert_symbol_eq(self, symbol_name:str, v):
method as_hdl_GenericItem (line 94) | def as_hdl_GenericItem(self, g: HdlIdDef):
method as_hdl_HdlPortItem (line 107) | def as_hdl_HdlPortItem(self, pi: HdlPortItem):
method _as_hdl_HdlModuleDef_param_asserts (line 113) | def _as_hdl_HdlModuleDef_param_asserts(self, new_m: HdlModuleDec) -> L...
FILE: hwt/serializer/verilog/statements.py
class ToHdlAstVerilog_statements (line 11) | class ToHdlAstVerilog_statements():
method as_hdl_HdlAssignmentContainer (line 13) | def as_hdl_HdlAssignmentContainer(self, a: HdlAssignmentContainer):
method can_pop_process_wrap (line 34) | def can_pop_process_wrap(self, stms, hasToBeVhdlProcess):
method has_to_be_process (line 41) | def has_to_be_process(self, proc: HdlStmCodeBlockContainer):
method as_hdl_HdlStmCodeBlockContainer (line 48) | def as_hdl_HdlStmCodeBlockContainer(self, proc: HdlStmCodeBlockContain...
FILE: hwt/serializer/verilog/types.py
class ToHdlAstVerilog_types (line 15) | class ToHdlAstVerilog_types():
method does_type_requires_extra_def (line 20) | def does_type_requires_extra_def(self, t: HdlType, other_types: list):
method as_hdl_HdlType_bits (line 27) | def as_hdl_HdlType_bits(self, typ: HBits, declaration=False):
method as_hdl_HdlType_array (line 58) | def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
method as_hdl_HdlType_enum (line 67) | def as_hdl_HdlType_enum(self, typ, declaration=False):
method as_hdl_HdlType_float (line 77) | def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
FILE: hwt/serializer/verilog/utils.py
function verilogTypeOfSig (line 14) | def verilogTypeOfSig(s: Union[HdlSignalItem, HdlPortItem]):
FILE: hwt/serializer/verilog/value.py
class ToHdlAstVerilog_Value (line 23) | class ToHdlAstVerilog_Value(ToHdlAst_Value):
method as_hdl_HBoolConst (line 28) | def as_hdl_HBoolConst(self, val: HBitsConst):
method as_hdl_cond (line 31) | def as_hdl_cond(self, c, forceBool):
method as_hdl_HEnumConst (line 42) | def as_hdl_HEnumConst(self, val: HEnumConst):
method as_hdl_HdlSignalItem (line 47) | def as_hdl_HdlSignalItem(self, si, declaration=False):
method as_hdl_HSliceConst (line 54) | def as_hdl_HSliceConst(self, val: HSliceConst):
method sensitivityListItem (line 59) | def sensitivityListItem(self, item, anyIsEventDependent):
method as_hdl_HArrayConst (line 72) | def as_hdl_HArrayConst(self, val):
method as_hdl_BitString (line 79) | def as_hdl_BitString(self, v: int, width: int, force_vector: bool, vld...
FILE: hwt/serializer/vhdl/__init__.py
class Vhdl2008Serializer (line 9) | class Vhdl2008Serializer():
FILE: hwt/serializer/vhdl/ops.py
function isResultOfTypeConversionForIndex (line 32) | def isResultOfTypeConversionForIndex(sig: RtlSignal):
function matchZextOrSextArg (line 43) | def matchZextOrSextArg(op: Union[RtlSignal, HConst]) -> tuple[Optional[A...
function matchFullWidthMul (line 88) | def matchFullWidthMul(op0: Union[RtlSignal, HConst], op1: Union[RtlSigna...
class ToHdlAstVhdl2008_ops (line 106) | class ToHdlAstVhdl2008_ops(ToHdlAstVhdl2008_types):
method _tmp_var_for_ternary (line 136) | def _tmp_var_for_ternary(self, val: RtlSignal) -> RtlSignal:
method _tmp_var_for_arrayAggregate (line 166) | def _tmp_var_for_arrayAggregate(self, val: RtlSignal) -> RtlSignal:
method _as_Bits (line 182) | def _as_Bits(self, val: Union[RtlSignal, HConst]):
method _as_Bits_vec (line 203) | def _as_Bits_vec(self, val: Union[RtlSignal, HConst]):
method as_hdl_operand (line 222) | def as_hdl_operand(self, operand: Union[RtlSignal, HConst]):
method apply_cast (line 253) | def apply_cast(self, t: HdlValueId, op):
method _wrapConcatInTmpVariable (line 256) | def _wrapConcatInTmpVariable(self, op):
method _as_hdl_HOperatorNode_mulWithTrunc (line 269) | def _as_hdl_HOperatorNode_mulWithTrunc(self, op: HOperatorNode,
method _as_hdl_HOperatorNode_castArg (line 304) | def _as_hdl_HOperatorNode_castArg(self, op0: Union[HBitsConst, HBitsRt...
method as_hdl_HOperatorNode_indexRhs (line 309) | def as_hdl_HOperatorNode_indexRhs(self, op1: Union[HBitsConst, HBitsRt...
method as_hdl_HOperatorNode_TRUNC_SEXT_ZEXT (line 325) | def as_hdl_HOperatorNode_TRUNC_SEXT_ZEXT(self, op: HOperatorNode, o: H...
method as_hdl_HOperatorNode_INDEX (line 387) | def as_hdl_HOperatorNode_INDEX(self, op: HOperatorNode):
method as_hdl_HOperatorNode_TERNARY (line 407) | def as_hdl_HOperatorNode_TERNARY(self, op: HOperatorNode):
method as_hdl_HOperatorNode_asVhdlFn (line 423) | def as_hdl_HOperatorNode_asVhdlFn(self, op: HOperatorNode, vhldFn: Hdl...
method as_hdl_HOperatorNode (line 445) | def as_hdl_HOperatorNode(self, op: HOperatorNode):
FILE: hwt/serializer/vhdl/serializer.py
class VhdlNameScope (line 22) | class VhdlNameScope(NameScope):
method checked_name (line 25) | def checked_name(self, suggested_name, actualObj):
class ToHdlAstVhdl2008 (line 38) | class ToHdlAstVhdl2008(ToHdlAstVhdl2008_Value,
method getBaseNameScope (line 56) | def getBaseNameScope(cls):
method _find_HdlCompInst (line 62) | def _find_HdlCompInst(o):
method _static_assert_false (line 81) | def _static_assert_false(self, msg:str):
method _static_assert_symbol_eq (line 87) | def _static_assert_symbol_eq(self, symbol_name:str, v):
method _as_hdl_HdlModuleDef_param_asserts (line 93) | def _as_hdl_HdlModuleDef_param_asserts(self, new_m: HdlModuleDec) -> L...
method as_hdl_HdlModuleDef (line 96) | def as_hdl_HdlModuleDef(self, o: HdlModuleDef):
method as_hdl_HldComponent (line 125) | def as_hdl_HldComponent(self, o: HdlCompInst):
FILE: hwt/serializer/vhdl/statements.py
class ToHdlAstVhdl2008_statements (line 21) | class ToHdlAstVhdl2008_statements():
method _expandBitsOperandType (line 24) | def _expandBitsOperandType(v):
method as_hdl_HdlAssignmentContainer (line 34) | def as_hdl_HdlAssignmentContainer(self, a: HdlAssignmentContainer):
method as_hdl_SwitchContainer (line 96) | def as_hdl_SwitchContainer(self, sw: SwitchContainer) -> HdlStmCase:
method can_pop_process_wrap (line 111) | def can_pop_process_wrap(self, stms, hasToBeVhdlProcess):
method has_to_be_process (line 118) | def has_to_be_process(self, proc: HdlStmCodeBlockContainer):
FILE: hwt/serializer/vhdl/types.py
class ToHdlAstVhdl2008_types (line 14) | class ToHdlAstVhdl2008_types():
method as_hdl_HdlType_str (line 29) | def as_hdl_HdlType_str(self, typ: HString, declaration=False):
method as_hdl_HdlType_bits (line 33) | def as_hdl_HdlType_bits(self, typ: HBits, declaration=False):
method as_hdl_HdlType_array (line 62) | def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
method as_hdl_HdlType_float (line 83) | def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
FILE: hwt/serializer/vhdl/value.py
class ToHdlAstVhdl2008_Value (line 16) | class ToHdlAstVhdl2008_Value(ToHdlAst_Value):
method as_hdl_cond (line 23) | def as_hdl_cond(self, c, forceBool):
method as_hdl_HEnumConst (line 34) | def as_hdl_HEnumConst(self, val: HEnumConst):
method as_hdl_HArrayConst (line 38) | def as_hdl_HArrayConst(self, val):
method sensitivityListItem (line 41) | def sensitivityListItem(self, item, anyIsEventDependnt):
method as_hdl_BitString (line 46) | def as_hdl_BitString(self, v, width: int,
method as_hdl_HBoolConst (line 73) | def as_hdl_HBoolConst(self, val: HBitsConst):
method as_hdl_HBitsConst (line 79) | def as_hdl_HBitsConst(self, val: HBitsConst):
method as_hdl_HSliceConst (line 96) | def as_hdl_HSliceConst(self, val: HSliceConst):
FILE: hwt/serializer/xdc/serializer.py
class XdcSerializer (line 13) | class XdcSerializer():
method __init__ (line 19) | def __init__(self, out):
method _get (line 22) | def _get(self, o: Union[Tuple[HwModule, RtlSignal, HwIO], iHdlConstrai...
method visit_get_clock_of (line 72) | def visit_get_clock_of(self, o: get_clock_of):
method visit_iHdlConstrain (line 81) | def visit_iHdlConstrain(self, o):
method visit_HdlConstraintList (line 88) | def visit_HdlConstraintList(self, o_list):
method visit_set_async_reg (line 91) | def visit_set_async_reg(self, o: set_async_reg):
method visit_set_false_path (line 97) | def visit_set_false_path(self, o: set_false_path):
method visit_set_max_delay (line 110) | def visit_set_max_delay(self, o: set_max_delay):
FILE: hwt/simulator/agentBase.py
class AgentWitReset (line 8) | class AgentWitReset(pcAgentWitReset):
method __init__ (line 10) | def __init__(self, sim: HdlSimulator, hwIO, allowNoReset=False):
method _discoverReset (line 15) | def _discoverReset(cls, hwIO, allowNoReset: bool):
method notReset (line 27) | def notReset(self):
class SyncAgentBase (line 36) | class SyncAgentBase(AgentWitReset, pcSyncAgentBase):
method __init__ (line 46) | def __init__(self, sim: HdlSimulator, hwIO, allowNoReset=False):
FILE: hwt/simulator/agentConnector.py
function autoAddAgents (line 8) | def autoAddAgents(module: HwModule, sim: HdlSimulator):
function collect_processes_from_sim_agents (line 23) | def collect_processes_from_sim_agents(module: HwModule):
FILE: hwt/simulator/rtlSimulator.py
class BasicRtlSimulatorWithSignalRegisterMethods (line 37) | class BasicRtlSimulatorWithSignalRegisterMethods(BasicRtlSimulator):
method __init__ (line 40) | def __init__(self, model_cls, synthesised_unit):
method __call__ (line 50) | def __call__(self) -> "BasicRtlSimulatorVcd":
method _init_listeners (line 61) | def _init_listeners(self):
method build (line 66) | def build(cls,
method _get_rtl_instance_name_from_submodule_name (line 129) | def _get_rtl_instance_name_from_submodule_name(name: str):
method get_trace_formatter (line 137) | def get_trace_formatter(t)\
method set_trace_file (line 149) | def set_trace_file(self, file_name, trace_depth):
method create_wave_writer (line 162) | def create_wave_writer(self, file_name: str):
method finalize (line 165) | def finalize(self):
method _collect_empty_hiearchy_containers (line 168) | def _collect_empty_hiearchy_containers(self,
method _wave_register_signals (line 203) | def _wave_register_signals(self,
method _wave_register_remaining_signals (line 252) | def _wave_register_remaining_signals(self, unitScope,
method logChange (line 265) | def logChange(self, nowTime: int,
FILE: hwt/simulator/rtlSimulatorJson.py
class BasicRtlSimulatorJson (line 24) | class BasicRtlSimulatorJson(BasicRtlSimulatorWithSignalRegisterMethods):
method get_trace_formatter (line 28) | def get_trace_formatter(self, t: HdlType)\
method create_wave_writer (line 49) | def create_wave_writer(self, data):
method logChange (line 52) | def logChange(self, nowTime: int,
FILE: hwt/simulator/rtlSimulatorVcd.py
class BasicRtlSimulatorVcd (line 18) | class BasicRtlSimulatorVcd(BasicRtlSimulatorWithSignalRegisterMethods):
method create_wave_writer (line 23) | def create_wave_writer(self, file_name):
method finalize (line 27) | def finalize(self):
method _logChange (line 37) | def _logChange(self, nowTime: int,
FILE: hwt/simulator/simTestCase.py
class DummySimPlatform (line 20) | class DummySimPlatform(DummyPlatform):
class SimTestCase (line 30) | class SimTestCase(unittest.TestCase):
method assertValEqual (line 62) | def assertValEqual(self, first, second, msg=None):
method assertEmpty (line 73) | def assertEmpty(self, val, msg=None):
method assertValSequenceEqual (line 76) | def assertValSequenceEqual(self, seq1, seq2, msg=None, seq_type=None):
method getTestName (line 103) | def getTestName(self):
method runSim (line 107) | def runSim(self, until: int, name=None):
method randomize (line 133) | def randomize(self, hwIO):
method restartSim (line 147) | def restartSim(self):
method rmSim (line 168) | def rmSim(self):
method get_unique_name (line 186) | def get_unique_name(cls, module: HwModule):
method compileSim (line 191) | def compileSim(cls, dut: HwModule, build_dir: Optional[str]=_UNSPECIFIED,
method compileSimAndStart (line 228) | def compileSimAndStart(
method setUp (line 249) | def setUp(self):
function simpleRandomizationProcess (line 258) | def simpleRandomizationProcess(tc: SimTestCase, agent, timeQuantum=CLK_P...
FILE: hwt/simulator/utils.py
function pprintHwIO (line 19) | def pprintHwIO(hwio: Union[HwModule, HwIOBase], indent:int=0, prefix:str...
function pprintAgents (line 45) | def pprintAgents(hwModuleOrHwIO: HwModuleOrHwIOBase, indent:int=0, prefi...
function reconnectHwModuleSignalsToModel (line 65) | def reconnectHwModuleSignalsToModel(synthesisedHwModuleOrHwIO: HwModuleO...
function HConstSequenceToInts (line 103) | def HConstSequenceToInts(values: Sequence[HConst]):
function agentDataToInts (line 110) | def agentDataToInts(interface):
function Bits3valToInt (line 118) | def Bits3valToInt(v: HConst):
function allHConstsToInts (line 125) | def allHConstsToInts(sequenceOrVal):
FILE: hwt/synth.py
function to_rtl (line 15) | def to_rtl(hmodule_or_cls: HwModule, store_manager: StoreManager,
function _HwModule_constraints_copy_recursively (line 64) | def _HwModule_constraints_copy_recursively(m: HwModule, path_orig: Compo...
function to_rtl_str (line 81) | def to_rtl_str(hwmodule_or_cls: HwModule,
function serializeAsIpcore (line 93) | def serializeAsIpcore(m: HwModule, folderName=".", name=None,
function synthesised (line 107) | def synthesised(m: HwModule, target_platform=DummyPlatform()):
FILE: hwt/synthesizer/componentPath.py
function to_tuple_of_names (line 8) | def to_tuple_of_names(objs):
class ComponentPath (line 18) | class ComponentPath(tuple):
method __new__ (line 20) | def __new__ (cls, *objs):
method __truediv__ (line 23) | def __truediv__(self, other):
method resolve (line 29) | def resolve(self) -> "ComponentPath":
method is_absolute (line 81) | def is_absolute(self):
method update_prefix (line 88) | def update_prefix(self, old_path_prefix: "ComponentPath", new_path_pre...
method __getitem__ (line 98) | def __getitem__(self, key):
method __repr__ (line 104) | def __repr__(self):
method __str__ (line 107) | def __str__(self):
method __copy__ (line 110) | def __copy__(self):
method __deepcopy__ (line 113) | def __deepcopy__(self, memo):
FILE: hwt/synthesizer/dummyPlatform.py
class DummyPlatform (line 9) | class DummyPlatform():
method __init__ (line 19) | def __init__(self):
FILE: hwt/synthesizer/exceptions.py
class TypeConversionErr (line 4) | class TypeConversionErr(TypeError):
class ConfErr (line 8) | class ConfErr(Exception):
class IntfLvlConfErr (line 12) | class IntfLvlConfErr(ConfErr):
class SigLvlConfErr (line 19) | class SigLvlConfErr(ConfErr):
class InterfaceStructureErr (line 26) | class InterfaceStructureErr(IntfLvlConfErr):
method __init__ (line 34) | def __init__(self, dst: "HwIOBase", src: "HwIOBase", exclude: Set["HwI...
method __str__ (line 40) | def __str__(self):
method __repr__ (line 43) | def __repr__(self):
method __copy__ (line 79) | def __copy__(self):
FILE: hwt/synthesizer/interfaceLevel/directionFns.py
class HwIODirectionFns (line 6) | class HwIODirectionFns():
method _setDirectionsLikeIn (line 9) | def _setDirectionsLikeIn(self, hioDir: INTF_DIRECTION):
method _setAsExtern (line 24) | def _setAsExtern(self, isExtern: bool):
method _reverseDirection (line 34) | def _reverseDirection(self):
FILE: hwt/synthesizer/interfaceLevel/getDefaultClkRts.py
function getClk (line 5) | def getClk(module: HwModuleBase):
function getRst (line 17) | def getRst(module: HwModuleBase):
FILE: hwt/synthesizer/interfaceLevel/hwModuleImplHelpers.py
function getSignalName (line 22) | def getSignalName(sig: RtlSignalBase):
function HwIO_getName (line 29) | def HwIO_getName(top: HwModuleBase, io: Union[HwIOBase, RtlSignal,
function _default_param_updater (line 59) | def _default_param_updater(self, myP: "HwParam", otherP_val):
function _normalize_default_value_dict_for_HwIO_array (line 64) | def _normalize_default_value_dict_for_HwIO_array(root_val: dict,
function _instantiate_signals (line 99) | def _instantiate_signals(hwIO: Union[HwIOSignal, HwIOArray, HwIOStruct],
function _loadHwDeclarations (line 185) | def _loadHwDeclarations(intf_or_list: HwIOBase, suggested_name: str):
function HwIO_without_registration (line 194) | def HwIO_without_registration(
class HwModuleImplHelpers (line 217) | class HwModuleImplHelpers(HwModuleBase):
method _reg (line 219) | def _reg(self, name: str,
method _sig (line 272) | def _sig(self, name: str,
method _cleanThisSubunitRtlSignals (line 289) | def _cleanThisSubunitRtlSignals(self):
method _signalsForSubHwModuleEntity (line 297) | def _signalsForSubHwModuleEntity(self, context: RtlNetlist, prefix: str):
FILE: hwt/synthesizer/interfaceLevel/implDependent.py
class HwIOImplDependentFns (line 8) | class HwIOImplDependentFns():
method _getIpCoreIntfClass (line 14) | def _getIpCoreIntfClass(self):
method _initSimAgent (line 17) | def _initSimAgent(self, sim: HdlSimulator):
method _getAssociatedRst (line 22) | def _getAssociatedRst(self):
method _getAssociatedClk (line 40) | def _getAssociatedClk(self):
method __copy__ (line 58) | def __copy__(self):
FILE: hwt/synthesizer/interfaceLevel/propDeclrCollector.py
function nameAvailabilityCheck (line 14) | def nameAvailabilityCheck(obj: "PropDeclrCollector", propName: str, prop...
class MakeParamsShared (line 26) | class MakeParamsShared(object):
method __init__ (line 32) | def __init__(self, module: "HwModule", exclude:Optional[Tuple[Set[str]...
method __enter__ (line 37) | def __enter__(self):
method __exit__ (line 52) | def __exit__(self, exc_type, exc_val, exc_tb):
class MakeClkRstAssociations (line 58) | class MakeClkRstAssociations(object):
method __init__ (line 64) | def __init__(self, module: "HwModule", clk=None, rst=None):
method __enter__ (line 69) | def __enter__(self):
method __exit__ (line 84) | def __exit__(self, exc_type, exc_val, exc_tb):
class PropDeclrCollector (line 89) | class PropDeclrCollector(object):
method hwConfig (line 100) | def hwConfig(self) -> None:
method hwDeclr (line 110) | def hwDeclr(self) -> None:
method hwImpl (line 121) | def hwImpl(self) -> None:
method __setattr__ (line 130) | def __setattr__(self, attr:str, value) -> None:
method _loadConfig (line 144) | def _loadConfig(self) -> None:
method _registerParameter (line 156) | def _registerParameter(self, pName:str, parameter: HwParam) -> None:
method _hwParamsShared (line 171) | def _hwParamsShared(self,
method _make_association (line 189) | def _make_association(self, clk=None, rst=None) -> None:
method _associated (line 201) | def _associated(self, clk=None, rst=None) -> MakeClkRstAssociations:
method _updateHwParamsFrom (line 220) | def _updateHwParamsFrom(self,
method _registerSubmodule (line 266) | def _registerSubmodule(self, mName:str, submodule:"HwModule", onParent...
method _registerHwIO (line 278) | def _registerHwIO(self, hwIOName: str, hwIO: HwIOBase, onParentPropert...
method _declrCollector (line 298) | def _declrCollector(self, name: str, prop: object):
method _registerArray (line 313) | def _registerArray(self, name: Optional[str], items: HObjList[Self], o...
method _registerArray_append (line 327) | def _registerArray_append(self, arr: HObjList[Self], item: Self, index...
method _loadImpl (line 347) | def _loadImpl(self):
method _registerSubmoduleInImpl (line 353) | def _registerSubmoduleInImpl(self, name: str, m: HwModuleBase, onParen...
method _registerHwIOInHwImpl (line 367) | def _registerHwIOInHwImpl(self, hwIOName: str, hwio: HwIOBase, onParen...
method _paramCollector (line 374) | def _paramCollector(self, pName: str, prop):
method _implCollector (line 382) | def _implCollector(self, name: str, prop):
FILE: hwt/synthesizer/interfaceLevel/utils.py
class NotSpecifiedError (line 12) | class NotSpecifiedError(Exception):
function HwIO_walkSignals (line 23) | def HwIO_walkSignals(hwio: HwIOBase):
function HwIO_connectPacked (line 31) | def HwIO_connectPacked(srcPacked: RtlSignalBase,
function HwIO_walkFlatten (line 73) | def HwIO_walkFlatten(hwio: HwIOBase, shouldEnterHwIOFn: Optional[Callabl...
function HwIO_pack (line 87) | def HwIO_pack(hio: HwIOBase,
FILE: hwt/synthesizer/rtlLevel/exceptions.py
class SignalDriverErrType (line 4) | class SignalDriverErrType(Enum):
class SignalDriverErr (line 21) | class SignalDriverErr(Exception):
method __str__ (line 30) | def __str__(self):
FILE: hwt/synthesizer/rtlLevel/extract_part_drivers.py
function _format_indexes (line 24) | def _format_indexes(indexes):
function construct_tmp_dst_sig_for_slice (line 33) | def construct_tmp_dst_sig_for_slice(dst: RtlSignal,
function resolve_splitpoints (line 79) | def resolve_splitpoints(s: RtlSignal, parts):
class RtlNetlistPassExtractPartDrivers (line 108) | class RtlNetlistPassExtractPartDrivers(RtlNetlistPass):
method find_independent_slice_drivers (line 134) | def find_independent_slice_drivers(cls, stm: HdlStatement):
method find_all_independent_slice_drivers (line 154) | def find_all_independent_slice_drivers(cls, statements: Sequence[HdlSt...
method _collect_indexes_on_variables (line 160) | def _collect_indexes_on_variables(cls, statements: Sequence[HdlStateme...
method resolve_final_parts_from_splitpoints_and_parts (line 167) | def resolve_final_parts_from_splitpoints_and_parts(cls, signal_parts):
method extract_part_drivers_stm (line 304) | def extract_part_drivers_stm(cls, stm: HdlStatement,
method runOnRtlNetlist (line 391) | def runOnRtlNetlist(self, netlist: "RtlNetlist"):
FILE: hwt/synthesizer/rtlLevel/fill_stm_list_with_enclosure.py
class HdlAssignmentContainer_constructor (line 10) | class HdlAssignmentContainer_constructor():
method __init__ (line 12) | def __init__(self, src, dst):
method __call__ (line 16) | def __call__(self) -> HdlAssignmentContainer:
function fill_stm_list_with_enclosure (line 21) | def fill_stm_list_with_enclosure(parentStm: Optional[HdlStatement],
FILE: hwt/synthesizer/rtlLevel/mark_visibility_of_signals_and_check_drivers.py
function walk_assignments (line 16) | def walk_assignments(stm: HdlStatement, dst: RtlSignal)\
class RtlNetlistPassMarkVisibilityOfSignalsAndCheckDrivers (line 27) | class RtlNetlistPassMarkVisibilityOfSignalsAndCheckDrivers(RtlNetlistPass):
method runOnRtlNetlist (line 29) | def runOnRtlNetlist(self, netlist: "RtlNetlist"):
FILE: hwt/synthesizer/rtlLevel/netlist.py
class RtlNetlist (line 27) | class RtlNetlist():
method __init__ (line 40) | def __init__(self, parent: Optional["HwModule"]=None):
method sig (line 49) | def sig(self, name: str, dtype=BIT, clk=None, syncRst=None,
method create_HdlModuleDec (line 119) | def create_HdlModuleDec(self, name: str,
method create_HdlModuleDef (line 141) | def create_HdlModuleDef(self,
method getDebugScopeName (line 201) | def getDebugScopeName(self):
function _try_cast_any_to_HValue (line 215) | def _try_cast_any_to_HValue(v, dtype: HdlType, require_const: bool):
FILE: hwt/synthesizer/rtlLevel/reduce_processes.py
class HwtStmIncompatibleStructure (line 12) | class HwtStmIncompatibleStructure(Exception):
function checkIfIsTooSimple (line 19) | def checkIfIsTooSimple(proc):
function tryToMerge (line 32) | def tryToMerge(procA: HdlStmCodeBlockContainer,
function reduceProcesses (line 58) | def reduceProcesses(processes):
FILE: hwt/synthesizer/rtlLevel/remove_unconnected_signals.py
function walkInputsForSpecificOutput (line 21) | def walkInputsForSpecificOutput(output_sig: RtlSignalBase, stm: HdlState...
class RtlNetlistPassRemoveUnconnectedSignals (line 49) | class RtlNetlistPassRemoveUnconnectedSignals(RtlNetlistPass):
method __init__ (line 51) | def __init__(self, traceOutput:Optional[StringIO]=None):
method runOnRtlNetlist (line 54) | def runOnRtlNetlist(self, netlist: "RtlNetlist"):
FILE: hwt/synthesizer/rtlLevel/rtlNetlistPass.py
class RtlNetlistPass (line 3) | class RtlNetlistPass():
method runOnRtlNetlist (line 5) | def runOnRtlNetlist(self, netlist: "RtlNetlist"):
FILE: hwt/synthesizer/rtlLevel/rtlSignal.py
class CREATE_NEXT_SIGNAL (line 32) | class CREATE_NEXT_SIGNAL():
method __init__ (line 34) | def __init__(self):
class RtlSignal (line 38) | class RtlSignal(RtlSignalBase, HdlSignalItem):
method __init__ (line 83) | def __init__(self, ctx: 'RtlNetlist',
method _nextInstId (line 149) | def _nextInstId(cls):
method staticEval (line 157) | def staticEval(self):
method singleDriver (line 182) | def singleDriver(self):
method _walk_sensitivity (line 195) | def _walk_sensitivity(self, casualSensitivity: Set[RtlSignalBase], see...
method _walk_public_drivers (line 225) | def _walk_public_drivers(self, seen: set) -> Generator["RtlSignal", No...
method _auto_cast (line 241) | def _auto_cast(self, toType: HdlType):
method _reinterpret_cast (line 249) | def _reinterpret_cast(self, toType: HdlType):
method _create_HOperator (line 258) | def _create_HOperator(self, operator: HOperatorDef, opCreateDelegate ,...
method _getIndexCascade (line 299) | def _getIndexCascade(self):
method _getDestinationSignalForAssignmentToThis (line 355) | def _getDestinationSignalForAssignmentToThis(self):
method __call__ (line 361) | def __call__(self, source,
method _getAssociatedClk (line 462) | def _getAssociatedClk(self) -> Self:
method _getAssociatedRst (line 470) | def _getAssociatedRst(self) -> Self:
method _is_full_valid (line 480) | def _is_full_valid(self) -> bool:
method _is_partially_valid (line 483) | def _is_partially_valid(self) -> bool:
FILE: hwt/synthesizer/rtlLevel/rtlSignalWalkers.py
function discoverEventDependency (line 9) | def discoverEventDependency(sig: RtlSignalBase):
function discover_sensitivity_of_sig (line 30) | def discover_sensitivity_of_sig(signal: RtlSignalBase,
FILE: hwt/synthesizer/rtlLevel/statements_to_HdlStmCodeBlockContainers.py
function cut_off_drivers_of (line 19) | def cut_off_drivers_of(dstSignal: RtlSignal, statements: ListOfHdlStatem...
function name_for_process (line 39) | def name_for_process(outputs: List[RtlSignal]) -> str:
function _statements_to_HdlStmCodeBlockContainers (line 55) | def _statements_to_HdlStmCodeBlockContainers(_statements, tryToSolveComb...
function statements_to_HdlStmCodeBlockContainers (line 160) | def statements_to_HdlStmCodeBlockContainers(statements: ListOfHdlStateme...
FILE: hwt/synthesizer/typePath.py
class TypePath (line 5) | class TypePath(tuple[Union[str, int], ...]):
method __new__ (line 10) | def __new__ (cls, *objs):
method __truediv__ (line 13) | def __truediv__(self, other: Union[int, str, "TypePath"]):
method getOnObject (line 20) | def getOnObject(self, o):
method __getitem__ (line 29) | def __getitem__(self, key:SupportsIndex)->Union[Self, int, str]:
method setOnObject (line 35) | def setOnObject(self, o, newV):
method __copy__ (line 45) | def __copy__(self):
method __deepcopy__ (line 48) | def __deepcopy__(self, memo):
FILE: hwt/synthesizer/vectorUtils.py
class NotEnoughtBitsErr (line 11) | class NotEnoughtBitsErr(Exception):
class BitWalker (line 17) | class BitWalker():
method __init__ (line 26) | def __init__(self, sigOrConst: Union[RtlSignalBase, HConst],
method _get (line 39) | def _get(self, numberOfBits: int, doCollect: bool):
method get (line 102) | def get(self, numberOfBits: int) -> Union[RtlSignalBase, HConst]:
method skip (line 109) | def skip(self, numberOfBits: int) -> None:
method assertIsOnEnd (line 117) | def assertIsOnEnd(self):
function iterBits (line 129) | def iterBits(sigOrConst: Union[RtlSignalBase, HConst], bitsInOne: int=1,
Condensed preview — 208 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (920K chars).
[
{
"path": ".circleci/config.yml",
"chars": 630,
"preview": "version: 2.1\n\norbs:\n python: circleci/python@3.1.0\n py: nic30/python-all-in-1@0.3.1\n\njobs:\n install-test-deploy:\n "
},
{
"path": ".coveragerc",
"chars": 188,
"preview": "[run]\nbranch = True\n\nsource =\n hwt\n\n[report]\nexclude_lines =\n pragma: no cover\n def __repr__\n raise Assertio"
},
{
"path": ".gitignore",
"chars": 154,
"preview": "*.pyc\n*.dill\n*.class\n\n# python egg folders\nbuild/\ndist/\nhwt.egg-info/\n\n# eclipse project files\n.project\n.pydevproject\n.s"
},
{
"path": ".readthedocs.yml",
"chars": 203,
"preview": "version: 2\nbuild:\n os: ubuntu-lts-latest\n tools:\n python: \"3.12\"\n apt_packages:\n - graphviz\npython:\n install:\n"
},
{
"path": "LICENSE",
"chars": 1073,
"preview": "The MIT License (MIT)\n\nCopyright (c) 2015 Nic30\n\nPermission is hereby granted, free of charge, to any person obtaining a"
},
{
"path": "MANIFEST.in",
"chars": 37,
"preview": "include README.md\ninclude MANIFEST.in"
},
{
"path": "README.md",
"chars": 13653,
"preview": "# HWToolkit (hwt),\n# the library for hardware development in Python\n[![CircleCI](https://circleci.com/gh/Nic30/hwt.svg?s"
},
{
"path": "doc/conf.py",
"chars": 5942,
"preview": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# This file is execfile()d with the current directory set to its\n# cont"
},
{
"path": "doc/gtkwave.rst",
"chars": 109,
"preview": "GTKWave useful tweaks\n======================\n\n.. code-block:: text\n\n echo splash_disable 1 >> ~/.gtkwaverc"
},
{
"path": "doc/hwtCircuitNormalForm.rst",
"chars": 5742,
"preview": "HWT Circuit normal form (hwtCircuitNF)\n======================================\n\nHWT Circuit normal form (hwtCircuitNF) is"
},
{
"path": "doc/index.rst",
"chars": 2533,
"preview": "Welcome to hwt (HWToolkit) generated documentation!\n===================================================\n\nThis documentat"
},
{
"path": "doc/requirements.doc.txt",
"chars": 42,
"preview": "-r requirements.txt\nsphinx_bootstrap_theme"
},
{
"path": "doc/requirements.txt",
"chars": 374,
"preview": "git+https://github.com/Nic30/pyMathBitPrecise.git@master#egg=pyMathBitPrecise\ngit+https://github.com/Nic30/pyDigitalWave"
},
{
"path": "hwt/__init__.py",
"chars": 0,
"preview": ""
},
{
"path": "hwt/code.py",
"chars": 14102,
"preview": "from operator import and_, or_, xor, add, eq\nfrom types import GeneratorType\nfrom typing import Union, Sequence, Optiona"
},
{
"path": "hwt/code_utils.py",
"chars": 2812,
"preview": "from typing import Union\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.defs "
},
{
"path": "hwt/constants.py",
"chars": 631,
"preview": "\"\"\"\nCommonly used constants during HW development.\n\"\"\"\n\n# import constants from other packages to have them on one place"
},
{
"path": "hwt/constraints.py",
"chars": 5166,
"preview": "\"\"\"\nThis module contains the objects to store hardware constraints.\nHardware constrains are usually stored in XDC/UCF fi"
},
{
"path": "hwt/doc_markers.py",
"chars": 414,
"preview": "\n\ndef internal(fn):\n \"\"\"\n Decorator which does not affect functionality but it is used as marker\n which tells t"
},
{
"path": "hwt/hObjList.py",
"chars": 5865,
"preview": "from typing import TypeVar, Iterable, List, Union, Tuple, Optional, \\\n Self\n\nfrom hwt.mainBases import HwIOBase, HwMo"
},
{
"path": "hwt/hdl/__init__.py",
"chars": 322,
"preview": "\"\"\"\nThis package contains classes for representation of HDL\nlanguages (hdl types, RtlSignal, HdlAssignmentContainer, Hdl"
},
{
"path": "hwt/hdl/commonConstants.py",
"chars": 75,
"preview": "from hwt.hdl.types.defs import BIT\nb1 = BIT.from_py(1)\nb0 = BIT.from_py(0)\n"
},
{
"path": "hwt/hdl/const.py",
"chars": 3259,
"preview": "from typing import TypeVar, Generic, Self, Set\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.sensitivityCtx import "
},
{
"path": "hwt/hdl/constUtils.py",
"chars": 879,
"preview": "from typing import Union, List\n\nfrom hwt.hdl.const import HConst\n\n\ndef isSameHConst(a: HConst, b: HConst) -> bool:\n \""
},
{
"path": "hwt/hdl/frameTmpl.py",
"chars": 17877,
"preview": "from itertools import zip_longest\nfrom math import ceil, floor, inf\nfrom typing import Union, Generator, List, Tuple\n\nfr"
},
{
"path": "hwt/hdl/frameTmplUtils.py",
"chars": 8133,
"preview": "from typing import Tuple\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.transPart import TransPart\nfrom hwt.hdl.tran"
},
{
"path": "hwt/hdl/hdlObject.py",
"chars": 677,
"preview": "from io import StringIO\n\nfrom hdlConvertorAst.translate.common.name_scope import NameScope\n\n\nclass HdlObject():\n \"\"\"\n"
},
{
"path": "hwt/hdl/operator.py",
"chars": 8626,
"preview": "from typing import Generator, Union, Tuple, Optional, Set, Sequence\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.c"
},
{
"path": "hwt/hdl/operatorDefs.py",
"chars": 8374,
"preview": "from operator import floordiv, add, sub, inv, mul, ne, and_, or_, \\\n xor, gt, ge, lt, le, getitem, neg\nfrom typing im"
},
{
"path": "hwt/hdl/operatorUtils.py",
"chars": 2584,
"preview": "from typing import Union, Tuple\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.port"
},
{
"path": "hwt/hdl/portItem.py",
"chars": 3711,
"preview": "from hwt.constants import DIRECTION\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.sensitivityCtx import SensitivityC"
},
{
"path": "hwt/hdl/sensitivityCtx.py",
"chars": 738,
"preview": "from hwt.doc_markers import internal\nfrom hwt.pyUtils.setList import SetList\n\n\nclass SensitivityCtx(SetList):\n \"\"\"\n "
},
{
"path": "hwt/hdl/statements/__init__.py",
"chars": 0,
"preview": ""
},
{
"path": "hwt/hdl/statements/assignmentContainer.py",
"chars": 7345,
"preview": "from typing import Tuple, List, Dict, Union, Optional, Generator\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.cons"
},
{
"path": "hwt/hdl/statements/codeBlockContainer.py",
"chars": 4227,
"preview": "from itertools import compress\nfrom typing import List, Set, Tuple, Generator\n\nfrom hwt.doc_markers import internal\nfrom"
},
{
"path": "hwt/hdl/statements/ifContainter.py",
"chars": 18210,
"preview": "\n\nfrom copy import deepcopy\nfrom functools import reduce\nfrom itertools import compress\nfrom operator import and_\nfrom t"
},
{
"path": "hwt/hdl/statements/statement.py",
"chars": 18962,
"preview": "from copy import deepcopy, copy\nfrom itertools import chain\nfrom typing import List, Tuple, Union, Optional, Dict, Calla"
},
{
"path": "hwt/hdl/statements/switchContainer.py",
"chars": 16772,
"preview": "from copy import deepcopy, copy\nfrom functools import reduce\nfrom itertools import compress\nfrom operator import and_\nfr"
},
{
"path": "hwt/hdl/statements/utils/__init__.py",
"chars": 0,
"preview": ""
},
{
"path": "hwt/hdl/statements/utils/comparison.py",
"chars": 805,
"preview": "from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement\n\n\ndef isSameStatementList(stmListA: ListOfHd"
},
{
"path": "hwt/hdl/statements/utils/ioDiscovery.py",
"chars": 1026,
"preview": "from typing import List, Set\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.statements.utils.listOfHdlStatements imp"
},
{
"path": "hwt/hdl/statements/utils/listOfHdlStatements.py",
"chars": 4369,
"preview": "from copy import deepcopy\nfrom itertools import islice\nfrom typing import Sequence, Dict, List, Union\n\nfrom hwt.doc_mark"
},
{
"path": "hwt/hdl/statements/utils/reduction.py",
"chars": 6289,
"preview": "from itertools import islice, zip_longest\nfrom typing import Tuple\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.st"
},
{
"path": "hwt/hdl/statements/utils/signalCut.py",
"chars": 1539,
"preview": "from typing import List\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.statements.utils.listOfHdlStatements import L"
},
{
"path": "hwt/hdl/transPart.py",
"chars": 2342,
"preview": "from typing import Tuple, Optional\n\nfrom hwt.hdl.transTmpl import TransTmpl\n\n\nclass TransPart(object):\n \"\"\"\n Conta"
},
{
"path": "hwt/hdl/transTmpl.py",
"chars": 11804,
"preview": "from builtins import isinstance\nfrom copy import deepcopy\nfrom typing import Callable, Tuple, Generator, Union, Optional"
},
{
"path": "hwt/hdl/types/__init__.py",
"chars": 102,
"preview": "\"\"\"\nThis package contains HDL types (e.g. Bits), value classes\nand conversion functions for them.\n\"\"\"\n"
},
{
"path": "hwt/hdl/types/array.py",
"chars": 2961,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt.mainBases import RtlSignalBase\nf"
},
{
"path": "hwt/hdl/types/arrayCast.py",
"chars": 3927,
"preview": "from typing import Union, Optional\n\nfrom hwt.code import Concat\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.types."
},
{
"path": "hwt/hdl/types/arrayConst.py",
"chars": 7834,
"preview": "from copy import copy\nfrom typing import Union, Self\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HCo"
},
{
"path": "hwt/hdl/types/bitConstFunctions.py",
"chars": 17499,
"preview": "from operator import ne, eq\nfrom typing import Callable, Union, Optional\n\nfrom hwt.doc_markers import internal\nfrom hwt."
},
{
"path": "hwt/hdl/types/bitConstFunctionsGetitem.py",
"chars": 15872,
"preview": "from typing import Union, Optional, Literal\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom "
},
{
"path": "hwt/hdl/types/bitConst_opReduce.py",
"chars": 2369,
"preview": "from typing import Union\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.mainBases impor"
},
{
"path": "hwt/hdl/types/bits.py",
"chars": 5958,
"preview": "from typing import Union, Literal, Optional, Self\n\nfrom hwt.constants import NOT_SPECIFIED\nfrom hwt.doc_markers import i"
},
{
"path": "hwt/hdl/types/bitsCast.py",
"chars": 8169,
"preview": "from typing import Union\n\nfrom hwt.doc_markers import internal\nfrom hwt.hObjList import HObjList\nfrom hwt.hdl.const impo"
},
{
"path": "hwt/hdl/types/bitsCastUtils.py",
"chars": 1338,
"preview": "from typing import Union\n\nfrom hwt.hdl.types.bits import HBits\n\n\nclass BitWidthErr(Exception):\n \"\"\"\n Wrong bit wid"
},
{
"path": "hwt/hdl/types/bitsConst.py",
"chars": 13259,
"preview": "from copy import copy\nfrom operator import eq\nfrom typing import Union, Self\n\nfrom hdlConvertorAst.to.hdlUtils import bi"
},
{
"path": "hwt/hdl/types/bitsRtlSignal.py",
"chars": 19188,
"preview": "from copy import copy\nfrom operator import eq\nfrom typing import Union, Optional, Self, Literal\n\nfrom hwt.constants impo"
},
{
"path": "hwt/hdl/types/defs.py",
"chars": 483,
"preview": "\"\"\"\nDefinitions of most common types\n\"\"\"\n\nfrom hwt.hdl.types.bits import HBits\nfrom hwt.hdl.types.float import HFloat\nfr"
},
{
"path": "hwt/hdl/types/enum.py",
"chars": 1757,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt.pyUtils.typingFuture import over"
},
{
"path": "hwt/hdl/types/enumConst.py",
"chars": 2377,
"preview": "from typing import Union, Self\n\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.operator import HOperatorNode\nfrom hwt.hdl"
},
{
"path": "hwt/hdl/types/float.py",
"chars": 1086,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt.pyUtils.typingFuture import over"
},
{
"path": "hwt/hdl/types/floatConst.py",
"chars": 2470,
"preview": "from copy import copy\nfrom decimal import DecimalTuple\nimport math\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.co"
},
{
"path": "hwt/hdl/types/function.py",
"chars": 589,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt"
},
{
"path": "hwt/hdl/types/hdlType.py",
"chars": 9630,
"preview": "from enum import Enum\nfrom typing import Union, Type, Self, Optional\n\nfrom hwt.doc_markers import internal\nfrom hwt.synt"
},
{
"path": "hwt/hdl/types/slice.py",
"chars": 806,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt.pyUtils.typingFuture import over"
},
{
"path": "hwt/hdl/types/sliceConst.py",
"chars": 3151,
"preview": "from copy import copy\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.bits imp"
},
{
"path": "hwt/hdl/types/sliceUtils.py",
"chars": 713,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.defs import INT, SLICE\nfrom hwt.hdl.types.slice import HSlice\nfr"
},
{
"path": "hwt/hdl/types/stream.py",
"chars": 2941,
"preview": "from math import inf, isinf\nfrom typing import List, Optional\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.types.h"
},
{
"path": "hwt/hdl/types/streamConst.py",
"chars": 4059,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.bits import HBits\nfrom hwt.hdl."
},
{
"path": "hwt/hdl/types/string.py",
"chars": 909,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.types.hdlType import HdlType\nfrom hwt.pyUtils.typingFuture import over"
},
{
"path": "hwt/hdl/types/stringConst.py",
"chars": 1723,
"preview": "from hwt.hdl.const import HConst\nfrom hwt.hdl.operator import HOperatorNode\nfrom hwt.hdl.operatorDefs import HwtOps\nfrom"
},
{
"path": "hwt/hdl/types/struct.py",
"chars": 9989,
"preview": "from typing import Self\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.hdlTyp"
},
{
"path": "hwt/hdl/types/structCast.py",
"chars": 2273,
"preview": "from typing import Union\n\nfrom hwt.code import Concat\nfrom hwt.doc_markers import internal\nfrom hwt.hObjList import HObj"
},
{
"path": "hwt/hdl/types/structUtils.py",
"chars": 3462,
"preview": "from copy import copy\nfrom typing import Union, Dict\n\nfrom hwt.hdl.types.array import HArray\nfrom hwt.hdl.types.bits imp"
},
{
"path": "hwt/hdl/types/structValBase.py",
"chars": 7378,
"preview": "from typing import Optional, Union\n\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.operator import HOperatorNode\nfrom hwt"
},
{
"path": "hwt/hdl/types/typeCast.py",
"chars": 1573,
"preview": "\nfrom typing import Optional, Any, Union\n\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.defs import INT, STR, BOOL"
},
{
"path": "hwt/hdl/types/union.py",
"chars": 8073,
"preview": "from collections import OrderedDict\nfrom typing import Optional, Tuple, Any\n\nfrom hwt.doc_markers import internal\nfrom h"
},
{
"path": "hwt/hdl/types/utils.py",
"chars": 4033,
"preview": "from typing import Union, List\n\nfrom hwt.hdl.const import HConst\nfrom hwt.hdl.types.array import HArray\nfrom hwt.hdl.typ"
},
{
"path": "hwt/hdl/variables.py",
"chars": 1255,
"preview": "from hwt.doc_markers import internal\nfrom hwt.hdl.hdlObject import HdlObject\nfrom hwt.mainBases import RtlSignalBase\n\n\nc"
},
{
"path": "hwt/hwIO.py",
"chars": 15977,
"preview": "from copy import copy\nfrom typing import Optional, Union, Generator, Callable, Self, Collection\n\nfrom hdlConvertorAst.tr"
},
{
"path": "hwt/hwIOs/__init__.py",
"chars": 61,
"preview": "\"\"\"\nThis package contains primitive hardware interfaces.\n\"\"\"\n"
},
{
"path": "hwt/hwIOs/agents/__init__.py",
"chars": 150,
"preview": "\"\"\"\nThis package contains a UVM like simulation agents to handle IO between circuit running in simulator and the code wh"
},
{
"path": "hwt/hwIOs/agents/bramPort.py",
"chars": 10943,
"preview": "from collections import deque\nfrom typing import Literal, Union\n\nfrom hwt.constants import READ, WRITE, NOP\nfrom hwt.hdl"
},
{
"path": "hwt/hwIOs/agents/fifo.py",
"chars": 7672,
"preview": "from collections import deque\n\nfrom hwt.simulator.agentBase import SyncAgentBase\nfrom hwtSimApi.constants import CLK_PER"
},
{
"path": "hwt/hwIOs/agents/rdSync.py",
"chars": 2788,
"preview": "from collections import deque\n\nfrom hwt.constants import NOP\nfrom hwt.simulator.agentBase import SyncAgentBase\nfrom hwtS"
},
{
"path": "hwt/hwIOs/agents/rdVldSync.py",
"chars": 4561,
"preview": "from hwt.simulator.agentBase import SyncAgentBase\nfrom hwtSimApi.agents.rdVldSync import DataRdVldAgent\nfrom hwtSimApi.h"
},
{
"path": "hwt/hwIOs/agents/regCntrl.py",
"chars": 1395,
"preview": "from hwt.hwIOs.agents.signal import HwIOSignalAgent\nfrom hwt.hwIOs.agents.vldSync import HwIODataVldAgent\nfrom hwt.simul"
},
{
"path": "hwt/hwIOs/agents/signal.py",
"chars": 5020,
"preview": "from collections import deque\n\nfrom hwt.simulator.agentBase import SyncAgentBase\nfrom hwt.synthesizer.exceptions import "
},
{
"path": "hwt/hwIOs/agents/struct.py",
"chars": 1368,
"preview": "from typing import Union\n\nfrom hwt.hdl.types.structValBase import HStructConstBase\nfrom hwtSimApi.agents.base import Age"
},
{
"path": "hwt/hwIOs/agents/tuleWithCallback.py",
"chars": 192,
"preview": "\nclass TupleWithCallback(tuple):\n\n def __new__(cls, *args, onDone=None):\n t = tuple.__new__(cls, args)\n "
},
{
"path": "hwt/hwIOs/agents/union.py",
"chars": 576,
"preview": "from hwt.hwIOs.agents.struct import HwIOStructAgent\n\n\nclass HwIOUnionSourceAgent(HwIOStructAgent):\n\n def getMonitors("
},
{
"path": "hwt/hwIOs/agents/universalComposite.py",
"chars": 1276,
"preview": "from hwt.hwIO import HwIO\nfrom hwtSimApi.agents.base import AgentBase\nfrom hwtSimApi.hdlSimulator import HdlSimulator\nfr"
},
{
"path": "hwt/hwIOs/agents/vldSync.py",
"chars": 2378,
"preview": "from collections import deque\n\nfrom hwt.constants import NOP\nfrom hwt.simulator.agentBase import SyncAgentBase\nfrom hwtS"
},
{
"path": "hwt/hwIOs/hwIOArray.py",
"chars": 4604,
"preview": "from copy import copy\nfrom itertools import zip_longest\nfrom typing import Sequence, Optional, Union, Self\n\nfrom hwt.doc"
},
{
"path": "hwt/hwIOs/hwIODifferential.py",
"chars": 353,
"preview": "from hwt.hdl.types.bits import HBits\nfrom hwt.hwIO import HwIO\nfrom hwt.hwIOs.std import HwIOSignal\nfrom hwt.pyUtils.typ"
},
{
"path": "hwt/hwIOs/hwIOStruct.py",
"chars": 12375,
"preview": "from copy import copy\nfrom typing import Optional, Union, Set\n\nfrom hwt.code import And, Or\nfrom hwt.doc_markers import "
},
{
"path": "hwt/hwIOs/hwIOTristate.py",
"chars": 1551,
"preview": "from hwt.hdl.types.bits import HBits\nfrom hwt.hwIO import HwIO\nfrom hwt.hwIOs.std import HwIOSignal, HwIOClk\nfrom hwt.hw"
},
{
"path": "hwt/hwIOs/hwIOUnion.py",
"chars": 1125,
"preview": "from hwt.hwIOs.agents.union import HwIOUnionSourceAgent\nfrom hwt.hwIOs.hwIOStruct import HwIOStruct\nfrom hwt.hwIOs.std i"
},
{
"path": "hwt/hwIOs/hwIO_map.py",
"chars": 8770,
"preview": "from typing import Union, Tuple, Optional, List\n\nfrom hwt.doc_markers import internal\nfrom hwt.hwIO import HwIO\nfrom hwt"
},
{
"path": "hwt/hwIOs/signalOps.py",
"chars": 4704,
"preview": "from hwt.doc_markers import internal\n\n\nclass SignalOps(object):\n \"\"\"\n Operands for Signal interface,\n These ope"
},
{
"path": "hwt/hwIOs/std.py",
"chars": 12210,
"preview": "from typing import TypeVar, Generic, Union, Optional, Dict\n\nfrom hwt.hdl.types.bits import HBits\nfrom hwt.hdl.types.defs"
},
{
"path": "hwt/hwIOs/std_ip_defs.py",
"chars": 6089,
"preview": "from typing import List\n\nfrom hwt.hwIOs.std import HwIORst, HwIORst_n, HwIOClk\nfrom hwt.pyUtils.arrayQuery import where\n"
},
{
"path": "hwt/hwIOs/utils.py",
"chars": 2808,
"preview": "from hwt.constants import NOT_SPECIFIED\nfrom hwt.hwIOs.std import HwIOClk, HwIORst_n, HwIORst\nfrom hwt.mainBases import "
},
{
"path": "hwt/hwModule.py",
"chars": 14738,
"preview": "from copy import copy\nfrom natsort.natsort import natsorted\nfrom typing import Optional, Union\n\nfrom hdlConvertorAst.hdl"
},
{
"path": "hwt/hwParam.py",
"chars": 2113,
"preview": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\nfrom hwt.hdl.types.defs import INT, STR, BOOL, FLOAT64\nfrom hwt.hdl.const"
},
{
"path": "hwt/mainBases.py",
"chars": 439,
"preview": "from typing import TypeVar, Generic, Union\n\nfrom hwt.hdl.types.hdlType import HdlType\n\nT = TypeVar(\"T\", bound=HdlType)\n\n"
},
{
"path": "hwt/math.py",
"chars": 4653,
"preview": "from copy import copy\nimport math\nfrom typing import List, Union\n\nfrom hwt.doc_markers import hwt_expr_producer\nfrom hwt"
},
{
"path": "hwt/mathAutoExt.py",
"chars": 4140,
"preview": "from operator import add, sub\nfrom typing import Callable, Optional\n\nfrom hwt.code import Concat\nfrom hwt.doc_markers im"
},
{
"path": "hwt/pyUtils/__init__.py",
"chars": 65,
"preview": "\"\"\"\nThis package contains python utils used in this library.\n\"\"\"\n"
},
{
"path": "hwt/pyUtils/arrayQuery.py",
"chars": 3552,
"preview": "# select = map, groupBy = itertools.groupby\nfrom collections import deque\nfrom itertools import zip_longest\nfrom math im"
},
{
"path": "hwt/pyUtils/fileHelpers.py",
"chars": 857,
"preview": "import fnmatch\nimport os\n\n\ndef find_files(directory, pattern, recursive=True):\n \"\"\"\n Find files by pattern in dire"
},
{
"path": "hwt/pyUtils/setList.py",
"chars": 2561,
"preview": "from typing import Generic, TypeVar, Set, Sequence, Optional, Union\n\nT = TypeVar('T')\n\n\nclass SetList(Generic[T], list):"
},
{
"path": "hwt/pyUtils/testUtils.py",
"chars": 1932,
"preview": "from itertools import product\n\n# [todo] https://docs.python.org/3/library/unittest.html#distinguishing-test-iterations-u"
},
{
"path": "hwt/pyUtils/typingFuture.py",
"chars": 2063,
"preview": "import inspect\nimport re\nRE_CLASS_HEADER = re.compile(r'class.+\\(([^,]*)(?:,\\s*?(([^,]*)))*\\)\\s*\\:') # match comma sepa"
},
{
"path": "hwt/serializer/__init__.py",
"chars": 437,
"preview": "\"\"\"\nThis package contains serializers. Purpose of serializer class\nis to convert hwt representations of designed archite"
},
{
"path": "hwt/serializer/combLoopAnalyzer/__init__.py",
"chars": 5772,
"preview": "from copy import copy\nfrom itertools import chain\nfrom typing import Tuple\n\nfrom hdlConvertorAst.hdlAst._bases import iH"
},
{
"path": "hwt/serializer/combLoopAnalyzer/tarjan.py",
"chars": 2161,
"preview": "from typing import Generator\n\n\ndef _tarjan_head(index, lowlink, S, S_set, T, g, v):\n lowlink[v] = index[v] = len(inde"
},
{
"path": "hwt/serializer/exceptions.py",
"chars": 251,
"preview": "\nclass SerializerException(Exception):\n pass\n\n\nclass UnsupportedEventOpErr(SerializerException):\n \"\"\"\n Target H"
},
{
"path": "hwt/serializer/generic/__init__.py",
"chars": 59,
"preview": "\"\"\"\nThis package contains common parts of serializers.\n\"\"\"\n"
},
{
"path": "hwt/serializer/generic/constant_cache.py",
"chars": 1456,
"preview": "from hwt.hdl.const import HConst\nfrom hwt.serializer.generic.tmpVarConstructor import TmpVarConstructor\nfrom hwt.mainBas"
},
{
"path": "hwt/serializer/generic/indent.py",
"chars": 297,
"preview": "_indent = \" \"\n_indentCache = {}\n\n\ndef getIndent(indentNum: int):\n \"\"\"\n Cached indent getter function\n \"\"\"\n "
},
{
"path": "hwt/serializer/generic/ops.py",
"chars": 1077,
"preview": "from hdlConvertorAst.hdlAst._expr import HdlOpType\nfrom hwt.hdl.operatorDefs import HwtOps\n\n\nHWT_TO_HDLCONVERTOR_OPS = {"
},
{
"path": "hwt/serializer/generic/tmpVarConstructor.py",
"chars": 3230,
"preview": "from typing import Optional, Union, Tuple\n\nfrom hdlConvertorAst.hdlAst import HdlIdDef\nfrom hdlConvertorAst.translate.co"
},
{
"path": "hwt/serializer/generic/to_hdl_ast.py",
"chars": 18642,
"preview": "from copy import copy, deepcopy\nfrom typing import Optional, List, Union\n\nfrom hdlConvertorAst.hdlAst import iHdlStateme"
},
{
"path": "hwt/serializer/generic/utils.py",
"chars": 713,
"preview": "from ipCorePackager.constants import DIRECTION\nfrom hdlConvertorAst.hdlAst._expr import HdlDirection\nfrom hwt.doc_marker"
},
{
"path": "hwt/serializer/generic/value.py",
"chars": 5885,
"preview": "from copy import copy\nfrom typing import Union\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.h"
},
{
"path": "hwt/serializer/hwt/__init__.py",
"chars": 860,
"preview": "\"\"\"\nHwt serializer converts HDL objects back to code in python for hwt.\n\"\"\"\nfrom hdlConvertorAst.hdlAst import iHdlObj\n"
},
{
"path": "hwt/serializer/hwt/context.py",
"chars": 545,
"preview": "class ValueWidthRequirementScope():\n \"\"\"\n Context manager which temporarily swaps the _valueWidthRequired on speci"
},
{
"path": "hwt/serializer/hwt/ops.py",
"chars": 2697,
"preview": "from hdlConvertorAst.hdlAst._expr import HdlOp, HdlValueId\nfrom hdlConvertorAst.translate.common.name_scope import Langu"
},
{
"path": "hwt/serializer/hwt/serializer.py",
"chars": 2305,
"preview": "\nfrom typing import Optional, Union\n\nfrom hdlConvertorAst.hdlAst import HdlStmBlock\nfrom hdlConvertorAst.hdlAst._expr im"
},
{
"path": "hwt/serializer/hwt/types.py",
"chars": 2431,
"preview": "from hdlConvertorAst.hdlAst._expr import HdlValueId, HdlValueInt\nfrom hdlConvertorAst.translate.verilog_to_basic_hdl_sim"
},
{
"path": "hwt/serializer/hwt/value.py",
"chars": 5005,
"preview": "from copy import copy\nfrom typing import Union\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.h"
},
{
"path": "hwt/serializer/ip_packager.py",
"chars": 7608,
"preview": "from io import StringIO\nimport math\nfrom typing import List, Tuple, Union\n\nfrom hdlConvertorAst.hdlAst import HdlValueId"
},
{
"path": "hwt/serializer/mode.py",
"chars": 3444,
"preview": "\"\"\"\nSerializer mode specifies if hdl objects derived from parent unit\nshould be serialized to target HDL or not\n\nuse ser"
},
{
"path": "hwt/serializer/resourceAnalyzer/__init__.py",
"chars": 82,
"preview": "\"\"\"\nResource analyzer has serializer API, but it's output is resource report.\n\"\"\"\n"
},
{
"path": "hwt/serializer/resourceAnalyzer/analyzer.py",
"chars": 6750,
"preview": "from itertools import chain\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.hdlAst._structural i"
},
{
"path": "hwt/serializer/resourceAnalyzer/resourceTypes.py",
"chars": 3068,
"preview": "\n\nclass ResourceError(Exception):\n \"\"\"\n An error which means that the resource of this kind\n does not exists in"
},
{
"path": "hwt/serializer/resourceAnalyzer/utils.py",
"chars": 5288,
"preview": "from typing import Union\n\nfrom hwt.hdl.operator import HOperatorNode\nfrom hwt.hdl.statements.statement import HdlStateme"
},
{
"path": "hwt/serializer/serializer_config.py",
"chars": 378,
"preview": "from hwt.serializer.generic.to_hdl_ast import ToHdlAst\n\n\nclass DummySerializerConfig():\n \"\"\"\n The serializer which"
},
{
"path": "hwt/serializer/serializer_filter.py",
"chars": 2538,
"preview": "from typing import Optional, Tuple\n\nfrom hwt.serializer.mode import _serializeExclude_eval\nfrom hwt.hwModule import HwMo"
},
{
"path": "hwt/serializer/simModel/__init__.py",
"chars": 473,
"preview": "\"\"\"\nSim model serializer serialize HDL objects to simulation model writen in python.\nFor hwtSimApi.basic_rtl_simulator\n\""
},
{
"path": "hwt/serializer/simModel/serializer.py",
"chars": 8309,
"preview": "from copy import copy\nfrom typing import Optional, List\n\nfrom hdlConvertorAst.hdlAst._expr import HdlValueId, HdlValueIn"
},
{
"path": "hwt/serializer/simModel/tmpVarConstructorConstOnly.py",
"chars": 439,
"preview": "from hwt.serializer.generic.tmpVarConstructor import TmpVarConstructor\nfrom hwt.synthesizer.rtlLevel.rtlSignal import Rt"
},
{
"path": "hwt/serializer/simModel/types.py",
"chars": 1769,
"preview": "from hdlConvertorAst.hdlAst import HdlValueId, HdlValueInt\nfrom hdlConvertorAst.translate.common.name_scope import Langu"
},
{
"path": "hwt/serializer/simModel/value.py",
"chars": 7666,
"preview": "from typing import Union\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.hdlAst._expr import Hdl"
},
{
"path": "hwt/serializer/store_manager.py",
"chars": 5552,
"preview": "from io import StringIO\nimport os\nfrom typing import Type, Optional, Union\n\nfrom hdlConvertorAst.hdlAst import HdlModule"
},
{
"path": "hwt/serializer/systemC/__init__.py",
"chars": 475,
"preview": "\"\"\"\nSystemC serializer serializes HDL objects to systemC code.\n\"\"\"\nfrom hdlConvertorAst.to.systemc._main import ToSystem"
},
{
"path": "hwt/serializer/systemC/expr.py",
"chars": 6631,
"preview": "from typing import Union\n\nfrom hdlConvertorAst.hdlAst._expr import HdlValueId, HdlOp, HdlOpType\nfrom hdlConvertorAst.to."
},
{
"path": "hwt/serializer/systemC/serializer.py",
"chars": 3409,
"preview": "from copy import copy\nfrom typing import Optional\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAs"
},
{
"path": "hwt/serializer/systemC/statements.py",
"chars": 3542,
"preview": "from hdlConvertorAst.hdlAst._bases import iHdlStatement\nfrom hdlConvertorAst.hdlAst._statements import HdlStmAssign, Hdl"
},
{
"path": "hwt/serializer/systemC/type.py",
"chars": 2797,
"preview": "from hdlConvertorAst.hdlAst._expr import HdlOp, HdlOpType, HdlValueId\nfrom hdlConvertorAst.to.verilog.constants import S"
},
{
"path": "hwt/serializer/systemC/utils.py",
"chars": 1167,
"preview": "from hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.to.verilog.constants import SIGNAL_TYPE\nfrom hwt."
},
{
"path": "hwt/serializer/utils.py",
"chars": 1096,
"preview": "from natsort.natsort import natsort_keygen\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.statements.assignmentConta"
},
{
"path": "hwt/serializer/verilog/__init__.py",
"chars": 486,
"preview": "\"\"\"\nVerilog serializer serializes HDL objects to verilog code.\n\"\"\"\nfrom hdlConvertorAst.to.verilog.verilog2005 import To"
},
{
"path": "hwt/serializer/verilog/context.py",
"chars": 559,
"preview": "from hdlConvertorAst.to.verilog.constants import SIGNAL_TYPE\n\n\nclass SignalTypeSwap():\n \"\"\"\n An object which is us"
},
{
"path": "hwt/serializer/verilog/ops.py",
"chars": 8704,
"preview": "from builtins import isinstance\nfrom typing import Union\n\nfrom hdlConvertorAst.hdlAst import HdlValueInt\nfrom hdlConvert"
},
{
"path": "hwt/serializer/verilog/serializer.py",
"chars": 5037,
"preview": "from copy import copy\nfrom typing import Optional, List\n\nfrom hdlConvertorAst.hdlAst import HdlStmIf, HdlOp, \\\n HdlOp"
},
{
"path": "hwt/serializer/verilog/statements.py",
"chars": 2733,
"preview": "from hdlConvertorAst.hdlAst._bases import iHdlStatement\nfrom hdlConvertorAst.hdlAst._expr import HdlAll\nfrom hdlConverto"
},
{
"path": "hwt/serializer/verilog/types.py",
"chars": 3147,
"preview": "from hdlConvertorAst.hdlAst._expr import HdlTypeAuto, HdlValueId, HdlOp, \\\n HdlOpType\nfrom hdlConvertorAst.translate."
},
{
"path": "hwt/serializer/verilog/utils.py",
"chars": 1577,
"preview": "from typing import Union\n\nfrom hdlConvertorAst.hdlAst import iHdlStatement\nfrom hdlConvertorAst.to.verilog.constants imp"
},
{
"path": "hwt/serializer/verilog/value.py",
"chars": 3221,
"preview": "from typing import Optional\n\nfrom hdlConvertorAst.hdlAst._expr import HdlValueInt, HdlOpType, \\\n HdlOp\nfrom hdlConver"
},
{
"path": "hwt/serializer/vhdl/__init__.py",
"chars": 383,
"preview": "\"\"\"\nVHDL serializer serializes HDL objects to VHDL code.\n\"\"\"\nfrom hdlConvertorAst.to.vhdl.vhdl2008 import ToVhdl2008\nfro"
},
{
"path": "hwt/serializer/vhdl/ops.py",
"chars": 21259,
"preview": "from typing import Union, Optional\n\nfrom hdlConvertorAst.hdlAst import HdlValueInt\nfrom hdlConvertorAst.hdlAst._expr imp"
},
{
"path": "hwt/serializer/vhdl/serializer.py",
"chars": 5144,
"preview": "from natsort.natsort import natsorted\nimport re\nfrom typing import List\n\nfrom hdlConvertorAst.hdlAst import HdlOp, HdlMo"
},
{
"path": "hwt/serializer/vhdl/statements.py",
"chars": 4835,
"preview": "from copy import copy\n\nfrom hdlConvertorAst.hdlAst import HdlStmCase\nfrom hdlConvertorAst.hdlAst._statements import HdlS"
},
{
"path": "hwt/serializer/vhdl/types.py",
"chars": 3079,
"preview": "from hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlConvertorAst.hdlAst._expr import HdlValueId, HdlOp, HdlOpType,"
},
{
"path": "hwt/serializer/vhdl/value.py",
"chars": 3911,
"preview": "from hdlConvertorAst.hdlAst import HdlValueId, HdlValueInt, HdlOp, \\\n HdlOpType\nfrom hdlConvertorAst.to.hdlUtils impo"
},
{
"path": "hwt/serializer/xdc/__init__.py",
"chars": 0,
"preview": ""
},
{
"path": "hwt/serializer/xdc/serializer.py",
"chars": 3535,
"preview": "from itertools import islice\nfrom typing import Union, Tuple\n\nfrom hwt.constraints import set_max_delay, set_false_path,"
},
{
"path": "hwt/simulator/__init__.py",
"chars": 157,
"preview": "\"\"\"\nA package for binding to simulators and simulation utils.\n\n:note: hwt package does not contain any RTL simulator, th"
},
{
"path": "hwt/simulator/agentBase.py",
"chars": 1698,
"preview": "from hwt.synthesizer.exceptions import IntfLvlConfErr\nfrom hwtSimApi.agents.base import AgentBase, SyncAgentBase as pcSy"
},
{
"path": "hwt/simulator/agentConnector.py",
"chars": 1082,
"preview": "from hwt.doc_markers import internal\nfrom hwt.constants import INTF_DIRECTION\nfrom hwt.hwModule import HwModule\nfrom hwt"
},
{
"path": "hwt/simulator/rtlSimulator.py",
"chars": 11525,
"preview": "from datetime import datetime\nimport importlib\nfrom io import StringIO\nimport os\nimport sys\nfrom types import ModuleType"
},
{
"path": "hwt/simulator/rtlSimulatorJson.py",
"chars": 2567,
"preview": "from typing import Tuple, Callable, Union\n\nfrom pyMathBitPrecise.array3t import Array3t\nfrom pyMathBitPrecise.bits3t imp"
},
{
"path": "hwt/simulator/rtlSimulatorVcd.py",
"chars": 1759,
"preview": "\nimport sys\nfrom typing import Union\n\nfrom hwt.hdl.types.bits import HBits\nfrom hwt.hdl.types.enum import HEnum\nfrom hwt"
},
{
"path": "hwt/simulator/simTestCase.py",
"chars": 10236,
"preview": "import os\nfrom random import Random\nfrom typing import Optional\nimport unittest\n\nfrom hwt.simulator.agentConnector impor"
},
{
"path": "hwt/simulator/utils.py",
"chars": 4565,
"preview": "from collections import deque\nfrom inspect import isgenerator\nimport sys\nfrom typing import Union, Sequence\n\nfrom hwt.do"
},
{
"path": "hwt/synth.py",
"chars": 4310,
"preview": "# -*- coding: utf-8 -*-\n\nfrom io import StringIO\n\nfrom hwt.constraints import _get_absolute_path\nfrom hwt.hwModule impor"
},
{
"path": "hwt/synthesizer/__init__.py",
"chars": 390,
"preview": "\"\"\"\nSythesizer converts :class:`hwt.hwModule.HwModule` instances to HDL objects.\n\n:func:`hwt.synth.to_rtl` function is o"
},
{
"path": "hwt/synthesizer/componentPath.py",
"chars": 3837,
"preview": "from copy import deepcopy\n\nfrom hwt.hwIO import HwIO\nfrom hwt.hwModule import HwModule\nfrom hwt.synthesizer.rtlLevel.rtl"
},
{
"path": "hwt/synthesizer/dummyPlatform.py",
"chars": 1272,
"preview": "from typing import List\n\nfrom hwt.synthesizer.rtlLevel.extract_part_drivers import RtlNetlistPassExtractPartDrivers\nfrom"
},
{
"path": "hwt/synthesizer/exceptions.py",
"chars": 2379,
"preview": "from typing import Set\n\n\nclass TypeConversionErr(TypeError):\n pass\n\n\nclass ConfErr(Exception):\n pass\n\n\nclass IntfL"
},
{
"path": "hwt/synthesizer/interfaceLevel/__init__.py",
"chars": 81,
"preview": "\"\"\"\ninterfaceLevel is responsible for manipulation of high-level interfaces.\n\"\"\"\n"
},
{
"path": "hwt/synthesizer/interfaceLevel/directionFns.py",
"chars": 1241,
"preview": "from hwt.doc_markers import internal\nfrom ipCorePackager.constants import INTF_DIRECTION, DIRECTION\n\n\n@internal\nclass Hw"
},
{
"path": "hwt/synthesizer/interfaceLevel/getDefaultClkRts.py",
"chars": 656,
"preview": "from hwt.synthesizer.exceptions import IntfLvlConfErr\nfrom hwt.mainBases import HwModuleBase\n\n\ndef getClk(module: HwModu"
},
{
"path": "hwt/synthesizer/interfaceLevel/hwModuleImplHelpers.py",
"chars": 12013,
"preview": "from itertools import chain\nfrom typing import Union, Optional, Tuple\n\nfrom hwt.constants import NOT_SPECIFIED\nfrom hwt."
},
{
"path": "hwt/synthesizer/interfaceLevel/implDependent.py",
"chars": 1838,
"preview": "from hwt.mainBases import HwModuleBase\nfrom hwt.synthesizer.interfaceLevel.getDefaultClkRts import getRst, getClk\nfrom h"
},
{
"path": "hwt/synthesizer/interfaceLevel/propDeclrCollector.py",
"chars": 14524,
"preview": "from types import MethodType\nfrom typing import Tuple, Set, Optional, Callable, Self\n\nfrom hdlConvertorAst.translate.com"
},
{
"path": "hwt/synthesizer/interfaceLevel/utils.py",
"chars": 4356,
"preview": "from collections.abc import Container, Callable\nfrom typing import Union, Optional\n\nfrom hwt.constants import DIRECTION\n"
},
{
"path": "hwt/synthesizer/rtlLevel/__init__.py",
"chars": 71,
"preview": "\"\"\"\nrtlLevel is responsible for RtlSignal manipulation and design.\n\"\"\"\n"
},
{
"path": "hwt/synthesizer/rtlLevel/exceptions.py",
"chars": 1769,
"preview": "from enum import Enum\n\n\nclass SignalDriverErrType(Enum):\n (\n MISSING_DRIVER,\n MULTIPLE_COMB_DRIVERS,\n "
},
{
"path": "hwt/synthesizer/rtlLevel/extract_part_drivers.py",
"chars": 17208,
"preview": "from itertools import islice\nfrom typing import Dict, List, Tuple, Union, Optional, Sequence\n\nfrom hwt.code import Conca"
},
{
"path": "hwt/synthesizer/rtlLevel/fill_stm_list_with_enclosure.py",
"chars": 2329,
"preview": "from typing import Set, List, Dict, Optional, Callable\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.statements.ass"
},
{
"path": "hwt/synthesizer/rtlLevel/mark_visibility_of_signals_and_check_drivers.py",
"chars": 3777,
"preview": "from typing import Generator, Tuple, List\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.operator import HOperatorNo"
},
{
"path": "hwt/synthesizer/rtlLevel/netlist.py",
"chars": 9262,
"preview": "from typing import List, Optional, Union, Dict, Set, Type\n\nfrom hdlConvertorAst.hdlAst._defs import HdlIdDef\nfrom hdlCon"
},
{
"path": "hwt/synthesizer/rtlLevel/reduce_processes.py",
"chars": 2899,
"preview": "from itertools import islice\n\nfrom hwt.doc_markers import internal\nfrom hwt.hdl.statements.assignmentContainer import Hd"
},
{
"path": "hwt/synthesizer/rtlLevel/remove_unconnected_signals.py",
"chars": 5907,
"preview": "from collections import deque\nfrom io import StringIO\nfrom typing import Optional\n\nfrom hwt.doc_markers import internal\n"
},
{
"path": "hwt/synthesizer/rtlLevel/rtlNetlistPass.py",
"chars": 187,
"preview": "\n\nclass RtlNetlistPass():\n\n def runOnRtlNetlist(self, netlist: \"RtlNetlist\"):\n raise NotImplementedError(\"Over"
},
{
"path": "hwt/synthesizer/rtlLevel/rtlSignal.py",
"chars": 18713,
"preview": "from copy import copy\nfrom typing import Generator, Dict, Tuple, Set, Union, Self, List, \\\n Literal, Optional\n\nfrom h"
}
]
// ... and 8 more files (download for full content)
About this extraction
This page contains the full source code of the Nic30/hwt GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 208 files (856.1 KB), approximately 216.4k tokens, and a symbol index with 1669 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.