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Repository: Piker-Alpha/AppleIntelInfo
Branch: master
Commit: 029207ed2a02
Files: 12
Total size: 301.7 KB
Directory structure:
gitextract_6thlbe9e/
├── .gitignore
├── AppleIntelInfo/
│ ├── AppleIntelInfo-Info.plist
│ ├── AppleIntelInfo-Prefix.pch
│ ├── AppleIntelInfo.cpp
│ ├── AppleIntelInfo.h
│ ├── essentials.h
│ └── intel_family.h
├── AppleIntelInfo.xcodeproj/
│ └── project.pbxproj
├── AppleIntelRegisterDumper/
│ ├── AppleIntelRegisterDumper.h
│ ├── intel_chipset.h
│ └── intel_reg.h
└── README.md
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
.DS_Store
.git
xcuserdata
project.xcworkspace
/AppleIntelInfo/AppleIntelInfo.xcodeproj/xcuserdata
/AppleIntelInfo/AppleIntelInfo.xcodeproj/project.xcworkspace
================================================
FILE: AppleIntelInfo/AppleIntelInfo-Info.plist
================================================
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>CFBundleDevelopmentRegion</key>
<string>en</string>
<key>CFBundleExecutable</key>
<string>${EXECUTABLE_NAME}</string>
<key>CFBundleIdentifier</key>
<string>$(PRODUCT_BUNDLE_IDENTIFIER)</string>
<key>CFBundleInfoDictionaryVersion</key>
<string>6.0</string>
<key>CFBundleName</key>
<string>${PRODUCT_NAME}</string>
<key>CFBundlePackageType</key>
<string>KEXT</string>
<key>CFBundleShortVersionString</key>
<string>2.9</string>
<key>CFBundleSignature</key>
<string>????</string>
<key>CFBundleVersion</key>
<string>2.9</string>
<key>IOKitPersonalities</key>
<dict>
<key>AppleIntelInfo</key>
<dict>
<key>CFBundleIdentifier</key>
<string>com.pikeralpha.driver.${PRODUCT_NAME:rfc1034identifier}</string>
<key>IOClass</key>
<string>${PRODUCT_NAME:rfc1034identifier}</string>
<key>IOMatchCategory</key>
<string>${PRODUCT_NAME:rfc1034identifier}</string>
<key>IOProviderClass</key>
<string>IOResources</string>
<key>IOResourceMatch</key>
<string>IOKit</string>
<key>logCStates</key>
<true/>
<key>logIGPU</key>
<true/>
<key>logIPGStyle</key>
<true/>
<key>logIntelRegs</key>
<false/>
<key>logMSRs</key>
<true/>
<key>enableHWP</key>
<false/>
</dict>
</dict>
<key>NSHumanReadableCopyright</key>
<string>Copyright © 2014-2017 Pike R. Alpha. All rights reserved.</string>
<key>OSBundleLibraries</key>
<dict>
<key>com.apple.kpi.bsd</key>
<string>10.4</string>
<key>com.apple.kpi.iokit</key>
<string>10.4</string>
<key>com.apple.kpi.libkern</key>
<string>10.4</string>
<key>com.apple.kpi.mach</key>
<string>10.4</string>
<key>com.apple.kpi.unsupported</key>
<string>10.5</string>
</dict>
<key>OSBundleRequired</key>
<string>Root</string>
</dict>
</plist>
================================================
FILE: AppleIntelInfo/AppleIntelInfo-Prefix.pch
================================================
//
// Prefix header
//
// The contents of this file are implicitly included at the beginning of every source file.
//
================================================
FILE: AppleIntelInfo/AppleIntelInfo.cpp
================================================
/*
* Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.
*
* Original idea and initial development of MSRDumper.kext (c) 2011 by RevoGirl.
*
* Thanks to George for his help and continuation of Sam's work, but it is
* time for us to push the envelope and add some really interesting stuff.
*
* This work is licensed under the Creative Commons Attribution-NonCommercial
* 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
*/
#include "AppleIntelInfo.h"
#if WRITE_LOG_REPORT
//==============================================================================
int AppleIntelInfo::writeReport(void)
{
int error = 0;
int length = (int)strlen(logBuffer);
struct vnode * vp;
if (mCtx)
{
if ((error = vnode_open(FILE_PATH, (O_TRUNC | O_CREAT | FWRITE | O_NOFOLLOW), S_IRUSR | S_IWUSR, VNODE_LOOKUP_NOFOLLOW, &vp, mCtx)))
{
IOLOG("AppleIntelInfo.kext: Error, vnode_open(%s) failed with error %d!\n", FILE_PATH, error);
}
else
{
if ((error = vnode_isreg(vp)) == VREG)
{
if ((error = vn_rdwr(UIO_WRITE, vp, logBuffer, length, reportFileOffset, UIO_SYSSPACE, IO_NOCACHE|IO_NODELOCKED|IO_UNIT, vfs_context_ucred(mCtx), (int *) 0, vfs_context_proc(mCtx))))
{
IOLOG("AppleIntelInfo.kext: Error, vn_rdwr(%s) failed with error %d!\n", FILE_PATH, error);
}
else
{
reportFileOffset += length;
}
}
else
{
IOLOG("AppleIntelInfo.kext: Error, vnode_isreg(%s) failed with error %d!\n", FILE_PATH, error);
}
if ((error = vnode_close(vp, FWASWRITTEN, mCtx)))
{
IOLOG("AppleIntelInfo.kext: Error, vnode_close() failed with error %d!\n", error);
}
}
}
else
{
IOLOG("AppleIntelInfo.kext: mCtx == NULL!\n");
error = 0xFFFF;
}
return error;
}
#endif
#if REPORT_RAPL_MSRS
//==============================================================================
bool AppleIntelInfo::supportsRAPL(UInt16 aTargetRAPLFeature)
{
UInt16 supportedRAPLFeatures = 0;
switch (gCpuModel)
{
case INTEL_FAM6_SANDYBRIDGE: // 0x2A
case INTEL_FAM6_IVYBRIDGE: // 0x3A
case INTEL_FAM6_HASWELL_CORE: // 0x3C
case INTEL_FAM6_HASWELL_ULT: // 0x45
case INTEL_FAM6_HASWELL_GT3E: // 0x46
case INTEL_FAM6_BROADWELL_CORE: // 0x3D
case INTEL_FAM6_BROADWELL_GT3E: // 0x47
supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO);
break;
case INTEL_FAM6_SKYLAKE_MOBILE: // 0x4E
case INTEL_FAM6_SKYLAKE_DESKTOP: // 0x5E
case INTEL_FAM6_CANNONLAKE_CORE: // 0x66
case INTEL_FAM6_KABYLAKE_MOBILE: // 0x8E
case INTEL_FAM6_KABYLAKE_DESKTOP: // 0x9E
supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO);
break;
case INTEL_FAM6_HASWELL_X: // 0x3F
case INTEL_FAM6_SKYLAKE_X: // 0x55
case INTEL_FAM6_BROADWELL_X: // 0x56
case INTEL_FAM6_BROADWELL_XEON_D: // 0x56
case INTEL_FAM6_XEON_PHI_KNL: // 0x57
case INTEL_FAM6_XEON_PHI_KNM: // 0x85
supportedRAPLFeatures = (RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO);
break;
case INTEL_FAM6_SANDYBRIDGE_X: // 0x2D
case INTEL_FAM6_IVYBRIDGE_X: // 0x3E
supportedRAPLFeatures = (RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO);
break;
}
if (supportedRAPLFeatures & aTargetRAPLFeature)
{
return true;
}
return false;
}
//==============================================================================
void AppleIntelInfo::reportRAPL(UInt16 aTargetRAPL)
{
unsigned int Y = 0;
unsigned int Z = 0;
unsigned long long msr = rdmsr64(MSR_RAPL_POWER_UNIT);
uint8_t power_unit = bitfield32(msr, 3, 0);
uint8_t energy_status_unit = bitfield32(msr, 12, 8);
uint8_t time_unit = bitfield32(msr, 19, 16);
float joulesPerEnergyUnit = 1. / float(1ULL << energy_status_unit);
switch(aTargetRAPL)
{
case RAPL_BASE: /* 0x606 MSR_RAPL_POWER_UNIT */
IOLOG("\nMSR_RAPL_POWER_UNIT..............(0x606) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Power Units.......................... : %u (1/%d Watt)\n", power_unit, (1 << power_unit));
IOLOG(" - Energy Status Units.................. : %u (%sJoules)\n", energy_status_unit, getUnitText(energy_status_unit));
IOLOG(" - Time Units .......................... : %u (%sSeconds)\n", time_unit, getUnitText(time_unit));
}
break;
case RAPL_PKG: /* 0x610 MSR_PKG_POWER_LIMIT / 0x611 MSR_PKG_ENERGY_STATUS */
msr = rdmsr64(MSR_PKG_POWER_LIMIT);
IOLOG("\nMSR_PKG_POWER_LIMIT..............(0x610) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Package Power Limit #1............... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
IOLOG(" - Enable Power Limit #1................ : %s\n", bitfield32(msr, 15, 15) ? "1 (enabled)": "0 (disabled)");
IOLOG(" - Package Clamping Limitation #1....... : %s\n", bitfield32(msr, 16, 16) ? "1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)": "0 (disabled)");
Y = bitfield32(msr, 21, 17);
Z = bitfield32(msr, 23, 22);
IOLOG(" - Time Window for Power Limit #1....... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z) / 4.0) * time_unit));
IOLOG(" - Package Power Limit #2............... : %llu Watt\n", (bitfield32(msr, 46, 32) >> power_unit));
IOLOG(" - Enable Power Limit #2................ : %s\n", (msr & (1UL << 47)) ? "1 (enabled)": "0 (disabled)");
IOLOG(" - Package Clamping Limitation #2....... : %s\n", (msr & (1UL << 48)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
Y = bitfield32(msr, 53, 49);
Z = bitfield32(msr, 55, 54);
IOLOG(" - Time Window for Power Limit #2....... : %llu (%u milli-Seconds)\n", bitfield32(msr, 55, 49), (unsigned int)(((1 << Y) * (1.0 + Z) / 4.0) * time_unit));
IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 63, 63) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
}
msr = rdmsr64(MSR_PKG_ENERGY_STATUS);
IOLOG("\nMSR_PKG_ENERGY_STATUS............(0x611) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
}
break;
case RAPL_PKG_PERF_STATUS: /* 0x613 MSR_PKG_PERF_STATUS */
break;
case RAPL_PKG_POWER_INFO: /* 0x614 MSR_PKG_POWER_INFO */
msr = rdmsr64(MSR_PKG_POWER_INFO);
IOLOG("\nMSR_PKG_POWER_INFO...............(0x614) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Thermal Spec Power................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
IOLOG(" - Minimum Power........................ : %llu\n", (bitfield32(msr, 16, 30) >> power_unit));
IOLOG(" - Maximum Power........................ : %llu\n", (bitfield32(msr, 46, 32) >> power_unit));
IOLOG(" - Maximum Time Window.................. : %llu\n", (bitfield32(msr, 58, 48) >> time_unit));
}
break;
case RAPL_DRAM: /* 0x618 MSR_DRAM_POWER_LIMIT / 0x619 MSR_DRAM_ENERGY_STATUS */
break;
case RAPL_DRAM_PERF_STATUS: /* 0x61b MSR_DRAM_PERF_STATUS */
break;
case RAPL_DRAM_POWER_INFO: /* 0x61c MSR_DRAM_POWER_INFO */
break;
case RAPL_CORES: /* 0x638 MSR_PP0_POWER_LIMIT / 0x639 MSR_PP0_ENERGY_STATUS */
msr = rdmsr64(MSR_PP0_POWER_LIMIT);
IOLOG("\nMSR_PP0_POWER_LIMIT..............(0x638) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Power Limit.......................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
IOLOG(" - Enable Power Limit................... : %s\n", (msr & (1UL << 15)) ? "1 (enabled)": "0 (disabled)");
IOLOG(" - Clamping Limitation.................. : %s\n", (msr & (1UL << 16)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
Y = bitfield32(msr, 21, 17);
Z = bitfield32(msr, 23, 22);
IOLOG(" - Time Window for Power Limit.......... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z)) * time_unit));
IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 31, 31) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
}
msr = rdmsr64(MSR_PP0_ENERGY_STATUS);
IOLOG("\nMSR_PP0_ENERGY_STATUS............(0x639) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
}
break;
case RAPL_CORE_POLICY: /* 0x63a MSR_PP0_POLICY */
if (gCpuModel == INTEL_FAM6_SANDYBRIDGE) // 0x2A - Intel 325462.pdf Vol.3C 35-120
{
msr = rdmsr64(MSR_PP0_POLICY);
IOLOG("\nMSR_PP0_POLICY...................(0x63a) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Priority Level....................... : %llu\n", bitfield32(msr, 4, 0));
}
}
break;
case RAPL_GFX: /* 0x640 MSR_PP1_POWER_LIMIT / 0x641 MSR_PP1_ENERGY_STATUS /0x642 MSR_PP1_POLICY */
msr = rdmsr64(MSR_PP1_POWER_LIMIT);
IOLOG("\nMSR_PP1_POWER_LIMIT..............(0x640) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Power Limit.......................... : %llu Watt\n", (bitfield32(msr, 14, 0) >> power_unit));
IOLOG(" - Enable Power Limit................... : %s\n", (msr & (1UL << 15)) ? "1 (enabled)": "0 (disabled)");
IOLOG(" - Clamping Limitation.................. : %s\n", (msr & (1UL << 16)) ? "1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)": "0 (disabled)");
Y = bitfield32(msr, 21, 17);
Z = bitfield32(msr, 23, 22);
IOLOG(" - Time Window for Power Limit.......... : %llu (%u milli-Seconds)\n", bitfield32(msr, 23, 17), (unsigned int)(((1 << Y) * (1.0 + Z)) * time_unit));
IOLOG(" - Lock................................. : %s\n", bitfield32(msr, 31, 31) ? "1 (MSR locked until next reset)": "0 (MSR not locked)");
}
msr = rdmsr64(MSR_PP1_ENERGY_STATUS);
IOLOG("\nMSR_PP1_ENERGY_STATUS............(0x641) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Total Energy Consumed................ : %llu Joules (Watt = Joules / seconds)\n", (long long unsigned)(bitfield32(msr, 31, 0) * joulesPerEnergyUnit));
}
msr = rdmsr64(MSR_PP1_POLICY);
IOLOG("\nMSR_PP1_POLICY...................(0x642) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Priority Level....................... : %llu\n", bitfield32(msr, 4, 0));
}
break;
}
}
#endif
#if (REPORT_MSRS && REPORT_HWP)
//==============================================================================
void AppleIntelInfo::reportHWP(void)
{
uint32_t cpuid_reg[4];
unsigned long long msr;
do_cpuid(0x00000006, cpuid_reg);
if ((cpuid_reg[eax] & 0x80) == 0x80)
{
msr = rdmsr64(IA32_PM_ENABLE);
if (msr & 1)
{
short mantissa = 0;
short exponent = 0;
switch (gCpuModel)
{
case INTEL_FAM6_SKYLAKE_MOBILE:
case INTEL_FAM6_SKYLAKE_DESKTOP:
case INTEL_FAM6_KABYLAKE_MOBILE:
case INTEL_FAM6_KABYLAKE_DESKTOP:
UInt64 pPerf = rdmsr64(IA32_PPERF);
UInt64 aPerf = rdmsr64(IA32_APERF);
float busy = ((pPerf * 100) / aPerf);
UInt8 multiplier = (UInt8)(((gClockRatio + 0.5) * busy) / 100);
IOLOG("MSR_PPERF........................(0x63E) : 0x%llX (%d)\n", msr, multiplier);
break;
}
IOLOG("\nIA32_PM_ENABLE...................(0x770) : 0x%llX (HWP Supported and Enabled)\n", msr);
msr = rdmsr64(IA32_HWP_CAPABILITIES);
IOLOG("\nIA32_HWP_CAPABILITIES............(0x771) : 0x%llX\n", msr);
IOLOG("-----------------------------------------\n");
IOLOG(" - Highest Performance.................. : %llu\n", bitfield32(msr, 7, 0));
IOLOG(" - Guaranteed Performance............... : %llu\n", bitfield32(msr, 15, 8));
IOLOG(" - Most Efficient Performance........... : %llu\n", bitfield32(msr, 23, 16));
IOLOG(" - Lowest Performance................... : %llu\n", bitfield32(msr, 31, 24));
if ((cpuid_reg[eax] & 0x800) == 0x800)
{
msr = rdmsr64(IA32_HWP_REQUEST_PKG);
IOLOG("\nIA32_HWP_REQUEST_PKG.............(0x772) : 0x%llX\n", msr);
IOLOG("-----------------------------------------\n");
IOLOG(" - Minimum Performance.................. : %llu\n", bitfield32(msr, 7, 0));
IOLOG(" - Maximum Performance.................. : %llu\n", bitfield32(msr, 15, 8));
IOLOG(" - Desired Performance.................. : %llu\n", bitfield32(msr, 23, 16));
IOLOG(" - Energy Efficient Performance......... : %llu\n", bitfield32(msr, 31, 24));
mantissa = bitfield32(msr, 38, 32);
exponent = bitfield32(msr, 41, 39);
IOLOG(" - Activity Window...................... : %d, %d\n", mantissa, exponent);
}
if ((cpuid_reg[eax] & 0x100) == 0x100)
{
msr = rdmsr64(IA32_HWP_INTERRUPT);
IOLOG("\nIA32_HWP_INTERRUPT...............(0x773) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
IOLOG(" - Guaranteed Performance Change........ : %s\n", (msr & 1) ? "1 (Interrupt generated on change of)": "0 (Interrupt generation disabled)");
IOLOG(" - Excursion Minimum.................... : %s\n", (msr & 2) ? "1 (Interrupt generated when unable to meet)": "0 (Interrupt generation disabled)");
}
msr = rdmsr64(IA32_HWP_REQUEST);
IOLOG("\nIA32_HWP_REQUEST................(0x774) : 0x%llX\n", msr);
IOLOG("-----------------------------------------\n");
IOLOG(" - Minimum Performance................. : %llu\n", bitfield32(msr, 7, 0));
IOLOG(" - Maximum Performance................. : %llu\n", bitfield32(msr, 15, 8));
IOLOG(" - Desired Performance................. : %llu\n", bitfield32(msr, 23, 16));
IOLOG(" - Energy Efficient Performance........ : %llu\n", bitfield32(msr, 31, 24));
if ((cpuid_reg[eax] & 0x200) == 0x200)
{
mantissa = bitfield32(msr, 38, 32);
exponent = bitfield32(msr, 41, 39);
IOLOG(" - Activity Window..................... : %d, %d\n", mantissa, exponent);
}
IOLOG(" - Package Control..................... : %s\n", (msr & 0x40000000000) ? "1 (control inputs to be derived from IA32_HWP_REQUEST_PKG)": "0");
msr = rdmsr64(IA32_HWP_STATUS);
IOLOG("\nIA32_HWP_STATUS..................(0x777) : 0x%llX\n", msr);
IOLOG("-----------------------------------------\n");
IOLOG(" - Guaranteed Performance Change....... : %s\n", (msr & 1) ? "1 (has occured)" : "0 (has not occured)");
IOLOG(" - Excursion To Minimum................ : %s\n", (msr & 4) ? "1 (has occured)" : "0 (has not occured)");
}
else
{
IOLOG("\nIA32_PM_ENABLE...................(0x770) : 0x%llX (HWP Supported but not, yet, enabled)\n", msr);
}
}
}
#endif
#if (REPORT_MSRS && REPORT_HDC)
//==============================================================================
void AppleIntelInfo::reportHDC(void)
{
uint8_t index = 0;
unsigned long long msr;
IOLOG("HDC Supported\n");
msr = rdmsr64(IA32_PKG_HDC_CTL);
IOLOG("\nIA32_PKG_HDC_CTL.................(0xDB0) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG("HDC Pkg Enable...................(0x652) : %s\n", bitfield32(msr, 0, 0) ? "1 (HDC allowed)" : "0 (HDC not allowed)");
}
msr = rdmsr64(IA32_PM_CTL1);
IOLOG("\nIA32_PM_CTL1.....................(0xDB1) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG("HDC Allow Block..................(0xDB1) : %s\n", bitfield32(msr, 0, 0) ? "1 (HDC blocked)" : "0 (HDC not blocked/allowed)");
}
msr = rdmsr64(IA32_THREAD_STALL);
IOLOG("\nIA32_THREAD_STALL................(0xDB2) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG("Stall Cycle Counter...............(0xDB2) : %llu, %s\n", msr, msr ? "1 (forced-idle supported)" : "0 (forced-idle not supported)");
}
msr = rdmsr64(MSR_PKG_HDC_CONFIG);
index = bitfield32(msr, 2, 0);
IOLOG("\nMSR_PKG_HDC_CONFIG...............(0x652) : 0x%llX\n", msr);
if (msr)
{
const char * cxCountText[5] = { "no-counting", "count package C2 only", "count package C3 and deeper", "count package C6 and deeper", "count package C7 and deeper" };
IOLOG("------------------------------------------\n");
IOLOG("Pkg Cx Monitor ..................(0x652) : %d (%s)", index, cxCountText[index]);
}
msr = rdmsr64(MSR_CORE_HDC_RESIDENCY);
IOLOG("\nMSR_CORE_HDC_RESIDENCY...........(0x653) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG("Core Cx Duty Cycle Count................ : %llu %s\n", msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
}
msr = rdmsr64(MSR_PKG_HDC_SHALLOW_RESIDENCY);
IOLOG("\nMSR_PKG_HDC_SHALLOW_RESIDENCY....(0x655) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG("Pkg C2 Duty Cycle Count................. : %llu %s\n", msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
}
msr = rdmsr64(MSR_PKG_HDC_DEEP_RESIDENCY);
IOLOG("\nMSR_PKG_HDC_DEEP_RESIDENCY.......(0x656) : 0x%llX\n", msr);
if (msr)
{
const char * cxText[5] = { "x", "2", "3", "6", "7" };
IOLOG("------------------------------------------\n");
IOLOG("Pkg C%s Duty Cycle Count................ : %llu %s\n", cxText[index], msr, msr ? "(forced-idle cycle count)": "(not supported/no forced-idle serviced)");
}
}
#endif
//==============================================================================
uint32_t AppleIntelInfo::getBusFrequency(void)
{
size_t size = 4;
uint32_t frequency = 0;
switch (gCpuModel)
{
case INTEL_FAM6_NEHALEM:
case INTEL_FAM6_NEHALEM_EP:
case INTEL_FAM6_NEHALEM_EX:
case INTEL_FAM6_WESTMERE:
case INTEL_FAM6_WESTMERE_EP:
case INTEL_FAM6_WESTMERE_EX:
return (133 * 1000000);
break;
default:
// Check sysctl hw.busfrequency to see if the setup is right or wrong.
if (sysctlbyname("hw.busfrequency", &frequency, &size, NULL, 0) == 0)
{
// Is it 100000000?
if ((frequency / 1000000) > 100)
{
// No. Log warning.
IOLOG("\nWarning: Clover hw.busfrequency error detected : %x\n", frequency);
}
}
return (100 * 1000000);
break;
}
return 0;
}
//==============================================================================
const char * AppleIntelInfo::getUnitText(uint8_t unit)
{
const char * milliText[10] = { "1 ", "500 milli-", "250 milli-", "125 milli-", "62.5 milli-", "31.2 milli-", "15.6 milli-", "7.8 milli-", "3.9 milli-", "2 milli-" };
const char * microText[7] = { "976.6 micro-", "488.3 micro-", "244.1 micro-", "122.1 micro-", "61 micro-", "30.5 micro-", "15.3 micro-" };
if (unit <= 9)
{
return milliText[unit];
}
else
{
return microText[unit-10];
}
return NULL;
}
#if REPORT_MSRS
//==============================================================================
bool AppleIntelInfo::hasCPUFeature(long targetCPUFeature)
{
uint32_t cpuid_reg[4];
do_cpuid(0x00000001, cpuid_reg);
uint64_t cpuFeatures = cpuid_reg[ecx];
cpuFeatures = (cpuFeatures << 32) | cpuid_reg[eax];
if (cpuFeatures & targetCPUFeature)
{
return true;
}
return false;
}
#endif
#if REPORT_MSRS
//==============================================================================
void AppleIntelInfo::reportMSRs(void)
{
uint8_t core_limit;
uint32_t performanceState;
uint32_t cpuid_reg[4];
uint64_t msr;
char brandstring[48];
do_cpuid(0x80000002, cpuid_reg); // First 16 bytes.
bcopy((char *)cpuid_reg, &brandstring[0], 16);
do_cpuid(0x80000003, cpuid_reg); // Next 16 bytes.
bcopy((char *)cpuid_reg, &brandstring[16], 16);
do_cpuid(0x80000004, cpuid_reg); // Last 16 bytes.
bcopy((char *)cpuid_reg, &brandstring[32], 16);
IOLOG("\nProcessor Brandstring....................: %s\n", brandstring);
do_cpuid(0x00000001, cpuid_reg);
uint8_t model = (bitfield32(cpuid_reg[eax], 19, 16) << 4) + bitfield32(cpuid_reg[eax], 7, 4);
IOLOG("\nProcessor Signature..................... : 0x%X\n", cpuid_reg[eax]);
IOLOG("------------------------------------------\n");
IOLOG(" - Family............................... : %lu\n", bitfield32(cpuid_reg[eax], 11, 8));
IOLOG(" - Stepping............................. : %lu\n", bitfield32(cpuid_reg[eax], 3, 0));
IOLOG(" - Model................................ : 0x%X (%d)\n", model, model);
do_cpuid(0x00000006, cpuid_reg);
IOLOG("\nModel Specific Registers (MSRs)\n------------------------------------------\n");
msr = rdmsr64(MSR_IA32_PLATFORM_ID);
IOLOG("\nMSR_IA32_PLATFORM_ID.............(0x17) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
IOLOG(" - Processor Flags...................... : %d\n", (uint8_t)bitfield32(msr, 52, 50));
msr = rdmsr64(MSR_CORE_THREAD_COUNT);
IOLOG("\nMSR_CORE_THREAD_COUNT............(0x35) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
IOLOG(" - Core Count........................... : %d\n", gCoreCount);
IOLOG(" - Thread Count......................... : %d\n", gThreadCount);
msr = rdmsr64(MSR_PLATFORM_INFO);
performanceState = bitfield32(msr, 15, 8);
IOLOG("\nMSR_PLATFORM_INFO................(0xCE) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
IOLOG(" - Maximum Non-Turbo Ratio.............. : 0x%X (%u MHz)\n", performanceState, (performanceState * gBclk));
IOLOG(" - Ratio Limit for Turbo Mode........... : %s\n", (msr & (1 << 28)) ? "1 (programmable)" : "0 (not programmable)");
IOLOG(" - TDP Limit for Turbo Mode............. : %s\n", (msr & (1 << 29)) ? "1 (programmable)" : "0 (not programmable)");
IOLOG(" - Low Power Mode Support............... : %s\n", (msr & (1UL << 32)) ? "1 (LPM supported)": "0 (LMP not supported)");
if (bitfield32(msr, 34, 33) == 0)
{
IOLOG(" - Number of ConfigTDP Levels........... : 0 (only base TDP level available)\n");
}
else
{
IOLOG(" - Number of ConfigTDP Levels........... : %llu (additional TDP level(s) available)\n", bitfield32(msr, 34, 33));
}
IOLOG(" - Maximum Efficiency Ratio............. : %llu\n", bitfield32(msr, 47, 40));
if (bitfield32(msr, 55, 48) > 0)
{
IOLOG(" - Minimum Operating Ratio.............. : %llu\n", bitfield32(msr, 55, 48));
}
UInt64 msr_pmg_cst_config_control = rdmsr64(MSR_PKG_CST_CONFIG_CONTROL);
IOLOG("\nMSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x%llX\n", msr_pmg_cst_config_control);
IOLOG("------------------------------------------\n");
IOLOG(" - I/O MWAIT Redirection Enable......... : %s\n", (msr_pmg_cst_config_control & (1 << 10)) ? "1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)" : "0 (not enabled)");
IOLOG(" - CFG Lock............................. : %s\n", (msr_pmg_cst_config_control & (1 << 15)) ? "1 (MSR locked until next reset)" : "0 (MSR not locked)");
IOLOG(" - C3 State Auto Demotion............... : %s\n", (msr_pmg_cst_config_control & (1 << 25)) ? "1 (enabled)" : "0 (disabled/unsupported)");
IOLOG(" - C1 State Auto Demotion............... : %s\n", (msr_pmg_cst_config_control & (1 << 26)) ? "1 (enabled)" : "0 (disabled/unsupported)");
IOLOG(" - C3 State Undemotion.................. : %s\n", (msr_pmg_cst_config_control & (1 << 27)) ? "1 (enabled)" : "0 (disabled/unsupported)");
IOLOG(" - C1 State Undemotion.................. : %s\n", (msr_pmg_cst_config_control & (1 << 28)) ? "1 (enabled)" : "0 (disabled/unsupported)");
// Intel® CoreTM M Processors and 5th Generation Intel® CoreTM Processors
// Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture
IOLOG(" - Package C-State Auto Demotion........ : %s\n", (msr_pmg_cst_config_control & (1 << 29)) ? "1 (enabled)" : "0 (disabled/unsupported)");
IOLOG(" - Package C-State Undemotion........... : %s\n", (msr_pmg_cst_config_control & (1 << 30)) ? "1 (enabled)" : "0 (disabled/unsupported)");
msr = rdmsr64(MSR_PMG_IO_CAPTURE_BASE);
IOLOG("\nMSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - LVL_2 Base Address................... : 0x%llx\n", bitfield32(msr, 15, 0));
}
if (msr_pmg_cst_config_control & (1 << 10))
{
switch(bitfield32(msr, 18, 16))
{
case 0: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C3 is the max C-State to include");
break;
case 1: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C6 is the max C-State to include");
break;
case 2: IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C7 is the max C-State to include");
break;
}
}
else
{
IOLOG(" - C-state Range........................ : %llu (%s)\n", bitfield32(msr, 18, 16), "C-States not included, I/O MWAIT redirection not enabled");
}
if (bitfield32(cpuid_reg[ecx], 0, 0) == 1) // Are APERF and MPERF supported?
{
IOLOG("\nIA32_MPERF.......................(0xE7) : 0x%llX\n", (unsigned long long)rdmsr64(IA32_MPERF));
UInt64 aPerf = rdmsr64(IA32_APERF);
IOLOG("IA32_APERF.......................(0xE8) : 0x%llX\n", aPerf);
}
if (gCpuModel == INTEL_FAM6_BROADWELL_X)
{
IOLOG("MSR_0x150........................(0x150) : 0x%llX\n", (unsigned long long)rdmsr64(0x150));
}
IOLOG("\nMSR_FLEX_RATIO...................(0x194) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_FLEX_RATIO));
if (msr)
{
IOLOG("------------------------------------------\n");
}
msr = rdmsr64(MSR_IA32_PERF_STATUS);
performanceState = bitfield32(msr, 15, 0);
IOLOG("\nMSR_IA32_PERF_STATUS.............(0x198) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Current Performance State Value...... : 0x%X (%u MHz)\n", performanceState, ((performanceState >> 8) * gBclk));
}
msr = rdmsr64(MSR_IA32_PERF_CONTROL);
performanceState = bitfield32(msr, 15, 0);
IOLOG("\nMSR_IA32_PERF_CONTROL............(0x199) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Target performance State Value....... : 0x%X (%u MHz)\n", performanceState, ((performanceState >> 8) * gBclk));
}
if (cpuid_reg[eax] & (1 << 0))
{
IOLOG(" - Intel Dynamic Acceleration........... : %s\n", (msr & (1UL << 32)) ? "1 (IDA disengaged)" : "0 (IDA engaged)");
}
do_cpuid(0x00000001, cpuid_reg);
if (bitfield32(cpuid_reg[edx], 22, 22) == 1)
{
IOLOG("\nIA32_CLOCK_MODULATION............(0x19A) : 0x%llX\n", (unsigned long long)rdmsr64(IA32_CLOCK_MODULATION));
msr = rdmsr64(IA32_THERM_INTERRUPT);
IOLOG("\nIA32_THERM_INTERRUPT.............(0x19B) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - High-Temperature Interrupt Enable.... : %s\n", (msr & (1 << 0)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - Low-Temperature Interrupt Enable..... : %s\n", (msr & (1 << 1)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - PROCHOT# Interrupt Enable............ : %s\n", (msr & (1 << 2)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - FORCEPR# Interrupt Enable............ : %s\n", (msr & (1 << 3)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - Critical Temperature Interrupt Enable : %s\n", (msr & (1 << 4)) ? "1 (enabled)" : "0 (disabled)");
// bit 7:5 Reserved.
IOLOG(" - Threshold #1 Value................... : %llu\n", bitfield32(msr, 14, 8));
IOLOG(" - Threshold #1 Interrupt Enable........ : %s\n", (msr & (1 << 15)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - Threshold #2 Value................... : %llu\n", bitfield32(msr, 22, 16));
IOLOG(" - Threshold #2 Interrupt Enable........ : %s\n", (msr & (1 << 23)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - Power Limit Notification Enable...... : %s\n", (msr & (1 << 24)) ? "1 (enabled)" : "0 (disabled)");
// bit 63:25 Reserved.
}
msr = rdmsr64(IA32_THERM_STATUS);
IOLOG("\nIA32_THERM_STATUS................(0x19C) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Thermal Status....................... : %s\n", (msr & (1 << 0)) ? "1" : "0");
IOLOG(" - Thermal Log.......................... : %s\n", (msr & (1 << 1)) ? "1" : "0");
IOLOG(" - PROCHOT # or FORCEPR# event.......... : %s\n", (msr & (1 << 2)) ? "1" : "0");
IOLOG(" - PROCHOT # or FORCEPR# log............ : %s\n", (msr & (1 << 3)) ? "1" : "0");
IOLOG(" - Critical Temperature Status.......... : %s\n", (msr & (1 << 4)) ? "1" : "0");
IOLOG(" - Critical Temperature log............. : %s\n", (msr & (1 << 5)) ? "1" : "0");
IOLOG(" - Thermal Threshold #1 Status.......... : %s\n", (msr & (1 << 6)) ? "1" : "0");
IOLOG(" - Thermal Threshold #1 log............. : %s\n", (msr & (1 << 7)) ? "1" : "0");
IOLOG(" - Thermal Threshold #2 Status.......... : %s\n", (msr & (1 << 8)) ? "1" : "0");
IOLOG(" - Thermal Threshold #2 log............. : %s\n", (msr & (1 << 9)) ? "1" : "0");
IOLOG(" - Power Limitation Status.............. : %s\n", (msr & (1 << 10)) ? "1" : "0");
IOLOG(" - Power Limitation log................. : %s\n", (msr & (1 << 11)) ? "1" : "0");
IOLOG(" - Current Limit Status................. : %s\n", (msr & (1 << 12)) ? "1" : "0");
IOLOG(" - Current Limit log.................... : %s\n", (msr & (1 << 13)) ? "1" : "0");
IOLOG(" - Cross Domain Limit Status............ : %s\n", (msr & (1 << 14)) ? "1" : "0");
IOLOG(" - Cross Domain Limit log............... : %s\n", (msr & (1 << 15)) ? "1" : "0");
IOLOG(" - Digital Readout...................... : %llu\n", bitfield32(msr, 22, 16));
// bit 23-26 Reserved.
IOLOG(" - Resolution in Degrees Celsius........ : %llu\n", bitfield32(msr, 30, 27));
IOLOG(" - Reading Valid........................ : %s\n", (msr & (1 << 31)) ? "1 (valid)" : "0 (invalid)");
// bit 63-32 Reserved.
}
}
if (hasCPUFeature(CPUID_FEATURE_TM2))
{
msr = rdmsr64(MSR_THERM2_CTL);
IOLOG("\nMSR_THERM2_CTL...................(0x19D) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Thermal Monitor Selection (TM1/TM2).. : %s\n", (msr & (1 << 16)) ? "1 (TM1 thermally-initiated on-die modulation of the stop-clock duty cycle)" : "0 (TM2 thermally-initiated frequency transitions)");
}
}
msr = rdmsr64(IA32_MISC_ENABLES);
IOLOG("\nIA32_MISC_ENABLES................(0x1A0) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Fast-Strings......................... : %s\n", (msr & (1 << 0)) ? "1 (enabled)" : "0 (disabled)");
// bit 2:1 Reserved.
IOLOG(" - FOPCODE compatibility mode Enable.... : %llu\n", (msr & (1 << 2)));
IOLOG(" - Automatic Thermal Control Circuit.... : %s\n", (msr & (1 << 3)) ? "1 (enabled)" : "0 (disabled)");
// bit 6:4 Reserved.
IOLOG(" - Split-lock Disable................... : %llu\n", (msr & (1 << 4)));
IOLOG(" - Performance Monitoring............... : %s\n", (msr & (1 << 7)) ? "1 (available)" : "not available");
// bit 8 Reserved.
IOLOG(" - Bus Lock On Cache Line Splits Disable : %llu\n", (msr & (1 << 8)));
IOLOG(" - Hardware prefetch Disable............ : %llu\n", (msr & (1 << 9)));
IOLOG(" - Processor Event Based Sampling....... : %s\n", (msr & (1 << 12)) ? "1 (PEBS not supported)" : "0 (PEBS supported)");
IOLOG(" - GV1/2 legacy Enable.................. : %llu\n", (msr & (1 << 15)));
IOLOG(" - Enhanced Intel SpeedStep Technology.. : %s\n", (msr & (1 << 16)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - MONITOR FSM.......................... : %s\n", (msr & (1 << 18)) ? "1 (MONITOR/MWAIT supported)" : "0 (MONITOR/MWAIT not supported)");
IOLOG(" - Adjacent sector prefetch Disable..... : %llu\n", (msr & (1 << 19)));
IOLOG(" - CFG Lock............................. : %s\n", (msr & (1 << 20)) ? "1 (MSR locked until next reset)" : "0 (MSR not locked)");
IOLOG(" - xTPR Message Disable................. : %s\n", (msr & (1 << 23)) ? "1 (disabled)" : "0 (enabled)");
}
msr = rdmsr64(MSR_TEMPERATURE_TARGET);
uint8_t time_unit = bitfield32(msr, 6, 0);
IOLOG("\nMSR_TEMPERATURE_TARGET...........(0x1A2) : 0x%llX\n", msr);
if (msr)
{
char timeString[25];
memset(timeString, 0, 25);
IOLOG("------------------------------------------\n");
if (time_unit)
{
snprintf(timeString, 25, "(%sSeconds)", getUnitText(time_unit));
}
IOLOG(" - Turbo Attenuation Units.............. : %u %s\n", time_unit, timeString);
IOLOG(" - Temperature Target................... : %llu\n", bitfield32(msr, 23, 16));
IOLOG(" - TCC Activation Offset................ : %llu\n", bitfield32(msr, 29, 24));
}
msr = rdmsr64(MSR_MISC_PWR_MGMT);
IOLOG("\nMSR_MISC_PWR_MGMT................(0x1AA) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - EIST Hardware Coordination........... : %s\n", (msr & (1 << 0)) ? "1 (hardware coordination disabled)" : "0 (hardware coordination enabled)");
IOLOG(" - Energy/Performance Bias support...... : %lu\n", bitfield32(cpuid_reg[ecx], 3, 3) );
IOLOG(" - Energy/Performance Bias.............. : %s\n", (msr & (1 << 1)) ? "1 (enabled/MSR visible to software)" : "0 (disabled/MSR not visible to software)");
IOLOG(" - Thermal Interrupt Coordination Enable : %s\n", (msr & (1 << 22)) ? "1 (thermal interrupt routed to all cores)" : "0 (thermal interrupt not rerouted)");
/* HWP related SpeedShift settings */
IOLOG(" - SpeedShift Technology Enable......... : %s\n", (msr & (1 << 6)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - SpeedShift Interrupt Coordination.... : %s\n", (msr & (1 << 7)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - SpeedShift Energy Efficient Perf..... : %s\n", (msr & (1 << 12)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - SpeedShift Technology Setup for HWP.. : %s\n", (msr & 0x10c0) ? "Yes (setup for HWP)" : "No (not setup for HWP)");
}
msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
IOLOG("\nMSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
for (int i = 1; (i < 9) && (i <= gCoreCount); i++)
{
core_limit = bitfield32(msr, 7, 0);
if (core_limit)
{
IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
msr = (msr >> 8);
}
}
//
// Intel® Xeon® Processor E5 v3 Family
//
if (gCoreCount > 8)
{
msr = rdmsr64(MSR_TURBO_RATIO_LIMIT1);
IOLOG("\nMSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
for (int i = 9; (i < 17) && (i <= gCoreCount); i++)
{
core_limit = bitfield32(msr, 7, 0);
if (core_limit)
{
IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
msr = (msr >> 8);
}
}
}
//
// Intel® Xeon® Processor E5 v3 Family
//
if (gCoreCount > 16)
{
msr = rdmsr64(MSR_TURBO_RATIO_LIMIT2);
IOLOG("\nMSR_TURBO_RATIO_LIMIT2...........(0x1AF) : 0x%llX\n", msr);
IOLOG("------------------------------------------\n");
for (int i = 17; (i < 33) && (i <= gCoreCount); i++)
{
core_limit = bitfield32(msr, 7, 0);
if (core_limit)
{
IOLOG(" - Maximum Ratio Limit for C%02d.......... : %X (%u MHz) %s\n", i, core_limit, (core_limit * gBclk), ((i > gCoreCount) && core_limit) ? "(garbage / unused)" : "");
msr = (msr >> 8);
}
}
}
do_cpuid(0x00000006, cpuid_reg);
if (bitfield32(cpuid_reg[ecx], 3, 3) == 1)
{
msr = rdmsr64(IA32_ENERGY_PERF_BIAS);
IOLOG("\nIA32_ENERGY_PERF_BIAS............(0x1B0) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
switch(bitfield32(msr, 3, 0))
{
case 0:
case 1:
IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "highest performance");
break;
case 5:
IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "balanced performance and energy saving");
break;
case 15:
IOLOG(" - Power Policy Preference...............: %llu (%s)\n", bitfield32(msr, 3, 0), "maximize energy saving");
break;
}
}
}
msr = rdmsr64(MSR_POWER_CTL);
IOLOG("\nMSR_POWER_CTL....................(0x1FC) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - Bi-Directional Processor Hot..........: %s\n", (msr & (1 << 0)) ? "1 (enabled)" : "0 (disabled)");
IOLOG(" - C1E Enable............................: %s\n", (msr & (1 << 1)) ? "1 (enabled)": "0 (disabled)");
}
if (supportsRAPL(RAPL_PKG))
{
reportRAPL(RAPL_BASE);
}
if (supportsRAPL(RAPL_PKG))
{
reportRAPL(RAPL_PKG);
}
if (gCpuModel == INTEL_FAM6_SANDYBRIDGE) // 0x2A - Intel 325462.pdf Vol.3C 35-120
{
IOLOG("\nMSR_PP0_CURRENT_CONFIG...........(0x601) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PP0_CURRENT_CONFIG));
}
if (supportsRAPL(RAPL_CORES))
{
reportRAPL(RAPL_CORES);
}
if (supportsRAPL(RAPL_CORE_POLICY))
{
reportRAPL(RAPL_CORES);
}
if (igpuEnabled && supportsRAPL(RAPL_GFX))
{
reportRAPL(RAPL_GFX);
}
IOLOG("\n");
switch (gCpuModel)
{
case INTEL_FAM6_IVYBRIDGE: // 0x3A - Intel 325462.pdf (Table 35-23) 35-174 Vol.3C
case INTEL_FAM6_IVYBRIDGE_X: // 0x3E
case INTEL_FAM6_HASWELL_CORE: // 0x3C - Intel 325462.pdf (Table 35-27) 35-192 Vol.3C
case INTEL_FAM6_HASWELL_X: // 0x3F
case INTEL_FAM6_HASWELL_ULT: // 0x45
case INTEL_FAM6_HASWELL_GT3E: // 0x46
case INTEL_FAM6_BROADWELL_GT3E: // 0x47
case INTEL_FAM6_SKYLAKE_MOBILE: // 0x4E
case INTEL_FAM6_SKYLAKE_X: // 0x55
case INTEL_FAM6_BROADWELL_XEON_D:
case INTEL_FAM6_XEON_PHI_KNL: // 0x57 - Intel 325462.pdf (Table 35-40) Vol.3C 35-275
case INTEL_FAM6_SKYLAKE_DESKTOP: // 0x5E - Intel 325462.pdf (Table 35-27) 35-192 Vol.3C
case INTEL_FAM6_CANNONLAKE_CORE: // 0x66
case INTEL_FAM6_KABYLAKE_MOBILE: // 0x8E
case INTEL_FAM6_KABYLAKE_DESKTOP: // 0x9E
IOLOG("MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_NOMINAL));
IOLOG("MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_LEVEL1));
IOLOG("MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_LEVEL2));
IOLOG("MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_CONFIG_TDP_CONTROL));
IOLOG("MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_TURBO_ACTIVATION_RATIO));
break;
}
if (gCpuModel >= INTEL_FAM6_SANDYBRIDGE)
{
IOLOG("MSR_PKGC3_IRTL...................(0x60a) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC3_IRTL));
IOLOG("MSR_PKGC6_IRTL...................(0x60b) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC6_IRTL));
if (gCheckC7)
{
IOLOG("MSR_PKGC7_IRTL...................(0x60c) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKGC7_IRTL));
}
}
if (gCpuModel >= INTEL_FAM6_NEHALEM)
{
IOLOG("MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C2_RESIDENCY));
IOLOG("MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C3_RESIDENCY));
IOLOG("MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C2_RESIDENCY));
/*
* Is package C3 auto-demotion/undemotion enabled i.e. is bit-25 or bit-27 set?
*/
if ((msr_pmg_cst_config_control & 0x2000000) || (msr_pmg_cst_config_control & 0x8000000))
{
IOLOG("MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C3_RESIDENCY));
}
}
if (gCpuModel >= INTEL_FAM6_SANDYBRIDGE)
{
IOLOG("MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C6_RESIDENCY));
if (gCheckC7)
{
IOLOG("MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C7_RESIDENCY));
}
}
switch (gCpuModel)
{
case INTEL_FAM6_BROADWELL_CORE: // 0x3D
case INTEL_FAM6_HASWELL_ULT: // 0x45 - Intel 325462.pdf Vol.3C 35-136
case INTEL_FAM6_SKYLAKE_MOBILE: // 0x4E
case INTEL_FAM6_SKYLAKE_DESKTOP: // 0x5E
case INTEL_FAM6_CANNONLAKE_CORE: // 0x66
case INTEL_FAM6_KABYLAKE_MOBILE: // 0x8E
case INTEL_FAM6_KABYLAKE_DESKTOP: // 0x9E
IOLOG("MSR_PKG_C8_RESIDENCY.............(0x630) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C8_RESIDENCY));
IOLOG("MSR_PKG_C9_RESIDENCY.............(0x631) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C9_RESIDENCY));
IOLOG("MSR_PKG_C10_RESIDENCY............(0x632) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C10_RESIDENCY));
IOLOG("MSR_PKG_C8_LATENCY...............(0x633) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C8_RESIDENCY));
IOLOG("MSR_PKG_C9_LATENCY...............(0x634) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C9_RESIDENCY));
IOLOG("MSR_PKG_C10_LATENCY..............(0x635) : 0x%llX\n", (unsigned long long)rdmsr64(MSR_PKG_C10_RESIDENCY));
break;
}
switch (gCpuModel)
{
case INTEL_FAM6_SKYLAKE_MOBILE: // 0x4E
case INTEL_FAM6_SKYLAKE_DESKTOP: // 0x5E
case INTEL_FAM6_CANNONLAKE_CORE: // 0x66
case INTEL_FAM6_KABYLAKE_MOBILE: // 0x8E
case INTEL_FAM6_KABYLAKE_DESKTOP: // 0x9E
msr = rdmsr64(MSR_PLATFORM_ENERGY_COUNTER);
IOLOG("\nMSR_PLATFORM_ENERGY_COUNTER......(0x64D) : 0x%llX %s\n", bitfield32(msr, 31, 0), (bitfield32(msr, 31, 0) == 0) ? "(not supported by hardware/BIOS)" : "");
if (msr)
{
IOLOG("------------------------------------------\n");
}
msr = rdmsr64(MSR_PPERF);
IOLOG("\nMSR_PPERF........................(0x64E) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
// busy = ((aPerf * 100) / msr);
IOLOG(" - Hardware workload scalability........ : %llu\n", bitfield32(msr, 63, 0));
}
msr = rdmsr64(MSR_CORE_PERF_LIMIT_REASONS);
IOLOG("\nMSR_CORE_PERF_LIMIT_REASONS......(0x64F) : 0x%llX\n", msr);
if (msr)
{
IOLOG("------------------------------------------\n");
IOLOG(" - PROCHOT Status....................... : %s\n", bitfield32(msr, 1, 1) ? "1 (frequency reduced below OS request due to assertion of external PROCHOT)": "0");
IOLOG(" - Thermal Status....................... : %s\n", bitfield32(msr, 2, 2) ? "1 (frequency reduced below OS request due to a thermal event)": "0");
// bit 3 Reserved.
IOLOG(" - Residency State Regulation Status.... : %s\n", bitfield32(msr, 4, 4) ? "1 (frequency reduced below OS request due to residency state regulation limit)": "0");
IOLOG(" - Running Average Thermal Limit Status. : %s\n", bitfield32(msr, 5, 5) ? "1 (frequency reduced below OS request due to Running Average Thermal Limit)": "0");
IOLOG(" - VR Therm Alert Status................ : %s\n", bitfield32(msr, 6, 6) ? "1 (frequency reduced below OS request due to a thermal alert from a processor Voltage Regulator)" : "0");
IOLOG(" - VR Therm Design Current Status....... : %s\n", bitfield32(msr, 7, 7) ? "1 (frequency reduced below OS request due to VR thermal design current limit)" : "0");
IOLOG(" - Other Status......................... : %s\n", bitfield32(msr, 8, 8) ? "1 (frequency reduced below OS request due to electrical or other constraints)" : "0");
// bit 9 Reserved.
IOLOG(" - Package/Platform-Level #1 Power Limit : %s\n", bitfield32(msr, 10, 10) ? "1 (frequency reduced below OS request due to power limit)" : "0");
IOLOG(" - Package/Platform-Level #2 Power Limit : %s\n", bitfield32(msr, 11, 11) ? "1 (frequency reduced below OS request due to power limit)" : "0");
IOLOG(" - Max Turbo Limit Status............... : %s\n", bitfield32(msr, 12, 12) ? "1 (frequency reduced below OS request due to multi-core turbo limits)" : "0");
IOLOG(" - Turbo Transition Attenuation Status.. : %s\n", bitfield32(msr, 13, 13) ? "1 (frequency reduced below OS request due to turbo transition attenuation)": "0");
// bit 15-14 Reserved.
IOLOG(" - PROCHOT Log.......................... : %s\n", bitfield32(msr, 16, 16) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Thermal Log.......................... : %s\n", bitfield32(msr, 17, 17) ? "1 (status bit has asserted)" : "0");
// bit 19-18 Reserved.
IOLOG(" - Residency State Regulation Log....... : %s\n", bitfield32(msr, 20, 20) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Running Average Thermal Limit Log.... : %s\n", bitfield32(msr, 21, 21) ? "1 (status bit has asserted)" : "0");
IOLOG(" - VR Therm Alert Log................... : %s\n", bitfield32(msr, 22, 22) ? "1 (status bit has asserted)" : "0");
IOLOG(" - VR Thermal Design Current Log........ : %s\n", bitfield32(msr, 23, 23) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Other Status Log..................... : %s\n", bitfield32(msr, 24, 24) ? "1 (status bit has asserted)" : "0");
// bit 25 Reserved.
IOLOG(" - Package/Platform-Level #1 Power Limit : %s\n", bitfield32(msr, 26, 26) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Package/Platform-Level #2 Power Limit : %s\n", bitfield32(msr, 27, 27) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Max Turbo Limit Log.................. : %s\n", bitfield32(msr, 28, 28) ? "1 (status bit has asserted)" : "0");
IOLOG(" - Turbo Transition Attenuation Log..... : %s\n", bitfield32(msr, 29, 29) ? "1 (status bit has asserted)" : "0");
// bit 63-30 Reserved.
}
#if REPORT_HDC
if ((cpuid_reg[eax] & 0x2000) == 0x2000) // bit-13 HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.
{
reportHDC();
}
#endif
}
do_cpuid(0x00000001, cpuid_reg);
if (bitfield32(cpuid_reg[ecx], 24, 24) == 1)
{
IOLOG("\nIA32_TSC_DEADLINE................(0x6E0) : 0x%llX\n", (unsigned long long)rdmsr64(IA32_TSC_DEADLINE));
}
#if REPORT_HWP
reportHWP();
#endif
}
#endif
#if REPORT_C_STATES
//==============================================================================
inline void getCStates(void *magic)
{
UInt32 logicalCoreNumber = cpu_number();
if (gCheckC3 && rdmsr64(MSR_CORE_C3_RESIDENCY) > 0)
{
gC3Cores |= (1 << logicalCoreNumber);
}
if (gCheckC6 && rdmsr64(MSR_CORE_C6_RESIDENCY) > 0)
{
gC6Cores |= (1 << logicalCoreNumber);
}
if (gCheckC7 && rdmsr64(MSR_CORE_C7_RESIDENCY) > 0)
{
gC7Cores |= (1 << logicalCoreNumber);
}
if (logicalCoreNumber < gThreadCount)
{
// wrmsr64(0x1FC, rdmsr64(0x1FC) & 0xFFFFFFFE);
// wrmsr64(0x1FC, rdmsr64(0x1FC) | 0x1);
}
uint64_t msr = rdmsr64(0x10);
gTSC = rdtsc64();
// IOLOG("AICPUI: TSC of logical core %d is: msr(0x10) = 0x%llx, rdtsc = 0x%llx\n", logicalCoreNumber, msr, gTSC);
if (msr > (gTSC + 4096))
{
IOLog("Error: TSC of logical core %d is out of sync (0x%llx)!\n", logicalCoreNumber, msr);
}
}
#endif
//==============================================================================
IOReturn AppleIntelInfo::loopTimerEvent(void)
{
UInt8 currentMultiplier = (rdmsr64(MSR_IA32_PERF_STS) >> 8);
gCoreMultipliers |= (1ULL << currentMultiplier);
#if REPORT_IGPU_P_STATES
UInt8 currentIgpuMultiplier = 0;
if (igpuEnabled)
{
if (gCpuModel == INTEL_FAM6_SKYLAKE_MOBILE || gCpuModel == INTEL_FAM6_SKYLAKE_DESKTOP)
{
currentIgpuMultiplier = (UInt8)(((gMchbar[1] * 16.666) + 0.5) / 50);
}
else
{
currentIgpuMultiplier = (UInt8)gMchbar[1];
}
gIGPUMultipliers |= (1ULL << currentIgpuMultiplier);
}
#endif
timerEventSource->setTimeoutTicks(Interval);
if (loopLock)
{
return kIOReturnTimeout;
}
loopLock = true;
#if REPORT_IPG_STYLE
UInt8 pState = 0;
if (logIPGStyle)
{
UInt64 aPerf = 0;
float busy = 0;
aPerf = (rdmsr64(IA32_APERF));
wrmsr64(IA32_APERF, 0ULL);
if (gHwpEnabled)
{
UInt64 pPerf = (rdmsr64(IA32_MPERF));
busy = ((aPerf * 100) / pPerf);
}
else
{
UInt64 mPerf = (rdmsr64(IA32_MPERF));
wrmsr64(IA32_MPERF, 0ULL);
busy = ((aPerf * 100) / mPerf);
}
pState = (UInt8)(((gClockRatio + 0.5) * busy) / 100);
/* if (pState != currentMultiplier)
{ */
gCoreMultipliers |= (1ULL << pState);
if ((pState < currentMultiplier) && (pState < gMinRatio))
{
pState = gMinRatio;
}
/*
* Commented out after fabio67 (fabiosun) confirmed that
* the wrmsr() below triggered a KP on his configuration
* wrmsr64(199, (pState << 8));
*/
// }
}
#endif
#if REPORT_C_STATES
if (logCStates)
{
UInt32 magic = 0;
mp_rendezvous_no_intrs(getCStates, &magic);
IOSleep(1);
}
#endif
int currentBit = 0;
UInt64 value = 0ULL;
#if REPORT_IGPU_P_STATES
if ((gCoreMultipliers != gTriggeredPStates) || (gIGPUMultipliers != gTriggeredIGPUPStates))
#else
#if REPORT_IPG_STYLE
if ((gCoreMultipliers != gTriggeredPStates) || (currentMultiplier != pState))
#else
if (gCoreMultipliers != gTriggeredPStates)
#endif
#endif
{
gTriggeredPStates = gCoreMultipliers;
IOLOG("CPU P-States [ ");
for (currentBit = gMinRatio; currentBit <= gMaxRatio; currentBit++)
{
value = (1ULL << currentBit);
if ((gTriggeredPStates & value) == value)
{
if (currentBit == currentMultiplier)
{
IOLOG("(%d) ", currentBit);
}
else
{
IOLOG("%d ", currentBit);
}
}
}
#if REPORT_IGPU_P_STATES
if (igpuEnabled)
{
gTriggeredIGPUPStates = gIGPUMultipliers;
IOLOG("] iGPU P-States [ ");
for (currentBit = 1; currentBit <= 32; currentBit++)
{
value = (1ULL << currentBit);
if ((gTriggeredIGPUPStates & value) == value)
{
if (currentBit == currentIgpuMultiplier)
{
IOLOG("(%d) ", currentBit);
}
else
{
IOLOG("%d ", currentBit);
}
}
}
}
#endif
IOLOG("]\n");
}
#if REPORT_C_STATES
if (gCheckC3 && (gTriggeredC3Cores != gC3Cores))
{
gTriggeredC3Cores = gC3Cores;
IOLOG("CPU C3-Cores [ ");
for (currentBit = 0; currentBit < gThreadCount; currentBit++)
{
value = (1ULL << currentBit);
if ((gTriggeredC3Cores & value) == value)
{
IOLOG("%d ", currentBit);
}
}
IOLOG("]\n");
}
if (gCheckC6 && (gTriggeredC6Cores != gC6Cores))
{
gTriggeredC6Cores = gC6Cores;
IOLOG("CPU C6-Cores [ ");
for (currentBit = 0; currentBit < gThreadCount; currentBit++)
{
value = (1ULL << currentBit);
if ((gTriggeredC6Cores & value) == value)
{
IOLOG("%d ", currentBit);
}
}
IOLOG("]\n");
}
if (gCheckC7 && (gTriggeredC7Cores != gC7Cores))
{
gTriggeredC7Cores = gC7Cores;
IOLOG("CPU C7-Cores [ ");
for (currentBit = 0; currentBit < gThreadCount; currentBit++)
{
value = (1ULL << currentBit);
if ((gTriggeredC7Cores & value) == value)
{
IOLOG("%d ", currentBit);
}
}
IOLOG("]\n");
}
#endif
loopLock = false;
return kIOReturnSuccess;
}
//==============================================================================
IOService* AppleIntelInfo::probe(IOService *provider, SInt32 *score)
{
IOService *ret = super::probe(provider, score);
if (ret != this)
{
return 0;
}
return ret;
}
//==============================================================================
bool AppleIntelInfo::start(IOService *provider)
{
if (IOService::start(provider))
{
simpleLock = IOSimpleLockAlloc();
if (simpleLock)
{
#if WRITE_LOG_REPORT
mCtx = vfs_context_create(NULL);
#endif
uint32_t cpuid_reg[4];
IOLOG("AppleIntelInfo.kext v%s Copyright © 2012-2017 Pike R. Alpha. All rights reserved.\n", VERSION);
do_cpuid(0x00000006, cpuid_reg);
if ((cpuid_reg[eax] & 0x80) == 0x80) // Is HWP supported?
{
if (rdmsr64(IA32_PM_ENABLE) & 1) // Yes. Is HWP enabled?
{
gHwpEnabled = true; // Yes.
}
#if ENABLE_HWP
else
{
/*
* HWP is supported but not enabled (yet) and thus we
* check the preference to see if we should enable it.
*/
OSBoolean * key_enableHWP = OSDynamicCast(OSBoolean, getProperty("enableHWP"));
if (key_enableHWP) // Key found?
{
if ((bool)key_enableHWP->getValue()) // Yes. Check value.
{
wrmsr64(IA32_PM_ENABLE, 1); // Enable HWP.
}
}
IOLOG("enableHWP................................: %d\n", (bool)key_enableHWP->getValue());
}
#endif
}
#if REPORT_MSRS
OSBoolean * key_logMSRs = OSDynamicCast(OSBoolean, getProperty("logMSRs"));
if (key_logMSRs)
{
logMSRs = (bool)key_logMSRs->getValue();
}
IOLOG("\nSettings:\n------------------------------------------\nlogMSRs..................................: %d\n", logMSRs);
#endif
#if REPORT_IGPU_P_STATES
OSBoolean * key_logIGPU = OSDynamicCast(OSBoolean, getProperty("logIGPU"));
if (key_logIGPU)
{
igpuEnabled = (bool)key_logIGPU->getValue();
}
if (igpuEnabled)
{
if ((READ_PCI8_NB(DEVEN) & DEVEN_D2EN_MASK) == 0) // Is the IGPU enabled and visible?
{
igpuEnabled = false;
}
}
IOLOG("logIGPU..................................: %d\n", igpuEnabled);
#endif
#if REPORT_INTEL_REGS
OSBoolean * key_logIntelRegs = OSDynamicCast(OSBoolean, getProperty("logIntelRegs"));
if (key_logIntelRegs)
{
logIntelRegs = (bool)key_logIntelRegs->getValue();
}
IOLOG("logIntelRegs............................: %d\n", logIntelRegs);
#endif
#if REPORT_C_STATES
OSBoolean * key_logCStates = OSDynamicCast(OSBoolean, getProperty("logCStates"));
if (key_logCStates)
{
logCStates = (bool)key_logCStates->getValue();
}
IOLOG("logCStates...............................: %d\n", logCStates);
#endif
#if REPORT_IPG_STYLE
if ((cpuid_reg[ecx] & 1) == 1) // Are APERF and MPERF supported?
{
OSBoolean * key_logIPGStyle = OSDynamicCast(OSBoolean, getProperty("logIPGStyle"));
if (key_logIPGStyle)
{
logIPGStyle = (bool)key_logIPGStyle->getValue();
}
}
else
{
logIPGStyle = false;
}
IOLOG("logIPGStyle..............................: %d\n", logIPGStyle);
#endif
UInt64 msr = rdmsr64(MSR_PLATFORM_INFO);
gClockRatio = (UInt8)((msr >> 8) & 0xff);
msr = rdmsr64(MSR_IA32_PERF_STS);
gCoreMultipliers |= (1ULL << (msr >> 8));
do_cpuid(0x00000001, cpuid_reg);
gCpuModel = bitfield32(cpuid_reg[eax], 7, 4) + (bitfield32(cpuid_reg[eax], 19, 16) << 4);
gBclk = (getBusFrequency() / 1000000);
#if REPORT_C_STATES
switch (gCpuModel) // TODO: Verify me!
{
case INTEL_FAM6_SANDYBRIDGE: // 0x2A - Intel 325462.pdf Vol.3C 35-111
case INTEL_FAM6_SANDYBRIDGE_X: // 0x2D - Intel 325462.pdf Vol.3C 35-111
case INTEL_FAM6_IVYBRIDGE: // 0x3A - Intel 325462.pdf Vol.3C 35-125 (Refering to Table 35-12)
case INTEL_FAM6_IVYBRIDGE_X: // 0x3E - Intel 325462.pdf Vol.3C 35-125 (Refering to Table 35-12)
// No C7 support for Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 (Product Families Datasheet Volume One of Two page 19)
case INTEL_FAM6_HASWELL_CORE: // 0x3C - Intel 325462.pdf Vol.3C 35-136
case INTEL_FAM6_BROADWELL_CORE: // 0x3D
case INTEL_FAM6_HASWELL_ULT: // 0x45 - Intel 325462.pdf Vol.3C 35-136
case INTEL_FAM6_HASWELL_GT3E: // 0x46
case INTEL_FAM6_BROADWELL_X: // 0x47
case INTEL_FAM6_SKYLAKE_MOBILE: // 0x4E
case INTEL_FAM6_SKYLAKE_DESKTOP: // 0x5E
case INTEL_FAM6_CANNONLAKE_CORE: // 0x66
case INTEL_FAM6_KABYLAKE_MOBILE: // 0x8E
case INTEL_FAM6_KABYLAKE_DESKTOP: // 0x9E
gCheckC7 = true;
break;
}
#endif
msr = rdmsr64(MSR_PLATFORM_INFO);
gMinRatio = (UInt8)((msr >> 40) & 0xff);
gClockRatio = (UInt8)((msr >> 8) & 0xff);
msr = rdmsr64(MSR_CORE_THREAD_COUNT);
gCoreCount = bitfield32(msr, 31, 16);
gThreadCount = bitfield32(msr, 15, 0);
#if REPORT_MSRS
gTSC = rdtsc64();
IOLOG("InitialTSC...............................: 0x%llx (%llu MHz)\n", gTSC, ((gTSC / gClockRatio) / 1000000000));
// MWAIT information
do_cpuid(0x00000005, cpuid_reg);
uint32_t supportedMwaitCStates = bitfield32(cpuid_reg[edx], 31, 0);
IOLOG("MWAIT C-States...........................: %d\n", supportedMwaitCStates);
if (logMSRs)
{
reportMSRs();
}
#endif
#if REPORT_INTEL_REGS
if (logIntelRegs)
{
outl(0xcf8, 0x80001000);
uint32_t value = inl(0xcfc);
if ((value & 0x0000ffff) == 0x8086)
{
devid = ((value >> 16) & 0x0000ffff);
reportIntelRegs();
}
}
#endif
IOLOG("\nCPU Ratio Info:\n------------------------------------------\nBase Clock Frequency (BLCK)............. : %d MHz\n", gBclk);
IOLOG("Maximum Efficiency Ratio/Frequency.......: %2d (%4d MHz)\n", gMinRatio, (gMinRatio * gBclk));
IOLOG("Maximum non-Turbo Ratio/Frequency........: %2d (%4d MHz)\n", gClockRatio, (gClockRatio * gBclk));
if (!((rdmsr64(IA32_MISC_ENABLES) >> 32) & 0x40)) // Turbo Mode Enabled?
{
msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
gMaxRatio = (UInt8)(msr & 0xff);
IOLOG("Maximum Turbo Ratio/Frequency............: %2d (%4d MHz)\n", gMaxRatio, (gMaxRatio * gBclk));
}
else
{
gMaxRatio = gClockRatio;
IOLOG("Maximum Ratio/Frequency..................: %2d (%4d MHz)\n", gMaxRatio, (gMaxRatio * gBclk));
}
#if REPORT_IGPU_P_STATES
if (igpuEnabled)
{
IOPhysicalAddress address = (IOPhysicalAddress)(0xFED10000 + 0x5948);
memDescriptor = IOMemoryDescriptor::withPhysicalAddress(address, 0x53, kIODirectionInOut);
if (memDescriptor != NULL)
{
if ((result = memDescriptor->prepare()) == kIOReturnSuccess)
{
memoryMap = memDescriptor->map();
if (memoryMap != NULL)
{
gMchbar = (UInt8 *)memoryMap->getVirtualAddress();
// Preventing a stupid (UEFI) BIOS limit.
if (gMchbar[0x4C] < gMchbar[0x50])
{
gMchbar[0x4C] = gMchbar[0x50];
}
//
// Examples IGPU multiplier: 17 (multiplier) * 50 (frequency in MHz) = 850 MHz
// 22 (multiplier) * 50 (frequency in MHz) = 1100 MHz
// 6 P-States: 850, 900, 950, 1000, 1050 and 1100 MHz
//
// Current RP-State, when the graphics engine is in RC6, this reflects the last used ratio.
IOLOG("\nIGPU Info:\n------------------------------------------\n");
IOLOG("IGPU Current Frequency...................: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x01])); // RP_STATE_RATIO (CURRENT_FREQUENCY)
// Maximum RPN base frequency capability for the Integrated GFX Engine (GT).
IOLOG("IGPU Minimum Frequency...................: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x52])); // RPN_CAP (MIN_FREQUENCY) See also: DSDT->RPNC
// Maximum RP1 base frequency capability for the Integrated GFX Engine (GT).
IOLOG("IGPU Maximum Non-Turbo Frequency.........: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x51])); // RP1_CAP (MAX_NON_TURBO) See also: DSDT->RP1C
// Maximum RP0 base frequency capability for the Integrated GFX Engine (GT).
IOLOG("IGPU Maximum Turbo Frequency.............: %4d MHz\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x50])); // RP0_CAP (MAX_TURBO)) See also: DSDT->RP0C
// Maximum base frequency limit for the Integrated GFX Engine (GT) allowed during run-time.
if (gMchbar[0x4C] == 255)
{
IOLOG("IGPU Maximum limit.......................: No Limit\n\n"); // RPSTT_LIM
}
else
{
IOLOG("IGPU Maximum limit.......................: %4d MHz\n\n", IGPU_RATIO_TO_FREQUENCY((UInt8)gMchbar[0x4C])); // RPSTT_LIM
}
}
else
{
IOLOG("Error: memoryMap == NULL\n");
}
}
else
{
IOLOG("Error: memDescriptor->prepare() failed!\n");
}
}
else
{
IOLOG("Error: memDescriptor == NULL\n");
}
}
#endif
IOLOG("P-State ratio * %d = Frequency in MHz\n------------------------------------------\n", gBclk);
timerEventSource = IOTimerEventSource::timerEventSource(this, OSMemberFunctionCast(IOTimerEventSource::Action, this, &AppleIntelInfo::loopTimerEvent));
workLoop = getWorkLoop();
if (timerEventSource && workLoop && (kIOReturnSuccess == workLoop->addEventSource(timerEventSource)))
{
this->registerService(0);
timerEventSource->setTimeoutMS(1000);
return true;
}
}
}
return false;
}
//==============================================================================
void AppleIntelInfo::stop(IOService *provider)
{
#if WRITE_LOG_REPORT
if (mCtx)
{
vfs_context_rele(mCtx);
}
#endif
if (simpleLock)
{
IOSimpleLockFree(simpleLock);
}
if (timerEventSource)
{
if (workLoop)
{
timerEventSource->cancelTimeout();
workLoop->removeEventSource(timerEventSource);
}
timerEventSource->release();
timerEventSource = NULL;
}
super::stop(provider);
}
//==============================================================================
void AppleIntelInfo::free()
{
#if REPORT_IGPU_P_STATES
if (igpuEnabled)
{
if (memoryMap)
{
memoryMap->release();
memoryMap = NULL;
}
if (memDescriptor)
{
memDescriptor->release();
memDescriptor = NULL;
}
}
#endif
super::free();
}
================================================
FILE: AppleIntelInfo/AppleIntelInfo.h
================================================
/*
* Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.
*
* Original idea and initial development of MSRDumper.kext (c) 2011 by † RevoGirl.
*
* A big thank you to George for his help and continuation of Sam's work, but it
* was time for me to push the envelope and add some really interesting stuff.
*
* This work is licensed under the Creative Commons Attribution-NonCommercial
* 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
*/
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wdeprecated-register"
#include <IOKit/IOLib.h>
#pragma clang diagnostic pop
#include <IOKit/IOService.h>
#include <IOKit/IOWorkLoop.h>
#include <IOKit/IOMemoryDescriptor.h>
#include <IOKit/IOTimerEventSource.h>
#include <sys/vnode.h>
#include <sys/fcntl.h>
#include <sys/proc.h>
#include <i386/cpuid.h>
#include <libkern/sysctl.h>
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wdeprecated-register"
#include <i386/proc_reg.h>
#pragma clang diagnostic pop
#include <essentials.h>
#define super IOService
#define VERSION "2.9"
/*
* Build settings (0 = disable feature / 1 = enable feature)
*/
#define REPORT_MSRS 1
#define REPORT_RAPL_MSRS 1
#define REPORT_HWP 1
#define REPORT_HDC 1
#define REPORT_IGPU_P_STATES 1
#define REPORT_C_STATES 1
#define REPORT_IPG_STYLE 1
#define REPORT_INTEL_REGS 0
#define ENABLE_HWP 1
#define WRITE_LOG_REPORT 1
#define MMIO_READ8(Address) (*(volatile UInt8 *)(Address))
#define MMIO_READ16(Address) (*(volatile UInt16 *)(Address))
#define MMIO_READ32(Address) (*(volatile UInt32 *)(gMMIOAddress + Address))
#define NB_BUS 0x00
#define NB_DEV 0x00
#define NB_FUN 0x00
#define DEVEN (0x54)
#define DEVEN_D2EN_MASK (0x10)
#define NB_PCICFG_SPACE_INDEX_REG 0xcf8
#define NB_PCICFG_SPACE_DATA_REG 0xcfc
#define BIT31 0x80000000
#define PCIEX_BASE_ADDRESS 0xF8000000
#define NB_MCH_BASE_ADDRESS 0xFED10000 // (G)MCH Memory Mapped Register Range Base Address (D0:F0:Rx48).
#define READ_PCI8(Bx, Dx, Fx, Rx) ReadPci8(Bx, Dx, Fx, Rx)
#define READ_PCI8_NB(Rx) READ_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx)
#define IGPU_RATIO_TO_FREQUENCY(ratio) ((ratio * 100) / 2)
#define NB_PCI_CFG_ADDRESS(bus, dev, func, reg) \
(UInt64) ((((UInt8)(bus) << 24) + ((UInt8)(dev) << 16) + \
((UInt8)(func) << 8) + ((UInt8)(reg))) & 0xffffffff)
#define NB_PCIE_CFG_ADDRESS(bus, dev, func, reg) \
((UInt32)(PCIEX_BASE_ADDRESS + ((UInt8)(bus) << 20) + \
((UInt8)(dev) << 15) + ((UInt8)(func) << 12) + (reg)))
#if WRITE_LOG_REPORT
#define FILE_PATH "/tmp/AppleIntelInfo.dat"
#define TEMP_BUFFER_SIZE 256
#define WRITE_BUFFER_SIZE 1024
#define IOLOG(format, args...) \
memset(logBuffer, 0, TEMP_BUFFER_SIZE); \
snprintf(logBuffer, TEMP_BUFFER_SIZE, format, ##args); \
writeReport();
#else
#define IOLOG(fmt, args...) IOLog(fmt, ##args)
/*
* macOS Sierra only!
*/
#include <os/log.h>
#define IOLOG(fmt, args...) os_log_with_type(OS_LOG_DEFAULT, OS_LOG_TYPE_INFO, fmt, ##args)
#endif
#define RAPL_BASE 0
#define RAPL_PKG (1 << 0)
/* 0x610 MSR_PKG_POWER_LIMIT */
/* 0x611 MSR_PKG_ENERGY_STATUS */
#define RAPL_PKG_PERF_STATUS (1 << 1)
/* 0x613 MSR_PKG_PERF_STATUS */
#define RAPL_PKG_POWER_INFO (1 << 2)
/* 0x614 MSR_PKG_POWER_INFO */
#define RAPL_DRAM (1 << 3)
/* 0x618 MSR_DRAM_POWER_LIMIT */
/* 0x619 MSR_DRAM_ENERGY_STATUS */
#define RAPL_DRAM_PERF_STATUS (1 << 4)
/* 0x61b MSR_DRAM_PERF_STATUS */
#define RAPL_DRAM_POWER_INFO (1 << 5)
/* 0x61c MSR_DRAM_POWER_INFO */
#define RAPL_CORES_POWER_LIMIT (1 << 6)
/* 0x638 MSR_PP0_POWER_LIMIT */
#define RAPL_CORE_POLICY (1 << 7)
/* 0x63a MSR_PP0_POLICY */
#define RAPL_GFX (1 << 8)
/* 0x640 MSR_PP1_POWER_LIMIT */
/* 0x641 MSR_PP1_ENERGY_STATUS */
/* 0x642 MSR_PP1_POLICY */
#define RAPL_CORES_ENERGY_STATUS (1 << 9)
/* 0x639 MSR_PP0_ENERGY_STATUS */
#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
//------------------------------------------------------------------------------
static __inline__ void outl(UInt16 port, UInt32 value)
{
__asm__ volatile("outl %0, %w1" : : "a" (value), "Nd" (port));
}
//------------------------------------------------------------------------------
static __inline__ unsigned char inb(UInt16 port)
{
UInt8 value;
__asm__ volatile("inb %w1, %b0" : "=a" (value) : "Nd" (port));
return (value);
}
//------------------------------------------------------------------------------
static __inline__ unsigned int inl(UInt16 port)
{
UInt32 value;
__asm__ volatile("inl %w1, %0" : "=a" (value) : "Nd" (port));
return (value);
}
//------------------------------------------------------------------------------
UInt8 ReadPci8(UInt8 Bus, UInt8 Dev, UInt8 Fun, UInt16 Reg)
{
if (Reg >= 0x100)
{
return MMIO_READ8((UInt64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg));
}
else
{
outl(NB_PCICFG_SPACE_INDEX_REG, BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc));
return inb(NB_PCICFG_SPACE_DATA_REG | (UInt8)(Reg & 3));
}
}
extern "C" void mp_rendezvous_no_intrs(void (*action_func)(void *), void * arg);
extern "C" int cpu_number(void);
//------------------------------------------------------------------------------
class AppleIntelInfo : public IOService
{
OSDeclareDefaultStructors (AppleIntelInfo);
private:
IOSimpleLock *simpleLock;
IOWorkLoop *workLoop;
IOTimerEventSource *timerEventSource;
#ifdef REPORT_IGPU_P_STATES
IOMemoryDescriptor *memDescriptor;
IOMemoryMap *memoryMap;
bool igpuEnabled = false; // Set <key>logIGPU</key> to <true/> in Info.plist to enable this feature.
#endif
IOReturn result = kIOReturnSuccess;
virtual IOReturn loopTimerEvent(void);
int writeReport(void);
#ifdef REPORT_RAPL_MSRS
bool supportsRAPL(UInt16 aTargetRAPLFeature);
void reportRAPL(UInt16 aTargetRAPL);
#endif
#ifdef REPORT_MSRS
void reportMSRs(void);
#ifdef REPORT_HWP
void reportHWP(void);
#endif
#ifdef REPORT_HWP
void reportHDC(void);
#endif
bool hasCPUFeature(long targetCPUFeature);
bool logMSRs = true; // Set <key>logIGPU</key> to <false/> in Info.plist to disable this feature.
#endif
bool gHwpEnabled = false;
bool loopLock = false;
#ifdef REPORT_C_STATES
bool logCStates = true; // Set <key>logCStates</key> to <false/> in Info.plist to disable this feature.
#endif
#ifdef REPORT_IPG_STYLE
bool logIPGStyle = true; // Set <key>logIPGStyle</key> to <false/> in Info.plist to disable this feature.
#endif
#ifdef REPORT_INTEL_REGS
bool logIntelRegs = true; // Set <key>logIntelRegs</key> to <false/> in Info.plist to disable this feature.
#define DEBUGSTRING(func) void func(char *result, int len, UInt32 reg, UInt32 val)
#define DEFINEREG2(reg, func) { reg, #reg, func, 0 }
#define DEFINE_FUNC_VOID(func) void func(void)
#define DEFINE_FUNC_DUMP(func) void func(struct reg_debug *regs, uint32_t count)
void intel_dump_other_regs(void);
void dumpRegisters(struct reg_debug *regs, uint32_t count);
void getPCHDeviceID(void);
void reportIntelRegs(void);
#endif
uint32_t getBusFrequency(void);
const char * getUnitText(uint8_t unit);
UInt16 Interval = 50;
uint16_t gBclk = 0;
UInt64 gCoreMultipliers = 0ULL;
UInt64 gTriggeredPStates = 0ULL;
UInt64 gIGPUMultipliers = 0ULL;
UInt64 gTriggeredIGPUPStates = 0ULL;
#if WRITE_LOG_REPORT
vfs_context_t mCtx = NULL;
long reportFileOffset = 0L;
char tempBuffer[TEMP_BUFFER_SIZE];
char logBuffer[WRITE_BUFFER_SIZE];
#endif
public:
virtual IOService * probe(IOService * provider, SInt32 * score) override;
virtual bool start(IOService * provider) override;
virtual void stop(IOService * provider) override;
virtual void free(void) override;
UInt8 gMinRatio = 0;
UInt8 gClockRatio = 0;
UInt8 gMaxRatio = 0;
UInt8 gCpuModel = 0;
UInt8 gCoreCount = 0;
};
OSDefineMetaClassAndStructors(AppleIntelInfo, IOService)
UInt8 gThreadCount = 0;
UInt8 gCoreStates = 0ULL;
#if REPORT_C_STATES
bool gCheckC3 = true;
bool gCheckC6 = true;
bool gCheckC7 = false;
UInt64 gC3Cores = 0;
UInt64 gC6Cores = 0;
UInt64 gC7Cores = 0;
UInt64 gTriggeredC3Cores = 0;
UInt64 gTriggeredC6Cores = 0;
UInt64 gTriggeredC7Cores = 0;
#endif
UInt64 gCoreMultipliers = 0ULL;
uint64_t gTSC = 0;
#ifdef REPORT_IGPU_P_STATES
UInt8 * gMchbar = NULL;
#endif
#if REPORT_INTEL_REGS
#include "../AppleIntelRegisterDumper/AppleIntelRegisterDumper.h"
#endif
================================================
FILE: AppleIntelInfo/essentials.h
================================================
/*
* This work is licensed under the Creative Commons Attribution-NonCommercial
* 4.0 Unported License => http://creativecommons.org/licenses/by-nc/4.0
*/
#ifndef __LIBSAIO_CPU_ESSENTIALS_H
#define __LIBSAIO_CPU_ESSENTIALS_H
#include "intel_family.h"
/* Copied from xnu/osfmk/cpuid.c (modified for 64-bit values) */
#define bit(n) (1UL << (n))
#define bitmask64(h, l) ((bit(h) | (bit(h) - 1)) & ~ (bit(l) - 1))
#define bitfield32(x, h, l) (((x) & bitmask64(h, l)) >> l)
// Added by DHP in 2010.
#define CPU_VENDOR_INTEL 0x756E6547
#define CPU_VENDOR_AMD 0x68747541
/* Copied from xnu/osfmk/cpuid.h */
#define CPU_STRING_UNKNOWN "Unknown CPU Typ"
// Copied from xnu/osfmk/proc_reg.h
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_CORE_THREAD_COUNT 0x35
#ifndef MSR_PLATFORM_INFO
#define MSR_PLATFORM_INFO 0xCE
#endif
#define MSR_PKG_CST_CONFIG_CONTROL 0xE2 // MSR_PKG_CST_CONFIG_CONTROL
#define MSR_PMG_IO_CAPTURE_BASE 0xE4
#define IA32_MPERF 0xE7
#define IA32_APERF 0xE8
#define IA32_PPERF 0x64E
#define MSR_IA32_PERF_STATUS 0x0198 // MSR_IA32_PERF_STS in XNU
#define MSR_IA32_PERF_CONTROL 0x0199 // IA32_PERF_CTL
#ifndef MSR_FLEX_RATIO
#define MSR_FLEX_RATIO 0x0194
#endif
#define IA32_CLOCK_MODULATION 0x019A
#define IA32_THERM_INTERRUPT 0x019B
#define IA32_THERM_STATUS 0x019C
#define MSR_THERM2_CTL 0x019D
#define IA32_MISC_ENABLES 0x01A0
#define MSR_TEMPERATURE_TARGET 0x01A2
#define MSR_MISC_PWR_MGMT 0x01AA
#define MSR_TURBO_RATIO_LIMIT 0x01AD
#define MSR_TURBO_RATIO_LIMIT1 0x01AE
#define MSR_TURBO_RATIO_LIMIT2 0x01AF
#define IA32_ENERGY_PERF_BIAS 0x01B0
#define IA32_PLATFORM_DCA_CAP 0x01F8
#define MSR_POWER_CTL 0x01FC
#define MSR_PKGC3_IRTL 0x60A
#define MSR_PKGC6_IRTL 0x60B
#define MSR_PKGC7_IRTL 0x60C
#define MSR_PKG_C2_RESIDENCY 0x60D
#define MSR_PKG_C3_RESIDENCY 0x3F8
#define MSR_PKG_C6_RESIDENCY 0x3F9
#define MSR_PKG_C7_RESIDENCY 0x3FA
#define MSR_CORE_C3_RESIDENCY 0x3FC
#define MSR_CORE_C6_RESIDENCY 0x3FD
#define MSR_CORE_C7_RESIDENCY 0x3FE
#define MSR_PP0_CURRENT_CONFIG 0x601
#define MSR_PP1_CURRENT_CONFIG 0x602
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_PKG_ENERGY_STATUS 0x611
#define MSR_PKG_PERF_STATUS 0x613
#define MSR_PKG_POWER_INFO 0x614
// JakeTown only Memory MSR's.
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS 0x619
#define MSR_DRAM_PERF_STATUS 0x61B
#define MSR_DRAM_POWER_INFO 0x61C
#define MSR_UNCORE_RATIO_LIMIT 0x620
// Xeon (0x4F) Package residency MSR's.
// Haswell-ULT (0x45) Package residency MSR's.
#define MSR_PKG_C8_RESIDENCY 0x630
#define MSR_PKG_C9_RESIDENCY 0x631
#define MSR_PKG_C10_RESIDENCY 0x632
// Haswell-ULT C state latency control.
#define MSR_PKG_C8_LATENCY 0x633
#define MSR_PKG_C9_LATENCY 0x634
#define MSR_PKG_C10_LATENCY 0x635
// Haswell-ULT VR configurations.
#define VR_MISC_CONFIG2 0x636
// Haswell-ULT Alternate BCLK in deep Package C states.
#define MSR_COUNTER_24_MHZ 0x637
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP0_ENERGY_STATUS 0x639
#define MSR_PP0_POLICY 0x63A
#define MSR_PP0_PERF_STATUS 0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT 0x640
#define MSR_PP1_ENERGY_STATUS 0x641
#define MSR_PP1_POLICY 0x642
// Ivy Bridge Specific MSR's
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define MSR_CONFIG_TDP_LEVEL1 0x649
#define MSR_CONFIG_TDP_LEVEL2 0x64A
#define MSR_CONFIG_TDP_CONTROL 0x64B
#define MSR_TURBO_ACTIVATION_RATIO 0x64C
// Skylake Specific MSR's.
#define MSR_PLATFORM_ENERGY_COUNTER 0x64D
#define MSR_PPERF 0x64E
#define MSR_CORE_PERF_LIMIT_REASONS 0x64F
#define MSR_PKG_HDC_CONFIG 0x652
#define MSR_CORE_HDC_RESIDENCY 0x653
#define MSR_PKG_HDC_SHALLOW_RESIDENCY 0x655
#define MSR_PKG_HDC_DEEP_RESIDENCY 0x656
#define MSR_WEIGHTED_CORE_C0 0x658
#define MSR_ANY_CORE_C0 0x659
#define MSR_ANY_GFXE_C0 0x65A
#define MSR_CORE_GFXE_OVERLAP_C0 0x65B
#define MSR_PLATFORM_POWER_LIMIT 0x65C
#define IA32_TSC_DEADLINE 0x6E0
#define IA32_PKG_HDC_CTL 0xDB0
#define IA32_PM_CTL1 0xDB1
#define IA32_THREAD_STALL 0xDB2
// HPW MSR's
#define IA32_PM_ENABLE 0x770
#define IA32_HWP_CAPABILITIES 0x771
#define IA32_HWP_REQUEST_PKG 0x772
#define IA32_HWP_INTERRUPT 0x773
#define IA32_HWP_REQUEST 0x774
#define IA32_HWP_STATUS 0x777
// CPUID leaf index values (pointing to the right spot in CPUID/LEAF array).
#define LEAF_0 0 // DHP: Formerly known as CPUID_n
#define LEAF_1 1
#define LEAF_2 2
#define LEAF_4 3
#define LEAF_5 4
#define LEAF_6 5
#define LEAF_B 6
#define LEAF_80 7
#define LEAF_81 8
#define MAX_CPUID_LEAVES 9 // DHP: Formerly known as MAX_CPUID
/* Copied from: xnu/osfmk/i386/cpuid.h
#define CPU_MODEL_YONAH 0x0E
#define CPU_MODEL_MEROM 0x0F
#define CPU_MODEL_PENRYN 0x17
#define CPU_MODEL_NEHALEM 0x1A
#define CPU_MODEL_ATOM 0x1C
#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper (LGA 1156)
#define CPU_MODEL_DALES 0x1F // Havendale, Auburndale (LGA 1156)
#define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale
#define CPU_MODEL_SB_CORE 0x2A // Sandy Bridge Core Processors (LGA 1155)
#define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_SB_JAKETOWN 0x2D // Sandy Bridge-EP, Sandy Bridge Xeon Processors (LGA 2011)
#define CPU_MODEL_NEHALEM_EX 0x2E
#define CPU_MODEL_WESTMERE_EX 0x2F
#define CPU_MODEL_IB_CORE 0x3A // Ivy Bridge Core Processors (LGA 1155)
#define CPU_MODEL_IB_CORE_EX 0x3B // Ivy Bridge Core Processors (LGA 2011)
#define CPU_MODEL_IB_CORE_XEON 0x3E
#define CPU_MODEL_HASWELL 0x3C
#define CPU_MODEL_HASWELL_SVR 0x3F
#define CPU_MODEL_HASWELL_ULT 0x45
#define CPU_MODEL_CRYSTALWELL 0x46
#define CPU_MODEL_BROADWELL 0x3D
#define CPU_MODEL_BROADWELL_ULX 0x3D
#define CPU_MODEL_BROADWELL_ULT 0x3D
#define CPU_MODEL_BROADWELL_H 0x47
#define CPU_MODEL_BRYSTALWELL 0x4C
#define CPU_MODEL_BROADWELL_E 0x4F
#define CPU_MODEL_SKYLAKE 0x4E
#define CPU_MODEL_SKYLAKE_ULT 0x4E
#define CPU_MODEL_SKYLAKE_ULX 0x4E
#define CPU_MODEL_SKYLAKE_X 0x55
#define CPU_MODEL_SKYLAKE_DT 0x5E
#define CPU_MODEL_KABYLAKE 0x8E
#define CPU_MODEL_KABYLAKE_DT 0x9E
*/
#define DALES_BRIDGE 1
#define SANDY_BRIDGE 2
#define IVY_BRIDGE 4
#define HASWELL 8
#endif /* !__LIBSAIO_CPU_ESSENTIALS_H */
================================================
FILE: AppleIntelInfo/intel_family.h
================================================
#ifndef _ASM_X86_INTEL_FAMILY_H
#define _ASM_X86_INTEL_FAMILY_H
/*
* "Big Core" Processors (Branded as Core, Xeon, etc...)
*
* The "_X" parts are generally the EP and EX Xeons, or the
* "Extreme" ones, like Broadwell-E.
*
* Things ending in "2" are usually because we have no better
* name for them. There's no processor called "SILVERMONT2".
*/
#define INTEL_FAM6_CORE_YONAH 0x0E
#define INTEL_FAM6_CORE2_MEROM 0x0F
#define INTEL_FAM6_CORE2_MEROM_L 0x16
#define INTEL_FAM6_CORE2_PENRYN 0x17
#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
#define INTEL_FAM6_NEHALEM 0x1E
#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
#define INTEL_FAM6_NEHALEM_EP 0x1A
#define INTEL_FAM6_NEHALEM_EX 0x2E
#define INTEL_FAM6_WESTMERE 0x25
#define INTEL_FAM6_WESTMERE_EP 0x2C
#define INTEL_FAM6_WESTMERE_EX 0x2F
#define INTEL_FAM6_SANDYBRIDGE 0x2A
#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
#define INTEL_FAM6_IVYBRIDGE 0x3A
#define INTEL_FAM6_IVYBRIDGE_X 0x3E
#define INTEL_FAM6_HASWELL_CORE 0x3C
#define INTEL_FAM6_HASWELL_X 0x3F
#define INTEL_FAM6_HASWELL_ULT 0x45
#define INTEL_FAM6_HASWELL_GT3E 0x46
#define INTEL_FAM6_BROADWELL_CORE 0x3D
#define INTEL_FAM6_BROADWELL_XEON_D 0x56
#define INTEL_FAM6_BROADWELL_GT3E 0x47
#define INTEL_FAM6_BROADWELL_X 0x4F
#define INTEL_FAM6_BROADWELL_XEON_D 0x56
#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
#define INTEL_FAM6_SKYLAKE_X 0x55
#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
#define INTEL_FAM6_CANNONLAKE_CORE 0x66
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
#define INTEL_FAM6_ATOM_LINCROFT 0x26
#define INTEL_FAM6_ATOM_PENWELL 0x27
#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35
#define INTEL_FAM6_ATOM_CEDARVIEW 0x36
#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 /* BayTrail/BYT / Valleyview */
#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */
#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* CherryTrail / Braswell */
#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */
#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A
#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
/* Xeon Phi */
#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
#endif /* _ASM_X86_INTEL_FAMILY_H */
================================================
FILE: AppleIntelInfo.xcodeproj/project.pbxproj
================================================
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================================================
FILE: AppleIntelRegisterDumper/AppleIntelRegisterDumper.h
================================================
/*
* Copyright © 2006,2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
*
* Eric Anholt <eric@anholt.net>
* Pike R. Alpha <pikeralpha@yahoo.com> (OS X port)
*
*/
#include "intel_reg.h"
#include "intel_chipset.h"
#define DEBUGSTRING(func) void func(char *result, int len, UInt32 reg, UInt32 val)
#define DEFINEREG(reg) { reg, #reg, NULL, 0 }
#define DEFINEREG_16BIT(reg) { reg, #reg, i830_16bit_func, 0 }
#define DEFINEREG2(reg, func) { reg, #reg, func, 0 }
#define DEFINE_FUNC_DUMP(func) void func(struct reg_debug *regs, uint32_t count)
#define DEFINE_FUNC_VOID(func) void func(void)
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
#define intel_dump_regs(regs) dumpRegisters(regs, ARRAY_SIZE(regs))
static uint32_t devid = 0;
UInt64 gMMIOAddress = 0;
struct reg_debug
{
UInt32 reg;
const char *name;
void (*debug_output) (char *result, int len, UInt32 reg, UInt32 val);
UInt32 val;
};
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
{
const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input;
const char *width;
enable = (val & (1<<31)) ? "enabled" : "disabled";
switch ((val >> 28) & 7)
{
case 0:
port = "no port";
break;
case 1:
port = "DDIB";
break;
case 2:
port = "DDIC";
break;
case 3:
port = "DDID";
break;
case 4:
port = "DDIE";
break;
default:
port = "port reserved";
break;
}
switch ((val >> 24) & 7)
{
case 0:
mode = "HDMI";
break;
case 1:
mode = "DVI";
break;
case 2:
mode = "DP SST";
break;
case 3:
mode = "DP MST";
break;
case 4:
mode = "FDI";
break;
case 5:
default:
mode = "mode reserved";
break;
}
switch ((val >> 20) & 7)
{
case 0:
bpc = "8 bpc";
break;
case 1:
bpc = "10 bpc";
break;
case 2:
bpc = "6 bpc";
break;
case 3:
bpc = "12 bpc";
break;
default:
bpc = "bpc reserved";
break;
}
hsync = (val & (1<<16)) ? "+HSync" : "-HSync";
vsync = (val & (1<<17)) ? "+VSync" : "-VSync";
switch ((val >> 12) & 7)
{
case 0:
edp_input = "EDP A ON";
break;
case 4:
edp_input = "EDP A ONOFF";
break;
case 5:
edp_input = "EDP B ONOFF";
break;
case 6:
edp_input = "EDP C ONOFF";
break;
default:
edp_input = "EDP input reserved";
break;
}
switch ((val >> 1) & 7)
{
case 0:
width = "x1";
break;
case 1:
width = "x2";
break;
case 3:
width = "x4";
break;
default:
width = "reserved width";
break;
}
snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable, port, mode, bpc, vsync, hsync, edp_input, width);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_ddi_buf_ctl)
{
const char *enable, *reversal, *width, *detected;
enable = (val & (1<<31)) ? "enabled" : "disabled";
reversal = (val & (1<<16)) ? "reversed" : "not reversed";
switch ((val >> 1) & 7)
{
case 0:
width = "x1";
break;
case 1:
width = "x2";
break;
case 3:
width = "x4";
break;
default:
width = "reserved";
break;
}
detected = (val & 1) ? "detected" : "not detected";
snprintf(result, len, "%s %s %s %s", enable, reversal, width, detected);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_port_clk_sel)
{
const char *clock = NULL;
switch ((val >> 29 ) & 7)
{
case 0:
clock = "LCPLL 2700";
break;
case 1:
clock = "LCPLL 1350";
break;
case 2:
clock = "LCPLL 810";
break;
case 3:
clock = "SPLL";
break;
case 4:
clock = "WRPLL 1";
break;
case 5:
clock = "WRPLL 2";
break;
case 6:
clock = "Reserved";
break;
case 7:
clock = "None";
break;
}
snprintf(result, len, "%s", clock);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_pipe_clk_sel)
{
const char *clock;
switch ((val >> 29) & 7)
{
case 0:
clock = "None";
break;
case 2:
clock = "DDIB";
break;
case 3:
clock = "DDIC";
break;
case 4:
clock = "DDID";
break;
case 5:
clock = "DDIE";
break;
default:
clock = "Reserved";
break;
}
snprintf(result, len, "%s", clock);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_sfuse_strap)
{
const char *display, *crt, *lane_reversal, *portb, *portc, *portd;
display = (val & (1<<7)) ? "disabled" : "enabled";
crt = (val & (1<<6)) ? "yes" : "no";
lane_reversal = (val & (1<<4)) ? "yes" : "no";
portb = (val & (1<<2)) ? "yes" : "no";
portc = (val & (1<<1)) ? "yes" : "no";
portd = (val & (1<<0)) ? "yes" : "no";
snprintf(result, len, "display %s, crt %s, lane reversal %s, "
"port b %s, port c %s, port d %s", display, crt, lane_reversal,
portb, portc, portd);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_yxminus1)
{
snprintf(result, len, "%d, %d", ((val & 0xffff0000) >> 16) + 1, (val & 0xffff) + 1);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dspcntr)
{
const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
{
snprintf(result, len, "%s", enabled);
}
else
{
snprintf(result, len, "%s, pipe %c", enabled, plane);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_dspstride)
{
snprintf(result, len, "%d", val >> 6);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_xyminus1)
{
snprintf(result, len, "%d, %d", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_xy)
{
snprintf(result, len, "%d, %d", (val & 0xffff), ((val & 0xffff0000) >> 16));
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_pipeconf)
{
const char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
const char *bit30 = NULL;
const char *interlace = NULL;
int interlace_mode;
char buf[256];
int buf_len;
if (IS_965(devid))
{
bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
}
else
{
bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
}
if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
{
if (IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || IS_BROADWELL(devid) || IS_GEN9(devid))
{
interlace_mode = (val >> 21) & 3;
}
else
{
interlace_mode = (val >> 21) & 7;
}
buf_len = snprintf(buf, sizeof(buf), "%s, %s", enabled, bit30);
switch (interlace_mode)
{
case 0:
interlace = "pf-pd";
break;
case 1:
interlace = "pf-id";
break;
case 3:
interlace = "if-id";
break;
case 4:
interlace = "if-id-dbl";
break;
case 5:
interlace = "pf-id-dbl";
break;
default:
interlace = "rsvd";
break;
}
if (buf_len < sizeof(buf))
{
buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", interlace);
}
}
else if (IS_GEN4(devid) || IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
{
switch ((val >> 21) & 7)
{
case 0:
case 1:
case 2:
case 3:
interlace = "progressive";
break;
case 4:
interlace = "interlaced embedded";
break;
case 5:
interlace = "interlaced";
break;
case 6:
interlace = "interlaced sdvo";
break;
case 7:
interlace = "interlaced legacy";
break;
}
if (buf_len < sizeof(buf))
{
buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", interlace);
}
}
if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid))
{
const char *rotation = NULL;
switch ((val >> 14) & 3)
{
case 0:
rotation = "rotate 0";
break;
case 1:
rotation = "rotate 90";
break;
case 2:
rotation = "rotate 180";
break;
case 3:
rotation = "rotate 270";
break;
}
if (buf_len < sizeof(buf))
{
buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", rotation);
}
}
if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid))
{
const char *bpc = NULL;
switch (val & (7 << 5))
{
case PIPECONF_8BPP:
bpc = "8bpc";
break;
case PIPECONF_10BPP:
bpc = "10bpc";
break;
case PIPECONF_6BPP:
bpc = "6bpc";
break;
case PIPECONF_12BPP:
bpc = "12bpc";
break;
default:
bpc = "invalid bpc";
break;
}
if (buf_len < sizeof(buf))
{
buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, ", %s", bpc);
}
}
snprintf(result, len, "%s", buf);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_hvtotal)
{
snprintf(result, len, "%d active, %d total", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_hvsyncblank)
{
snprintf(result, len, "%d start, %d end", (val & 0xffff) + 1, ((val & 0xffff0000) >> 16) + 1);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_m_tu)
{
snprintf(result, len, "TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff, val & 0xffffff);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_n)
{
snprintf(result, len, "val 0x%x %d", val & 0xffffff, val & 0xffffff);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_panel_fitting)
{
const char *vadapt = NULL;
const char *filter_sel = NULL;
switch (val & (3 << 25))
{
case 0:
vadapt = "least";
break;
case (1 << 25):
vadapt = "moderate";
break;
case (2 << 25):
vadapt = "reserved";
break;
case (3 << 25):
vadapt = "most";
break;
}
switch (val & (3 << 23))
{
case 0:
filter_sel = "programmed";
break;
case (1 << 23):
filter_sel = "hardcoded";
break;
case (2 << 23):
filter_sel = "edge_enhance";
break;
case (3 << 23):
filter_sel = "edge_soften";
break;
}
snprintf(result, len,
"%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s,"
"chroma pre-filter %s, vert3tap %s, v_inter_invert %s",
val & PF_ENABLE ? "enable" : "disable",
val & (1 << 30) ? "no" : "yes",
val & (1 << 29) ? "yes" : "no",
val & (1 << 28) ? "bypass" : "enable",
val & (1 << 27) ? "enable" : "disable",
vadapt, filter_sel,
val & (1 << 22) ? "enable" : "disable",
val & (1 << 21) ? "force" : "auto",
val & (1 << 20) ? "field 0" : "field 1");
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_panel_fitting_2)
{
snprintf(result, len, "vscale %f", val / (float) (1<<15));
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_panel_fitting_3)
{
snprintf(result, len, "vscale initial phase %f", val / (float) (1<<15));
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_panel_fitting_4)
{
snprintf(result, len, "hscale %f", val / (float) (1<<15));
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_pf_win)
{
int a = (val >> 16) & 0x1fff;
int b = val & 0xfff;
snprintf(result, len, "%d, %d", a, b);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_transconf)
{
const char *enable = val & TRANS_ENABLE ? "enable" : "disable";
const char *state = val & TRANS_STATE_ENABLE ? "active" : "inactive";
const char *interlace;
switch ((val >> 21) & 7)
{
case 0:
interlace = "progressive";
break;
case 2:
if (IS_GEN5(devid))
{
interlace = "interlaced sdvo";
}
else
{
interlace = "rsvd";
}
break;
case 3:
interlace = "interlaced";
break;
default:
interlace = "rsvd";
}
snprintf(result, len, "%s, %s, %s", enable, state, interlace);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_fdi_rx_misc)
{
snprintf(result, len, "FDI Delay %d", val & ((1 << 13) - 1));
}
//------------------------------------------------------------------------------
DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2)
{
int enable, blinking, granularity;
const char *pipe = NULL;
enable = (val >> 31) & 1;
if (IS_GEN5(devid) || IS_GEN6(devid))
{
pipe = ((val >> 29) & 1) ? "B" : "A";
}
else
{
switch ((val >> 29) & 3)
{
case 0:
pipe = "A";
break;
case 1:
pipe = "B";
break;
case 2:
pipe = "C";
break;
case 3:
if (IS_IVYBRIDGE(devid))
{
pipe = "reserved";
}
else
{
pipe = "EDP";
}
break;
}
}
if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
{
snprintf(result, len, "enable %d, pipe %s", enable, pipe);
}
else
{
blinking = (val >> 28) & 1;
granularity = ((val >> 27) & 1) ? 8 : 128;
snprintf(result, len, "enable %d, pipe %s, blinking %d, "
"granularity %d", enable, pipe, blinking, granularity);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl)
{
int cycle, freq;
cycle = (val & 0xFFFF);
if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
{
snprintf(result, len, "cycle %d", cycle);
}
else
{
freq = (val >> 16) & 0xFFFF;
snprintf(result, len, "cycle %d, freq %d", cycle, freq);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ibx_debug_blc_pwm_ctl1)
{
int enable, override, inverted_polarity;
enable = (val >> 31) & 1;
override = (val >> 30) & 1;
inverted_polarity = (val >> 29) & 1;
snprintf(result, len, "enable %d, override %d, inverted polarity %d",
enable, override, inverted_polarity);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ibx_debug_blc_pwm_ctl2)
{
int freq, cycle;
freq = (val >> 16) & 0xFFFF;
cycle = val & 0xFFFF;
snprintf(result, len, "freq %d, cycle %d", freq, cycle);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_blc_misc_ctl)
{
const char *sel;
sel = (val & 1) ? "PWM1-CPU PWM2-PCH" : "PWM1-PCH PWM2-CPU";
snprintf(result, len, "%s", sel);
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_util_pin_ctl)
{
int enable, data, inverted_polarity;
const char *transcoder = NULL;
const char *mode = NULL;
enable = (val >> 31) & 1;
switch ((val >> 29) & 3)
{
case 0:
transcoder = "A";
break;
case 1:
transcoder = "B";
break;
case 2:
transcoder = "C";
break;
case 3:
transcoder = "EDP";
break;
}
switch ((val >> 24) & 0xF)
{
case 0:
mode = "data";
break;
case 1:
mode = "PWM";
break;
case 4:
mode = "Vblank";
break;
case 5:
mode = "Vsync";
break;
default:
mode = "reserved";
break;
}
data = (val >> 23) & 1;
inverted_polarity = (val >> 22) & 1;
snprintf(result, len, "enable %d, transcoder %s, mode %s, data %d "
"inverted polarity %d", enable, transcoder, mode, data,
inverted_polarity);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_pp_status)
{
const char *status = val & PP_ON ? "on" : "off";
const char *ready = val & PP_READY ? "ready" : "not ready";
const char *seq = "unknown";
switch (val & PP_SEQUENCE_MASK)
{
case PP_SEQUENCE_NONE:
seq = "idle";
break;
case PP_SEQUENCE_ON:
seq = "on";
break;
case PP_SEQUENCE_OFF:
seq = "off";
break;
}
snprintf(result, len, "%s, %s, sequencing %s", status, ready, seq);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ilk_debug_pp_control)
{
snprintf(result, len, "blacklight %s, %spower down on reset, panel %s",
(val & (1 << 2)) ? "enabled" : "disabled",
(val & (1 << 1)) ? "" : "do not ",
(val & (1 << 0)) ? "on" : "off");
}
//------------------------------------------------------------------------------
DEBUGSTRING(hsw_debug_sinterrupt)
{
int portd, portc, portb, crt;
portd = (val >> 23) & 1;
portc = (val >> 22) & 1;
portb = (val >> 21) & 1;
crt = (val >> 19) & 1;
snprintf(result, len, "port d:%d, port c:%d, port b:%d, crt:%d", portd, portc, portb, crt);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_vgacntrl)
{
snprintf(result, len, "%s", val & VGA_DISP_DISABLE ? "disabled" : "enabled");
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_rr_hw_ctl)
{
snprintf(result, len, "low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK, (val & RR_HW_HIGH_POWER_FRAMES_MASK) >> 8);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_dref_ctl)
{
const char *cpu_source;
const char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
const char *nonspread_source =
val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable" : "disable";
const char *superspread_source =
val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable" : "disable";
const char *ssc4_mode =
val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread";
const char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
const char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD)
{
case DREF_CPU_SOURCE_OUTPUT_DISABLE:
cpu_source = "disable";
break;
case DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD:
cpu_source = "downspread";
break;
case DREF_CPU_SOURCE_OUTPUT_NONSPREAD:
cpu_source = "nonspread";
break;
default:
cpu_source = "reserved";
}
snprintf(result, len, "cpu source %s, ssc_source %s, nonspread_source %s, "
"superspread_source %s, ssc4_mode %s, ssc1 %s, ssc4 %s",
cpu_source, ssc_source, nonspread_source,
superspread_source, ssc4_mode, ssc1, ssc4);
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_rawclk_freq)
{
const char *tp1 = NULL, *tp2 = NULL;
switch (val & FDL_TP1_TIMER_MASK)
{
case 0:
tp1 = "0.5us";
break;
case (1 << 12):
tp1 = "1.0us";
break;
case (2 << 12):
tp1 = "2.0us";
break;
case (3 << 12):
tp1 = "4.0us";
break;
}
switch (val & FDL_TP2_TIMER_MASK)
{
case 0:
tp2 = "1.5us";
break;
case (1 << 10):
tp2 = "3.0us";
break;
case (2 << 10):
tp2 = "6.0us";
break;
case (3 << 10):
tp2 = "12.0us";
break;
}
snprintf(result, len, "FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d", tp1, tp2, val & RAWCLK_FREQ_MASK);
}
DEBUGSTRING(snb_debug_dpll_sel)
{
const char *transa, *transb;
const char *dplla = NULL, *dpllb = NULL;
if (HAS_CPT)
{
if (val & TRANSA_DPLL_ENABLE)
{
transa = "enable";
if (val & TRANSA_DPLLB_SEL)
{
dplla = "B";
}
else
{
dplla = "A";
}
}
else
{
transa = "disable";
}
if (val & TRANSB_DPLL_ENABLE)
{
transb = "enable";
if (val & TRANSB_DPLLB_SEL)
{
dpllb = "B";
}
else
{
dpllb = "A";
}
}
else
{
transb = "disable";
}
snprintf(result, len, "TransA DPLL %s (DPLL %s), TransB DPLL %s (DPLL %s)", transa, dplla, transb, dpllb);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_pch_dpll)
{
const char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
const char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
const char *mode = NULL;
const char *p2 = NULL;
int fpa0_p1, fpa1_p1;
const char *refclk = NULL;
int sdvo_mul;
if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS)
{
mode = "LVDS";
if (val & DPLLB_LVDS_P2_CLOCK_DIV_7)
{
p2 = "Div 7";
}
else
{
p2 = "Div 14";
}
}
else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL)
{
mode = "Non-LVDS";
if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
{
p2 = "Div 5";
}
else
{
p2 = "Div 10";
}
}
fpa0_p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> 16);
fpa1_p1 = ffs((val & DPLL_FPA1_P1_POST_DIV_MASK));
switch (val & PLL_REF_INPUT_MASK)
{
case PLL_REF_INPUT_DREFCLK:
refclk = "default 120Mhz";
break;
case PLL_REF_INPUT_SUPER_SSC:
refclk = "SuperSSC 120Mhz";
break;
case PLL_REF_INPUT_TVCLKINBC:
refclk = "SDVO TVClkIn";
break;
case PLLB_REF_INPUT_SPREADSPECTRUMIN:
refclk = "SSC";
break;
case PLL_REF_INPUT_DMICLK:
refclk = "DMI RefCLK";
break;
}
sdvo_mul = ((val & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) >> 9) + 1;
snprintf(result, len, "%s, sdvo high speed %s, mode %s, p2 %s, "
"FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d",
enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk, sdvo_mul);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_fp)
{
if (IS_IGD(devid))
{
snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
ffs((val & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1,
((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
((val & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT));
}
snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT),
((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
((val & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT));
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
{
const char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw =
NULL;
switch (val & FDI_LINK_TRAIN_NONE)
{
case FDI_LINK_TRAIN_PATTERN_1:
train = "pattern_1";
break;
case FDI_LINK_TRAIN_PATTERN_2:
train = "pattern_2";
break;
case FDI_LINK_TRAIN_PATTERN_IDLE:
train = "pattern_idle";
break;
case FDI_LINK_TRAIN_NONE:
train = "not train";
break;
}
if (HAS_CPT)
{
/* SNB B0 */
switch (val & (0x3f << 22))
{
case FDI_LINK_TRAIN_400MV_0DB_SNB_B:
voltage = "0.4V";
pre_emphasis = "0dB";
break;
case FDI_LINK_TRAIN_400MV_6DB_SNB_B:
voltage = "0.4V";
pre_emphasis = "6dB";
break;
case FDI_LINK_TRAIN_600MV_3_5DB_SNB_B:
voltage = "0.6V";
pre_emphasis = "3.5dB";
break;
case FDI_LINK_TRAIN_800MV_0DB_SNB_B:
voltage = "0.8V";
pre_emphasis = "0dB";
break;
}
}
else
{
switch (val & (7 << 25))
{
case FDI_LINK_TRAIN_VOLTAGE_0_4V:
voltage = "0.4V";
break;
case FDI_LINK_TRAIN_VOLTAGE_0_6V:
voltage = "0.6V";
break;
case FDI_LINK_TRAIN_VOLTAGE_0_8V:
voltage = "0.8V";
break;
case FDI_LINK_TRAIN_VOLTAGE_1_2V:
voltage = "1.2V";
break;
default:
voltage = "reserved";
}
switch (val & (7 << 22))
{
case FDI_LINK_TRAIN_PRE_EMPHASIS_NONE:
pre_emphasis = "none";
break;
case FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X:
pre_emphasis = "1.5x";
break;
case FDI_LINK_TRAIN_PRE_EMPHASIS_2X:
pre_emphasis = "2x";
break;
case FDI_LINK_TRAIN_PRE_EMPHASIS_3X:
pre_emphasis = "3x";
break;
default:
pre_emphasis = "reserved";
}
}
switch (val & (7 << 19))
{
case FDI_DP_PORT_WIDTH_X1:
portw = "X1";
break;
case FDI_DP_PORT_WIDTH_X2:
portw = "X2";
break;
case FDI_DP_PORT_WIDTH_X3:
portw = "X3";
break;
case FDI_DP_PORT_WIDTH_X4:
portw = "X4";
break;
}
snprintf(result, len, "%s, train pattern %s, voltage swing %s,"
"pre-emphasis %s, port width %s, enhanced framing %s, FDI PLL %s, scrambing %s, master mode %s",
val & FDI_TX_ENABLE ? "enable" : "disable",
train, voltage, pre_emphasis, portw,
val & FDI_TX_ENHANCE_FRAME_ENABLE ? "enable" : "disable",
val & FDI_TX_PLL_ENABLE ? "enable" : "disable",
val & (1 << 7) ? "disable" : "enable",
val & (1 << 0) ? "enable" : "disable");
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_fdi_rx_ctl)
{
const char *train = NULL, *portw = NULL, *bpc = NULL;
if (HAS_CPT)
{
switch (val & FDI_LINK_TRAIN_PATTERN_MASK_CPT)
{
case FDI_LINK_TRAIN_PATTERN_1_CPT:
train = "pattern_1";
break;
case FDI_LINK_TRAIN_PATTERN_2_CPT:
train = "pattern_2";
break;
case FDI_LINK_TRAIN_PATTERN_IDLE_CPT:
train = "pattern_idle";
break;
case FDI_LINK_TRAIN_NORMAL_CPT:
train = "not train";
break;
}
}
else
{
switch (val & FDI_LINK_TRAIN_NONE)
{
case FDI_LINK_TRAIN_PATTERN_1:
train = "pattern_1";
break;
case FDI_LINK_TRAIN_PATTERN_2:
train = "pattern_2";
break;
case FDI_LINK_TRAIN_PATTERN_IDLE:
train = "pattern_idle";
break;
case FDI_LINK_TRAIN_NONE:
train = "not train";
break;
}
}
switch (val & (7 << 19))
{
case FDI_DP_PORT_WIDTH_X1:
portw = "X1";
break;
case FDI_DP_PORT_WIDTH_X2:
portw = "X2";
break;
case FDI_DP_PORT_WIDTH_X3:
portw = "X3";
break;
case FDI_DP_PORT_WIDTH_X4:
portw = "X4";
break;
}
switch (val & (7 << 16))
{
case FDI_8BPC:
bpc = "8bpc";
break;
case FDI_10BPC:
bpc = "10bpc";
break;
case FDI_6BPC:
bpc = "6bpc";
break;
case FDI_12BPC:
bpc = "12bpc";
break;
}
snprintf(result, len, "%s, train pattern %s, port width %s, %s,"
"link_reverse_strap_overwrite %s, dmi_link_reverse %s, FDI PLL %s,"
"FS ecc %s, FE ecc %s, FS err report %s, FE err report %s,"
"scrambing %s, enhanced framing %s, %s",
val & FDI_RX_ENABLE ? "enable" : "disable",
train, portw, bpc,
val & FDI_LINK_REVERSE_OVERWRITE ? "yes" : "no",
val & FDI_DMI_LINK_REVERSE_MASK ? "yes" : "no",
val & FDI_RX_PLL_ENABLE ? "enable" : "disable",
val & FDI_FS_ERR_CORRECT_ENABLE ? "enable" : "disable",
val & FDI_FE_ERR_CORRECT_ENABLE ? "enable" : "disable",
val & FDI_FS_ERR_REPORT_ENABLE ? "enable" : "disable",
val & FDI_FE_ERR_REPORT_ENABLE ? "enable" : "disable",
val & (1 << 7) ? "disable" : "enable",
val & FDI_RX_ENHANCE_FRAME_ENABLE ? "enable" :
"disable", val & FDI_SEL_PCDCLK ? "PCDClk" : "RawClk");
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_adpa)
{
char disp_pipe = (val & ADPA_PIPE_B_SELECT) ? 'B' : 'A';
const char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled";
char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
if (HAS_CPT)
{
disp_pipe = val & (1<<29) ? 'B' : 'A';
}
if (HAS_PCH_SPLIT(devid))
{
snprintf(result, len, "%s, transcoder %c, %chsync, %cvsync", enable, disp_pipe, hsync, vsync);
}
else
{
snprintf(result, len, "%s, pipe %c, %chsync, %cvsync", enable, disp_pipe, hsync, vsync);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ironlake_debug_hdmi)
{
int disp_pipe;
const char *enable, *bpc = NULL, *encoding;
const char *mode, *audio, *vsync, *hsync, *detect;
if (val & PORT_ENABLE)
{
enable = "enabled";
}
else
{
enable = "disabled";
}
if (HAS_CPT)
{
disp_pipe = (val & (3<<29)) >> 29;
}
else
{
disp_pipe = (val & TRANSCODER_B) >> 29;
}
switch (val & (7 << 26))
{
case COLOR_FORMAT_8bpc:
bpc = "8bpc";
break;
case COLOR_FORMAT_12bpc:
bpc = "12bpc";
break;
}
if ((val & (3 << 10)) == TMDS_ENCODING)
{
encoding = "TMDS";
}
else
{
encoding = "SDVO";
}
if (val & (1 << 9))
{
mode = "HDMI";
}
else
{
mode = "DVI";
}
if (val & AUDIO_ENABLE)
{
audio = "enabled";
}
else
{
audio = "disabled";
}
if (val & VSYNC_ACTIVE_HIGH)
{
vsync = "+vsync";
}
else
{
vsync = "-vsync";
}
if (val & HSYNC_ACTIVE_HIGH)
{
hsync = "+hsync";
}
else
{
hsync = "-hsync";
}
if (val & PORT_DETECTED)
{
detect = "detected";
}
else
{
detect = "non-detected";
}
snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s", enable, disp_pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_lvds)
{
char disp_pipe = val & LVDS_PIPEB_SELECT ? 'B' : 'A';
const char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled";
int depth;
const char *channels;
if ((val & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
{
depth = 24;
}
else
{
depth = 18;
}
if ((val & LVDS_B0B3_POWER_MASK) == LVDS_B0B3_POWER_UP)
{
channels = "2 channels";
}
else
{
channels = "1 channel";
}
if (HAS_CPT)
{
disp_pipe = val & (1<<29) ? 'B' : 'A';
}
snprintf(result, len, "%s, pipe %c, %d bit, %s", enable, disp_pipe, depth, channels);
}
//------------------------------------------------------------------------------
DEBUGSTRING(snb_debug_trans_dp_ctl)
{
const char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync;
if (HAS_CPT)
{
if (val & TRANS_DP_OUTPUT_ENABLE)
{
enable = "enable";
}
else
{
enable = "disable";
}
switch (val & TRANS_DP_PORT_SEL_MASK)
{
case TRANS_DP_PORT_SEL_B:
port = "B";
break;
case TRANS_DP_PORT_SEL_C:
port = "C";
break;
case TRANS_DP_PORT_SEL_D:
port = "D";
break;
default:
port = "none";
break;
}
switch (val & (7<<9))
{
case TRANS_DP_8BPC:
bpc = "8bpc";
break;
case TRANS_DP_10BPC:
bpc = "10bpc";
break;
case TRANS_DP_6BPC:
bpc = "6bpc";
break;
case TRANS_DP_12BPC:
bpc = "12bpc";
break;
}
if (val & TRANS_DP_VSYNC_ACTIVE_HIGH)
{
vsync = "+vsync";
}
else
{
vsync = "-vsync";
}
if (val & TRANS_DP_HSYNC_ACTIVE_HIGH)
{
hsync = "+hsync";
}
else
{
hsync = "-hsync";
}
snprintf(result, len, "%s port %s %s %s %s", enable, port, bpc, vsync, hsync);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(ivb_debug_port)
{
const char *drrs = NULL;
switch (val & (2 << 30))
{
case PORT_DBG_DRRS_HW_STATE_OFF:
drrs = "off";
break;
case PORT_DBG_DRRS_HW_STATE_LOW:
drrs = "low";
break;
/* case PORT_DBG_DRRS_HW_STATE_HIGH:
drrs = "high";
break; */
}
snprintf(result, len, "HW DRRS %s", drrs);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_16bit_func)
{
snprintf(result, len, "0x%04x", (uint16_t) val);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dcc)
{
const char *addressing = NULL;
if (IS_MOBILE(devid))
{
if (IS_965(devid))
{
if (val & (1 << 1))
{
addressing = "dual channel interleaved";
}
else
{
addressing = "single or dual channel asymmetric";
}
}
else
{
switch (val & 3)
{
case 0:
addressing = "single channel";
break;
case 1:
addressing = "dual channel asymmetric";
break;
case 2:
addressing = "dual channel interleaved";
break;
case 3:
addressing = "unknown channel layout";
break;
}
}
snprintf(result, len, "%s, XOR randomization: %sabled, XOR bit: %d",
addressing, (val & (1 << 10)) ? "dis" : "en", (val & (1 << 9)) ? 17 : 11);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_chdecmisc)
{
const char *enhmodesel = NULL;
switch ((val >> 5) & 3)
{
case 1:
enhmodesel = "XOR bank/rank";
break;
case 2:
enhmodesel = "swap bank";
break;
case 3:
enhmodesel = "XOR bank";
break;
case 0:
enhmodesel = "none";
break;
}
snprintf(result, len,
"%s, ch2 enh %sabled, ch1 enh %sabled, "
"ch0 enh %sabled, "
"flex %sabled, ep %spresent", enhmodesel,
(val & (1 << 4)) ? "en" : "dis",
(val & (1 << 3)) ? "en" : "dis",
(val & (1 << 2)) ? "en" : "dis",
(val & (1 << 1)) ? "en" : "dis",
(val & (1 << 0)) ? "" : "not ");
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_vga_pd)
{
int vga0_p1, vga0_p2, vga1_p1, vga1_p2;
/* XXX: i9xx version */
if (val & VGA0_PD_P1_DIV_2)
{
vga0_p1 = 2;
}
else
{
vga0_p1 = ((val & VGA0_PD_P1_MASK) >> VGA0_PD_P1_SHIFT) + 2;
}
vga0_p2 = (val & VGA0_PD_P2_DIV_4) ? 4 : 2;
if (val & VGA1_PD_P1_DIV_2)
{
vga1_p1 = 2;
}
else
{
vga1_p1 = ((val & VGA1_PD_P1_MASK) >> VGA1_PD_P1_SHIFT) + 2;
}
vga1_p2 = (val & VGA1_PD_P2_DIV_4) ? 4 : 2;
snprintf(result, len, "vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d", vga0_p1, vga0_p2, vga1_p1, vga1_p2);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dpll_test)
{
const char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : "";
const char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : "";
const char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ? "" : ", DPLLA input buffer disabled";
const char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : "";
const char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : "";
const char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ? "" : ", DPLLB input buffer disabled";
snprintf(result, len, "%s%s%s%s%s%s", dpllandiv, dpllamdiv, dpllainput, dpllbndiv, dpllbmdiv, dpllbinput);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dspclk_gate_d)
{
const char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
const char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
const char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
const char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
const char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
const char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
const char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
const char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
const char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
const char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
const char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
const char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
const char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
const char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
const char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
const char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
const char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
const char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
const char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
const char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
const char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
const char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
const char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
const char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
const char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
const char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
const char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
const char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
const char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
const char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
const char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
const char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
snprintf(result, len,
"clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
DPUNIT_B, VSUNIT, VRHUNIT, VRDUNIT, AUDUNIT, DPUNIT_A, DPCUNIT,
TVRUNIT, TVCUNIT, TVFUNIT, TVEUNIT, DVSUNIT, DSSUNIT, DDBUNIT,
DPRUNIT, DPFUNIT, DPBMUNIT, DPLSUNIT, DPLUNIT, DPOUNIT, DPBUNIT,
DCUNIT, DPUNIT, VRUNIT, OVHUNIT, DPIOUNIT, OVFUNIT, OVBUNIT,
OVRUNIT, OVCUNIT, OVUUNIT, OVLUNIT);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_sdvo)
{
const char *enable = val & SDVO_ENABLE ? "enabled" : "disabled";
char disp_pipe = val & SDVO_PIPE_B_SELECT ? 'B' : 'A';
const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled";
const char *detected = val & SDVO_DETECTED ? "" : "not ";
const char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : "";
char sdvoextra[20];
if (IS_915(devid))
{
snprintf(sdvoextra, len, ", SDVO mult %d", (int)((val & SDVO_PORT_MULTIPLY_MASK) >> SDVO_PORT_MULTIPLY_SHIFT) + 1);
}
else
{
sdvoextra[0] = '\0';
}
snprintf(result, len, "%s, pipe %c, stall %s, %sdetected%s%s", enable, disp_pipe, stall, detected, sdvoextra, gang);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dvo)
{
const char *enable = val & DVO_ENABLE ? "enabled" : "disabled";
char disp_pipe = val & DVO_PIPE_B_SELECT ? 'B' : 'A';
const char *stall;
char hsync = val & DVO_HSYNC_ACTIVE_HIGH ? '+' : '-';
char vsync = val & DVO_VSYNC_ACTIVE_HIGH ? '+' : '-';
switch (val & DVO_PIPE_STALL_MASK)
{
case DVO_PIPE_STALL_UNUSED:
stall = "no stall";
break;
case DVO_PIPE_STALL:
stall = "stall";
break;
case DVO_PIPE_STALL_TV:
stall = "TV stall";
break;
default:
stall = "unknown stall";
break;
}
snprintf(result, len, "%s, pipe %c, %s, %chsync, %cvsync", enable, disp_pipe, stall, hsync, vsync);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_pp_control)
{
snprintf(result, len, "power target: %s", val & POWER_TARGET_ON ? "on" : "off");
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dspstride)
{
snprintf(result, len, "%d bytes", val);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_pipestat)
{
const char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
const char *_CRC_ERROR_ENABLE =
val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
const char *_CRC_DONE_ENABLE =
val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
const char *_GMBUS_EVENT_ENABLE =
val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
const char *_VSYNC_INT_ENABLE =
val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
const char *_DLINE_COMPARE_ENABLE =
val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
const char *_DPST_EVENT_ENABLE =
val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
const char *_LBLC_EVENT_ENABLE =
val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
const char *_OFIELD_INT_ENABLE =
val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
const char *_EFIELD_INT_ENABLE =
val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
const char *_SVBLANK_INT_ENABLE =
val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
const char *_VBLANK_INT_ENABLE =
val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
const char *_OREG_UPDATE_ENABLE =
val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
const char *_CRC_ERROR_INT_STATUS =
val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
const char *_CRC_DONE_INT_STATUS =
val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
const char *_GMBUS_INT_STATUS =
val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
const char *_VSYNC_INT_STATUS =
val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
const char *_DLINE_COMPARE_STATUS =
val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
const char *_DPST_EVENT_STATUS =
val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
const char *_LBLC_EVENT_STATUS =
val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
const char *_OFIELD_INT_STATUS =
val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
const char *_EFIELD_INT_STATUS =
val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
const char *_SVBLANK_INT_STATUS =
val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
const char *_VBLANK_INT_STATUS =
val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
const char *_OREG_UPDATE_STATUS =
val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
snprintf(result, len,
"status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
_FIFO_UNDERRUN,
_CRC_ERROR_ENABLE,
_CRC_DONE_ENABLE,
_GMBUS_EVENT_ENABLE,
_VSYNC_INT_ENABLE,
_DLINE_COMPARE_ENABLE,
_DPST_EVENT_ENABLE,
_LBLC_EVENT_ENABLE,
_OFIELD_INT_ENABLE,
_EFIELD_INT_ENABLE,
_SVBLANK_INT_ENABLE,
_VBLANK_INT_ENABLE,
_OREG_UPDATE_ENABLE,
_CRC_ERROR_INT_STATUS,
_CRC_DONE_INT_STATUS,
_GMBUS_INT_STATUS,
_VSYNC_INT_STATUS,
_DLINE_COMPARE_STATUS,
_DPST_EVENT_STATUS,
_LBLC_EVENT_STATUS,
_OFIELD_INT_STATUS,
_EFIELD_INT_STATUS,
_SVBLANK_INT_STATUS,
_VBLANK_INT_STATUS,
_OREG_UPDATE_STATUS);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i830_debug_dpll)
{
const char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled";
const char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo";
const char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA";
const char *mode = "unknown";
const char *clock = "unknown";
const char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : "";
char sdvoextra[20];
int p1, p2 = 0;
if (IS_GEN2(devid))
{
// char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
char is_lvds = (MMIO_READ32(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
if (is_lvds)
{
mode = "LVDS";
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT);
// if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
if ((MMIO_READ32(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
{
p2 = 7;
}
else
{
p2 = 14;
}
}
else
{
mode = "DAC/serial";
if (val & PLL_P1_DIVIDE_BY_TWO)
{
p1 = 2;
}
else
{
/* Map the number in the field to (3, 33) */
p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
}
if (val & PLL_P2_DIVIDE_BY_4)
{
p2 = 4;
}
else
{
p2 = 2;
}
}
}
else
{
if (IS_IGD(devid))
{
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
}
else
{
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> DPLL_FPA01_P1_POST_DIV_SHIFT);
}
switch (val & DPLL_MODE_MASK)
{
case DPLLB_MODE_DAC_SERIAL:
mode = "DAC/serial";
p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
break;
case DPLLB_MODE_LVDS:
mode = "LVDS";
p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
break;
}
}
switch (val & PLL_REF_INPUT_MASK)
{
case PLL_REF_INPUT_DREFCLK:
clock = "default";
break;
case PLL_REF_INPUT_TVCLKINA:
clock = "TV A";
break;
case PLL_REF_INPUT_TVCLKINBC:
clock = "TV B/C";
break;
case PLLB_REF_INPUT_SPREADSPECTRUMIN:
if (reg == DPLL_B)
clock = "spread spectrum";
break;
}
if (IS_945(devid))
{
snprintf(sdvoextra, len, ", SDVO mult %d", (int)((val & SDVO_MULTIPLIER_MASK) >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1);
}
else
{
sdvoextra[0] = '\0';
}
snprintf(result, len, "%s, %s%s, %s clock, %s mode, p1 = %d, p2 = %d%s%s", enabled, dvomode, vgamode, clock, mode, p1, p2, fpextra, sdvoextra);
}
//------------------------------------------------------------------------------
DEBUGSTRING(i810_debug_915_fence)
{
char format = (val & 1 << 12) ? 'Y' : 'X';
int pitch = 128 << ((val & 0x70) >> 4);
unsigned int offset = val & 0x0ff00000;
int size = (1024 * 1024) << ((val & 0x700) >> 8);
if (IS_965(devid) || (IS_915(devid) && reg >= FENCE_NEW))
{
return;
}
if (format == 'X')
{
pitch *= 4;
}
if (val & 1)
{
snprintf(result, len, "enabled, %c tiled, %4d pitch, 0x%08x - 0x%08x (%dkb)", format, pitch, offset, offset + size, size / 1024);
}
else
{
snprintf(result, len, "disabled");
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(i810_debug_965_fence_start)
{
const char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X';
int pitch = ((val & 0xffc) >> 2) * 128 + 128;
unsigned int offset = val & 0xfffff000;
if (IS_965(devid))
{
snprintf(result, len, "%s, %c tile walk, %4d pitch, 0x%08x start", enable, format, pitch, offset);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(i810_debug_965_fence_end)
{
unsigned int end = val & 0xfffff000;
if (IS_965(devid))
{
snprintf(result, len, " 0x%08x end", end);
}
}
//------------------------------------------------------------------------------
DEBUGSTRING(gen6_rp_control)
{
snprintf(result, len, "%s", (val & (1 << 7)) ? "enabled" : "disabled");
}
//------------------------------------------------------------------------------
static struct reg_debug gen6_fences[] = {
#define DEFINEFENCE_SNB(i) \
{ FENCE_REG_SANDYBRIDGE_0 + (i) * 8, "FENCE START "#i, NULL, 0 }, \
{ FENCE_REG_SANDYBRIDGE_0 + (i) * 8 + 4, "FENCE END "#i, NULL, 0 }
DEFINEFENCE_SNB(0),
DEFINEFENCE_SNB(1),
DEFINEFENCE_SNB(2),
DEFINEFENCE_SNB(3),
DEFINEFENCE_SNB(4),
DEFINEFENCE_SNB(5),
DEFINEFENCE_SNB(6),
DEFINEFENCE_SNB(7),
DEFINEFENCE_SNB(8),
DEFINEFENCE_SNB(9),
DEFINEFENCE_SNB(10),
DEFINEFENCE_SNB(11),
DEFINEFENCE_SNB(12),
DEFINEFENCE_SNB(13),
DEFINEFENCE_SNB(14),
DEFINEFENCE_SNB(15),
DEFINEFENCE_SNB(16),
DEFINEFENCE_SNB(17),
DEFINEFENCE_SNB(18),
DEFINEFENCE_SNB(19),
DEFINEFENCE_SNB(20),
DEFINEFENCE_SNB(20),
DEFINEFENCE_SNB(21),
DEFINEFENCE_SNB(22),
DEFINEFENCE_SNB(23),
DEFINEFENCE_SNB(24),
DEFINEFENCE_SNB(25),
DEFINEFENCE_SNB(26),
DEFINEFENCE_SNB(27),
DEFINEFENCE_SNB(28),
DEFINEFENCE_SNB(29),
DEFINEFENCE_SNB(30),
DEFINEFENCE_SNB(31),
};
//------------------------------------------------------------------------------
static struct reg_debug gen6_rp_debug_regs[] = {
DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),
DEFINEREG(GEN6_RPNSWREQ),
DEFINEREG(GEN6_RP_DOWN_TIMEOUT),
DEFINEREG(GEN6_RP_INTERRUPT_LIMITS),
DEFINEREG(GEN6_RP_UP_THRESHOLD),
DEFINEREG(GEN6_RP_UP_EI),
DEFINEREG(GEN6_RP_DOWN_EI),
DEFINEREG(GEN6_RP_IDLE_HYSTERSIS),
DEFINEREG(GEN6_RC_STATE),
DEFINEREG(GEN6_RC_CONTROL),
DEFINEREG(GEN6_RC1_WAKE_RATE_LIMIT),
DEFINEREG(GEN6_RC6_WAKE_RATE_LIMIT),
DEFINEREG(GEN6_RC_EVALUATION_INTERVAL),
DEFINEREG(GEN6_RC_IDLE_HYSTERSIS),
DEFINEREG(GEN6_RC_SLEEP),
DEFINEREG(GEN6_RC1e_THRESHOLD),
DEFINEREG(GEN6_RC6_THRESHOLD),
DEFINEREG(GEN6_RC_VIDEO_FREQ),
DEFINEREG(GEN6_PMIER),
DEFINEREG(GEN6_PMIMR),
DEFINEREG(GEN6_PMINTRMSK),
};
//------------------------------------------------------------------------------
static struct reg_debug intel_debug_regs[] = {
DEFINEREG2(DCC, i830_debug_dcc),
DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
DEFINEREG_16BIT(C0DRB0),
DEFINEREG_16BIT(C0DRB1),
DEFINEREG_16BIT(C0DRB2),
DEFINEREG_16BIT(C0DRB3),
DEFINEREG_16BIT(C1DRB0),
DEFINEREG_16BIT(C1DRB1),
DEFINEREG_16BIT(C1DRB2),
DEFINEREG_16BIT(C1DRB3),
DEFINEREG_16BIT(C0DRA01),
DEFINEREG_16BIT(C0DRA23),
DEFINEREG_16BIT(C1DRA01),
DEFINEREG_16BIT(C1DRA23),
DEFINEREG(PGETBL_CTL),
DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
DEFINEREG(CACHE_MODE_0),
DEFINEREG(D_STATE),
DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
DEFINEREG(RENCLK_GATE_D1),
DEFINEREG(RENCLK_GATE_D2),
/* DEFINEREG(RAMCLK_GATE_D), CRL only */
DEFINEREG2(SDVOB, i830_debug_sdvo),
DEFINEREG2(SDVOC, i830_debug_sdvo),
/* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
/* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
DEFINEREG(SDVOUDI),
DEFINEREG(DSPARB),
DEFINEREG(FW_BLC),
DEFINEREG(FW_BLC2),
DEFINEREG(FW_BLC_SELF),
DEFINEREG(DSPFW1),
DEFINEREG(DSPFW2),
DEFINEREG(DSPFW3),
DEFINEREG2(ADPA, i830_debug_adpa),
DEFINEREG2(LVDS, i830_debug_lvds),
DEFINEREG2(DVOA, i830_debug_dvo),
DEFINEREG2(DVOB, i830_debug_dvo),
DEFINEREG2(DVOC, i830_debug_dvo),
DEFINEREG(DVOA_SRCDIM),
DEFINEREG(DVOB_SRCDIM),
DEFINEREG(DVOC_SRCDIM),
DEFINEREG(BLC_PWM_CTL),
DEFINEREG(BLC_PWM_CTL2),
DEFINEREG2(PP_CONTROL, i830_debug_pp_control),
DEFINEREG2(PP_STATUS, i830_debug_pp_status),
DEFINEREG(PP_ON_DELAYS),
DEFINEREG(PP_OFF_DELAYS),
DEFINEREG(PP_DIVISOR),
DEFINEREG(PFIT_CONTROL),
DEFINEREG(PFIT_PGM_RATIOS),
DEFINEREG(PORT_HOTPLUG_EN),
DEFINEREG(PORT_HOTPLUG_STAT),
DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
DEFINEREG2(DSPASTRIDE, i830_debug_dspstride),
DEFINEREG2(DSPAPOS, i830_debug_xy),
DEFINEREG2(DSPASIZE, i830_debug_xyminus1),
DEFINEREG(DSPABASE),
DEFINEREG(DSPASURF),
DEFINEREG(DSPATILEOFF),
DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
DEFINEREG(PIPEA_GMCH_DATA_M),
DEFINEREG(PIPEA_GMCH_DATA_N),
DEFINEREG(PIPEA_DP_LINK_M),
DEFINEREG(PIPEA_DP_LINK_N),
DEFINEREG(CURSOR_A_BASE),
DEFINEREG(CURSOR_A_CONTROL),
DEFINEREG(CURSOR_A_POSITION),
DEFINEREG2(FPA0, i830_debug_fp),
DEFINEREG2(FPA1, i830_debug_fp),
DEFINEREG2(DPLL_A, i830_debug_dpll),
DEFINEREG(DPLL_A_MD),
DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
DEFINEREG(BCLRPAT_A),
DEFINEREG(VSYNCSHIFT_A),
DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride),
DEFINEREG2(DSPBPOS, i830_debug_xy),
DEFINEREG2(DSPBSIZE, i830_debug_xyminus1),
DEFINEREG(DSPBBASE),
DEFINEREG(DSPBSURF),
DEFINEREG(DSPBTILEOFF),
DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
DEFINEREG(PIPEB_GMCH_DATA_M),
DEFINEREG(PIPEB_GMCH_DATA_N),
DEFINEREG(PIPEB_DP_LINK_M),
DEFINEREG(PIPEB_DP_LINK_N),
DEFINEREG(CURSOR_B_BASE),
DEFINEREG(CURSOR_B_CONTROL),
DEFINEREG(CURSOR_B_POSITION),
DEFINEREG2(FPB0, i830_debug_fp),
DEFINEREG2(FPB1, i830_debug_fp),
DEFINEREG2(DPLL_B, i830_debug_dpll),
DEFINEREG(DPLL_B_MD),
DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
DEFINEREG(BCLRPAT_B),
DEFINEREG(VSYNCSHIFT_B),
DEFINEREG(VCLK_DIVISOR_VGA0),
DEFINEREG(VCLK_DIVISOR_VGA1),
DEFINEREG(VCLK_POST_DIV),
DEFINEREG2(VGACNTRL, i830_debug_vgacntrl),
DEFINEREG(TV_CTL),
DEFINEREG(TV_DAC),
DEFINEREG(TV_CSC_Y),
DEFINEREG(TV_CSC_Y2),
DEFINEREG(TV_CSC_U),
DEFINEREG(TV_CSC_U2),
DEFINEREG(TV_CSC_V),
DEFINEREG(TV_CSC_V2),
DEFINEREG(TV_CLR_KNOBS),
DEFINEREG(TV_CLR_LEVEL),
DEFINEREG(TV_H_CTL_1),
DEFINEREG(TV_H_CTL_2),
DEFINEREG(TV_H_CTL_3),
DEFINEREG(TV_V_CTL_1),
DEFINEREG(TV_V_CTL_2),
DEFINEREG(TV_V_CTL_3),
DEFINEREG(TV_V_CTL_4),
DEFINEREG(TV_V_CTL_5),
DEFINEREG(TV_V_CTL_6),
DEFINEREG(TV_V_CTL_7),
DEFINEREG(TV_SC_CTL_1),
DEFINEREG(TV_SC_CTL_2),
DEFINEREG(TV_SC_CTL_3),
DEFINEREG(TV_WIN_POS),
DEFINEREG(TV_WIN_SIZE),
DEFINEREG(TV_FILTER_CTL_1),
DEFINEREG(TV_FILTER_CTL_2),
DEFINEREG(TV_FILTER_CTL_3),
DEFINEREG(TV_CC_CONTROL),
DEFINEREG(TV_CC_DATA),
DEFINEREG(TV_H_LUMA_0),
DEFINEREG(TV_H_LUMA_59),
DEFINEREG(TV_H_CHROMA_0),
DEFINEREG(TV_H_CHROMA_59),
DEFINEREG(FBC_CFB_BASE),
DEFINEREG(FBC_LL_BASE),
DEFINEREG(FBC_CONTROL),
DEFINEREG(FBC_COMMAND),
DEFINEREG(FBC_STATUS),
DEFINEREG(FBC_CONTROL2),
DEFINEREG(FBC_FENCE_OFF),
DEFINEREG(FBC_MOD_NUM),
DEFINEREG(MI_MODE),
/* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */
DEFINEREG(MI_ARB_STATE),
DEFINEREG(MI_RDRET_STATE),
DEFINEREG(ECOSKPD),
DEFINEREG(DP_B),
DEFINEREG(DPB_AUX_CH_CTL),
DEFINEREG(DPB_AUX_CH_DATA1),
DEFINEREG(DPB_AUX_CH_DATA2),
DEFINEREG(DPB_AUX_CH_DATA3),
DEFINEREG(DPB_AUX_CH_DATA4),
DEFINEREG(DPB_AUX_CH_DATA5),
DEFINEREG(DP_C),
DEFINEREG(DPC_AUX_CH_CTL),
DEFINEREG(DPC_AUX_CH_DATA1),
DEFINEREG(DPC_AUX_CH_DATA2),
DEFINEREG(DPC_AUX_CH_DATA3),
DEFINEREG(DPC_AUX_CH_DATA4),
DEFINEREG(DPC_AUX_CH_DATA5),
DEFINEREG(DP_D),
DEFINEREG(DPD_AUX_CH_CTL),
DEFINEREG(DPD_AUX_CH_DATA1),
DEFINEREG(DPD_AUX_CH_DATA2),
DEFINEREG(DPD_AUX_CH_DATA3),
DEFINEREG(DPD_AUX_CH_DATA4),
DEFINEREG(DPD_AUX_CH_DATA5),
DEFINEREG(AUD_CONFIG),
DEFINEREG(AUD_HDMIW_STATUS),
DEFINEREG(AUD_CONV_CHCNT),
DEFINEREG(VIDEO_DIP_CTL),
DEFINEREG(AUD_PINW_CNTR),
DEFINEREG(AUD_CNTL_ST),
DEFINEREG(AUD_PIN_CAP),
DEFINEREG(AUD_PINW_CAP),
DEFINEREG(AUD_PINW_UNSOLRESP),
DEFINEREG(AUD_OUT_DIG_CNVT),
DEFINEREG(AUD_OUT_CWCAP),
DEFINEREG(AUD_GRP_CAP),
#define DEFINEFENCE_915(i) \
{ FENCE+i*4, "FENCE " #i, i810_debug_915_fence, 0 }
#define DEFINEFENCE_945(i) \
{ FENCE_NEW+(i - 8) * 4, "FENCE " #i, i810_debug_915_fence, 0 }
DEFINEFENCE_915(0),
DEFINEFENCE_915(1),
DEFINEFENCE_915(2),
DEFINEFENCE_915(3),
DEFINEFENCE_915(4),
DEFINEFENCE_915(5),
DEFINEFENCE_915(6),
DEFINEFENCE_915(7),
DEFINEFENCE_945(8),
DEFINEFENCE_945(9),
DEFINEFENCE_945(10),
DEFINEFENCE_945(11),
DEFINEFENCE_945(12),
DEFINEFENCE_945(13),
DEFINEFENCE_945(14),
DEFINEFENCE_945(15),
#define DEFINEFENCE_965(i) \
{ FENCE_NEW+i*8, "FENCE START " #i, i810_debug_965_fence_start, 0 }, \
{ FENCE_NEW+i*8+4, "FENCE END " #i, i810_debug_965_fence_end, 0 }
DEFINEFENCE_965(0),
DEFINEFENCE_965(1),
DEFINEFENCE_965(2),
DEFINEFENCE_965(3),
DEFINEFENCE_965(4),
DEFINEFENCE_965(5),
DEFINEFENCE_965(6),
DEFINEFENCE_965(7),
DEFINEFENCE_965(8),
DEFINEFENCE_965(9),
DEFINEFENCE_965(10),
DEFINEFENCE_965(11),
DEFINEFENCE_965(12),
DEFINEFENCE_965(13),
DEFINEFENCE_965(14),
DEFINEFENCE_965(15),
DEFINEREG(INST_PM),
};
//------------------------------------------------------------------------------
static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(INSTDONE_I965),
DEFINEREG(INSTDONE_1),
DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL),
DEFINEREG2(RR_HW_CTL, ironlake_debug_rr_hw_ctl),
DEFINEREG(FDI_PLL_BIOS_0),
DEFINEREG(FDI_PLL_BIOS_1),
DEFINEREG(FDI_PLL_BIOS_2),
DEFINEREG(DISPLAY_PORT_PLL_BIOS_0),
DEFINEREG(DISPLAY_PORT_PLL_BIOS_1),
DEFINEREG(DISPLAY_PORT_PLL_BIOS_2),
DEFINEREG(FDI_PLL_FREQ_CTL),
/* pipe B */
DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_A),
DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEA_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(PIPEA_DATA_N2, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_M2, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_N2, ironlake_debug_n),
DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
DEFINEREG(DSPABASE),
DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPASURF),
DEFINEREG2(DSPATILEOFF, i830_debug_xy),
/* pipe B */
DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_B),
DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
DEFINEREG(DSPBBASE),
DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPBSURF),
DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
/* pipe C */
DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_C),
DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
DEFINEREG(DSPCBASE),
DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPCSURF),
DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
/* Panel fitter */
DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4),
DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2),
DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3),
DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4),
DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFC_CTL_2, ironlake_debug_panel_fitting_2),
DEFINEREG2(PFC_CTL_3, ironlake_debug_panel_fitting_3),
DEFINEREG2(PFC_CTL_4, ironlake_debug_panel_fitting_4),
DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
/* PCH */
DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
DEFINEREG2(PCH_RAWCLK_FREQ, ironlake_debug_rawclk_freq),
DEFINEREG(PCH_DPLL_TMR_CFG),
DEFINEREG(PCH_SSC4_PARMS),
DEFINEREG(PCH_SSC4_AUX_PARMS),
DEFINEREG2(PCH_DPLL_SEL, snb_debug_dpll_sel),
DEFINEREG(PCH_DPLL_ANALOG_CTL),
DEFINEREG2(PCH_DPLL_A, ironlake_debug_pch_dpll),
DEFINEREG2(PCH_DPLL_B, ironlake_debug_pch_dpll),
DEFINEREG2(PCH_FPA0, i830_debug_fp),
DEFINEREG2(PCH_FPA1, i830_debug_fp),
DEFINEREG2(PCH_FPB0, i830_debug_fp),
DEFINEREG2(PCH_FPB1, i830_debug_fp),
DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
DEFINEREG(TRANS_VSYNCSHIFT_A),
DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
DEFINEREG2(TRANSA_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(TRANSA_DATA_N2, ironlake_debug_n),
DEFINEREG2(TRANSA_DP_LINK_M1, ironlake_debug_n),
DEFINEREG2(TRANSA_DP_LINK_N1, ironlake_debug_n),
DEFINEREG2(TRANSA_DP_LINK_M2, ironlake_debug_n),
DEFINEREG2(TRANSA_DP_LINK_N2, ironlake_debug_n),
DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
DEFINEREG(TRANS_VSYNCSHIFT_B),
DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
DEFINEREG2(TRANSB_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(TRANSB_DATA_N2, ironlake_debug_n),
DEFINEREG2(TRANSB_DP_LINK_M1, ironlake_debug_n),
DEFINEREG2(TRANSB_DP_LINK_N1, ironlake_debug_n),
DEFINEREG2(TRANSB_DP_LINK_M2, ironlake_debug_n),
DEFINEREG2(TRANSB_DP_LINK_N2, ironlake_debug_n),
DEFINEREG2(TRANS_HTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(TRANS_HBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_HSYNC_C, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
DEFINEREG(TRANS_VSYNCSHIFT_C),
DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),
DEFINEREG2(TRANSC_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(TRANSC_DATA_N2, ironlake_debug_n),
DEFINEREG2(TRANSC_DP_LINK_M1, ironlake_debug_n),
DEFINEREG2(TRANSC_DP_LINK_N1, ironlake_debug_n),
DEFINEREG2(TRANSC_DP_LINK_M2, ironlake_debug_n),
DEFINEREG2(TRANSC_DP_LINK_N2, ironlake_debug_n),
DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
DEFINEREG2(TRANSBCONF, ironlake_debug_transconf),
DEFINEREG2(TRANSCCONF, ironlake_debug_transconf),
DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl),
DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
DEFINEREG(DPAFE_BMFUNC),
DEFINEREG(DPAFE_DL_IREFCAL0),
DEFINEREG(DPAFE_DL_IREFCAL1),
DEFINEREG(DPAFE_DP_IREFCAL),
DEFINEREG(PCH_DSPCLK_GATE_D),
DEFINEREG(PCH_DSP_CHICKEN1),
DEFINEREG(PCH_DSP_CHICKEN2),
DEFINEREG(PCH_DSP_CHICKEN3),
DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG(FDI_RXA_TUSIZE1),
DEFINEREG(FDI_RXA_TUSIZE2),
DEFINEREG(FDI_RXB_TUSIZE1),
DEFINEREG(FDI_RXB_TUSIZE2),
DEFINEREG(FDI_RXC_TUSIZE1),
DEFINEREG(FDI_RXC_TUSIZE2),
DEFINEREG(FDI_PLL_CTL_1),
DEFINEREG(FDI_PLL_CTL_2),
DEFINEREG(FDI_RXA_IIR),
DEFINEREG(FDI_RXA_IMR),
DEFINEREG(FDI_RXB_IIR),
DEFINEREG(FDI_RXB_IMR),
DEFINEREG2(PCH_ADPA, i830_debug_adpa),
DEFINEREG2(HDMIB, ironlake_debug_hdmi),
DEFINEREG2(HDMIC, ironlake_debug_hdmi),
DEFINEREG2(HDMID, ironlake_debug_hdmi),
DEFINEREG2(PCH_LVDS, i830_debug_lvds),
DEFINEREG(CPU_eDP_A),
DEFINEREG(PCH_DP_B),
DEFINEREG(PCH_DP_C),
DEFINEREG(PCH_DP_D),
DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl),
DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl),
DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl),
DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
DEFINEREG(PCH_PP_ON_DELAYS),
DEFINEREG(PCH_PP_OFF_DELAYS),
DEFINEREG(PCH_PP_DIVISOR),
DEFINEREG2(PORT_DBG, ivb_debug_port),
DEFINEREG(RC6_RESIDENCY_TIME),
DEFINEREG(RC6p_RESIDENCY_TIME),
DEFINEREG(RC6pp_RESIDENCY_TIME),
};
//------------------------------------------------------------------------------
static struct reg_debug haswell_debug_regs[] = {
/* Power wells */
DEFINEREG(HSW_PWR_WELL_CTL1),
DEFINEREG(HSW_PWR_WELL_CTL2),
DEFINEREG(HSW_PWR_WELL_CTL3),
DEFINEREG(HSW_PWR_WELL_CTL4),
DEFINEREG(HSW_PWR_WELL_CTL5),
DEFINEREG(HSW_PWR_WELL_CTL6),
/* DDI pipe function */
DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
/* DP transport control */
DEFINEREG(DP_TP_CTL_A),
DEFINEREG(DP_TP_CTL_B),
DEFINEREG(DP_TP_CTL_C),
DEFINEREG(DP_TP_CTL_D),
DEFINEREG(DP_TP_CTL_E),
/* DP status */
DEFINEREG(DP_TP_STATUS_A),
DEFINEREG(DP_TP_STATUS_B),
DEFINEREG(DP_TP_STATUS_C),
DEFINEREG(DP_TP_STATUS_D),
DEFINEREG(DP_TP_STATUS_E),
/* DDI buffer control */
DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),
DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl),
DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl),
DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl),
DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl),
/* Clocks */
DEFINEREG(SPLL_CTL),
DEFINEREG(LCPLL_CTL),
DEFINEREG(WRPLL_CTL1),
DEFINEREG(WRPLL_CTL2),
/* DDI port clock control */
DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel),
DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel),
DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel),
DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel),
DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel),
/* Pipe clock control */
DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel),
DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
/* Fuses */
DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
/* Pipe A */
DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPASURF),
DEFINEREG2(DSPATILEOFF, i830_debug_xy),
/* Pipe B */
DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPBSURF),
DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
/* Pipe C */
DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPCSURF),
DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
/* Transcoder A */
DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_A),
DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
/* Transcoder B */
DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_B),
DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
/* Transcoder C */
DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_C),
DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
/* Transcoder EDP */
DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_EDP),
DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
/* CPU Panel fitter */
DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
/* LPT */
DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
DEFINEREG(TRANS_VSYNCSHIFT_A),
DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG(FDI_RXA_TUSIZE1),
DEFINEREG(FDI_RXA_IIR),
DEFINEREG(FDI_RXA_IMR),
DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
DEFINEREG2(BLC_PWM2_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
DEFINEREG2(BLC_PWM2_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
DEFINEREG2(BLC_MISC_CTL, hsw_debug_blc_misc_ctl),
DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
DEFINEREG2(UTIL_PIN_CTL, hsw_debug_util_pin_ctl),
DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
DEFINEREG(PCH_PP_ON_DELAYS),
DEFINEREG(PCH_PP_OFF_DELAYS),
DEFINEREG(PCH_PP_DIVISOR),
DEFINEREG(PIXCLK_GATE),
DEFINEREG2(SDEISR, hsw_debug_sinterrupt),
DEFINEREG(RC6_RESIDENCY_TIME)
};
//------------------------------------------------------------------------------
static struct reg_debug skylake_debug_regs[] = {
/* DDI pipe function */
DEFINEREG2(TRANS_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(TRANS_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(TRANS_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
DEFINEREG2(TRANS_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
};
//------------------------------------------------------------------------------
static struct reg_debug i945gm_mi_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(PGTBL_ER),
DEFINEREG(EXCC),
DEFINEREG(HWS_PGA),
DEFINEREG(IPEIR),
DEFINEREG(IPEHR),
DEFINEREG(INSTDONE),
DEFINEREG(NOP_ID),
DEFINEREG(HWSTAM),
DEFINEREG(SCPD0),
DEFINEREG(IER),
DEFINEREG(IIR),
DEFINEREG(IMR),
DEFINEREG(ISR),
DEFINEREG(EIR),
DEFINEREG(EMR),
DEFINEREG(ESR),
DEFINEREG(INST_PM),
DEFINEREG(ECOSKPD),
};
//------------------------------------------------------------------------------
// void AppleIntelInto::intel_dump_other_regs(void)
DEFINE_FUNC_VOID(AppleIntelInfo::intel_dump_other_regs)
{
int i;
int fp, dpll;
int disp_pipe;
int n, m1, m2, m, p1, p2;
int ref;
int dot;
int phase;
for (disp_pipe = 0; disp_pipe <= 1; disp_pipe++)
{
if (disp_pipe == 0)
{
fp = MMIO_READ32(FPA0);
dpll = MMIO_READ32(DPLL_A);
}
else
{
fp = MMIO_READ32(FPB0);
dpll = MMIO_READ32(DPLL_B);
}
if (IS_GEN2(devid))
{
uint32_t lvds = MMIO_READ32(LVDS);
if (devid == PCI_CHIP_I855_GM && (lvds & LVDS_PORT_EN) && (lvds & LVDS_PIPEB_SELECT) == (disp_pipe << 30))
{
if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
{
p2 = 7;
}
else
{
p2 = 14;
}
switch ((dpll >> 16) & 0x3f)
{
case 0x01:
p1 = 1;
break;
case 0x02:
p1 = 2;
break;
case 0x04:
p1 = 3;
break;
case 0x08:
p1 = 4;
break;
case 0x10:
p1 = 5;
break;
case 0x20:
p1 = 6;
break;
default:
p1 = 1;
IOLOG("LVDS P1 0x%x invalid encoding\n", (dpll >> 16) & 0x3f);
break;
}
}
else
{
if (dpll & (1 << 23))
{
p2 = 4;
}
else
{
p2 = 2;
}
if (dpll & PLL_P1_DIVIDE_BY_TWO)
{
p1 = 2;
}
else
{
p1 = ((dpll >> 16) & 0x3f) + 2;
}
}
switch ((dpll >> 13) & 0x3)
{
case 0:
ref = 48000;
break;
case 3:
ref = 66000;
break;
default:
ref = 0;
IOLOG("ref out of range\n");
break;
}
}
else
{
uint32_t lvds = MMIO_READ32(LVDS);
if ((lvds & LVDS_PORT_EN) && (lvds & LVDS_PIPEB_SELECT) == (disp_pipe << 30))
{
if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
{
p2 = 7;
}
else
{
p2 = 14;
}
}
else
{
switch ((dpll >> 24) & 0x3)
{
case 0:
p2 = 10;
break;
case 1:
p2 = 5;
break;
default:
p2 = 1;
IOLOG("p2 out of range\n");
break;
}
}
if (IS_IGD(devid))
{
i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD) & 0x1ff;
}
else
{
i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT) & 0xff;
}
switch (i)
{
case 1:
p1 = 1;
break;
case 2:
p1 = 2;
break;
case 4:
p1 = 3;
break;
case 8:
p1 = 4;
break;
case 16:
p1 = 5;
break;
case 32:
p1 = 6;
break;
case 64:
p1 = 7;
break;
case 128:
p1 = 8;
break;
case 256:
if (IS_IGD(devid))
{
p1 = 9;
break;
} // fallback
default:
p1 = 1;
IOLOG("p1 out of range\n");
break;
}
switch ((dpll >> 13) & 0x3)
{
case 0:
ref = 96000;
break;
case 3:
ref = 100000;
break;
default:
ref = 0;
IOLOG("ref out of range\n");
break;
}
}
if (IS_965(devid))
{
phase = (dpll >> 9) & 0xf;
switch (phase)
{
case 6:
break;
default:
IOLOG("SDVO phase shift %d out of range -- probably not an issue.\n", phase);
break;
}
}
switch ((dpll >> 8) & 1)
{
case 0:
break;
default:
IOLOG("fp select out of range\n");
break;
}
m1 = ((fp >> 8) & 0x3f);
if (IS_IGD(devid))
{
n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
m = m2 + 2;
dot = (ref * m) / n / (p1 * p2);
}
else
{
n = ((fp >> 16) & 0x3f);
m2 = ((fp >> 0) & 0x3f);
//m = 5 * (m1 + 2) + (m2 + 2);
dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
}
IOLOG("pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n", disp_pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2);
}
}
//------------------------------------------------------------------------------
// void AppleIntelInfo::dumpRegisters(struct reg_debug *regs, uint32_t count)
DEFINE_FUNC_DUMP(AppleIntelInfo::dumpRegisters)
{
char name[30];
char debug[1024];
for (int i = 0; i < count; i++)
{
UInt32 val = MMIO_READ32((UInt64)regs[i].reg);
memset(name, 0, 30);
memset(debug, 0, 1024);
memcpy(name, regs[i].name, strlen(regs[i].name));
// "123456789 123456789 1234567"
strncat(name, "...........................", (27 - strlen(regs[i].name)));
if (regs[i].debug_output != NULL)
{
regs[i].debug_output(debug, sizeof(debug), regs[i].reg, val);
IOLOG("%s: 0x%08x (%s)\n", name, val, debug);
}
else
{
IOLOG("%s: 0x%08x\n", name, val);
}
}
}
//------------------------------------------------------------------------------
// void AppleIntelInfo::getPCHDeviceID(void)
DEFINE_FUNC_VOID(AppleIntelInfo::getPCHDeviceID)
{
outl(0xcf8, 0x8000F800);
UInt64 pch_device = inl(0xcfc);
IOLOG("PCH device.................: 0x%llX\n", pch_device);
if ((pch_device & 0x0000ffff) == 0x8086)
{
switch ((pch_device & 0xff000000))
{
case 0x3b000000:
intel_pch = PCH_IBX;
break;
case 0x1c000000:
case 0x1e000000:
intel_pch = PCH_CPT;
break;
case 0x8c000000:
case 0x9c000000:
intel_pch = PCH_LPT;
break;
default:
intel_pch = PCH_NONE;
}
}
}
//------------------------------------------------------------------------------
// void AppleIntelInfo::reportIntelRegs(void)
DEFINE_FUNC_VOID(AppleIntelInfo::reportIntelRegs)
{
getPCHDeviceID();
outl(0xcf8, 0x80001010);
UInt64 mmio = (inl(0xcfc) & 0x7FFFC00000); // mask bits 38-22
IOPhysicalAddress address = (IOPhysicalAddress)(mmio);
// 16 MB combined for MMIO and Global GTT table aperture (2MB for MMIO, 6MB reserved and 8MB for GTT).
IOMemoryDescriptor * memDescriptor = IOMemoryDescriptor::withPhysicalAddress(address, 0x1000000, kIODirectionInOut);
if (memDescriptor != NULL)
{
IOReturn result = memDescriptor->prepare();
if (result == kIOReturnSuccess)
{
IOMemoryMap * memoryMap = memDescriptor->map();
if (memoryMap != NULL)
{
int64_t mmio = memoryMap->getVirtualAddress();
gMMIOAddress = mmio;
IOLOG("\nIntel Register Data\n------------------------------------\nCPU_VGACNTRL...............: 0x%X\n", MMIO_READ32(CPU_VGACNTRL));
if (IS_SKYLAKE(devid))
{
IOLOG("IS_SKYLAKE(devid)\n");
intel_dump_regs(haswell_debug_regs);
intel_dump_regs(skylake_debug_regs);
}
else if (IS_HASWELL(devid) || IS_BROADWELL(devid))
{
IOLOG("IS_HASWELL(devid) || IS_BROADWELL(devid)\n");
intel_dump_regs(haswell_debug_regs);
}
else if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid))
{
IOLOG("IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)\n");
intel_dump_regs(ironlake_debug_regs);
}
else if (IS_945GM(devid))
{
IOLOG("IS_945GM(devid)\n");
intel_dump_regs(i945gm_mi_regs);
intel_dump_regs(intel_debug_regs);
intel_dump_other_regs();
}
else
{
IOLOG("IS_ELSE(devid)\n");
intel_dump_regs(intel_debug_regs);
intel_dump_other_regs();
}
if (IS_GEN6(devid) || IS_GEN7(devid))
{
IOLOG("IS_GEN6(devid) || IS_GEN7(devid)\n");
intel_dump_regs(gen6_fences);
intel_dump_regs(gen6_rp_debug_regs);
}
memoryMap->release();
memoryMap = NULL;
}
}
memDescriptor->release();
memDescriptor = NULL;
}
}
================================================
FILE: AppleIntelRegisterDumper/intel_chipset.h
================================================
/*
* Copyright © 2007 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifndef _INTEL_CHIPSET_H
#define _INTEL_CHIPSET_H
UInt8 intel_pch = 0;
enum pch_type {
PCH_NONE,
PCH_IBX,
PCH_CPT,
PCH_LPT,
};
#define HAS_IBX (intel_pch == PCH_IBX)
#define HAS_CPT (intel_pch == PCH_CPT)
#define HAS_LPT (intel_pch == PCH_LPT)
/* Exclude chipset #defines, they just add noise */
#ifndef __GTK_DOC_IGNORE__
#define PCI_CHIP_I810 0x7121
#define PCI_CHIP_I810_DC100 0x7123
#define PCI_CHIP_I810_E 0x7125
#define PCI_CHIP_I815 0x1132
#define PCI_CHIP_I830_M 0x3577
#define PCI_CHIP_845_G 0x2562
#define PCI_CHIP_I855_GM 0x3582
#define PCI_CHIP_I865_G 0x2572
#define PCI_CHIP_I915_G 0x2582
#define PCI_CHIP_E7221_G 0x258A
#define PCI_CHIP_I915_GM 0x2592
#define PCI_CHIP_I945_G 0x2772
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_Q35_G 0x29B2
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_Q33_G 0x29D2
#define PCI_CHIP_IGD_GM 0xA011
#define PCI_CHIP_IGD_G 0xA001
#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_GM45_GM 0x2A42
#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_Q45_G 0x2E12
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G41_G 0x2E32
#define PCI_CHIP_ILD_G 0x0042
#define PCI_CHIP_ILM_G 0x0046
#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
#define PCI_CHIP_HASWELL_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
#define PCI_CHIP_HASWELL_S_GT3 0x042A
#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
#define PCI_CHIP_HASWELL_B_GT2 0x041B
#define PCI_CHIP_HASWELL_B_GT3 0x042B
#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
#define PCI_CHIP_HASWELL_E_GT2 0x041E
#define PCI_CHIP_HASWELL_E_GT3 0x042E
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
#define BDW_SPARE 0x2
#define BDW_ULT 0x6
#define BDW_IRIS 0xb
#define BDW_SERVER 0xa
#define BDW_WORKSTATION 0xd
#define BDW_ULX 0xe
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
#define PCI_CHIP_VALLEYVIEW_2 0x0f32
#define PCI_CHIP_VALLEYVIEW_3 0x0f33
#define PCI_CHIP_CHERRYVIEW_0 0x22b0
#define PCI_CHIP_CHERRYVIEW_1 0x22b1
#define PCI_CHIP_CHERRYVIEW_2 0x22b2
#define PCI_CHIP_CHERRYVIEW_3 0x22b3
#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
#define PCI_CHIP_BROXTON_0 0x0A84
#define PCI_CHIP_BROXTON_1 0x1A84
#define PCI_CHIP_BROXTON_2 0x5A84
#endif /* __GTK_DOC_IGNORE__ */
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
(devid) == PCI_CHIP_I945_GME || \
(devid) == PCI_CHIP_I965_GM || \
(devid) == PCI_CHIP_I965_GME || \
(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
(devid) == PCI_CHIP_Q45_G || \
(devid) == PCI_CHIP_G45_G || \
(devid) == PCI_CHIP_G41_G)
#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
(devid) == PCI_CHIP_E7221_G || \
(devid) == PCI_CHIP_I915_GM)
#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
(devid) == PCI_CHIP_I945_GME)
#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
(devid) == PCI_CHIP_I945_GM || \
(devid) == PCI_CHIP_I945_GME || \
IS_G33(devid))
#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
(devid) == PCI_CHIP_Q33_G || \
(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
(devid) == PCI_CHIP_845_G || \
(devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I865_G)
#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
(devid) == PCI_CHIP_I965_Q || \
(devid) == PCI_CHIP_I965_G_1 || \
(devid) == PCI_CHIP_I965_GM || \
(devid) == PCI_CHIP_I965_GME || \
(devid) == PCI_CHIP_I946_GZ || \
IS_G4X(devid))
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
(devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
(devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
(devid) == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
IS_HASWELL(devid) || \
IS_VALLEYVIEW(devid))
#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
(devid) == PCI_CHIP_IVYBRIDGE_S || \
(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
(devid) == PCI_CHIP_VALLEYVIEW_1 || \
(devid) == PCI_CHIP_VALLEYVIEW_2 || \
(devid) == PCI_CHIP_VALLEYVIEW_3)
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
(devid) == PCI_CHIP_HASWELL_B_GT1 || \
(devid) == PCI_CHIP_HASWELL_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
(devid) == PCI_CHIP_HASWELL_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_B_GT2 || \
(devid) == PCI_CHIP_HASWELL_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
(devid) == PCI_CHIP_HASWELL_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_S_GT3 || \
(devid) == PCI_CHIP_HASWELL_B_GT3 || \
(devid) == PCI_CHIP_HASWELL_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid) || \
IS_HSW_GT3(devid))
#define IS_BROADWELL(devid) ((((devid) & 0xff00) != 0x1600) ? 0 : \
((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
(((devid) & 0x000f) == BDW_SPARE) ? 1 : \
(((devid) & 0x000f) == BDW_ULT) ? 1 : \
(((devid) & 0x000f) == BDW_IRIS) ? 1 : \
(((devid) & 0x000f) == BDW_SERVER) ? 1 : \
(((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
(((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
(devid) == PCI_CHIP_CHERRYVIEW_1 || \
(devid) == PCI_CHIP_CHERRYVIEW_2 || \
(devid) == PCI_CHIP_CHERRYVIEW_3)
#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
IS_CHERRYVIEW(devid))
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
(devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
(devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
IS_SKL_GT2(devid) || \
IS_SKL_GT3(devid))
#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
(devid) == PCI_CHIP_BROXTON_1 || \
(devid) == PCI_CHIP_BROXTON_2)
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid))
#define IS_965(devid) (IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
IS_GEN8(devid))
#define IS_9XX(devid) (IS_GEN3(devid) || \
IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
IS_GEN8(devid) || \
IS_GEN9(devid))
#define IS_INTEL(devid) (IS_GEN2(devid) || \
IS_GEN3(devid) || \
IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
IS_GEN8(devid))
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
IS_BROADWELL(devid) || \
IS_SKYLAKE(devid))
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
IS_GEN7(devid) || \
IS_GEN8(devid))
#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
IS_GEN8(devid))
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
(devid) == PCI_CHIP_I965_G_1 || \
(devid) == PCI_CHIP_I965_Q || \
(devid) == PCI_CHIP_I965_G)
#define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
(devid) == PCI_CHIP_I965_GME)
#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
#endif /* _INTEL_CHIPSET_H */
================================================
FILE: AppleIntelRegisterDumper/intel_reg.h
================================================
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */
/**************************************************************************
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/** @file
* Register names and fields for Intel graphics.
*/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
* Eric Anholt <eric@anholt.net>
*
* based on the i740 driver by
* Kevin E. Martin <kevin@precisioninsight.com>
*
*/
#ifndef _I810_REG_H
#define _I810_REG_H
/* I/O register offsets
*/
#define SRX 0x3C4 /* p208 */
#define GRX 0x3CE /* p213 */
#define ARX 0x3C0 /* p224 */
/* VGA Color Palette Registers */
#define DACMASK 0x3C6 /* p232 */
#define DACSTATE 0x3C7 /* p232 */
#define DACRX 0x3C7 /* p233 */
#define DACWX 0x3C8 /* p233 */
#define DACDATA 0x3C9 /* p233 */
/* CRT Controller Registers (CRX) */
#define START_ADDR_HI 0x0C /* p246 */
#define START_ADDR_LO 0x0D /* p247 */
#define VERT_SYNC_END 0x11 /* p249 */
#define EXT_VERT_TOTAL 0x30 /* p257 */
#define EXT_VERT_DISPLAY 0x31 /* p258 */
#define EXT_VERT_SYNC_START 0x32 /* p259 */
#define EXT_VERT_BLANK_START 0x33 /* p260 */
#define EXT_HORIZ_TOTAL 0x35 /* p261 */
#define EXT_HORIZ_BLANK 0x39 /* p261 */
#define EXT_START_ADDR 0x40 /* p262 */
#define EXT_START_ADDR_ENABLE 0x80
#define EXT_OFFSET 0x41 /* p263 */
#define EXT_START_ADDR_HI 0x42 /* p263 */
#define INTERLACE_CNTL 0x70 /* p264 */
#define INTERLACE_ENABLE 0x80
#define INTERLACE_DISABLE 0x00
/* Miscellaneous Output Register
*/
#define MSR_R 0x3CC /* p207 */
#define MSR_W 0x3C2 /* p207 */
#define IO_ADDR_SELECT 0x01
#define MDA_BASE 0x3B0 /* p207 */
#define CGA_BASE 0x3D0 /* p207 */
/* CR80 - IO Control, p264
*/
#define IO_CTNL 0x80
#define EXTENDED_ATTR_CNTL 0x02
#define EXTENDED_CRTC_CNTL 0x01
/* GR10 - Address mapping, p221
*/
#define ADDRESS_MAPPING 0x10
#define PAGE_TO_LOCAL_MEM_ENABLE 0x10
#define GTT_MEM_MAP_ENABLE 0x08
#define PACKED_MODE_ENABLE 0x04
#define LINEAR_MODE_ENABLE 0x02
#define PAGE_MAPPING_ENABLE 0x01
#define HOTKEY_VBIOS_SWITCH_BLOCK 0x80
#define HOTKEY_SWITCH 0x20
#define HOTKEY_TOGGLE 0x10
/* Blitter control, p378
*/
#define BITBLT_CNTL 0x7000c
#define COLEXP_MODE 0x30
#define COLEXP_8BPP 0x00
#define COLEXP_16BPP 0x10
#define COLEXP_24BPP 0x20
#define COLEXP_RESERVED 0x30
#define BITBLT_STATUS 0x01
#define CHDECMISC 0x10111
#define DCC 0x10200
#define C0DRB0 0x10200
#define C0DRB1 0x10202
#define C0DRB2 0x10204
#define C0DRB3 0x10206
#define C0DRA01 0x10208
#define C0DRA23 0x1020a
#define C1DRB0 0x10600
#define C1DRB1 0x10602
#define C1DRB2 0x10604
#define C1DRB3 0x10606
#define C1DRA01 0x10608
#define C1DRA23 0x1060a
/* p375.
*/
#define DISPLAY_CNTL 0x70008
#define VGA_WRAP_MODE 0x02
#define VGA_WRAP_AT_256KB 0x00
#define VGA_NO_WRAP 0x02
#define GUI_MODE 0x01
#define STANDARD_VGA_MODE 0x00
#define HIRES_MODE 0x01
/* p375
*/
#define PIXPIPE_CONFIG_0 0x70009
#define DAC_8_BIT 0x80
#define DAC_6_BIT 0x00
#define HW_CURSOR_ENABLE 0x10
#define EXTENDED_PALETTE 0x01
/* p375
*/
#define PIXPIPE_CONFIG_1 0x7000a
#define DISPLAY_COLOR_MODE 0x0F
#define DISPLAY_VGA_MODE 0x00
#define DISPLAY_8BPP_MODE 0x02
#define DISPLAY_15BPP_MODE 0x04
#define DISPLAY_16BPP_MODE 0x05
#define DISPLAY_24BPP_MODE 0x06
#define DISPLAY_32BPP_MODE 0x07
/* p375
*/
#define PIXPIPE_CONFIG_2 0x7000b
#define DISPLAY_GAMMA_ENABLE 0x08
#define DISPLAY_GAMMA_DISABLE 0x00
#define OVERLAY_GAMMA_ENABLE 0x04
#define OVERLAY_GAMMA_DISABLE 0x00
/* p380
*/
#define DISPLAY_BASE 0x70020
#define DISPLAY_BASE_MASK 0x03fffffc
/* Cursor control registers, pp383-384
*/
/* Desktop (845G, 865G) */
#define CURSOR_CONTROL 0x70080
#define CURSOR_ENABLE 0x80000000
#define CURSOR_GAMMA_ENABLE 0x40000000
#define CURSOR_STRIDE_MASK 0x30000000
#define CURSOR_FORMAT_SHIFT 24
#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
/* Mobile and i810 */
#define CURSOR_A_CONTROL CURSOR_CONTROL
#define CURSOR_ORIGIN_SCREEN 0x00 /* i810 only */
#define CURSOR_ORIGIN_DISPLAY 0x1 /* i810 only */
#define CURSOR_MODE 0x27
#define CURSOR_MODE_DISABLE 0x00
#define CURSOR_MODE_32_4C_AX 0x01 /* i810 only */
#
gitextract_6thlbe9e/ ├── .gitignore ├── AppleIntelInfo/ │ ├── AppleIntelInfo-Info.plist │ ├── AppleIntelInfo-Prefix.pch │ ├── AppleIntelInfo.cpp │ ├── AppleIntelInfo.h │ ├── essentials.h │ └── intel_family.h ├── AppleIntelInfo.xcodeproj/ │ └── project.pbxproj ├── AppleIntelRegisterDumper/ │ ├── AppleIntelRegisterDumper.h │ ├── intel_chipset.h │ └── intel_reg.h └── README.md
SYMBOL INDEX (80 symbols across 5 files)
FILE: AppleIntelInfo/AppleIntelInfo.cpp
type vnode (line 24) | struct vnode
function getCStates (line 1202) | inline void getCStates(void *magic)
function IOReturn (line 1242) | IOReturn AppleIntelInfo::loopTimerEvent(void)
function IOService (line 1449) | IOService* AppleIntelInfo::probe(IOService *provider, SInt32 *score)
FILE: AppleIntelInfo/AppleIntelInfo.h
function outl (line 152) | static __inline__ void outl(UInt16 port, UInt32 value)
function inb (line 159) | static __inline__ unsigned char inb(UInt16 port)
function inl (line 168) | static __inline__ unsigned int inl(UInt16 port)
function UInt8 (line 177) | UInt8 ReadPci8(UInt8 Bus, UInt8 Dev, UInt8 Fun, UInt16 Reg)
function class (line 195) | class AppleIntelInfo : public IOService
FILE: AppleIntelRegisterDumper/AppleIntelRegisterDumper.h
type reg_debug (line 50) | struct reg_debug
function DEBUGSTRING (line 60) | DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
function DEBUGSTRING (line 174) | DEBUGSTRING(hsw_debug_ddi_buf_ctl)
function DEBUGSTRING (line 204) | DEBUGSTRING(hsw_debug_port_clk_sel)
function DEBUGSTRING (line 241) | DEBUGSTRING(hsw_debug_pipe_clk_sel)
function DEBUGSTRING (line 272) | DEBUGSTRING(hsw_debug_sfuse_strap)
function DEBUGSTRING (line 290) | DEBUGSTRING(i830_debug_yxminus1)
function DEBUGSTRING (line 297) | DEBUGSTRING(i830_debug_dspcntr)
function DEBUGSTRING (line 314) | DEBUGSTRING(ironlake_debug_dspstride)
function DEBUGSTRING (line 321) | DEBUGSTRING(i830_debug_xyminus1)
function DEBUGSTRING (line 328) | DEBUGSTRING(i830_debug_xy)
function DEBUGSTRING (line 335) | DEBUGSTRING(i830_debug_pipeconf)
function DEBUGSTRING (line 486) | DEBUGSTRING(i830_debug_hvtotal)
function DEBUGSTRING (line 493) | DEBUGSTRING(i830_debug_hvsyncblank)
function DEBUGSTRING (line 500) | DEBUGSTRING(ironlake_debug_m_tu)
function DEBUGSTRING (line 507) | DEBUGSTRING(ironlake_debug_n)
function DEBUGSTRING (line 514) | DEBUGSTRING(ironlake_debug_panel_fitting)
function DEBUGSTRING (line 567) | DEBUGSTRING(ironlake_debug_panel_fitting_2)
function DEBUGSTRING (line 574) | DEBUGSTRING(ironlake_debug_panel_fitting_3)
function DEBUGSTRING (line 581) | DEBUGSTRING(ironlake_debug_panel_fitting_4)
function DEBUGSTRING (line 588) | DEBUGSTRING(ironlake_debug_pf_win)
function DEBUGSTRING (line 598) | DEBUGSTRING(ironlake_debug_transconf)
function DEBUGSTRING (line 631) | DEBUGSTRING(ironlake_debug_fdi_rx_misc)
function DEBUGSTRING (line 638) | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2)
function DEBUGSTRING (line 691) | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl)
function DEBUGSTRING (line 711) | DEBUGSTRING(ibx_debug_blc_pwm_ctl1)
function DEBUGSTRING (line 725) | DEBUGSTRING(ibx_debug_blc_pwm_ctl2)
function DEBUGSTRING (line 737) | DEBUGSTRING(hsw_debug_blc_misc_ctl)
function DEBUGSTRING (line 748) | DEBUGSTRING(hsw_debug_util_pin_ctl)
function DEBUGSTRING (line 801) | DEBUGSTRING(i830_debug_pp_status)
function DEBUGSTRING (line 825) | DEBUGSTRING(ilk_debug_pp_control)
function DEBUGSTRING (line 835) | DEBUGSTRING(hsw_debug_sinterrupt)
function DEBUGSTRING (line 849) | DEBUGSTRING(i830_debug_vgacntrl)
function DEBUGSTRING (line 856) | DEBUGSTRING(ironlake_debug_rr_hw_ctl)
function DEBUGSTRING (line 863) | DEBUGSTRING(ironlake_debug_dref_ctl)
function DEBUGSTRING (line 898) | DEBUGSTRING(ironlake_debug_rawclk_freq)
function DEBUGSTRING (line 937) | DEBUGSTRING(snb_debug_dpll_sel)
function DEBUGSTRING (line 986) | DEBUGSTRING(ironlake_debug_pch_dpll)
function DEBUGSTRING (line 1054) | DEBUGSTRING(i830_debug_fp)
function DEBUGSTRING (line 1072) | DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
function DEBUGSTRING (line 1184) | DEBUGSTRING(ironlake_debug_fdi_rx_ctl)
function DEBUGSTRING (line 1277) | DEBUGSTRING(i830_debug_adpa)
function DEBUGSTRING (line 1301) | DEBUGSTRING(ironlake_debug_hdmi)
function DEBUGSTRING (line 1394) | DEBUGSTRING(i830_debug_lvds)
function DEBUGSTRING (line 1429) | DEBUGSTRING(snb_debug_trans_dp_ctl)
function DEBUGSTRING (line 1500) | DEBUGSTRING(ivb_debug_port)
function DEBUGSTRING (line 1522) | DEBUGSTRING(i830_16bit_func)
function DEBUGSTRING (line 1529) | DEBUGSTRING(i830_debug_dcc)
function DEBUGSTRING (line 1572) | DEBUGSTRING(i830_debug_chdecmisc)
function DEBUGSTRING (line 1605) | DEBUGSTRING(i830_debug_vga_pd)
function DEBUGSTRING (line 1638) | DEBUGSTRING(i830_debug_dpll_test)
function DEBUGSTRING (line 1652) | DEBUGSTRING(i830_debug_dspclk_gate_d)
function DEBUGSTRING (line 1698) | DEBUGSTRING(i830_debug_sdvo)
function DEBUGSTRING (line 1721) | DEBUGSTRING(i830_debug_dvo)
function DEBUGSTRING (line 1750) | DEBUGSTRING(i830_debug_pp_control)
function DEBUGSTRING (line 1757) | DEBUGSTRING(i830_debug_dspstride)
function DEBUGSTRING (line 1764) | DEBUGSTRING(i830_debug_pipestat)
function DEBUGSTRING (line 1846) | DEBUGSTRING(i830_debug_dpll)
function DEBUGSTRING (line 1955) | DEBUGSTRING(i810_debug_915_fence)
function DEBUGSTRING (line 1984) | DEBUGSTRING(i810_debug_965_fence_start)
function DEBUGSTRING (line 1999) | DEBUGSTRING(i810_debug_965_fence_end)
function DEBUGSTRING (line 2011) | DEBUGSTRING(gen6_rp_control)
type reg_debug (line 2018) | struct reg_debug
type reg_debug (line 2059) | struct reg_debug
type reg_debug (line 2085) | struct reg_debug
type reg_debug (line 2350) | struct reg_debug
type reg_debug (line 2617) | struct reg_debug
type reg_debug (line 2805) | struct reg_debug
type reg_debug (line 2815) | struct reg_debug
FILE: AppleIntelRegisterDumper/intel_chipset.h
type pch_type (line 33) | enum pch_type {
FILE: AppleIntelRegisterDumper/intel_reg.h
type DisplayType (line 2564) | typedef enum {
Condensed preview — 12 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (339K chars).
[
{
"path": ".gitignore",
"chars": 161,
"preview": ".DS_Store\n.git\n\nxcuserdata\nproject.xcworkspace\n\n/AppleIntelInfo/AppleIntelInfo.xcodeproj/xcuserdata\n/AppleIntelInfo/Appl"
},
{
"path": "AppleIntelInfo/AppleIntelInfo-Info.plist",
"chars": 1933,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!DOCTYPE plist PUBLIC \"-//Apple//DTD PLIST 1.0//EN\" \"http://www.apple.com/DTDs/P"
},
{
"path": "AppleIntelInfo/AppleIntelInfo-Prefix.pch",
"chars": 121,
"preview": "//\n// Prefix header\n//\n// The contents of this file are implicitly included at the beginning of every source file.\n//\n"
},
{
"path": "AppleIntelInfo/AppleIntelInfo.cpp",
"chars": 62289,
"preview": "/*\n * Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.\n *\n * Original idea and initial development of MSRDump"
},
{
"path": "AppleIntelInfo/AppleIntelInfo.h",
"chars": 8569,
"preview": "/*\n * Copyright (c) 2012-2017 Pike R. Alpha. All rights reserved.\n *\n * Original idea and initial development of MSRDump"
},
{
"path": "AppleIntelInfo/essentials.h",
"chars": 6605,
"preview": "/*\n * This work is licensed under the Creative Commons Attribution-NonCommercial\n * 4.0 Unported License => http://creat"
},
{
"path": "AppleIntelInfo/intel_family.h",
"chars": 2420,
"preview": "#ifndef _ASM_X86_INTEL_FAMILY_H\n#define _ASM_X86_INTEL_FAMILY_H\n\n/*\n * \"Big Core\" Processors (Branded as Core, Xeon, etc"
},
{
"path": "AppleIntelInfo.xcodeproj/project.pbxproj",
"chars": 13954,
"preview": "// !$*UTF8*$!\n{\n\tarchiveVersion = 1;\n\tclasses = {\n\t};\n\tobjectVersion = 46;\n\tobjects = {\n\n/* Begin PBXBuildFile section *"
},
{
"path": "AppleIntelRegisterDumper/AppleIntelRegisterDumper.h",
"chars": 80190,
"preview": "\n/*\n * Copyright © 2006,2009 Intel Corporation\n *\n * Permission is hereby granted, free of charge, to any person obtaini"
},
{
"path": "AppleIntelRegisterDumper/intel_chipset.h",
"chars": 16104,
"preview": "/*\n * Copyright © 2007 Intel Corporation\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n "
},
{
"path": "AppleIntelRegisterDumper/intel_reg.h",
"chars": 115407,
"preview": "/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */\n/*********"
},
{
"path": "README.md",
"chars": 1212,
"preview": "AppleIntelInfo.kext\n===================\n\nWhat do I need to do?\n\nStep 1.) Download the project from Github and compile it"
}
]
About this extraction
This page contains the full source code of the Piker-Alpha/AppleIntelInfo GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 12 files (301.7 KB), approximately 109.2k tokens, and a symbol index with 80 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.