Repository: WangXuan95/FPGA-UART Branch: master Commit: 8feacde6d15c Files: 10 Total size: 122.5 KB Directory structure: gitextract_3850cu_c/ ├── LICENSE ├── README.md ├── RTL/ │ ├── uart2axi4.v │ ├── uart_rx.v │ └── uart_tx.v └── SIM/ ├── tb_axis_inc_source.v ├── tb_uart.v ├── tb_uart2axi4.v ├── tb_uart2axi4_run_iverilog.bat └── tb_uart_run_iverilog.bat ================================================ FILE CONTENTS ================================================ ================================================ FILE: LICENSE ================================================ GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc. Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The GNU General Public License is a free, copyleft license for software and other kinds of works. The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program--to make sure it remains free software for all its users. We, the Free Software Foundation, use the GNU General Public License for most of our software; it applies also to any other work released this way by its authors. You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for them if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs, and that you know you can do these things. To protect your rights, we need to prevent others from denying you these rights or asking you to surrender the rights. Therefore, you have certain responsibilities if you distribute copies of the software, or if you modify it: responsibilities to respect the freedom of others. For example, if you distribute copies of such a program, whether gratis or for a fee, you must pass on to the recipients the same freedoms that you received. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. Developers that use the GNU GPL protect your rights with two steps: (1) assert copyright on the software, and (2) offer you this License giving you legal permission to copy, distribute and/or modify it. For the developers' and authors' protection, the GPL clearly explains that there is no warranty for this free software. For both users' and authors' sake, the GPL requires that modified versions be marked as changed, so that their problems will not be attributed erroneously to authors of previous versions. Some devices are designed to deny users access to install or run modified versions of the software inside them, although the manufacturer can do so. This is fundamentally incompatible with the aim of protecting users' freedom to change the software. The systematic pattern of such abuse occurs in the area of products for individuals to use, which is precisely where it is most unacceptable. Therefore, we have designed this version of the GPL to prohibit the practice for those products. If such problems arise substantially in other domains, we stand ready to extend this provision to those domains in future versions of the GPL, as needed to protect the freedom of users. Finally, every program is threatened constantly by software patents. States should not allow patents to restrict development and use of software on general-purpose computers, but in those that do, we wish to avoid the special danger that patents applied to a free program could make it effectively proprietary. To prevent this, the GPL assures that patents cannot be used to render the program non-free. The precise terms and conditions for copying, distribution and modification follow. TERMS AND CONDITIONS 0. Definitions. "This License" refers to version 3 of the GNU General Public License. "Copyright" also means copyright-like laws that apply to other kinds of works, such as semiconductor masks. "The Program" refers to any copyrightable work licensed under this License. Each licensee is addressed as "you". "Licensees" and "recipients" may be individuals or organizations. To "modify" a work means to copy from or adapt all or part of the work in a fashion requiring copyright permission, other than the making of an exact copy. The resulting work is called a "modified version" of the earlier work or a work "based on" the earlier work. A "covered work" means either the unmodified Program or a work based on the Program. To "propagate" a work means to do anything with it that, without permission, would make you directly or secondarily liable for infringement under applicable copyright law, except executing it on a computer or modifying a private copy. Propagation includes copying, distribution (with or without modification), making available to the public, and in some countries other activities as well. To "convey" a work means any kind of propagation that enables other parties to make or receive copies. Mere interaction with a user through a computer network, with no transfer of a copy, is not conveying. An interactive user interface displays "Appropriate Legal Notices" to the extent that it includes a convenient and prominently visible feature that (1) displays an appropriate copyright notice, and (2) tells the user that there is no warranty for the work (except to the extent that warranties are provided), that licensees may convey the work under this License, and how to view a copy of this License. If the interface presents a list of user commands or options, such as a menu, a prominent item in the list meets this criterion. 1. Source Code. The "source code" for a work means the preferred form of the work for making modifications to it. "Object code" means any non-source form of a work. A "Standard Interface" means an interface that either is an official standard defined by a recognized standards body, or, in the case of interfaces specified for a particular programming language, one that is widely used among developers working in that language. The "System Libraries" of an executable work include anything, other than the work as a whole, that (a) is included in the normal form of packaging a Major Component, but which is not part of that Major Component, and (b) serves only to enable use of the work with that Major Component, or to implement a Standard Interface for which an implementation is available to the public in source code form. A "Major Component", in this context, means a major essential component (kernel, window system, and so on) of the specific operating system (if any) on which the executable work runs, or a compiler used to produce the work, or an object code interpreter used to run it. The "Corresponding Source" for a work in object code form means all the source code needed to generate, install, and (for an executable work) run the object code and to modify the work, including scripts to control those activities. However, it does not include the work's System Libraries, or general-purpose tools or generally available free programs which are used unmodified in performing those activities but which are not part of the work. For example, Corresponding Source includes interface definition files associated with source files for the work, and the source code for shared libraries and dynamically linked subprograms that the work is specifically designed to require, such as by intimate data communication or control flow between those subprograms and other parts of the work. The Corresponding Source need not include anything that users can regenerate automatically from other parts of the Corresponding Source. The Corresponding Source for a work in source code form is that same work. 2. Basic Permissions. All rights granted under this License are granted for the term of copyright on the Program, and are irrevocable provided the stated conditions are met. This License explicitly affirms your unlimited permission to run the unmodified Program. The output from running a covered work is covered by this License only if the output, given its content, constitutes a covered work. This License acknowledges your rights of fair use or other equivalent, as provided by copyright law. You may make, run and propagate covered works that you do not convey, without conditions so long as your license otherwise remains in force. You may convey covered works to others for the sole purpose of having them make modifications exclusively for you, or provide you with facilities for running those works, provided that you comply with the terms of this License in conveying all material for which you do not control copyright. Those thus making or running the covered works for you must do so exclusively on your behalf, under your direction and control, on terms that prohibit them from making any copies of your copyrighted material outside their relationship with you. Conveying under any other circumstances is permitted solely under the conditions stated below. Sublicensing is not allowed; section 10 makes it unnecessary. 3. Protecting Users' Legal Rights From Anti-Circumvention Law. No covered work shall be deemed part of an effective technological measure under any applicable law fulfilling obligations under article 11 of the WIPO copyright treaty adopted on 20 December 1996, or similar laws prohibiting or restricting circumvention of such measures. When you convey a covered work, you waive any legal power to forbid circumvention of technological measures to the extent such circumvention is effected by exercising rights under this License with respect to the covered work, and you disclaim any intention to limit operation or modification of the work as a means of enforcing, against the work's users, your or third parties' legal rights to forbid circumvention of technological measures. 4. Conveying Verbatim Copies. You may convey verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice; keep intact all notices stating that this License and any non-permissive terms added in accord with section 7 apply to the code; keep intact all notices of the absence of any warranty; and give all recipients a copy of this License along with the Program. You may charge any price or no price for each copy that you convey, and you may offer support or warranty protection for a fee. 5. Conveying Modified Source Versions. You may convey a work based on the Program, or the modifications to produce it from the Program, in the form of source code under the terms of section 4, provided that you also meet all of these conditions: a) The work must carry prominent notices stating that you modified it, and giving a relevant date. b) The work must carry prominent notices stating that it is released under this License and any conditions added under section 7. This requirement modifies the requirement in section 4 to "keep intact all notices". c) You must license the entire work, as a whole, under this License to anyone who comes into possession of a copy. This License will therefore apply, along with any applicable section 7 additional terms, to the whole of the work, and all its parts, regardless of how they are packaged. This License gives no permission to license the work in any other way, but it does not invalidate such permission if you have separately received it. d) If the work has interactive user interfaces, each must display Appropriate Legal Notices; however, if the Program has interactive interfaces that do not display Appropriate Legal Notices, your work need not make them do so. A compilation of a covered work with other separate and independent works, which are not by their nature extensions of the covered work, and which are not combined with it such as to form a larger program, in or on a volume of a storage or distribution medium, is called an "aggregate" if the compilation and its resulting copyright are not used to limit the access or legal rights of the compilation's users beyond what the individual works permit. Inclusion of a covered work in an aggregate does not cause this License to apply to the other parts of the aggregate. 6. Conveying Non-Source Forms. You may convey a covered work in object code form under the terms of sections 4 and 5, provided that you also convey the machine-readable Corresponding Source under the terms of this License, in one of these ways: a) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by the Corresponding Source fixed on a durable physical medium customarily used for software interchange. b) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by a written offer, valid for at least three years and valid for as long as you offer spare parts or customer support for that product model, to give anyone who possesses the object code either (1) a copy of the Corresponding Source for all the software in the product that is covered by this License, on a durable physical medium customarily used for software interchange, for a price no more than your reasonable cost of physically performing this conveying of source, or (2) access to copy the Corresponding Source from a network server at no charge. c) Convey individual copies of the object code with a copy of the written offer to provide the Corresponding Source. This alternative is allowed only occasionally and noncommercially, and only if you received the object code with such an offer, in accord with subsection 6b. d) Convey the object code by offering access from a designated place (gratis or for a charge), and offer equivalent access to the Corresponding Source in the same way through the same place at no further charge. You need not require recipients to copy the Corresponding Source along with the object code. If the place to copy the object code is a network server, the Corresponding Source may be on a different server (operated by you or a third party) that supports equivalent copying facilities, provided you maintain clear directions next to the object code saying where to find the Corresponding Source. Regardless of what server hosts the Corresponding Source, you remain obligated to ensure that it is available for as long as needed to satisfy these requirements. e) Convey the object code using peer-to-peer transmission, provided you inform other peers where the object code and Corresponding Source of the work are being offered to the general public at no charge under subsection 6d. A separable portion of the object code, whose source code is excluded from the Corresponding Source as a System Library, need not be included in conveying the object code work. A "User Product" is either (1) a "consumer product", which means any tangible personal property which is normally used for personal, family, or household purposes, or (2) anything designed or sold for incorporation into a dwelling. In determining whether a product is a consumer product, doubtful cases shall be resolved in favor of coverage. For a particular product received by a particular user, "normally used" refers to a typical or common use of that class of product, regardless of the status of the particular user or of the way in which the particular user actually uses, or expects or is expected to use, the product. A product is a consumer product regardless of whether the product has substantial commercial, industrial or non-consumer uses, unless such uses represent the only significant mode of use of the product. "Installation Information" for a User Product means any methods, procedures, authorization keys, or other information required to install and execute modified versions of a covered work in that User Product from a modified version of its Corresponding Source. The information must suffice to ensure that the continued functioning of the modified object code is in no case prevented or interfered with solely because modification has been made. If you convey an object code work under this section in, or with, or specifically for use in, a User Product, and the conveying occurs as part of a transaction in which the right of possession and use of the User Product is transferred to the recipient in perpetuity or for a fixed term (regardless of how the transaction is characterized), the Corresponding Source conveyed under this section must be accompanied by the Installation Information. But this requirement does not apply if neither you nor any third party retains the ability to install modified object code on the User Product (for example, the work has been installed in ROM). The requirement to provide Installation Information does not include a requirement to continue to provide support service, warranty, or updates for a work that has been modified or installed by the recipient, or for the User Product in which it has been modified or installed. Access to a network may be denied when the modification itself materially and adversely affects the operation of the network or violates the rules and protocols for communication across the network. Corresponding Source conveyed, and Installation Information provided, in accord with this section must be in a format that is publicly documented (and with an implementation available to the public in source code form), and must require no special password or key for unpacking, reading or copying. 7. Additional Terms. "Additional permissions" are terms that supplement the terms of this License by making exceptions from one or more of its conditions. Additional permissions that are applicable to the entire Program shall be treated as though they were included in this License, to the extent that they are valid under applicable law. If additional permissions apply only to part of the Program, that part may be used separately under those permissions, but the entire Program remains governed by this License without regard to the additional permissions. When you convey a copy of a covered work, you may at your option remove any additional permissions from that copy, or from any part of it. (Additional permissions may be written to require their own removal in certain cases when you modify the work.) You may place additional permissions on material, added by you to a covered work, for which you have or can give appropriate copyright permission. Notwithstanding any other provision of this License, for material you add to a covered work, you may (if authorized by the copyright holders of that material) supplement the terms of this License with terms: a) Disclaiming warranty or limiting liability differently from the terms of sections 15 and 16 of this License; or b) Requiring preservation of specified reasonable legal notices or author attributions in that material or in the Appropriate Legal Notices displayed by works containing it; or c) Prohibiting misrepresentation of the origin of that material, or requiring that modified versions of such material be marked in reasonable ways as different from the original version; or d) Limiting the use for publicity purposes of names of licensors or authors of the material; or e) Declining to grant rights under trademark law for use of some trade names, trademarks, or service marks; or f) Requiring indemnification of licensors and authors of that material by anyone who conveys the material (or modified versions of it) with contractual assumptions of liability to the recipient, for any liability that these contractual assumptions directly impose on those licensors and authors. All other non-permissive additional terms are considered "further restrictions" within the meaning of section 10. If the Program as you received it, or any part of it, contains a notice stating that it is governed by this License along with a term that is a further restriction, you may remove that term. If a license document contains a further restriction but permits relicensing or conveying under this License, you may add to a covered work material governed by the terms of that license document, provided that the further restriction does not survive such relicensing or conveying. If you add terms to a covered work in accord with this section, you must place, in the relevant source files, a statement of the additional terms that apply to those files, or a notice indicating where to find the applicable terms. Additional terms, permissive or non-permissive, may be stated in the form of a separately written license, or stated as exceptions; the above requirements apply either way. 8. Termination. You may not propagate or modify a covered work except as expressly provided under this License. Any attempt otherwise to propagate or modify it is void, and will automatically terminate your rights under this License (including any patent licenses granted under the third paragraph of section 11). However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation. Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice. Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, you do not qualify to receive new licenses for the same material under section 10. 9. Acceptance Not Required for Having Copies. You are not required to accept this License in order to receive or run a copy of the Program. Ancillary propagation of a covered work occurring solely as a consequence of using peer-to-peer transmission to receive a copy likewise does not require acceptance. However, nothing other than this License grants you permission to propagate or modify any covered work. These actions infringe copyright if you do not accept this License. Therefore, by modifying or propagating a covered work, you indicate your acceptance of this License to do so. 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and propagate that work, subject to this License. You are not responsible for enforcing compliance by third parties with this License. An "entity transaction" is a transaction transferring control of an organization, or substantially all assets of one, or subdividing an organization, or merging organizations. If propagation of a covered work results from an entity transaction, each party to that transaction who receives a copy of the work also receives whatever licenses to the work the party's predecessor in interest had or could give under the previous paragraph, plus a right to possession of the Corresponding Source of the work from the predecessor in interest, if the predecessor has it or can get it with reasonable efforts. You may not impose any further restrictions on the exercise of the rights granted or affirmed under this License. For example, you may not impose a license fee, royalty, or other charge for exercise of rights granted under this License, and you may not initiate litigation (including a cross-claim or counterclaim in a lawsuit) alleging that any patent claim is infringed by making, using, selling, offering for sale, or importing the Program or any portion of it. 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. The work thus licensed is called the contributor's "contributor version". A contributor's "essential patent claims" are all patent claims owned or controlled by the contributor, whether already acquired or hereafter acquired, that would be infringed by some manner, permitted by this License, of making, using, or selling its contributor version, but do not include claims that would be infringed only as a consequence of further modification of the contributor version. For purposes of this definition, "control" includes the right to grant patent sublicenses in a manner consistent with the requirements of this License. Each contributor grants you a non-exclusive, worldwide, royalty-free patent license under the contributor's essential patent claims, to make, use, sell, offer for sale, import and otherwise run, modify and propagate the contents of its contributor version. In the following three paragraphs, a "patent license" is any express agreement or commitment, however denominated, not to enforce a patent (such as an express permission to practice a patent or covenant not to sue for patent infringement). To "grant" such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party. If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. "Knowingly relying" means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid. If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it. A patent license is "discriminatory" if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007. Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program. 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License "or any later version" applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . Also add information on how to contact you by electronic and paper mail. If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: Copyright (C) This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an "about box". You should also get your employer (if you work as a programmer) or school, if any, to sign a "copyright disclaimer" for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . ================================================ FILE: README.md ================================================ ![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) [English](#en) | [中文](#cn) 　 Verilog-UART =========================== This repository contains 3 useful modules: * **UART Receiver**, [uart_rx.v](./RTL/uart_rx.v) , has a AXI-stream master port, which can receive UART data and output it by AXI-stream. * **UART Transmitter**, [uart_tx.v](./RTL/uart_tx.v) , has a AXI-stream slave port, which can receive AXI-stream data and output it by UART. * **UART to AXI4 master**, [uart2axi4.v](./RTL/uart2axi4.v) . It can receive UART commands from Host-PC, do AXI4 bus reading and writing, and feedback the results to the Host-PC. It is a powerful tool for debugging SoC systems. Features: - Standard AXI-stream / AXI4 interface. - Configurable TX/RX buffer - Configurable UART baud rate, parity bit, and stop bits - Fractional frequency division: When the clock frequency cannot be divided by the baud rate, the cycles of each bit are different, thus rounding up a more accurate baud rate. - Baud rate check report: During simulation, the baud rate accuracy will be printed using `$display`. If it is too imprecise, an error will be reported. 　 　 # 1. UART Receiver: uart\_rx The code file of the UART receiver is [uart_rx.v](./RTL/uart_rx.v). This module has no sub modules. The module definition is as follows: ```verilog module uart_rx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // RX fifo depth parameter FIFO_EA = 0 // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... ) ( input wire rstn, input wire clk, // UART RX input signal input wire i_uart_rx, // output AXI-stream master. Associated clock = clk. input wire o_tready, output reg o_tvalid, output reg [ 7:0] o_tdata, // report whether there's a overflow output reg o_overflow ); ``` ### 1.1 config parameters - `CLK_FREQ` is the frequency of `clk` . User must correctly config it to get correnct baud rate. - `BAUD_RATE` is UART baud rate. - `PARITY` can be "NONE", "ODD", or "EVEN" - `FIFO_EA` is for configuring RX fifo. - `FIFO_EA=0` : no RX fifo, the receiving byte must be accepted by user immediately. - `FIFO_EA=1,2` : fifo depth = 4; - `FIFO_EA=3` : fifo depth = 8; - `FIFO_EA=4` : fifo depth = 16; - …… - When `FIFO_EA` is large (>8), it will be implemented by BRAM. ### 1.2 Clock and reset `rstn` is low reset `clk` is clock, all signals will be and should be changed at rise-edge of `clk` ### 1.3 UART signal `i_uart_rx` is UART input signal. ### 1.4 AXI-stream master `o_tready` , `o_tvalid` , `o_tdata` belong to a AXI-stream master. - When `o_tvalid=1` , the valid receive byte will appear on `o_tdata` - If user is ready to accept a received byte, let `o_tready=1` - When `o_tvalid=1` and `o_tready=1` simultaneously, a handshake success and current data is successfully dequeued from module's internal FIFO. At next cycle, next receiving byte may appear on `o_tdata` > :warning: If there is no receive FIFO (`FIFO_EA=0`), the module will not wait for the user to accept the current byte. As long as a byte is received, it will cause `o_tvalid=1` for one cycle, and make the byte appear on `o_tdata` . ### 1.5 `o_overflow` signal If users frequently make `o_tready=0` , that is, if the data is not taken away in time, the received data may be stored more and more in module's FIFO. When the FIFO overflow, the newly enqueue bytes will be discarded, and a one-cycle-high-pulse will appear on `o_overflow` . In other cases, `o_overflow` keeps low. ### 1.6 Baud rate checking During simulation, the module will print the time points and accuracy of the edges of each bit based on the user's configuration. If the accuracy is too poor (relative error>8%), the module will use `$error` to report an error, helping users detect configuration errors in advance. For example, if we config `CLK_FREQ=5000000` (5MHz) , `BAUD_RATE=115200` , `PARITY="ODD"` , it will print report: ``` uart_rx : parity = ODD uart_rx : clock period = 200 ns (5000000 Hz) uart_rx : baud rate period = 8681 ns (115200 Hz) uart_rx : baud cycles = 43 uart_rx : baud cycles frac = 4 uart_rx : __ ____ ____ ____ ____ ____ ____ ____ ____________ uart_rx : wave \____/____X____X____X____X____X____X____X____X____/ uart_rx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P | uart_rx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 uart_rx : uart_rx : t1 - t0 = 8681 ns (ideal) 8600 +- 200 ns (actual). error=281 ns relative_error=3.232% uart_rx : t2 - t0 = 17361 ns (ideal) 17400 +- 200 ns (actual). error=239 ns relative_error=2.752% uart_rx : t3 - t0 = 26042 ns (ideal) 26000 +- 200 ns (actual). error=242 ns relative_error=2.784% uart_rx : t4 - t0 = 34722 ns (ideal) 34800 +- 200 ns (actual). error=278 ns relative_error=3.200% uart_rx : t5 - t0 = 43403 ns (ideal) 43400 +- 200 ns (actual). error=203 ns relative_error=2.336% uart_rx : t6 - t0 = 52083 ns (ideal) 52000 +- 200 ns (actual). error=283 ns relative_error=3.264% uart_rx : t7 - t0 = 60764 ns (ideal) 60800 +- 200 ns (actual). error=236 ns relative_error=2.720% uart_rx : t8 - t0 = 69444 ns (ideal) 69400 +- 200 ns (actual). error=244 ns relative_error=2.816% uart_rx : t9 - t0 = 78125 ns (ideal) 78200 +- 200 ns (actual). error=275 ns relative_error=3.168% uart_rx : t10- t0 = 86806 ns (ideal) 86800 +- 200 ns (actual). error=206 ns relative_error=2.368% ``` 　 　 # 2. UART Transmitter: uart\_tx The code file of the UART Transmitter is [uart_tx.v](./RTL/uart_tx.v). This module has no sub modules. The module definition is as follows: ```verilog module uart_tx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" parameter STOP_BITS = 2, // can be 1, 2, 3, 4, ... // AXI stream data width parameter BYTE_WIDTH = 1, // can be 1, 2, 3, 4, ... // TX fifo depth parameter FIFO_EA = 0, // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... // do you want to send extra byte after each AXI-stream transfer or packet? parameter EXTRA_BYTE_AFTER_TRANSFER = "", // specify a extra byte to send after each AXI-stream transfer. when ="", do not send this extra byte parameter EXTRA_BYTE_AFTER_PACKET = "" // specify a extra byte to send after each AXI-stream packet . when ="", do not send this extra byte ) ( input wire rstn, input wire clk, // input stream : AXI-stream slave. Associated clock = clk output wire i_tready, input wire i_tvalid, input wire [8*BYTE_WIDTH-1:0] i_tdata, input wire [ BYTE_WIDTH-1:0] i_tkeep, input wire i_tlast, // UART TX output signal output reg o_uart_tx ); ``` ### 2.2 config parameters - `CLK_FREQ` is the frequency of `clk` . User must correctly config it to get correnct baud rate. - `BAUD_RATE` is UART baud rate. - `PARITY` can be "NONE", "ODD", or "EVEN" - `STOP_BITS` is the number of stop bits '1' - `BYTE_WIDTH` is the byte-width of AXI-stream slave's data (`i_tdata`) - `FIFO_EA` is for configuring TX fifo. - `FIFO_EA=0` : no TX fifo. For each successful handshake of data, we must wait for the UART transmission to complete before shaking the next data. - `FIFO_EA=1,2` : fifo depth = 4; - `FIFO_EA=3` : fifo depth = 8; - `FIFO_EA=4` : fifo depth = 16; - …… - When `FIFO_EA` is large (>8), it will be implemented by BRAM. - `EXTRA_BYTE_AFTER_TRANSFER` is to configure whether an extra byte needs to be sent through UART every time an AXI-stream transfer (i.e. a successful handshake) - If you don't want to send the extra byte, just let `EXTRA_BYTE_AFTER_TRANSFER=""` - If you want to send the extra byte, such as the space byte " ", let `EXTRA_BYTE_AFTER_TRANSFER=" "` - `EXTRA_BYTE_AFTER_PACKET` is to configure whether an extra byte needs to be sent through UART at the end of each AXI-stream packet (i.e. `i_tlast=1` when a successful handshake) - If you don't want to send the extra byte, just let `EXTRA_BYTE_AFTER_PACKET=""` - If you want to send the extra byte, such as the new-line byte "\n", let `EXTRA_BYTE_AFTER_PACKET="\n"` ### 2.2 Clock and reset `rstn` is low reset `clk` is clock, all signals will be and should be changed at rise-edge of `clk` ### 2.3 UART signal `o_uart_tx` is UART output signal. ### 2.4 AXI-stream slave `i_tready` , `i_tvalid` , `i_tdata` , `i_tdata` , `i_tkeep` , `t_tlast` belong to AXI-stream slave interface. - `i_tready=1` means the module yet has FIFO space. `i_tready=0` means the module has no more FIFO space for accept more data. - `i_tvalid=1` means the user want to enqueue a data to TX FIFO. Meanwhile, `i_tdata`, `i_tkeep` , `i_tlast` must valid. - When `i_tvalid=1` and `i_tready=1` simultaneously, a handshake success, a data is successfully enqueue to FIFO. - `i_tkeep` is byte-enable signal : - `i_tkeep[0]` means `i_tdata[7:0]` byte is valid, and will be send on UART, otherwise it will not be send. - `i_tkeep[1]` means `i_tdata[15:8]` byte is valid, and will be send on UART, otherwise it will not be send. - `i_tkeep[2]` means `i_tdata[23:16]` byte is valid, and will be send on UART, otherwise it will not be send. - ...... - `i_tlast` is the packet border indicator of AXI-stream. When sending a data, if `i_tlast=1` - If `EXTRA_BYTE_AFTER_PACKET` specify a extra byte, UART will send this extra byte. - If `EXTRA_BYTE_AFTER_PACKET=""` did not specify a extra byte, UART will not send this extra byte. In other words, at this point, `i_tlast` has no effect whether it is 0 or 1. ### 2.5 Baud rate checking During simulation, the module will print the time points and accuracy of the edges of each bit based on the user's configuration. If the accuracy is too poor (relative error>3%), the module will use `$error` to report an error, helping users detect configuration errors in advance. 　 　 # 3. UART to AXI4 master (uart2axi4) The code file is [RTL/uart2axi4.v](./RTL/uart2axi4.v). This module will call [uart_tx.v](./RTL/uart_tx.v) and [uart_rx.v](./RTL/uart_rx.v) This module is an AXI4 master that can receive UART commands from the upper computer, complete AXI4 bus reading and writing, and provide the results to the upper computer. It is a powerful tool for debugging SoC systems. The module definition is as follows: ```verilog module uart2axi4 #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // AXI4 config parameter BYTE_WIDTH = 2, // data width (bytes) parameter A_WIDTH = 32 // address width (bits) ) ( input wire rstn, input wire clk, // AXI4 master ---------------------- input wire awready, // AW output wire awvalid, output wire [A_WIDTH-1:0] awaddr, output wire [ 7:0] awlen, input wire wready, // W output wire wvalid, output wire wlast, output wire [8*BYTE_WIDTH-1:0] wdata, output wire bready, // B input wire bvalid, input wire arready, // AR output wire arvalid, output wire [A_WIDTH-1:0] araddr, output wire [ 7:0] arlen, output wire rready, // R input wire rvalid, input wire rlast, input wire [8*BYTE_WIDTH-1:0] rdata, // UART ---------------------- input wire i_uart_rx, output wire o_uart_tx ); ``` ### 3.1 config parameters - `CLK_FREQ` is the frequency of `clk` . User must correctly config it to get correnct baud rate. - `BAUD_RATE` is UART baud rate. - `PARITY` can be "NONE", "ODD", or "EVEN" - `BYTE_WIDTH` is the byte-width of AXI4's data (`wdata` and `rdata`) - `A_WIDTH` is the bit-width of AXI's address (`awaddr1` and `araddr`) ### 3.2 Clock and reset `rstn` is low reset `clk` is clock, all signals will be and should be changed at rise-edge of `clk` ### 3.3 UART signal `o_uart_tx` is UART output signal. `i_uart_rx` is UART input signal. ### 3.4 AXI4 master port This module has an AXI4 master interface that can read and write AXI4 bus. We will not provide a detailed explanation of AXI4 timing here, please refer to https://www.xilinx.com/products/intellectual-property/axi.html ### 3.5 UART Command Format To read and write to the AXI4 bus, a 'command-response' format is required: - Command: The Host-PC sends commands to `uart2axi4` module through `i_uart_rx`; - Execution: This module performs AXI4 read and write; - Response: This module response message through `o_uart_tx` , it will be send to Host-PC. Each command and response only contains printable ASCII characters and ends with carriage-return "\r", new-line "\n", or carriage return+new-line "\r\n". #### Write Command For AXI4 write operation, you should send command like: ``` w[address in hex] [write data 0 in hex] [write data 1 in hex] [write data 2 in hex] ... (end with "\n") ``` Write data must at least 1 and at most 256. These data will be written in one AXI4 burst. For example: ``` w123 456 789 abc def 4321 ``` means write address=0x0123, burst length=5, the 5 data are: 0x0456, 0x0789, 0x0abc, 0xdef, 0x4321. For write command, the module will response "okay", "ok", or "o" #### Read Command For AXI4 read operation, you should send command like: ``` r[address in hex] [read burst length] (end with "\n") ``` The range of read burst length is 1-100 (note that hexadecimal values need to be sent, corresponding to decimal values of 1-256) For example: ``` r123 a ``` means read address=0x123, burst length=0xa=10 for this command, the module may response: ``` 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ``` which means the ten read data are all 0x0000 #### Invalid Command If the command format is undefined, the module will response "invalid", "inva", "in", or "i" 　 　 # 4. RTL Simulation The simulation related files are all in the SIM folder. ### 4.1 Simulation for uart_tx and uart_rx This simulation connect module `uart_tx` and module `uart_rx` , let `uart_tx` sending increase bytes via UART, and `uart_rx` will receive these bytes. files: - tb_axis_inc_source.v is an AXI-stream master to send increase bytes on AXI-stream, its AXI-stream will connect on `uart_tx` 's AXI-stream slave. - tb_uart.v is simulation top. - tb_uart_run_iverilog.bat is the command script to run iverilog command Before using iverilog for simulation, you should install it, see [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) Then double-click tb_uart_run_iverilog.bat to run simulation (on Windows), Then you can open dump.vcd to see the waveform. ### 4.2 Simulation for uart2axi4 This simulation sends a write command and a read command to uart2axi4. files: - tb_uart2axi4.v is simulation top. - tb_uart2axi4_run_iverilog.bat is the command script to run iverilog command. Before using iverilog for simulation, you should install it, see [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) Then double-click tb_uart2axi4_run_iverilog.bat to run simulation (on Windows), Then you can open dump.vcd to see the waveform. 　 　 　 　 　 Verilog-UART =========================== 本库包含 3 个 Verilog 模块： * **UART接收器**：[uart_rx.v](./RTL/uart_rx.v) , 具有一个 AXI-stream master 口，解析 UART 协议并将数据通过 AXI-stream 发送出去。 * **UART发送器**：[uart_tx.v](./RTL/uart_tx.v) , 具有一个 AXI-stream slave 口，接受 AXI-stream 数据并通过 UART 发送出去。 * **UART to AXI4 master**：[uart2axi4.v](./RTL/uart2axi4.v) , 它能接收上位机的 UART 命令，完成 AXI4 总线读写，并将结果反馈给上位机。是调试 SoC 系统的有力工具。 特点： - 标准的 AXI 接口 - 可配置是否开启发送/接收 FIFO 以及 FIFO 的深度 - 可配置的 UART 波特率、校验位、停止位 - 分数分频：当时钟频率不能整除波特率时，各个 bit 的周期不一样，从而凑出一个更加接近的波特率。 - 波特率检查报告：仿真时会用 `$display` 打印波特率精确度。如果过于不精确则报错。 　 　 # 1. UART接收器 uart_rx UART接收器的代码文件是 [uart_rx.v](./RTL/uart_rx.v) 。该模块没有子模块。 定义如下： ```verilog module uart_rx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // RX fifo depth parameter FIFO_EA = 0 // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... ) ( input wire rstn, input wire clk, // UART RX input signal input wire i_uart_rx, // output AXI-stream master. Associated clock = clk. input wire o_tready, output reg o_tvalid, output reg [ 7:0] o_tdata, // report whether there's a overflow output reg o_overflow ); ``` ### 1.1 parameter 配置 - `CLK_FREQ` 是时钟 `clk` 的频率，用户必须正确配置它，从而产生正确的波特率。 - `BAUD_RATE` 是 UART 波特率 - `PARITY` 决定了校验位，`"NONE"`是无校验位，`"ODD"`是奇校验位，`"EVEN"`是偶校验位。 - `FIFO_EA` 用来配置接收缓存： - `FIFO_EA=0` 代表无接收缓存，收到的字节必须立刻被用户处理，否则就会丢弃。 - `FIFO_EA=1,2` 代表接收缓存大小=4； - `FIFO_EA=3` 代表接收缓存大小=8； - `FIFO_EA=4` 代表接收缓存大小=16； - …… - 当 `FIFO_EA` 较大 (通常是>8)，FIFO 会用 BRAM 实现。 ### 1.2 时钟和复位 `rstn` 是低电平复位。 `clk` 是时钟。所有信号的采样和改变都要在 `clk` 的上升沿进行。 ### 1.3 UART 信号 `i_uart_rx` 是 UART 输入信号 ### 1.4 AXI-stream master `o_tready` , `o_tvalid` , `o_tdata` 构成了 AXI-stream master 接口 - `o_tvalid=1` 时，`o_tdata` 上会产生有效的接收到的字节， - 如果用户能够接收当前字节，就让 `o_tready=1` 。 - 当 `o_tvalid` 和 `o_tready` 都是1时，握手成功，当前字节成功从模块的缓存中拿出。 - 当握手成功时，在下一周期： - 若缓存中还有收到的字节，则 `o_tvalid=1` ， `o_tdata` 上出现下一个收到的字节 - 若缓存暂时空了，则 `o_tvalid=0` > :warning: 如果没有接收缓存（参数 `FIFO_EA=0` ），则模块不会等待用户是否能接受当前的字节，只要收到一个字节就让 `o_tvalid=1` 一个周期，并让该字节出现在 `o_tdata` 上。 ### 1.5 溢出信号 `o_overflow` 如果用户经常让 `o_tready=0` ，也即不及时拿走数据，则接受数据会在模块里的缓存里越攒越多，当缓存溢出时，新接收到的字节会被丢弃，并在 `o_overflow` 信号上产生一个周期的高电平脉冲。否则 `o_overflow` 一直保持 0 。 ### 1.6 波特率检查 在仿真时，模块会根据用户的配置，打印各个 bit 的边沿的时间点以及其精确度。如果精度太差 (相对误差>8%) ，模块会使用 `$error` 系统调用报错，帮助用户提前发现配置错误。 例如，如果我们配置 `CLK_FREQ=5000000` (5MHz) ，`BAUD_RATE=115200` , `PARITY="ODD"`，则仿真会打印如下报告： ``` uart_rx : parity = ODD uart_rx : clock period = 200 ns (5000000 Hz) uart_rx : baud rate period = 8681 ns (115200 Hz) uart_rx : baud cycles = 43 uart_rx : baud cycles frac = 4 uart_rx : __ ____ ____ ____ ____ ____ ____ ____ ____________ uart_rx : wave \____/____X____X____X____X____X____X____X____X____/ uart_rx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P | uart_rx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 uart_rx : uart_rx : t1 - t0 = 8681 ns (ideal) 8600 +- 200 ns (actual). error=281 ns relative_error=3.232% uart_rx : t2 - t0 = 17361 ns (ideal) 17400 +- 200 ns (actual). error=239 ns relative_error=2.752% uart_rx : t3 - t0 = 26042 ns (ideal) 26000 +- 200 ns (actual). error=242 ns relative_error=2.784% uart_rx : t4 - t0 = 34722 ns (ideal) 34800 +- 200 ns (actual). error=278 ns relative_error=3.200% uart_rx : t5 - t0 = 43403 ns (ideal) 43400 +- 200 ns (actual). error=203 ns relative_error=2.336% uart_rx : t6 - t0 = 52083 ns (ideal) 52000 +- 200 ns (actual). error=283 ns relative_error=3.264% uart_rx : t7 - t0 = 60764 ns (ideal) 60800 +- 200 ns (actual). error=236 ns relative_error=2.720% uart_rx : t8 - t0 = 69444 ns (ideal) 69400 +- 200 ns (actual). error=244 ns relative_error=2.816% uart_rx : t9 - t0 = 78125 ns (ideal) 78200 +- 200 ns (actual). error=275 ns relative_error=3.168% uart_rx : t10- t0 = 86806 ns (ideal) 86800 +- 200 ns (actual). error=206 ns relative_error=2.368% ``` 　 　 # 2. UART发送器 uart_tx UART发送器的代码文件是 [RTL/uart_tx.v](./RTL/uart_tx.v) 。该模块没有子模块。 该模块的定义如下： ```verilog module uart_tx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" parameter STOP_BITS = 2, // can be 1, 2, 3, 4, ... // AXI stream data width parameter BYTE_WIDTH = 1, // can be 1, 2, 3, 4, ... // TX fifo depth parameter FIFO_EA = 0, // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... // do you want to send extra byte after each AXI-stream transfer or packet? parameter EXTRA_BYTE_AFTER_TRANSFER = "", // specify a extra byte to send after each AXI-stream transfer. when ="", do not send this extra byte parameter EXTRA_BYTE_AFTER_PACKET = "" // specify a extra byte to send after each AXI-stream packet . when ="", do not send this extra byte ) ( input wire rstn, input wire clk, // input stream : AXI-stream slave. Associated clock = clk output wire i_tready, input wire i_tvalid, input wire [8*BYTE_WIDTH-1:0] i_tdata, input wire [ BYTE_WIDTH-1:0] i_tkeep, input wire i_tlast, // UART TX output signal output reg o_uart_tx ); ``` ### 2.1 parameter 配置 - `CLK_FREQ` 是时钟 `clk` 的频率，用户必须正确配置它，从而产生正确的波特率。 - `BAUD_RATE` 是 UART 波特率 - `PARITY` 决定了校验位，`"NONE"`是无校验位，`"ODD"`是奇校验位，`"EVEN"`是偶校验位。 - `STOP_BITS` 是停止位数量，决定了模块会在发送完每字节后发送多少个停止位。 - `BYTE_WIDTH` 是 AXI-stream slave 接口的字节宽度 (也即 `i_tdata` 的字节数) - `FIFO_EA` 用来配置发送缓存： - `FIFO_EA=0` 代表无发送缓存，AXI-stream 每握手成功一个数据，都必须等待发送完成，才能握手下一个数据 - `FIFO_EA=1,2` 代表接收缓存大小=4； - `FIFO_EA=3` 代表接收缓存大小=8； - `FIFO_EA=4` 代表接收缓存大小=16； - …… - 当 `FIFO_EA` 较大 (通常是>8)，FIFO 会用 BRAM 实现。 - `EXTRA_BYTE_AFTER_TRANSFER` 用来配置每次 AXI-stream transfer (也即握手成功一次) 时，是否要通过 UART 发送一个额外的字节 - 如果不想发送额外的字节，就让 `EXTRA_BYTE_AFTER_TRANSFER=""` - 如果想发送额外的字节，比如空格字节 " "，就让 `EXTRA_BYTE_AFTER_TRANSFER=" "` - `EXTRA_BYTE_AFTER_PACKET` 用来配置每次 AXI-stream packet (也即握手成功一次且 `tlast=1`) 时，是否要通过 UART 发送一个额外的字节 - 如果不想发送额外的字节，就让 `EXTRA_BYTE_AFTER_PACKET=""` - 如果想发送额外的字节，比如回车字节 "\n"，就让 `EXTRA_BYTE_AFTER_PACKET="\n"` ### 2.2 时钟和复位 `rstn` 是低电平复位。 `clk` 是时钟。所有信号的采样和改变都要在 `clk` 的上升沿进行。 ### 2.3 UART 信号 `o_uart_tx` 是 UART 输出信号 ### 2.4 AXI-stream slave `i_tready` , `i_tvalid` , `i_tdata` , `i_tkeep` , `i_tlast` 构成了 AXI-stream slave 接口： - `i_tready=1` 代表模块内部缓存还有空间，可以接受数据。`i_tready=0` 代表模块内部缓存没空间了，无法接收数据。 - `i_tvalid=1` 代表用户想要发送一个数据到发送缓存里，同时 `i_tdata` , `i_tkeep` , `i_tlast` 需要有效。 - `i_tvalid` 和 `i_tready` 都是 1 时，握手成功，当前数据被成功存入缓存。 - `i_tdata` 的字节宽度通过参数 `BYTE_WIDTH` 来配置。 - `i_tdata` 遵循小端序，其低位字节先被发送，高位字节后被发送。 - `i_tkeep` 是字节有效信号： - `i_tkeep[0]=0` 代表 `i_tdata[7:0]` 这个字节有效，需要发送。否则不会发送； - `i_tkeep[1]=1` 代表 `i_tdata[15:8]` 这个字节有效，需要发送。否则不会发送； - `i_tkeep[2]=1` 代表 `i_tdata[23:16]` 这个字节有效，需要发送。否则不会发送； - …… - `i_tlast` 是 AXI-stream 的 packet 分界信号。当发送一个数据时，如果 `i_tlast=1` ： - 如果 `EXTRA_BYTE_AFTER_PACKET` 指定了一个字节，UART 会额外发送这个字节； - 如果 `EXTRA_BYTE_AFTER_PACKET=""` ，不发送额外字节。换句话说，此时 `i_tlast` 无论是 0 还是 1 都没有任何影响。 ### 2.5 波特率检查 在仿真时，模块会根据用户的配置，打印各个 bit 的边沿的时间点以及其精确度。如果精度太差 (相对误差>3%) ，模块会使用 `$error` 系统调用报错，帮助用户提前发现配置错误。 在前面 `uart_rx` 模块中已经对波特率检查举例，这里不再举例。 　 　 # 3. UART to AXI4 master (uart2axi4) 代码文件是 [RTL/uart2axi4.v](./RTL/uart2axi4.v) 。该模块会调用 [RTL/uart_tx.v](./RTL/uart_tx.v) 和 [RTL/uart_rx.v](./RTL/uart_rx.v) 。 该模块是一个 AXI4 master，它能接收上位机的 UART 命令，完成 AXI4 总线读写，并将结果反馈给上位机。是调试 SoC 系统的有力工具。 模块定义如下： ```verilog module uart2axi4 #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // AXI4 config parameter BYTE_WIDTH = 2, // data width (bytes) parameter A_WIDTH = 32 // address width (bits) ) ( input wire rstn, input wire clk, // AXI4 master ---------------------- input wire awready, // AW output wire awvalid, output wire [A_WIDTH-1:0] awaddr, output wire [ 7:0] awlen, input wire wready, // W output wire wvalid, output wire wlast, output wire [8*BYTE_WIDTH-1:0] wdata, output wire bready, // B input wire bvalid, input wire arready, // AR output wire arvalid, output wire [A_WIDTH-1:0] araddr, output wire [ 7:0] arlen, output wire rready, // R input wire rvalid, input wire rlast, input wire [8*BYTE_WIDTH-1:0] rdata, // UART ---------------------- input wire i_uart_rx, output wire o_uart_tx ); ``` ### 3.1 parameter 配置 - `CLK_FREQ` 是时钟 `clk` 的频率，用户必须正确配置它，从而产生正确的波特率。 - `BAUD_RATE` 是 UART 波特率 - `PARITY` 决定了校验位，`"NONE"`是无校验位，`"ODD"`是奇校验位，`"EVEN"`是偶校验位。 - `BYTE_WIDTH` 是 AXI4 的宽度 (`wdata` 和 `rdata` 的字节宽度) - `A_WIDTH` 是 AXI4 的地址宽度 (`awaddr` 和 `araddr` 的位宽) ### 3.2 时钟和复位 `rstn` 是低电平复位。 `clk` 是时钟。所有信号的采样和改变都要在 `clk` 的上升沿进行。 ### 3.3 UART 信号 `o_uart_tx` 是 UART 输出信号 (连接上位机的 UART-RX) `i_uart_rx` 是 UART 输入信号 (连接上位机的 UART-TX) ### 3.4 AXI4 master 该模块有一个 AXI4 master 接口，可读写 AXI4 总线。这里不对 AXI4 时序做详解，详见 https://www.xilinx.com/products/intellectual-property/axi.html ### 3.5 UART 命令格式 要读写 AXI4 总线，需要进行一次 "命令-响应" ： - 命令：上位机通过 UART 发送命令给该模块的 `i_uart_rx` ； - 执行：该模块执行 AXI4 读写； - 响应：该模块通过 `o_uart_tx` 发送一个反馈信息给上位机的 UART 。 每个命令和响应都只包含可打印的 ASCII 字符，且以 回车 "\r" 、换行 "\n" 、或 回车+换行 "\r\n" 结尾。 #### 写命令 要进行 AXI4 写操作，格式如下： ``` w[地址的十六进制值] [写数据0的十六进制值] [写数据1的十六进制值] [写数据2的十六进制值] ... (注意命令要用"\n"结尾) ``` 其中写数据最少1个，最多256个。这些数据会在一次 AXI4 burst 内写完。 例如： ``` w123 456 789 abc def 4321 ``` 代表写地址=0x0123，突发长度=5，写入的5个数据为 0x0456, 0x0789, 0x0abc, 0xdef, 0x4321 。 对于写命令，模块会响应 "okay" , "ok" , 或 "o" ### 读命令 要进行 AXI4 读操作，格式如下： ``` r[地址的十六进制值] [读突发长度] (注意命令要用"\n"结尾) ``` 其中读突发长度的取值范围为 1~100 (注意需要发送十六进制值，对应的十进制值为1~256) 例如： ``` r123 a ``` 代表读地址=0x123，突发长度=0xa=10。 对于读命令，模块会响应读到的数据 + "\n" ，各个数据之间用空格 " " 隔开。 例如，上述命令可能会响应： ``` 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ``` 代表读到的10个数据都是 0x0000 ### 非法命令 如果命令格式错误，模块会响应 "invalid" , "inva" , “in" , 或者 "i" 　 　 # 4. 仿真 仿真相关的文件都在 SIM 文件夹中。 ### 4.1 针对 uart_tx 和 uart_rx 模块的仿真 该仿真将 uart_tx 和 uart_rx 连起来，让 uart_tx 发送递增的字节，uart_rx 会解析出这些字节。 相关文件 - tb_axis_inc_source.v 是个 AXI-master ，产生递增的字节。它会连接到 uart_tx 的 AXI-slave 上。 - tb_uart.v 是仿真的顶层。 - tb_uart_run_iverilog.bat 包含了运行 iverilog 仿真的命令。 使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) 然后双击 tb_uart_run_iverilog.bat 运行仿真 (仅Windows)，然后可以打开生成的 dump.vcd 文件查看波形。 ### 4.2 针对 uart2axi4 模块的仿真 该仿真发送一个写命令和一个读命令给 uart2axi4 。 相关文件 - tb_uart2axi4.v 是仿真的顶层。 - tb_uart2axi4_run_iverilog.bat 包含了运行 iverilog 仿真的命令。 使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) 然后双击 tb_uart2axi4_run_iverilog.bat 运行仿真 (仅Windows)，然后可以打开生成的 dump.vcd 文件查看波形。 ================================================ FILE: RTL/uart2axi4.v ================================================ //-------------------------------------------------------------------------------------------------------- // Module : uart2axi4 // Type : synthesizable // Standard: Verilog 2001 (IEEE1364-2001) // Function: convert UART command to AXI4 read/write action //-------------------------------------------------------------------------------------------------------- module uart2axi4 #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // AXI4 config parameter BYTE_WIDTH = 2, // data width (bytes) parameter A_WIDTH = 32 // address width (bits) ) ( input wire rstn, input wire clk, // AXI4 master ---------------------- input wire awready, // AW output wire awvalid, output wire [A_WIDTH-1:0] awaddr, output wire [ 7:0] awlen, input wire wready, // W output wire wvalid, output wire wlast, output wire [8*BYTE_WIDTH-1:0] wdata, output wire bready, // B input wire bvalid, input wire arready, // AR output wire arvalid, output wire [A_WIDTH-1:0] araddr, output wire [ 7:0] arlen, output wire rready, // R input wire rvalid, input wire rlast, input wire [8*BYTE_WIDTH-1:0] rdata, // UART ---------------------- input wire i_uart_rx, output wire o_uart_tx ); wire rx_valid; wire [ 7:0] rx_byte; uart_rx #( .CLK_FREQ ( CLK_FREQ ), .BAUD_RATE ( BAUD_RATE ), .PARITY ( PARITY ), .FIFO_EA ( 0 ) ) u_uart_rx ( .rstn ( rstn ), .clk ( clk ), .i_uart_rx ( i_uart_rx ), .o_tready ( 1'b1 ), .o_tvalid ( rx_valid ), .o_tdata ( rx_byte ), .o_overflow ( ) ); wire rx_space = (rx_valid && (rx_byte == 8'h20)); // " " wire rx_newline = (rx_valid && (rx_byte == 8'h0D || rx_byte == 8'h0A)); // \r, \n wire rx_char_w = (rx_valid && (rx_byte == 8'h57 || rx_byte == 8'h77)); // W, w wire rx_char_r = (rx_valid && (rx_byte == 8'h52 || rx_byte == 8'h72)); // R, r wire rx_is_hex = (rx_valid && ((rx_byte>=8'h30 && rx_byte<=8'h39) || (rx_byte>=8'h41 && rx_byte<=8'h46) || (rx_byte>=8'h61 && rx_byte<=8'h66))); // 0~9, A~F, a~f wire [ 3:0] rx_hex = (rx_byte>=8'h30 && rx_byte<=8'h39) ? rx_byte[3:0] : (rx_byte[3:0] + 4'd9); reg rwtype = 1'b0; reg [A_WIDTH-1:0] addr = 0; reg [ 8:0] len = 9'h0; reg wwen = 1'b0; reg [8*BYTE_WIDTH-1:0] wwdata = 0; reg [ 7:0] wraddr = 8'h0; localparam [ 3:0] S_IDLE = 4'd0, S_PARSE_ADDR = 4'd1, S_PARSE_LEN = 4'd2, S_PARSE_WDATA = 4'd3, S_AXI_RADDR = 4'd4, S_AXI_WADDR = 4'd5, S_AXI_RDATA = 4'd6, S_AXI_WDATA = 4'd7, S_AXI_B = 4'd8, S_W_DONE = 4'd9, S_INVALID = 4'd10, S_FAILED = 4'd11; reg [ 3:0] state = S_IDLE; always @ (posedge clk or negedge rstn) if (~rstn) begin rwtype <= 1'b0; addr <= 0; len <= 9'h0; wwen <= 1'b0; wwdata <= 0; wraddr <= 8'h0; state <= S_IDLE; end else begin case (state) S_IDLE : begin rwtype <= rx_char_w; addr <= 0; len <= 9'h0; wwen <= 1'b0; wwdata <= 0; wraddr <= 8'h0; if (rx_char_w | rx_char_r) state <= S_PARSE_ADDR; else if (rx_space | rx_newline) state <= S_IDLE; else if (rx_valid) state <= S_INVALID; end S_PARSE_ADDR : if (rx_is_hex) begin addr <= (addr << 4); addr[3:0] <= rx_hex; end else if (rx_space) state <= rwtype ? S_PARSE_WDATA : S_PARSE_LEN; else if (rx_newline) state <= S_FAILED; else if (rx_valid) state <= S_INVALID; S_PARSE_LEN : if (rx_is_hex) begin len <= (len << 4); len[3:0] <= rx_hex; end else if (rx_newline) begin len <= (len >= 9'h100) ? 9'hFF : (len == 9'h0) ? 9'h0 : (len - 9'h1); state <= S_AXI_RADDR; end else if (rx_space) begin state <= S_PARSE_LEN; end else if (rx_valid) begin state <= S_INVALID; end S_PARSE_WDATA : if (rx_is_hex) begin wwen <= 1'b1; wwdata <= (wwdata << 4); wwdata[3:0] <= rx_hex; end else if (rx_space) begin wwen <= 1'b0; if (wwen) begin wwdata <= 0; len <= len + 9'd1; end end else if (rx_newline) begin if (wwen) begin state <= ( len < 9'h100) ? S_AXI_WADDR : S_FAILED; end else begin state <= (len >= 9'd0 && len <= 9'd100) ? S_AXI_WADDR : S_FAILED; len <= len - 9'd1; end end else if (rx_valid) begin state <= S_INVALID; end S_AXI_RADDR : if (arready) state <= S_AXI_RDATA; S_AXI_WADDR : if (awready) state <= S_AXI_WDATA; S_AXI_RDATA : if (rvalid) begin len <= len - 9'd1; if (rlast || (len==9'd0)) state <= S_IDLE; end S_AXI_WDATA : if (wready) begin wraddr <= wraddr + 8'd1; if (wraddr >= len[7:0]) state <= S_AXI_B; end S_AXI_B : if (bvalid) state <= S_W_DONE; S_W_DONE : state <= S_IDLE; S_INVALID : if (rx_newline) state <= S_FAILED; default : // S_FAILED : state <= S_IDLE; endcase end reg [8*BYTE_WIDTH-1:0] wbuf [0:255]; always @ (posedge clk) if ( (state == S_PARSE_WDATA) && (rx_space || rx_newline) && wwen ) wbuf[len[7:0]] <= wwdata; wire [ 7:0] wraddr_next = (wvalid & wready) ? (wraddr + 8'd1) : wraddr; reg [8*BYTE_WIDTH-1:0] wrdata; always @ (posedge clk) wrdata <= wbuf[wraddr_next]; assign arvalid = (state == S_AXI_RADDR); assign araddr = addr; assign arlen = len[7:0]; assign awvalid = (state == S_AXI_WADDR); assign awaddr = addr; assign awlen = len[7:0]; assign rready = (state == S_AXI_RDATA); assign wvalid = (state == S_AXI_WDATA); assign wlast = (wraddr >= len[7:0]); assign wdata = wrdata; assign bready = 1'b1; // (state == S_AXI_B) function [7:0] toHex; input [3:0] val; begin toHex = (val <= 4'd9) ? {4'h3, val} : {4'd6, 1'b0, val[2:0]-3'h1}; end endfunction wire tx_w_done = (state == S_W_DONE); wire tx_failed = (state == S_FAILED); wire tx_number = (rvalid & rready); wire [8*2*BYTE_WIDTH-1:0] tx_data_failed = 64'h20_64_69_6C_61_76_6E_69; // "invalid" wire [8*2*BYTE_WIDTH-1:0] tx_data_w_done = 64'h20_20_20_20_79_61_6B_6F; // "okay" wire [8*2*BYTE_WIDTH-1:0] tx_data_number; wire tx_valid = tx_failed | tx_w_done | tx_number; wire [8*2*BYTE_WIDTH-1:0] tx_data = tx_failed ? tx_data_failed : tx_w_done ? tx_data_w_done : tx_data_number; wire tx_last = tx_failed ? 1'b1 : tx_w_done ? 1'b1 : (rlast || (len==9'd0)); generate genvar i; for (i=0; i<2*BYTE_WIDTH; i=i+1) begin : gen_tx_tdata assign tx_data_number[8*i +: 8] = toHex(rdata[4*(2*BYTE_WIDTH-1-i) +: 4]); end endgenerate uart_tx #( .CLK_FREQ ( CLK_FREQ ), .BAUD_RATE ( BAUD_RATE ), .PARITY ( PARITY ), .STOP_BITS ( 4 ), .BYTE_WIDTH ( 2 * BYTE_WIDTH ), .FIFO_EA ( 9 ), .EXTRA_BYTE_AFTER_TRANSFER ( " " ), .EXTRA_BYTE_AFTER_PACKET ( "\n" ) ) u_uart_tx ( .rstn ( rstn ), .clk ( clk ), .i_tready ( ), .i_tvalid ( tx_valid ), .i_tdata ( tx_data ), .i_tkeep ( {(2*BYTE_WIDTH){1'b1}} ), .i_tlast ( tx_last ), .o_uart_tx ( o_uart_tx ) ); endmodule ================================================ FILE: RTL/uart_rx.v ================================================ //-------------------------------------------------------------------------------------------------------- // Module : uart_rx // Type : synthesizable, IP's top // Standard: Verilog 2001 (IEEE1364-2001) // Function: input UART signal, // output AXI-stream (1 byte data width) //-------------------------------------------------------------------------------------------------------- module uart_rx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" // RX fifo depth parameter FIFO_EA = 0 // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... ) ( input wire rstn, input wire clk, // UART RX input signal input wire i_uart_rx, // output AXI-stream master. Associated clock = clk. input wire o_tready, output reg o_tvalid, output reg [ 7:0] o_tdata, // report whether there's a overflow output reg o_overflow ); //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // Generate fractional precise upper limit for counter //--------------------------------------------------------------------------------------------------------------------------------------------------------------- localparam BAUD_CYCLES = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) / 10 ; localparam BAUD_CYCLES_FRAC = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) % 10 ; localparam HALF_BAUD_CYCLES = BAUD_CYCLES / 2; localparam THREE_QUARTER_BAUD_CYCLES = (BAUD_CYCLES*3) / 4; localparam [9:0] ADDITION_CYCLES = (BAUD_CYCLES_FRAC == 0) ? 10'b0000000000 : (BAUD_CYCLES_FRAC == 1) ? 10'b0000010000 : (BAUD_CYCLES_FRAC == 2) ? 10'b0010000100 : (BAUD_CYCLES_FRAC == 3) ? 10'b0010010010 : (BAUD_CYCLES_FRAC == 4) ? 10'b0101001010 : (BAUD_CYCLES_FRAC == 5) ? 10'b0101010101 : (BAUD_CYCLES_FRAC == 6) ? 10'b1010110101 : (BAUD_CYCLES_FRAC == 7) ? 10'b1101101101 : (BAUD_CYCLES_FRAC == 8) ? 10'b1101111011 : /*BAUD_CYCLES_FRAC == 9)*/ 10'b1111101111 ; wire [31:0] cycles [9:0]; assign cycles[0] = BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0); assign cycles[1] = BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0); assign cycles[2] = BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0); assign cycles[3] = BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0); assign cycles[4] = BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0); assign cycles[5] = BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0); assign cycles[6] = BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0); assign cycles[7] = BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0); assign cycles[8] = BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0); assign cycles[9] = BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0); //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // Input beat //--------------------------------------------------------------------------------------------------------------------------------------------------------------- reg rx_d1 = 1'b0; always @ (posedge clk or negedge rstn) if (~rstn) rx_d1 <= 1'b0; else rx_d1 <= i_uart_rx; //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // count continuous '1' //--------------------------------------------------------------------------------------------------------------------------------------------------------------- reg [31:0] count1 = 0; always @ (posedge clk or negedge rstn) if (~rstn) begin count1 <= 0; end else begin if (rx_d1) count1 <= (count1 < 'hFFFFFFFF) ? (count1 + 1) : count1; else count1 <= 0; end //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // main FSM //--------------------------------------------------------------------------------------------------------------------------------------------------------------- localparam [ 3:0] TOTAL_BITS_MINUS1 = (PARITY == "ODD" || PARITY == "EVEN") ? 4'd9 : 4'd8; localparam [ 1:0] S_IDLE = 2'd0 , S_RX = 2'd1 , S_STOP_BIT = 2'd2 ; reg [ 1:0] state = S_IDLE; reg [ 8:0] rxbits = 9'b0; reg [ 3:0] rxcnt = 4'd0; reg [31:0] cycle = 1; reg [32:0] countp = 33'h1_0000_0000; // countp>=0x100000000 means '1' is majority , countp<0x100000000 means '0' is majority wire rxbit = countp[32]; // countp>=0x100000000 corresponds to countp[32]==1, countp<0x100000000 corresponds to countp[32]==0 wire [ 7:0] rbyte = (PARITY == "ODD" ) ? rxbits[7:0] : (PARITY == "EVEN") ? rxbits[7:0] : /*(PARITY == "NONE")*/ rxbits[8:1] ; wire parity_correct = (PARITY == "ODD" ) ? ((~(^(rbyte))) == rxbits[8]) : (PARITY == "EVEN") ? ( (^(rbyte)) == rxbits[8]) : /*(PARITY == "NONE")*/ 1'b1 ; always @ (posedge clk or negedge rstn) if (~rstn) begin state <= S_IDLE; rxbits <= 9'b0; rxcnt <= 4'd0; cycle <= 1; countp <= 33'h1_0000_0000; end else begin case (state) S_IDLE : begin if ((count1 >= THREE_QUARTER_BAUD_CYCLES) && (rx_d1 == 1'b0)) // receive a '0' which is followed by continuous '1' for half baud cycles state <= S_RX; rxcnt <= 4'd0; cycle <= 2; // we've already receive a '0', so here cycle = 2 countp <= (33'h1_0000_0000 - 33'd1); // we've already receive a '0', so here countp = initial_value - 1 end S_RX : if ( cycle < cycles[rxcnt] ) begin // cycle loop from 1 to cycles[rxcnt] cycle <= cycle + 1; countp <= rx_d1 ? (countp + 33'd1) : (countp - 33'd1); end else begin cycle <= 1; // reset counter countp <= 33'h1_0000_0000; // reset counter if ( rxcnt < TOTAL_BITS_MINUS1 ) begin // rxcnt loop from 0 to TOTAL_BITS_MINUS1 rxcnt <= rxcnt + 4'd1; if ((rxcnt == 4'd0) && (rxbit == 1'b1)) // except start bit, but get '1' state <= S_IDLE; // RX failed, back to IDLE end else begin rxcnt <= 4'd0; state <= S_STOP_BIT; end rxbits <= {rxbit, rxbits[8:1]}; // put current rxbit to MSB of rxbits, and right shift other bits end default : // S_STOP_BIT if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin // cycle loop from 1 to THREE_QUARTER_BAUD_CYCLES cycle <= cycle + 1; end else begin cycle <= 1; // reset counter state <= S_IDLE; // back to IDLE end endcase end //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // RX result byte //--------------------------------------------------------------------------------------------------------------------------------------------------------------- reg f_tvalid = 1'b0; reg [7:0] f_tdata = 8'h0; always @ (posedge clk or negedge rstn) if (~rstn) begin f_tvalid <= 1'b0; f_tdata <= 8'h0; end else begin f_tvalid <= 1'b0; f_tdata <= 8'h0; if (state == S_STOP_BIT) begin if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin end else begin if ((count1 >= HALF_BAUD_CYCLES) && parity_correct) begin // stop bit have enough '1', and parity correct f_tvalid <= 1'b1; f_tdata <= rbyte; // received a correct byte, output it end end end end //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // RX fifo //--------------------------------------------------------------------------------------------------------------------------------------------------------------- wire f_tready; generate if (FIFO_EA <= 0) begin // no RX fifo assign f_tready = o_tready; always @ (*) o_tvalid = f_tvalid; always @ (*) o_tdata = f_tdata; end else begin // TX fifo localparam EA = (FIFO_EA <= 2) ? 2 : FIFO_EA; reg [7:0] buffer [ ((1<= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 ) + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 ) + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 ) + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 ) + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 ) + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 ) + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 ) + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 ) + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 ) + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ; localparam real ideal_time_ns = ((index+1)*1000000000.0/BAUD_RATE); localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ); localparam real uncertainty = (1000000000.0/CLK_FREQ); localparam real error = ( (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns) ) + uncertainty; localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0; initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin $display("uart_rx : t%-2d- t0 = %.0f ns (ideal) %.0f +- %.0f ns (actual). error=%.0f ns relative_error=%.3f%%" , (index+1) , ideal_time_ns , actual_time_ns, uncertainty, error, relative_error_percent ); if ( relative_error_percent > 8.0 ) begin $error("relative_error is too large"); $stop; end // if relative error larger than 8% end end endgenerate endmodule ================================================ FILE: RTL/uart_tx.v ================================================ //-------------------------------------------------------------------------------------------------------- // Module : uart_tx // Type : synthesizable, IP's top // Standard: Verilog 2001 (IEEE1364-2001) // Function: input AXI-stream (configurable data width), // output UART signal //-------------------------------------------------------------------------------------------------------- module uart_tx #( // clock frequency parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz // UART format parameter BAUD_RATE = 115200, // Unit : Hz parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" parameter STOP_BITS = 2, // can be 1, 2, 3, 4, ... // AXI stream data width parameter BYTE_WIDTH = 1, // can be 1, 2, 3, 4, ... // TX fifo depth parameter FIFO_EA = 0, // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... // do you want to send extra byte after each AXI-stream transfer or packet? parameter EXTRA_BYTE_AFTER_TRANSFER = "", // specify a extra byte to send after each AXI-stream transfer. when ="", do not send this extra byte parameter EXTRA_BYTE_AFTER_PACKET = "" // specify a extra byte to send after each AXI-stream packet . when ="", do not send this extra byte ) ( input wire rstn, input wire clk, // input stream : AXI-stream slave. Associated clock = clk output wire i_tready, input wire i_tvalid, input wire [8*BYTE_WIDTH-1:0] i_tdata, input wire [ BYTE_WIDTH-1:0] i_tkeep, input wire i_tlast, // UART TX output signal output reg o_uart_tx ); //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // TX fifo //--------------------------------------------------------------------------------------------------------------------------------------------------------------- wire f_tready; reg f_tvalid; reg [8*BYTE_WIDTH-1:0] f_tdata; reg [ BYTE_WIDTH-1:0] f_tkeep; reg f_tlast; generate if (FIFO_EA <= 0) begin // no TX fifo assign i_tready = f_tready; always @ (*) f_tvalid = i_tvalid; always @ (*) f_tdata = i_tdata; always @ (*) f_tkeep = i_tkeep; always @ (*) f_tlast = i_tlast; end else begin // TX fifo localparam EA = (FIFO_EA<=2) ? 2 : FIFO_EA; localparam DW = ( 1 + BYTE_WIDTH + 8*BYTE_WIDTH ); // 1-bit tlast, (BYTE_WIDTH)-bit tkeep, (8*BYTE_WIDTH)-bit tdata reg [DW-1:0] buffer [ ((1<= ('hFFFFFFFF-9-PARITY_BITS)) ? 'hFFFFFFFF : (PARITY_BITS+STOP_BITS+9); localparam [ 0:0] BYTE_T_EN = (EXTRA_BYTE_AFTER_TRANSFER == "") ? 1'b0 : 1'b1; localparam [ 0:0] BYTE_B_EN = (EXTRA_BYTE_AFTER_PACKET == "") ? 1'b0 : 1'b1; localparam [ 7:0] BYTE_T = EXTRA_BYTE_AFTER_TRANSFER; localparam [ 7:0] BYTE_P = EXTRA_BYTE_AFTER_PACKET; //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // function for calculate parity bit //--------------------------------------------------------------------------------------------------------------------------------------------------------------- function [0:0] get_parity; input [7:0] data; begin get_parity = (PARITY == "ODD" ) ? (~(^(data[7:0]))) : (PARITY == "EVEN") ? (^(data[7:0])) : /*(PARITY == "NONE")*/ 1'b1 ; end endfunction //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // main FSM //--------------------------------------------------------------------------------------------------------------------------------------------------------------- localparam [ 1:0] S_IDLE = 2'b01 , // only in state S_IDLE, state[0]==1, the goal is to make f_tready pure register-out S_PREPARE = 2'b00 , S_TX = 2'b10 ; reg [ 1:0] state = S_IDLE; // FSM state register reg [8*BYTE_WIDTH-1:0] data = 0; reg [ BYTE_WIDTH-1:0] keep = 0; reg byte_t_en = 1'b0; reg byte_p_en = 1'b0; reg [ 9:0] txbits = 10'b0; reg [ 31:0] txcnt = 0; reg [ 31:0] cycle = 1; always @ (posedge clk or negedge rstn) if (~rstn) begin state <= S_IDLE; data <= 0; keep <= 0; byte_t_en <= 1'b0; byte_p_en <= 1'b0; txbits <= 10'b0; txcnt <= 0; cycle <= 1; end else begin case (state) S_IDLE : begin state <= f_tvalid ? S_PREPARE : S_IDLE; data <= f_tdata; keep <= f_tkeep; byte_t_en <= BYTE_T_EN; byte_p_en <= BYTE_B_EN & f_tlast; txbits <= 10'b0; txcnt <= 0; cycle <= 1; end S_PREPARE : begin data <= (data >> 8); keep <= (keep >> 1); if ( keep[0] == 1'b1 ) begin txbits <= {get_parity(data[7:0]), data[7:0], 1'b0}; state <= S_TX; end else if ( keep != ZERO_KEEP ) begin state <= S_PREPARE; end else if ( byte_t_en ) begin byte_t_en <= 1'b0; txbits <= {get_parity(BYTE_T), BYTE_T, 1'b0}; state <= S_TX; end else if ( byte_p_en ) begin byte_p_en <= 1'b0; txbits <= {get_parity(BYTE_P), BYTE_P, 1'b0}; state <= S_TX; end else begin state <= S_IDLE; end txcnt <= 0; cycle <= 1; end default : begin // S_TX if (keep[0] == 1'b0) begin data <= (data >> 8); keep <= (keep >> 1); end if ( cycle < ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES) ) begin // cycle loop from 1 to ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES) cycle <= cycle + 1; end else begin cycle <= 1; txbits <= {1'b1, txbits[9:1]}; // right shift txbits, and fill '1' to MSB if ( txcnt < (TOTAL_BITS-1) ) begin // txcnt loop from 0 to (TOTAL_BITS-1) txcnt <= txcnt + 1; end else begin txcnt <= 0; state <= S_PREPARE; end end end endcase end //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // generate UART output //--------------------------------------------------------------------------------------------------------------------------------------------------------------- initial o_uart_tx = 1'b1; always @ (posedge clk or negedge rstn) if (~rstn) o_uart_tx <= 1'b1; else o_uart_tx <= (state == S_TX) ? txbits[0] : 1'b1; //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // generate AXI-stream TREADY //--------------------------------------------------------------------------------------------------------------------------------------------------------------- assign f_tready = state[0]; // (state == S_IDLE) //--------------------------------------------------------------------------------------------------------------------------------------------------------------- // parameter checking //--------------------------------------------------------------------------------------------------------------------------------------------------------------- initial begin if (BYTE_WIDTH <= 0) begin $error("invalid parameter : BYTE_WIDTH<=0"); $stop; end if (STOP_BITS <= 0) begin $error("invalid parameter : STOP_BITS <=0"); $stop; end if (BAUD_CYCLES < 1) begin $error("invalid parameter : BAUD_CYCLES < 1, please use a faster driving clock"); $stop; end $display("uart_tx : parity = %s" , PARITY ); $display("uart_tx : clock period = %.0f ns (%-10d Hz)" , 1000000000.0/CLK_FREQ , CLK_FREQ ); $display("uart_tx : baud rate period = %.0f ns (%-10d Hz)" , 1000000000.0/BAUD_RATE , BAUD_RATE); $display("uart_tx : baud cycles = %-10d" , BAUD_CYCLES ); $display("uart_tx : baud cycles frac = %-10d" , BAUD_CYCLES_FRAC ); if (PARITY == "ODD" || PARITY == "EVEN") begin $display("uart_tx : __ ____ ____ ____ ____ ____ ____ ____ ____________ "); $display("uart_tx : wave \\____/____X____X____X____X____X____X____X____X____/ "); $display("uart_tx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P | "); $display("uart_tx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 "); $display("uart_tx :"); end else begin $display("uart_tx : __ ____ ____ ____ ____ ____ ____ ____ _______ "); $display("uart_tx : wave \\____/____X____X____X____X____X____X____X____/ "); $display("uart_tx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | "); $display("uart_tx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 "); $display("uart_tx :"); end end generate genvar index, i; for (index=0; index<=9; index=index+1) begin : print_and_check_time localparam cycles_acc = ( (index >= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 ) + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 ) + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 ) + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 ) + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 ) + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 ) + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 ) + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 ) + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 ) + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ; localparam real ideal_time_ns = ((index+1)*1000000000.0/BAUD_RATE); localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ); localparam real error = (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns); localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0; initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin $display("uart_tx : t%-2d- t0 = %.0f ns (ideal) %.0f ns (actual). error=%.0f ns relative_error=%.3f%%" , (index+1) , ideal_time_ns , actual_time_ns, error, relative_error_percent ); if ( relative_error_percent > 3.0 ) begin $error("relative_error is too large"); $stop; end // if relative error larger than 3% end end endgenerate endmodule ================================================ FILE: SIM/tb_axis_inc_source.v ================================================ module tb_axis_inc_source # ( parameter BYTE_WIDTH = 4 ) ( input wire rstn, input wire clk, // AXI-stream master input wire o_tready, output reg o_tvalid, output reg [8*BYTE_WIDTH-1:0] o_tdata, output reg [ BYTE_WIDTH-1:0] o_tkeep, output reg o_tlast ); //----------------------------------------------------------------------------------------------------------------------------- // function : generate random unsigned integer //----------------------------------------------------------------------------------------------------------------------------- function [31:0] randuint; input [31:0] min; input [31:0] max; begin randuint = $random; if ( min != 0 || max != 'hFFFFFFFF ) randuint = (randuint % (1+max-min)) + min; end endfunction initial {o_tvalid, o_tdata, o_tkeep, o_tlast} = 0; reg [BYTE_WIDTH-1:0] keep = 0; reg [7:0] next_byte = 8'h0; reg [31:0] delay = 100000; integer i; always @ (posedge clk or negedge rstn) if (~rstn) begin {o_tvalid, o_tdata, o_tkeep, o_tlast} <= 0; next_byte = 8'h0; delay <= 100000; end else begin if (delay > 0) begin delay <= delay - 1; end else begin if (o_tready | ~o_tvalid) begin if ( randuint(0,4) == 0 ) begin o_tvalid <= 1'b1; keep = randuint(0, 'hFFFFFFFF); for (i=0; i