[ { "path": "README.md", "content": "# MobileNet in FPGA\nGenerator of verilog description for FPGA MobileNet implementation.\nThere are several pre-trained models available for frequent tasks like detection of people, cars and animals.\nYou can train your own model easily on your dataset using code from this repository and have the same very fast detector on FPGA working in real time for your own task.\n\n\n## Software requirements\nPython 3.*, keras 2.2.4, tensorflow, kito\n\n\n## Hardware requirements\n1) TFT-screen ILI9341 Size: 2.8\", Resolution: 240x320, Interface: SPI\n2) Camera OV5640. Active array size: 2592 x 1944\n3) OpenVINO Starter Kit. Cyclone V (301K LE, 13,917 Kbits embedded memory)\n\n## Demo\n\n[![Youtube demo](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/Youtube-Screenshot.jpg)](https://www.youtube.com/watch?v=EQ9MJnWeHlo)\n\n## How to run\n1) `python3 r01_prepare_open_images_dataset.py` - it will create training files using [Open Images Dataset (OID)](https://storage.googleapis.com/openimages/web/index.html).\n2) `python3 r02_train_mobilenet.py` - run training process. Will create weights for model and output accuracy of model.\n3) `python3 r03_mobilenet_v1_reduce_and_scale_model.py` - batchnorm fusion and rescale model on range (0, 1) instead of (0, 6). Returns new rescaled model\n\nNote: You can skip part 1, 2 and 3 if you use our pretrained weight files below\n\n4) `python3 r04_find_optimal_bit_for_weights.py` - code to find optimal bit for feature maps, weights and biases, also returns maximum overflow for weights and biases over 1.0 value.\n5) `python3 r05_gen_weights_in_verilog_format.py` - generate weights in verliog format using optimal bits from previous step \n6) `python3 r06_generate_debug_data.py` - generate intermediate feature maps for each layer and details about first pixel calculation (can be used for debug)\n7) `python3 r07_generate_verilog_for_mobilenet.py` - generate verilog based on given model and parameters like number of convolution blocks\n\n## Updates\n\n* **2019.10.04** We greatly improved speed of image reading and preprocessing. Now it takes only 5% of total time instead of 77% earlier. Speed for 8 convolution version of device increased from ~10 FPS up to ~ 40 FPS.\n\n## Pre-trained models\n\n| | People detector (128px) | Cars detector (128px) | Animals detector (128px) |\n| --- | --- | --- | --- |\n| Accuracy (%) | 84.42 | 96.31 | 89.67 |\n| Init model (can be used for training and fine-tuning) | [people.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38.h5) | [cars.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67.h5) | [animals.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5) |\n| Reduced and rescaled model | [people.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5) | [cars.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5) | [animals.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5) |\n| Optimal bits found | 12, 11, 10, 7, 3 | 10, 9, 8, 7, 3 | 12, 11, 10, 7, 3 |\n| Quartus project (verilog) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_people.zip) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_cars.zip) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_animals.zip) |\n\n## Connection of peripherals\n\n![Connection of peripherals](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/Connection-of-Periferals.png)\n\n## Writing weights in memory\n\n[See guide](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/docs/Writing_weights_to_memory_using_UART.md)\n\n## Description of method\n\n[Innovate FPGA](http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=EM031)" }, { "path": "a00_common_functions.py", "content": "# Util functions\nimport pickle\nimport gzip\nimport cv2\nimport numpy as np\nimport pandas as pd\nimport os\nimport glob\nimport random\n\nROOT_PATH = os.path.dirname(os.path.realpath(__file__)) + '/'\nMODEL_PATH = ROOT_PATH + 'models/'\nif not os.path.isdir(MODEL_PATH):\n os.mkdir(MODEL_PATH)\nCACHE_PATH = ROOT_PATH + 'cache/'\nif not os.path.isdir(CACHE_PATH):\n os.mkdir(CACHE_PATH)\n\n\ndef save_in_file(arr, file_name):\n pickle.dump(arr, gzip.open(file_name, 'wb+', compresslevel=3))\n\n\ndef load_from_file(file_name):\n return pickle.load(gzip.open(file_name, 'rb'))\n\n\ndef show_image(im, name='image'):\n cv2.imshow(name, im.astype(np.uint8))\n cv2.waitKey(0)\n cv2.destroyAllWindows()\n\n\ndef show_resized_image(P, w=1000, h=1000):\n res = cv2.resize(P.astype(np.uint8), (w, h), interpolation=cv2.INTER_CUBIC)\n show_image(res)\n\n\ndef relu_1(x):\n from keras.activations import relu\n return relu(x, max_value=1.0)\n\n\ndef save_history(history, path, columns=('loss', 'val_loss')):\n import matplotlib.pyplot as plt\n import pandas as pd\n s = pd.DataFrame(history.history)\n s.to_csv(path + '.csv')\n plt.plot(s[list(columns)])\n plt.savefig(path + '.png')\n plt.close()\n\n\ndef get_model(weights_path):\n from keras.models import load_model\n print('Load: {}'.format(weights_path))\n model = load_model(weights_path, custom_objects={'relu_1': relu_1})\n print('Number of layers: {}'.format(len(model.layers)))\n return model\n\n\ndef get_model_memory_usage(batch_size, model):\n import numpy as np\n from keras import backend as K\n\n shapes_mem_count = 0\n for l in model.layers:\n single_layer_mem = 1\n for s in l.output_shape:\n if s is None:\n continue\n single_layer_mem *= s\n shapes_mem_count += single_layer_mem\n\n trainable_count = np.sum([K.count_params(p) for p in set(model.trainable_weights)])\n non_trainable_count = np.sum([K.count_params(p) for p in set(model.non_trainable_weights)])\n\n number_size = 4.0\n if K.floatx() == 'float16':\n number_size = 2.0\n if K.floatx() == 'float64':\n number_size = 8.0\n\n total_memory = number_size*(batch_size*shapes_mem_count + trainable_count + non_trainable_count)\n gbytes = np.round(total_memory / (1024.0 ** 3), 3)\n return gbytes" }, { "path": "a01_oid_utils.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\nimport platform\nfrom PIL import Image\nfrom a00_common_functions import *\n\n# Paths and constants\nif platform.processor() == 'Intel64 Family 6 Model 79 Stepping 1, GenuineIntel':\n DATASET_PATH = 'E:/Projects_M2/2019_06_Google_Open_Images/input/'\nelse:\n DATASET_PATH = 'E:/Projects_2TB/2019_06_Google_Open_Images/input/'\nSTORAGE_PATH_TRAIN = DATASET_PATH + 'train/'\nSTORAGE_PATH_TEST = DATASET_PATH + 'test/'\nSTORAGE_PATH_VALID = DATASET_PATH + 'validation/'\nOID_CLASS_DESCRIPTION = DATASET_PATH + 'data_detection/challenge-2019-classes-description-500.csv'\nOID_ANNOTATIONS_TRAIN = DATASET_PATH + 'data_detection/challenge-2019-train-detection-bbox.csv'\nOID_ANNOTATIONS_VALID = DATASET_PATH + 'data_detection/challenge-2019-validation-detection-bbox.csv'\n\n\ndef get_model_memory_usage(batch_size, model):\n import numpy as np\n from keras import backend as K\n\n shapes_mem_count = 0\n for l in model.layers:\n single_layer_mem = 1\n for s in l.output_shape:\n if s is None:\n continue\n single_layer_mem *= s\n shapes_mem_count += single_layer_mem\n\n trainable_count = np.sum([K.count_params(p) for p in set(model.trainable_weights)])\n non_trainable_count = np.sum([K.count_params(p) for p in set(model.non_trainable_weights)])\n\n number_size = 4.0\n if K.floatx() == 'float16':\n number_size = 2.0\n if K.floatx() == 'float64':\n number_size = 8.0\n\n total_memory = number_size*(batch_size*shapes_mem_count + trainable_count + non_trainable_count)\n gbytes = np.round(total_memory / (1024.0 ** 3), 3)\n return gbytes\n\n\ndef get_description_for_labels():\n out = open(OID_CLASS_DESCRIPTION)\n lines = out.readlines()\n ret_1, ret_2 = dict(), dict()\n for l in lines:\n arr = l.strip().split(',')\n ret_1[arr[0]] = arr[1]\n ret_2[arr[1]] = arr[0]\n return ret_1, ret_2\n\n\ndef random_intensity_change(img, max_change):\n img = img.astype(np.float32)\n for j in range(3):\n delta = random.randint(-max_change, max_change)\n img[:, :, j] += delta\n img[img < 0] = 0\n img[img > 255] = 255\n return img\n\n\ndef random_rotate(image, max_angle):\n cols = image.shape[1]\n rows = image.shape[0]\n\n angle = random.uniform(-max_angle, max_angle)\n M = cv2.getRotationMatrix2D((cols // 2, rows // 2), angle, 1)\n dst = cv2.warpAffine(image, M, (cols, rows), borderMode=cv2.BORDER_REFLECT)\n return dst\n\n\ndef read_single_image(path):\n try:\n img = np.array(Image.open(path))\n except:\n try:\n img = cv2.cvtColor(cv2.imread(path), cv2.COLOR_BGR2RGB)\n except:\n print('Fail')\n return None\n\n if len(img.shape) == 2:\n img = cv2.cvtColor(img, cv2.COLOR_GRAY2RGB)\n\n if img.shape[2] == 2:\n img = img[:, :, :1]\n\n if img.shape[2] == 1:\n img = np.concatenate((img, img, img), axis=2)\n\n if img.shape[2] > 3:\n img = img[:, :, :3]\n\n return img\n\n\ndef read_image_bgr_fast(path):\n img2 = cv2.imread(path)\n return img2\n\n\ndef prepare_training_csv(type, true_labels_enc, output_path, side_size=128, min_class_size=5):\n print('Go for: {} True labels: {}'.format(type, true_labels_enc))\n if type == 'train':\n boxes = pd.read_csv(OID_ANNOTATIONS_TRAIN)\n else:\n boxes = pd.read_csv(OID_ANNOTATIONS_VALID)\n print('Initial boxes: {}'.format(len(boxes)))\n image_ids = boxes['ImageID'].unique()\n print('Unique images: {}'.format(len(image_ids)))\n boxes_part = boxes[boxes['LabelName'].isin(true_labels_enc)]\n print('Potential needed class boxes: {}'.format(len(boxes_part)))\n print('Potential images with class: {}'.format(len(boxes_part['ImageID'].unique())))\n\n images_with_needed_class = set()\n for index, row in boxes_part.iterrows():\n x1 = row['XMin']\n x2 = row['XMax']\n y1 = row['YMin']\n y2 = row['YMax']\n if (x2-x1)*side_size >= min_class_size and (y2-y1)*side_size >= min_class_size:\n images_with_needed_class |= {row['ImageID']}\n print('Images with class reduced: {}'.format(len(images_with_needed_class)))\n no_class = list(set(image_ids) - set(images_with_needed_class))\n print('Images without class: {}'.format(len(no_class)))\n\n out = open(output_path, 'w')\n out.write('id,target\\n')\n for id in sorted(list(images_with_needed_class)):\n out.write(id + ',1\\n')\n for id in sorted(list(no_class)):\n out.write(id + ',0\\n')\n out.close()\n\n\ndef check_validation_set(input_csv):\n s = pd.read_csv(input_csv)\n\n print('Go for true')\n s_true = s[s['target'] == 1]\n ids_true = list(s_true['id'].values)\n for id in ids_true[:10]:\n img = cv2.imread(STORAGE_PATH_VALID + id + '.jpg')\n show_image(img)\n\n print('Go for false')\n s_true = s[s['target'] == 0]\n ids_true = list(s_true['id'].values)\n for id in ids_true[:10]:\n img = cv2.imread(STORAGE_PATH_VALID + id + '.jpg')\n show_image(img)\n\n\ndef check_train_set(input_csv):\n s = pd.read_csv(input_csv)\n\n print('Go for true')\n s_true = s[s['target'] == 1]\n ids_true = list(s_true['id'].values)\n for id in ids_true[:10]:\n img = cv2.imread(STORAGE_PATH_TRAIN + id[:3] + '/' + id + '.jpg')\n show_image(img)\n\n print('Go for false')\n s_true = s[s['target'] == 0]\n ids_true = list(s_true['id'].values)\n for id in ids_true[:10]:\n img = cv2.imread(STORAGE_PATH_TRAIN + id[:3] + '/' + id + '.jpg')\n show_image(img)\n\n\ndef get_class_labels(true_labels):\n d1, d2 = get_description_for_labels()\n arr = []\n for t in true_labels:\n arr.append(d2[t])\n print(arr)\n return arr\n" }, { "path": "docs/Writing_weights_to_memory_using_UART.md", "content": "The [UART](https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter) port is used to write the neural net weights to the FPGA memory. And the weights are transferred directly from \nthe PC using the Python language. First you need to connect all the necessary wires to OpenVino. See picture below.\n\n![Wires](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/FPGA-Img-01.jpg)\n\nNext, turn on the device. Then launch Quartus Prime (we used version 18.0) and flash the entire project \nusing Programmer. Next, run a special Python script: \n[data_uart_to_fpga.py](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/utils/data_uart_to_fpga.py). \nMake sure that your folder with weights is next to the executable file and has the correct name.\nDepending on what weights you need - for people, animals or cars - select the appropriate file. \nIt must be written in the code [WEIGHT_FILE_TO_USE](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/utils/data_uart_to_fpga.py#L4). \nIf everything is done correctly then progress will go.\n\n![Wires](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/FPGA-Img-04.png)\n\nUpon completion of loading weights, an image from the camera will appear on the screen and the \nneural network will start to recognize it. The result will be displayed in the upper left corner \nin red (there is an required object) or in green (the required object is missing)." }, { "path": "r01_prepare_open_images_dataset.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n'''\nPrepare dataset for different classes from Open Images Dataset (OID) from google\n1) Class must be at least 5px size (for 128x128 image)\n'''\n\n\nif __name__ == '__main__':\n import os\n gpu_use = 0\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n\nfrom a01_oid_utils import *\n\n# Definition for people\nTRUE_LABELS_PEOPLE = ['Person', 'Man', 'Woman', 'Boy', 'Girl', 'Human body', 'Human eye', 'Skull', 'Human head', 'Human face',\n 'Human mouth', 'Human ear', 'Human nose', 'Human hair', 'Human hand', 'Human foot', 'Human arm', 'Human leg',\n 'Human beard']\nTRUE_LABELS_PEOPLE_ENC = ['/m/01g317', '/m/04yx4', '/m/03bt1vf', '/m/01bl7v', '/m/05r655', '/m/02p0tk3',\n '/m/014sv8', '/m/016m2d', '/m/04hgtk', '/m/0dzct', '/m/0283dt1', '/m/039xj_',\n '/m/0k0pj', '/m/03q69', '/m/0k65p', '/m/031n1', '/m/0dzf4', '/m/035r7c', '/m/015h_t']\n\n# Definition for cars\nTRUE_LABELS_CAR = ['Car', 'Van', 'Taxi', 'Limousine', 'Truck', 'Bus', 'Ambulance']\nTRUE_LABELS_CAR_ENC = ['/m/0k4j', '/m/0h2r6', '/m/0pg52', '/m/01lcw4', '/m/07r04', '/m/01bjv', '/m/012n7d']\n\n# Definition for animals\nTRUE_LABELS_ANIMAL = ['Animal', 'Bird', 'Woodpecker', 'Blue jay', 'Ostrich', 'Penguin', 'Raven', 'Chicken',\n 'Eagle', 'Owl', 'Duck', 'Canary', 'Goose', 'Swan', 'Falcon', 'Parrot', 'Sparrow',\n 'Turkey', 'Invertebrate', 'Tick', 'Centipede', 'Marine invertebrates', 'Starfish',\n 'Lobster', 'Jellyfish', 'Shrimp', 'Crab', 'Insect', 'Bee', 'Beetle', 'Ladybug',\n 'Ant', 'Moths and butterflies', 'Caterpillar', 'Butterfly', 'Dragonfly', 'Spider',\n 'Oyster', 'Snail', 'Bat', 'Carnivore', 'Bear', 'Brown bear', 'Polar bear', 'Cat',\n 'Fox', 'Jaguar', 'Lynx', 'Tiger', 'Lion', 'Dog', 'Leopard', 'Cheetah', 'Otter',\n 'Raccoon', 'Camel', 'Cattle', 'Giraffe', 'Rhinoceros', 'Goat', 'Horse', 'Hamster',\n 'Kangaroo', 'Mouse', 'Pig', 'Rabbit', 'Squirrel', 'Sheep', 'Zebra', 'Monkey', 'Deer',\n 'Elephant', 'Porcupine', 'Bull', 'Antelope', 'Mule', 'Marine mammal', 'Dolphin', 'Whale',\n 'Sea lion', 'Harbor seal', 'Alpaca', 'Reptile', 'Dinosaur', 'Lizard', 'Snake', 'Turtle',\n 'Tortoise', 'Sea turtle', 'Crocodile', 'Frog', 'Fish', 'Goldfish', 'Shark', 'Seahorse',\n 'Shellfish']\n\nTRUE_LABELS_ANIMAL_ENC = ['/m/0jbk', '/m/015p6', '/m/01dy8n', '/m/01f8m5', '/m/05n4y', '/m/05z6w', '/m/06j2d',\n '/m/09b5t', '/m/09csl', '/m/09d5_', '/m/09ddx', '/m/0ccs93', '/m/0dbvp', '/m/0dftk',\n '/m/0f6wt', '/m/0gv1x', '/m/0h23m', '/m/0jly1', '/m/03xxp', '/m/0175cv', '/m/019h78',\n '/m/03hl4l9', '/m/01h8tj', '/m/0cjq5', '/m/0d8zb', '/m/0ll1f78', '/m/0n28_', '/m/03vt0',\n '/m/01h3n', '/m/020jm', '/m/0gj37', '/m/0_k2', '/m/0d_2m', '/m/0cydv', '/m/0cyf8',\n '/m/0ft9s', '/m/09kmb', '/m/0_cp5', '/m/0f9_l', '/m/01h44', '/m/01lrl', '/m/01dws',\n '/m/01dxs', '/m/0633h', '/m/01yrx', '/m/0306r', '/m/0449p', '/m/04g2r', '/m/07dm6',\n '/m/096mb', '/m/0bt9lr', '/m/0c29q', '/m/0cd4d', '/m/0cn6p', '/m/0dq75', '/m/01x_v',\n '/m/01xq0k1', '/m/03bk1', '/m/03d443', '/m/03fwl', '/m/03k3r', '/m/03qrc', '/m/04c0y',\n '/m/04rmv', '/m/068zj', '/m/06mf6', '/m/071qp', '/m/07bgp', '/m/0898b', '/m/08pbxl',\n '/m/09kx5', '/m/0bwd_0j', '/m/0c568', '/m/0cnyhnx', '/m/0czz2', '/m/0dbzx', '/m/0gd2v',\n '/m/02hj4', '/m/084zz', '/m/0gd36', '/m/02l8p9', '/m/0pcr', '/m/06bt6', '/m/029tx',\n '/m/04m9y', '/m/078jl', '/m/09dzg', '/m/011k07', '/m/0120dh', '/m/09f_2', '/m/09ld4',\n '/m/0ch_cf', '/m/03fj2', '/m/0by6g', '/m/0nybt', '/m/0fbdv']\n\nSIDE_SIZE = 128\nMIN_CLASS_SIZE = 5\n\n\nif __name__ == '__main__':\n # Prepare people CSV\n prepare_training_csv('validation', TRUE_LABELS_PEOPLE_ENC, CACHE_PATH + 'oid_validation_people.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n prepare_training_csv('train', TRUE_LABELS_PEOPLE_ENC, CACHE_PATH + 'oid_train_people.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n\n # Prepare cars CSV\n prepare_training_csv('validation', TRUE_LABELS_CAR_ENC, CACHE_PATH + 'oid_validation_cars.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n prepare_training_csv('train', TRUE_LABELS_CAR_ENC, CACHE_PATH + 'oid_train_cars.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n\n # Prepare animals CSV\n prepare_training_csv('validation', TRUE_LABELS_ANIMAL_ENC, CACHE_PATH + 'oid_validation_animals.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n prepare_training_csv('train', TRUE_LABELS_ANIMAL_ENC, CACHE_PATH + 'oid_train_animals.csv', SIDE_SIZE, MIN_CLASS_SIZE)\n" }, { "path": "r02_train_mobilenet.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n# Train MobileNet with batch generator and augmentations\n# Made for training with tensorflow only\n\nimport os\nimport glob\n\nif __name__ == '__main__':\n # Block to choose GPU\n gpu_use = 2\n print('GPU use: {}'.format(gpu_use))\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n import tensorflow as tf\n config = tf.ConfigProto()\n config.gpu_options.allow_growth = True\n session = tf.Session(config=config)\n\n\nMOBILENET_VERSION = 1\nMOBILENET_ALFA = 0.25\nMOBILENET_INPUT_SIZE = 128\nCHANNEL_TYPE = 'RGB'\n\n\nfrom functools import partial\nfrom keras import backend as K\nfrom keras.optimizers import SGD, Adam\nif MOBILENET_VERSION == 1:\n from keras.applications.mobilenet import MobileNet, preprocess_input\nelse:\n from keras.applications.mobilenet_v2 import MobileNetV2, preprocess_input\nfrom keras.layers.core import Dense\nfrom keras.models import Model\nfrom a01_oid_utils import *\nfrom a00_common_functions import *\nfrom albumentations import *\nimport pandas as pd\nfrom r01_prepare_open_images_dataset import DATASET_PATH\nfrom multiprocessing.pool import ThreadPool\nfrom multiprocessing import cpu_count\nimport random\n\n\ndef strong_aug(p=.5):\n return Compose([\n # RandomRotate90(),\n HorizontalFlip(p=0.5),\n # Transpose(),\n OneOf([\n IAAAdditiveGaussianNoise(),\n GaussNoise(),\n ], p=0.1),\n OneOf([\n MotionBlur(p=.2),\n MedianBlur(blur_limit=3, p=.1),\n Blur(blur_limit=3, p=.1),\n ], p=0.1),\n ShiftScaleRotate(shift_limit=0.0625, scale_limit=0.2, rotate_limit=10, p=0.1),\n OneOf([\n OpticalDistortion(p=0.3),\n GridDistortion(p=0.1),\n IAAPiecewiseAffine(p=0.3),\n ], p=0.1),\n OneOf([\n CLAHE(clip_limit=2),\n IAASharpen(),\n IAAEmboss(),\n ], p=0.3),\n RGBShift(p=0.1, r_shift_limit=(-30, 30), g_shift_limit=(-30, 30), b_shift_limit=(-30, 30)),\n RandomBrightnessContrast(p=0.05),\n HueSaturationValue(p=0.05),\n ToGray(p=0.05),\n JpegCompression(p=0.05, quality_lower=55, quality_upper=99),\n ElasticTransform(p=0.05),\n ], p=p)\n\n\nGLOBAL_AUG = strong_aug(p=1.0)\n\n\ndef process_single_item(id, box_size, validation=True):\n global global_aug\n\n # Important: RGB order!\n if validation is not True:\n file_path = DATASET_PATH + 'train/' + id[:3] + '/' + id + '.jpg'\n else:\n file_path = DATASET_PATH + 'validation/' + id + '.jpg'\n if CHANNEL_TYPE == 'RGB':\n img = read_single_image(file_path)\n else:\n img = read_image_bgr_fast(file_path)\n if img is None:\n img = np.zeros((box_size, box_size, 3), dtype=np.uint8)\n\n if validation is not True:\n # img = GLOBAL_AUG(image=img)['image']\n if 1:\n img = random_intensity_change(img, 10)\n img = random_rotate(img, 10)\n if random.randint(0, 1) == 0:\n # fliplr\n img = img[:, ::-1, :]\n if img.shape[0] != box_size:\n img = cv2.resize(img, (box_size, box_size), interpolation=cv2.INTER_LINEAR)\n\n return img\n\n\ndef batch_generator(X_train, Y_train, batch_size, input_size, prep_input, validation):\n threads = cpu_count() - 1\n p = ThreadPool(threads)\n process_item_func = partial(process_single_item, validation=validation, box_size=input_size)\n\n # Do around 50% of batch to have required class\n X_train_no_class = X_train[Y_train[:, 1] == 0]\n X_train_with_class = X_train[Y_train[:, 1] == 1]\n Y_train_no_class = Y_train[Y_train[:, 1] == 0]\n Y_train_with_class = Y_train[Y_train[:, 1] == 1]\n print('Use threads: {}'.format(threads))\n print(X_train_no_class.shape, X_train_with_class.shape, Y_train_no_class.shape, Y_train_with_class.shape)\n b1 = batch_size // 2\n b2 = batch_size - b1\n\n while True:\n batch_indexes_no_cars = np.random.choice(X_train_no_class.shape[0], b1)\n batch_indexes_with_cars = np.random.choice(X_train_with_class.shape[0], b2)\n batch_image_files = np.concatenate(\n (X_train_no_class[batch_indexes_no_cars].copy(), X_train_with_class[batch_indexes_with_cars].copy())\n )\n batch_classes = np.concatenate(\n (Y_train_no_class[batch_indexes_no_cars].copy(), Y_train_with_class[batch_indexes_with_cars].copy())\n )\n batch_images = p.map(process_item_func, batch_image_files)\n batch_images = np.array(batch_images, np.float32)\n batch_images = prep_input(batch_images)\n yield batch_images, batch_classes\n\n\ndef evaluate_generator(X_test, Y_test, batch_size, input_size, prep_input):\n number_of_batches = X_test.shape[0] // batch_size\n target_size = input_size\n\n i = 0\n while 1:\n batch_images = np.zeros((batch_size, target_size, target_size, 3))\n if i >= number_of_batches:\n print('Current {}'.format(i))\n batch_image_files = X_test[-batch_size:]\n batch_classes = Y_test[-batch_size:]\n else:\n batch_image_files = X_test[i*batch_size:(i+1)*batch_size]\n batch_classes = Y_test[i*batch_size:(i+1)*batch_size]\n\n # Rescale to 128x128\n for j in range(batch_size):\n path = DATASET_PATH + 'validation/' + batch_image_files[j] + '.jpg'\n if CHANNEL_TYPE == 'RGB':\n img = read_single_image(path)\n else:\n img = read_image_bgr_fast(path)\n if img.shape[0] != target_size:\n img = cv2.resize(img, (target_size, target_size), interpolation=cv2.INTER_LINEAR)\n batch_images[j, :, :, :] = img\n batch_images = prep_input(batch_images)\n i += 1\n yield batch_images, batch_classes\n\n\ndef load_train_valid_data(train_csv, valid_csv):\n from keras.utils import to_categorical\n valid = pd.read_csv(valid_csv)\n train = pd.read_csv(train_csv)\n X_train = train['id'].values\n Y_train = to_categorical(train['target'].values, num_classes=2)\n X_valid = valid['id'].values\n Y_valid = to_categorical(valid['target'].values, num_classes=2)\n return X_train, Y_train, X_valid, Y_valid\n\n\ndef train_mobile_net_v1(input_size, train_csv, valid_csv, type):\n from keras.callbacks import EarlyStopping, ModelCheckpoint, CSVLogger, ReduceLROnPlateau\n batch_size = 1024\n nb_classes = 2\n nb_epoch = 1000\n patience = 50\n optimizer = 'Adam'\n learning_rate = 0.0001\n restore = 1\n\n print('Train MobileNet version: {} Input size: {}'.format(MOBILENET_VERSION, input_size))\n print('Train for {} epochs with patience {}. Batch size: {}. Optimizer: {} Learing rate: {}'.\n format(nb_epoch, patience, batch_size, optimizer, learning_rate))\n\n X_train, Y_train, X_valid, Y_valid = load_train_valid_data(train_csv, valid_csv)\n print('Train shape: {}'.format(X_train.shape))\n print('Valid shape: {}'.format(X_valid.shape))\n\n print('Dim ordering:', K.image_dim_ordering())\n if MOBILENET_VERSION == 1:\n alpha = MOBILENET_ALFA\n base_model = MobileNet((input_size, input_size, 3), depth_multiplier=1, alpha=alpha,\n include_top=False, pooling='avg', weights='imagenet')\n else:\n alpha = 0.35\n base_model = MobileNetV2((input_size, input_size, 3), depth_multiplier=1, alpha=alpha,\n include_top=False, pooling='avg', weights='imagenet')\n x = base_model.output\n x = Dense(nb_classes, activation='softmax', name='predictions', use_bias=False)(x)\n model = Model(inputs=base_model.input, outputs=x)\n print(model.summary())\n\n if optimizer == 'SGD':\n optim = SGD(lr=learning_rate, decay=1e-6, momentum=0.9, nesterov=True)\n else:\n optim = Adam(lr=learning_rate)\n model.compile(optimizer=optim, loss='categorical_crossentropy', metrics=['accuracy'])\n print('Model memory usage: {:.3f} GB'.format(get_model_memory_usage(batch_size, model)))\n\n if not os.path.isdir('cache'):\n os.mkdir('cache')\n prefix = 'mobilenet_{}_{:.2f}_{}px_{}'.format(MOBILENET_VERSION, alpha, input_size, type)\n cache_model_path = os.path.join(MODEL_PATH, 'weights_{}.h5'.format(prefix))\n cache_model_path_score = MODEL_PATH + 'weights_{}_'.format(prefix) + 'loss_{val_loss:.4f}_acc_{val_acc:.4f}_epoch_{epoch:02d}_' + '{}.h5'.format(CHANNEL_TYPE)\n if os.path.isfile(cache_model_path) and restore:\n print('Restore weights from cache: {}'.format(cache_model_path))\n model.load_weights(cache_model_path)\n\n history_path = os.path.join(MODEL_PATH,\n 'weights_mobilenet_{}_{:.2f}_{}px_people_v2.csv'.format(MOBILENET_VERSION, alpha,\n input_size))\n callbacks = [\n EarlyStopping(monitor='val_loss', patience=patience, verbose=0),\n ModelCheckpoint(cache_model_path, monitor='val_loss', save_best_only=True, verbose=0),\n ModelCheckpoint(cache_model_path_score, monitor='val_loss', save_best_only=False, verbose=0),\n CSVLogger(MODEL_PATH + 'history_{}_lr_{}_optim_{}_v2.csv'.format(type, learning_rate, optimizer), append=True),\n ReduceLROnPlateau(monitor='val_loss', factor=0.9, patience=5, min_lr=1e-9, min_delta=0.00001, verbose=1, mode='min'),\n ]\n\n steps_per_epoch = 100\n validation_steps = X_valid.shape[0] // batch_size\n history = model.fit_generator(generator=batch_generator(X_train, Y_train, batch_size, input_size, preprocess_input, validation=False),\n epochs=nb_epoch,\n steps_per_epoch=steps_per_epoch,\n validation_data=batch_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input, validation=True),\n validation_steps=validation_steps,\n verbose=1,\n max_queue_size=16,\n initial_epoch=0,\n callbacks=callbacks)\n pd.DataFrame(history.history).to_csv(history_path, index=False)\n\n score = model.evaluate_generator(generator=evaluate_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input),\n steps=X_valid.shape[0] // batch_size,\n max_queue_size=1)\n print('Full validation loss: {:.4f} Full validation accuracy: {:.4f} (For best model)'.format(score[0], score[1]))\n print('Best model stored in {}'.format(cache_model_path))\n return cache_model_path\n\n\ndef evaluate_model(model_path, input_size, train_csv, valid_csv):\n from keras.models import load_model\n print('Load model: {}'.format(model_path))\n model = load_model(model_path)\n\n batch_size = 1024\n X_train, Y_train, X_valid, Y_valid = load_train_valid_data(train_csv, valid_csv)\n print('Train shape: {}'.format(X_train.shape))\n print('Valid shape: {}'.format(X_valid.shape))\n score = model.evaluate_generator(\n generator=evaluate_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input),\n steps=X_valid.shape[0] // batch_size,\n max_queue_size=10, verbose=1)\n print('Full validation loss: {:.4f} Full validation accuracy: {:.4f} (For best model)'.format(score[0], score[1]))\n\n\nif __name__ == '__main__':\n type = 'people'\n # type = 'cars'\n # type = 'animals'\n\n train_csv = CACHE_PATH + 'oid_train_{}.csv'.format(type)\n valid_csv = CACHE_PATH + 'oid_validation_{}.csv'.format(type)\n # best_model_path = train_mobile_net_v1(MOBILENET_INPUT_SIZE, train_csv, valid_csv, type)\n best_model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38.h5'\n evaluate_model(best_model_path, MOBILENET_INPUT_SIZE, train_csv, valid_csv)\n\n\n'''\nAnimals MobileNet v1 (0.25, 128px): \nEp 1: 1563s 16s/step - loss: 0.3970 - acc: 0.8251 - val_loss: 0.4029 - val_acc: 0.8228\nEp 2: 1413s 14s/step - loss: 0.3499 - acc: 0.8453 - val_loss: 0.4436 - val_acc: 0.7914\nEp 3: 1435s 14s/step - loss: 0.3365 - acc: 0.8518 - val_loss: 0.3098 - val_acc: 0.8671\nEp 4: 1425s 14s/step - loss: 0.3279 - acc: 0.8563 - val_loss: 0.3208 - val_acc: 0.8587\nEp 5: 1441s 14s/step - loss: 0.3204 - acc: 0.8597 - val_loss: 0.3832 - val_acc: 0.8334\nEp 6: 1501s 15s/step - loss: 0.3198 - acc: 0.8610 - val_loss: 0.5252 - val_acc: 0.7404\nEp 7: 1506s 15s/step - loss: 0.3170 - acc: 0.8621 - val_loss: 0.3017 - val_acc: 0.8725\nEp 8: 1502s 15s/step - loss: 0.3124 - acc: 0.8643 - val_loss: 0.2960 - val_acc: 0.8740\nEp 14:1464s 15s/step - loss: 0.3020 - acc: 0.8687 - val_loss: 0.2765 - val_acc: 0.8811\nEp 17:1504s 15s/step - loss: 0.2951 - acc: 0.8712 - val_loss: 0.2786 - val_acc: 0.8853\nEp 18:1495s 15s/step - loss: 0.2944 - acc: 0.8733 - val_loss: 0.3067 - val_acc: 0.8671\nEp 19:1547s 15s/step - loss: 0.2923 - acc: 0.8738 - val_loss: 0.3065 - val_acc: 0.8663\nEp 33:1687s 17s/step - loss: 0.2748 - acc: 0.8826 - val_loss: 0.2486 - val_acc: 0.8967 - best\nEp 35:1750s 18s/step - loss: 0.2751 - acc: 0.8817 - val_loss: 0.2686 - val_acc: 0.8831\nEp 38:1789s 18s/step - loss: 0.2729 - acc: 0.8822 - val_loss: 0.2726 - val_acc: 0.8883\nEp 39:1814s 18s/step - loss: 0.2722 - acc: 0.8837 - val_loss: 0.2951 - val_acc: 0.8752\nFull validation loss: 0.2788 Full validation accuracy: 0.8866 (For best model)\n\nCars MobileNet v1 (0.25, 128px): \nEp 1: 1566s 16s/step - loss: 0.3212 - acc: 0.8624 - val_loss: 0.1829 - val_acc: 0.9324\nEp 2: 1429s 14s/step - loss: 0.2557 - acc: 0.8907 - val_loss: 0.1463 - val_acc: 0.9472\nEp 3: 1564s 16s/step - loss: 0.2438 - acc: 0.8968 - val_loss: 0.1586 - val_acc: 0.9424\nEp 4: 1566s 16s/step - loss: 0.2360 - acc: 0.9003 - val_loss: 0.1453 - val_acc: 0.9473\nEp 17:1664s 17s/step - loss: 0.1947 - acc: 0.9208 - val_loss: 0.1188 - val_acc: 0.9586 LR: 0.00090\nEp 21:1726s 17s/step - loss: 0.1908 - acc: 0.9214 - val_loss: 0.1240 - val_acc: 0.9552\nEp 24:1739s 17s/step - loss: 0.1819 - acc: 0.9261 - val_loss: 0.1183 - val_acc: 0.9567 LR: 0.00081\nEp 25:1747s 17s/step - loss: 0.1841 - acc: 0.9246 - val_loss: 0.1406 - val_acc: 0.9500\nEp 47:2232s 22s/step - loss: 0.1657 - acc: 0.9336 - val_loss: 0.1188 - val_acc: 0.9597 \nEp 48:1713s 17s/step - loss: 0.1720 - acc: 0.9299 - val_loss: 0.1183 - val_acc: 0.9556\nEp 49:1544s 15s/step - loss: 0.1662 - acc: 0.9321 - val_loss: 0.1265 - val_acc: 0.9564 \nEp 55:1558s 16s/step - loss: 0.1659 - acc: 0.9334 - val_loss: 0.1134 - val_acc: 0.9613 LR: 0.00045\nEp 67:1584s 16s/step - loss: 0.1576 - acc: 0.9355 - val_loss: 0.1088 - val_acc: 0.9631 LR: 0.0003645 - Best\nEp 72:1625s 16s/step - loss: 0.1528 - acc: 0.9393 - val_loss: 0.1273 - val_acc: 0.9594 LR: 0.00032805\nFull validation loss: 0.0993 Full validation accuracy: 0.9662 (For best model)\n\nPeople MobileNet v1 (0.25, 128px):\nEp 1: 1716s 17s/step - loss: 0.4718 - acc: 0.7887 - val_loss: 0.7406 - val_acc: 0.7069 \nEp 2: 1550s 15s/step - loss: 0.3771 - acc: 0.8368 - val_loss: 0.5902 - val_acc: 0.7573\nEp 20:1625s 16s/step - loss: 0.3022 - acc: 0.8749 - val_loss: 0.3756 - val_acc: 0.8370\nEp 25:1710s 17s/step - loss: 0.2953 - acc: 0.8794 - val_loss: 0.3769 - val_acc: 0.8374\nEp 30:1726s 17s/step - loss: 0.2953 - acc: 0.8775 - val_loss: 0.3741 - val_acc: 0.8411\nEp 32:1748s 17s/step - loss: 0.2911 - acc: 0.8813 - val_loss: 0.3645 - val_acc: 0.8442\nEp 38:1818s 18s/step - loss: 0.2844 - acc: 0.8844 - val_loss: 0.3600 - val_acc: 0.8442 - best\nEp 41:1871s 19s/step - loss: 0.2891 - acc: 0.8810 - val_loss: 0.3963 - val_acc: 0.8322 LR: 8.100000122794882e-05\nEp 43:1895s 19s/step - loss: 0.2851 - acc: 0.8838 - val_loss: 0.3851 - val_acc: 0.8361 LR: 7.289999848580919e-05\nEp 52:1999s 20s/step - loss: 0.2805 - acc: 0.8852 - val_loss: 0.3790 - val_acc: 0.8433\nEp 68:2276s 23s/step - loss: 0.2795 - acc: 0.8862 - val_loss: 0.4114 - val_acc: 0.8298 LR: 4.304672074795235e-05\nFull validation loss: 0.3053 Full validation accuracy: 0.8739 (For best model)\n'''" }, { "path": "r03_mobilenet_v1_reduce_and_scale_model.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n'''\nCode to find reduction coefficients for fixed point representation of weights.\nIt run some images from validation part of dataset to find maximum ranges of values.\nThen convert RELU6 -> RELU1 and rescale some weights and biases.\nAt the end code checks that initial and rescaled models gives totally same result. \n'''\n\nimport os\nimport glob\nfrom a01_oid_utils import read_single_image, DATASET_PATH\n\n\nif __name__ == '__main__':\n # Block to choose backend\n gpu_use = 4\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n print('GPU use: {}'.format(gpu_use))\n\n\nfrom keras import backend as K\nfrom a00_common_functions import *\n\n\n# Coefficient to make safe gap for found range to prevent overflow. Lower - less safe, higher - more rounding error.\nGAP_COEFF = 1.0\n\n\ndef preproc_input_mathmodel(x):\n x /= 127.5\n x -= 1.\n return x\n\n\ndef rescale_weights(model, layer_num, coeff):\n w = model.layers[layer_num].get_weights()\n model.layers[layer_num].set_weights(w / coeff)\n return model\n\n\ndef rescale_weights_with_bias(model, layer_num, coeff, current_scale):\n w, b = model.layers[layer_num].get_weights()\n w_new = w / coeff\n b_new = b / (coeff * current_scale)\n model.layers[layer_num].set_weights((w_new, b_new))\n return model\n\n\ndef rescale_only_bias(model, layer_num, coeff, current_scale):\n w, b = model.layers[layer_num].get_weights()\n w_new = w.copy()\n b_new = b / (coeff * current_scale)\n model.layers[layer_num].set_weights((w_new, b_new))\n return model\n\n\ndef rescale_batch_norm_weights_initital_v1(model, layer_num, coeff, current_scale):\n eps = 0.001\n gamma, beta, run_mean, run_std = model.layers[layer_num].get_weights()\n gamma /= (coeff * current_scale)\n beta /= (coeff * current_scale)\n run_mean /= (coeff * current_scale)\n # Из за квадратного корня и EPS тут не всё так просто. Надо пересчитывать по формуле\n # после решения уравнения sqrt(Mx+e) = sqrt(x+e)/K\n # M = 1/(K*K) + e*(1-K*K)/(K*K*x)\n c2 = (coeff*coeff*current_scale*current_scale)\n # print('Run std: {}'.format(run_std))\n run_std = run_std/c2 + eps*(1-c2)/c2\n model.layers[layer_num].set_weights((gamma, beta, run_mean, run_std))\n return model\n\n\ndef rescale_batch_norm_weights_initital(model, layer_num, coeff, current_scale):\n gamma, beta, run_mean, run_std = model.layers[layer_num].get_weights()\n beta /= (coeff * current_scale)\n run_mean /= current_scale\n gamma /= coeff\n model.layers[layer_num].set_weights((gamma, beta, run_mean, run_std))\n return model\n\n\ndef rescale_dense_weights(model, layer_num, current_scale, coeff):\n weights = model.layers[layer_num].get_weights()\n if len(weights) == 2:\n w, b = weights\n w /= coeff\n b /= (current_scale*coeff)\n model.layers[layer_num].set_weights((w, b))\n else:\n w = weights\n w /= coeff\n model.layers[layer_num].set_weights(w)\n return model\n\n\ndef is_next_relu6(model, layer_id):\n if layer_id >= len(model.layers) - 1:\n return False\n layer = model.layers[layer_id + 1]\n layer_type = layer.__class__.__name__\n if layer_type == 'Activation':\n config = layer.get_config()\n activation = config['activation']\n if activation == 'relu6':\n return True\n return False\n\n\ndef replace_intermediate_layer_in_keras(model, layer_id, new_layer):\n from keras.models import Model\n\n layers = [l for l in model.layers]\n\n x = layers[0].output\n for i in range(1, len(layers)):\n if i == layer_id:\n x = new_layer(x)\n else:\n x = layers[i](x)\n\n new_model = Model(inputs=layers[0].input, outputs=x)\n return new_model\n\n\ndef get_min_max_for_model(model, img_list):\n from keras.models import Model\n from keras.layers import ReLU\n from keras.models import load_model\n from keras.optimizers import Adam\n\n reduction_koeffs = dict()\n current_six_value = 1.0\n current_scale = 6.0\n eps = 0.001\n first_rescale = True\n\n for i in range(len(model.layers)):\n class_name = model.layers[i].__class__.__name__\n layer = model.layers[i]\n print('Layer {}: {} Name {}'.format(i, class_name, layer.name))\n print('In nodes: {}'.format(len(layer._inbound_nodes)))\n w1 = layer.get_weights()\n red_coeff = 1.0\n if len(w1) > 0:\n submodel = Model(inputs=model.inputs, outputs=layer.output)\n print(submodel.summary())\n # out = submodel.predict(img_list)\n if class_name == 'Conv2D':\n config = layer.get_config()\n use_bias = config['use_bias']\n\n print('Min weights value: {} Max weights value: {}'.format(w1[0].min(), w1[0].max()))\n print('Min bias value: {} Max bias value: {}'.format(w1[1].min(), w1[1].max()))\n\n if first_rescale is True:\n model = rescale_weights_with_bias(model, i, 6.0, 1.0)\n first_rescale = False\n else:\n model = rescale_only_bias(model, i, red_coeff, current_scale)\n\n elif class_name == 'DepthwiseConv2D':\n config = layer.get_config()\n print(config)\n use_bias = config['use_bias']\n\n print('Min weights value: {} Max weights value: {}'.format(w1[0].min(), w1[0].max()))\n print('Min bias value: {} Max bias value: {}'.format(w1[1].min(), w1[1].max()))\n\n model = rescale_only_bias(model, i, red_coeff, current_scale)\n\n elif class_name == 'Dense':\n config = layer.get_config()\n use_bias = config['use_bias']\n print('Bias state: {}'.format(use_bias))\n\n if use_bias == False:\n print('We dont need to rescale Dense')\n else:\n print('Bias not supported yet!')\n exit()\n else:\n continue\n\n reduction_koeffs[i] = red_coeff\n print('Layer: {} Scale: {} Reduction coeff: {} Six value: {}'.format(i, current_scale, red_coeff, current_six_value))\n\n if class_name == 'Activation' or class_name == 'ReLU':\n print(layer.get_config())\n\n # Replace model with new activation\n # model = replace_intermediate_layer_in_keras(model, i, Activation(lambda x: relu(x, max_value=current_six_value), name='custom_relu_{}'.format(i)))\n print('Activation six value: {}'.format(current_six_value))\n if abs(current_six_value - 1.0) > 0.0000001:\n print('Not expected six value!')\n exit()\n\n # We always add relu_1 activation (due to scaling algorithm)\n model = replace_intermediate_layer_in_keras(model, i, ReLU(max_value=1.0, name='custom_relu_{}'.format(i)))\n model.compile(optimizer=Adam(), loss='categorical_crossentropy', metrics=['accuracy'])\n model.save(MODEL_PATH + 'debug.h5')\n model = load_model(MODEL_PATH + 'debug.h5')\n print(model.summary)\n\n if i == 0:\n continue\n\n # Check new min, max\n layer = model.layers[i]\n o = layer.output\n submodel = Model(inputs=model.inputs, outputs=o)\n print(submodel.summary())\n out = submodel.predict(img_list)\n print('Rescaled submodel: {} Min out value: {} Max out value: {}'.format(out.shape, out.min(), out.max()))\n\n print('Reduction koeffs: ', reduction_koeffs)\n return model, reduction_koeffs\n\n\ndef load_oid_data(type):\n from keras.utils import to_categorical\n valid = pd.read_csv(CACHE_PATH + 'oid_validation_{}.csv'.format(type))\n train = pd.read_csv(CACHE_PATH + 'oid_train_{}.csv'.format(type))\n X_train = train['id'].values\n Y_train = to_categorical(train['target'].values, num_classes=2)\n X_valid = valid['id'].values\n Y_valid = to_categorical(valid['target'].values, num_classes=2)\n return X_train, Y_train, X_valid, Y_valid\n\n\ndef process_single_item(id, box_size):\n img = read_single_image(DATASET_PATH + 'validation/' + id + '.jpg')\n img = cv2.resize(img, (box_size, box_size), interpolation=cv2.INTER_LINEAR)\n return img\n\n\ndef check_results_are_the_same(model_path1, model_path2, img_list):\n from keras.models import load_model\n modelA = load_model(model_path1)\n modelB = load_model(model_path2)\n\n resA = modelA.predict(img_list)\n resB = modelB.predict(img_list)\n print(resA)\n print(resB)\n print('Probabilities shape: {}'.format(resA.shape))\n\n maxA = resA.argmax(axis=1)\n maxB = resB.argmax(axis=1)\n print(maxA)\n print(maxB)\n print('Answer shape: {}'.format(maxA.shape))\n\n print(np.unique(maxA, return_counts=True))\n print(np.unique(maxB, return_counts=True))\n\n diff = len(maxA[maxA != maxB])\n print('Answer difference: {}'.format(diff))\n print((maxA - maxB).sum())\n\n\nif __name__ == '__main__':\n from kito import reduce_keras_model\n from keras.models import load_model\n from keras.applications.mobilenet import preprocess_input\n\n # Params\n image_limit = 10000\n input_size = 128\n model_type = 'animals'\n model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5'\n model_path_reduced = model_path[:-3] + '_reduced.h5'\n model_path_rescaled = model_path[:-3] + '_reduced_rescaled.h5'\n\n if not os.path.isfile(model_path_reduced):\n model = load_model(model_path)\n model = reduce_keras_model(model, verbose=True)\n model.save(model_path_reduced)\n else:\n model = load_model(model_path_reduced)\n print(model.summary())\n print('Number of layers: {}'.format(len(model.layers)))\n\n X_train, Y_train, X_test, Y_test = load_oid_data(model_type)\n print(X_train.shape, X_test.shape)\n X_test = X_test[:image_limit]\n Y_test = Y_test[:image_limit]\n uni = np.unique(Y_test, return_counts=True)\n print(uni[0].sum())\n\n img_list = []\n for i in range(len(X_test)):\n img = process_single_item(X_test[i], input_size)\n img_list.append(img)\n img_list = np.array(img_list, dtype=np.float32)\n img_list = preprocess_input(img_list)\n print(\"Image limit: {} Images shape: {}\".format(image_limit, img_list.shape))\n\n model, reduction_koeffs = get_min_max_for_model(model, img_list)\n\n overall_reduction_rate = 1.0\n for i in sorted(reduction_koeffs.keys()):\n print('Layer {} reduction coeff: {}'.format(i, reduction_koeffs[i]))\n overall_reduction_rate *= reduction_koeffs[i]\n print('Overall scale change: {}'.format(overall_reduction_rate))\n\n print('Save model in {}'.format(model_path_rescaled))\n model.save(model_path_rescaled)\n\n check_results_are_the_same(model_path, model_path_rescaled, img_list)\n" }, { "path": "r03_remove_batchnorm_layers.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n# Remove layers which is not needed for inference using KITO script\n\nimport os\nimport glob\n\nif __name__ == '__main__':\n # Block to choose GPU\n gpu_use = 4\n print('GPU use: {}'.format(gpu_use))\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n\nfrom kito import reduce_keras_model\nfrom keras.models import load_model\nfrom a00_common_functions import *\n\n\nif __name__ == '__main__':\n model_path_in = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5'\n model_path_out = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_bnfused.h5'\n model = load_model(model_path_in, custom_objects={'relu_1': relu_1})\n model_reduced = reduce_keras_model(model, verbose=True)\n print(model_reduced.summary())\n print('Initial layers: {}'.format(len(model.layers)))\n print('Reduced layers: {}'.format(len(model_reduced.layers)))\n model_reduced.save(model_path_out)\n\n\n'''\nMobileNet V1 (Keras 2.2.4)\nInitial layers: 89\nReduced layers: 62\n'''" }, { "path": "r04_find_optimal_bit_for_weights.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n\n'''\nThis code finds out which bit size for weight lead to zero classification error on fixed point test data\ncomparing with floating point test data. Start search from 8 bits up to 32 bits.\n'''\n\nif __name__ == '__main__':\n import os\n\n # Block to choose backend\n gpu_use = 2\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n\nfrom a00_common_functions import *\nfrom scipy.signal import convolve2d\nimport math\nimport tensorflow as tf\n\nsess = tf.Session()\nsess.run(tf.global_variables_initializer())\ntf.logging.set_verbosity(tf.logging.ERROR)\n\n\n# Note: We suppose that every Conv2D layer has type \"same\"\n# In Tensorflow weight matrices already transposed\ndef my_convolve(input, kernel):\n output = np.zeros((input.shape[0], input.shape[1]))\n zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = input\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n for i in range(1, zero_pad.shape[0] - 1):\n for j in range(1, zero_pad.shape[1] - 1):\n sub = zero_pad[i-1:i+2, j-1:j+2]\n output[i-1, j-1] = np.sum(sub*kernel)\n return output\n\n\ndef my_convolve_fixed_point(input, kernel, bit):\n output = np.zeros((input.shape[0], input.shape[1]))\n zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = input\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n for i in range(1, zero_pad.shape[0] - 1):\n for j in range(1, zero_pad.shape[1] - 1):\n sub = zero_pad[i-1:i+2, j-1:j+2]\n output[i-1, j-1] = np.sum((sub*kernel).astype(np.int64))\n return output\n\n\ndef preprocess_forward(arr, val):\n arr1 = arr.copy().astype(np.float32)\n arr1 /= val\n return arr1\n\n\ndef convert_to_fix_point(arr1, bit):\n arr2 = arr1.copy().astype(np.float32)\n arr2[arr2 < 0] = 0.0\n arr2 = np.round(np.abs(arr2) * (2 ** bit))\n arr3 = arr1.copy().astype(np.float32)\n arr3[arr3 > 0] = 0.0\n arr3 = -np.round(np.abs(-arr3) * (2 ** bit))\n arr4 = arr2 + arr3\n return arr4.astype(np.int64)\n\n\ndef from_fix_point_to_float(arr, bit):\n return arr / (2 ** bit)\n\n\ndef compare_outputs(s1, s2, debug_info=True):\n if s1.shape != s2.shape:\n print('Shape of arrays is different! {} != {}'.format(s1.shape, s2.shape))\n s = np.abs(s1 - s2)\n size = 1\n for dim in np.shape(s): size *= dim\n if debug_info:\n print('Max difference: {}'.format(s.max()))\n print('Avg difference: {}'.format(s.mean()))\n print('Value range float: {} - {}'.format(s1.min(), s1.max()))\n print('Value range fixed: {} - {}'.format(s2.min(), s2.max()))\n\n\ndef print_first_pixel_detailed_calculation_dense(previous_layer_output, wgt_bit, bit_precizion):\n i = 10\n conv_my = 0\n for j in range(0, previous_layer_output.shape[0]):\n print('Pixel {}: {}'.format(j, int(previous_layer_output[j])))\n print('Weight {}: {}'.format(j, wgt_bit[j][i]))\n conv_my += np.right_shift((previous_layer_output[j]*wgt_bit[j][i]).astype(np.int64), bit_precizion)\n if j > 0 and j % 9 == 8:\n print('Current conv_my: {}'.format(conv_my))\n print('Result first pixel: {}'.format(conv_my))\n exit()\n\n\ndef print_first_pixel_detailed_calculation(previous_layer_output, wgt_bit, bit_precizion):\n i = 0\n x = 0\n y = 0\n conv_my = 0\n print('Point: {} X: {} Y: {}'.format(i, x, y))\n print('Weights shape: {}'.format(wgt_bit.shape))\n for j in range(wgt_bit.shape[2]):\n full_image = previous_layer_output[:, :, j]\n zero_pad = np.zeros((full_image.shape[0] + 2, full_image.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = full_image\n pics = zero_pad[x+1-1:x+1+2, y+1-1:y+1+2].astype(np.int64)\n print('Pixel area 3x3 for [{}, {}]:'.format(x, y), pics)\n kernel = wgt_bit[:, :, j, i].copy()\n # Не надо переворачивать для TensorFlow\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n print('Weights {}: {}'.format(j, kernel))\n res = np.sum(np.right_shift((pics*kernel).astype(np.int64), bit_precizion))\n print('Convolution result {}: {}'.format(j, res))\n conv_my += res\n\n print('Overall result: {}'.format(conv_my))\n if conv_my[conv_my > 2 ** bit_precizion].any() or conv_my[conv_my < - 2 ** bit_precizion].any():\n print('Overflow! {}'.format(conv_my[conv_my > 2 ** bit_precizion]))\n exit()\n if conv_my < 0:\n conv_my = 0\n exit()\n\n\ndef mmZeroPadding2D_floating_point(layer, img):\n config = layer.get_config()\n print(config)\n if len(config['padding']) == 1:\n padding1_start = config['padding']\n padding1_end = config['padding']\n padding2_start = config['padding']\n padding2_end = config['padding']\n elif len(config['padding']) == 2:\n padding1_start = config['padding'][0][0]\n padding1_end = config['padding'][0][1]\n padding2_start = config['padding'][1][0]\n padding2_end = config['padding'][1][1]\n out = np.zeros((img.shape[0],\n img.shape[1] + padding1_start + padding1_end,\n img.shape[2] + padding2_start + padding2_end,\n img.shape[3]), dtype=np.float64)\n out[:, padding1_start:out.shape[1] - padding1_end, padding2_start:out.shape[2] - padding2_end, :] = img.copy()\n return out\n\n\ndef mmZeroPadding2D_fixed_point(layer, img):\n config = layer.get_config()\n print(config)\n if len(config['padding']) == 1:\n padding1_start = config['padding']\n padding1_end = config['padding']\n padding2_start = config['padding']\n padding2_end = config['padding']\n elif len(config['padding']) == 2:\n padding1_start = config['padding'][0][0]\n padding1_end = config['padding'][0][1]\n padding2_start = config['padding'][1][0]\n padding2_end = config['padding'][1][1]\n out = np.zeros((img.shape[0],\n img.shape[1] + padding1_start + padding1_end,\n img.shape[2] + padding2_start + padding2_end,\n img.shape[3]), dtype=np.int64)\n out[:, padding1_start:out.shape[1] - padding1_end, padding2_start:out.shape[2] - padding2_end, :] = img.copy()\n return out\n\n\ndef run_TF_Conv2D(img, w, b, strides, padding, type='float'):\n global sess\n in1 = tf.Variable(img.astype(np.float64))\n w1 = tf.Variable(w.astype(np.float64))\n b1 = tf.Variable(b.astype(np.float64))\n data = tf.nn.conv2d(in1, w1, (1,) + strides + (1,), str(padding).upper())\n data = tf.nn.bias_add(data, b1)\n sess.run(tf.global_variables_initializer())\n out = sess.run(data)\n if type == 'float':\n out = out.astype(np.float64)\n else:\n out = out.astype(np.int64)\n tf.reset_default_graph()\n sess = tf.Session()\n return out\n\n\ndef run_TF_Depthwise_Conv2D(img, w, b, strides, padding, type='float'):\n global sess\n in1 = tf.Variable(img.astype(np.float64))\n w1 = tf.Variable(w.astype(np.float64))\n b1 = tf.Variable(b.astype(np.float64))\n data = tf.nn.depthwise_conv2d(in1, w1, (1,) + strides + (1,), str(padding).upper())\n data = tf.nn.bias_add(data, b1)\n sess.run(tf.global_variables_initializer())\n out = sess.run(data)\n if type == 'float':\n out = out.astype(np.float64)\n else:\n out = out.astype(np.int64)\n tf.reset_default_graph()\n sess = tf.Session()\n return out\n\n\ndef mmConv2D_floating_point(layer, img, debug_info):\n global sess\n calc_type = 'tf'\n config = layer.get_config()\n filters = config['filters']\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n if debug_info and 0:\n print(config)\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2 - (img.shape[1] % 2)\n sh2 -= 2 - (img.shape[2] % 2)\n\n if strides == (1, 1):\n out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64)\n elif strides == (2, 2):\n out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64)\n # calc_type = 'slow'\n else:\n print('Not supported conditions yet!')\n exit()\n\n if kernel_size != (3, 3) and kernel_size != (1, 1):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n if debug_info:\n print(w.shape, b.shape, out.shape)\n\n if calc_type == 'slow':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # output filters cycle\n for wi in range(w.shape[-1]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n # convolution\n for i in range(1, zero_pad.shape[0] - 1, strides[0]):\n for j in range(1, zero_pad.shape[1] - 1, strides[0]):\n if kernel_size == (3, 3):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += np.sum(sub * kernel)\n elif kernel_size == (1, 1):\n sub = zero_pad[i, j]\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += sub * kernel[0, 0]\n out[sh0, :, :, wi] += b[wi]\n elif calc_type == 'fast':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # output filters cycle\n for wi in range(w.shape[-1]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj].copy()\n conv_my = convolve2d(slice, kernel, mode=padding)\n out[sh0, :, :, wi] += conv_my\n out[sh0, :, :, wi] += b[wi]\n elif calc_type == 'tf':\n out[...] = run_TF_Conv2D(img, w, b, strides, padding, 'float')\n\n return out\n\n\ndef mmConv2D_fixed_point(layer, img, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info):\n global sess\n calc_type = 'tf'\n # Convolution with fixed point\n config = layer.get_config()\n filters = config['filters']\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n if debug_info and 0:\n print(config)\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2 - (img.shape[1] % 2)\n sh2 -= 2 - (img.shape[2] % 2)\n\n if strides == (1, 1):\n out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.int64)\n elif strides == (2, 2):\n out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.int64)\n else:\n print('Not supported conditions yet!')\n exit()\n\n if kernel_size != (3, 3) and kernel_size != (1, 1):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n if debug_info:\n print(w.shape, b.shape, out.shape)\n\n w = convert_to_fix_point(w.copy(), bit_precizion_weights)\n b = convert_to_fix_point(b.copy(), bit_precizion_bias)\n\n # We need to shift it to sum with result of multiplication\n b <<= bit_precizion_weights + (bit_precizion - bit_precizion_bias)\n\n\n if calc_type == 'slow':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # output filters cycle\n for wi in range(w.shape[-1]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n\n # convolution\n for i in range(1, zero_pad.shape[0] - 1, strides[0]):\n for j in range(1, zero_pad.shape[1] - 1, strides[0]):\n if kernel_size == (3, 3):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += np.sum((sub*kernel).astype(np.int64))\n elif kernel_size == (1, 1):\n sub = zero_pad[i, j]\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += (sub*kernel[0, 0]).astype(np.int64)\n\n out[sh0, :, :, wi] += b[wi]\n\n elif calc_type == 'fast':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # output filters cycle\n for wi in range(w.shape[-1]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj].copy()\n conv_my = convolve2d(slice, kernel, mode=padding)\n out[sh0, :, :, wi] += conv_my\n out[sh0, :, :, wi] += b[wi]\n elif calc_type == 'tf':\n out[...] = run_TF_Conv2D(img, w, b, strides, padding, 'int')\n\n # Shift it back to initial scale\n out = np.right_shift(out.astype(np.int64), bit_precizion_weights)\n\n return out\n\n\ndef mmGlobalAveragePooling2D_floating_point(img):\n # Standard glob pool\n result = np.zeros((img.shape[0], img.shape[-1]))\n for j in range(img.shape[0]):\n for i in range(img.shape[-1]):\n result[j, i] = img[j, :, :, i].mean()\n return result\n\n\ndef mmGlobalAveragePooling2D_fixed_point(img):\n # Standard glob pool\n result = np.zeros((img.shape[0], img.shape[-1]), dtype=np.int64)\n block_size = img.shape[1] * img.shape[2]\n for j in range(img.shape[0]):\n for i in range(img.shape[-1]):\n value = img[j, :, :, i].sum() // block_size\n result[j, i] = value\n return result\n\n\ndef mmActivation_floating_point(layer, img, one_value=1.0, debug_info=False):\n config = layer.get_config()\n activation = config['activation']\n\n if activation != 'relu_1':\n print('Unsupported activation {}!'.format(activation))\n exit()\n\n result = img.copy()\n result[result < 0] = 0.\n result[result > one_value] = one_value\n return result\n\n\ndef mmActivation_fixed_point(layer, img, bit_precizion, debug_info=False):\n config = layer.get_config()\n activation = config['activation']\n\n if activation != 'relu_1':\n print('Unsupported activation {}!'.format(activation))\n exit()\n\n result = img.copy()\n result[result < 0] = 0.\n result[result >= 2 ** bit_precizion] = 2 ** bit_precizion - 1\n return result\n\n\ndef mmReLU_floating_point(layer, img, one_value=1.0, debug_info=False):\n config = layer.get_config()\n max_value = config['max_value']\n\n if max_value != 1:\n print('Unsupported value for ReLU activation {}!'.format(max_value))\n exit()\n\n result = img.copy()\n result[result < 0] = 0.\n result[result > one_value] = one_value\n return result\n\n\ndef mmReLU_fixed_point(layer, img, bit_precizion, debug_info=False):\n config = layer.get_config()\n max_value = config['max_value']\n\n if max_value != 1:\n print('Unsupported value for ReLU activation {}!'.format(max_value))\n exit()\n\n result = img.copy()\n result[result < 0] = 0.\n result[result >= 2 ** bit_precizion] = 2 ** bit_precizion - 1\n return result\n\n\ndef mmDepthwiseConv2D_floating_point(layer, img, debug_info):\n config = layer.get_config()\n calc_type = 'tf'\n # print(config)\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n filters = img.shape[3]\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2 - (img.shape[1] % 2)\n sh2 -= 2 - (img.shape[2] % 2)\n\n if strides == (1, 1):\n out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64)\n elif strides == (2, 2):\n out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64)\n else:\n print('Not supported strides yet: {}'.format(strides))\n exit()\n\n if kernel_size != (3, 3):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n print(w.shape, b.shape, out.shape)\n\n if calc_type == 'slow':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, 0].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n # convolution\n for i in range(1, zero_pad.shape[0] - 1, strides[0]):\n for j in range(1, zero_pad.shape[1] - 1, strides[0]):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n # print((i - 1) // strides[0], (j - 1) // strides[1], wi)\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wj] = np.sum(sub * kernel)\n out[sh0, :, :, wj] += b[wj]\n elif calc_type == 'tf':\n out[...] = run_TF_Depthwise_Conv2D(img, w, b, strides, padding, 'float')\n\n return out\n\n\ndef mmDepthwiseConv2D_fixed_point(layer, img, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info):\n config = layer.get_config()\n calc_type = 'tf'\n # print(config)\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n filters = img.shape[3]\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2 - (img.shape[1] % 2)\n sh2 -= 2 - (img.shape[2] % 2)\n\n if strides == (1, 1):\n out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64)\n elif strides == (2, 2):\n out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64)\n else:\n print('Not supported strides yet: {}'.format(strides))\n exit()\n\n if kernel_size != (3, 3):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n print(w.shape, b.shape, out.shape)\n\n w = convert_to_fix_point(w.copy(), bit_precizion_weights)\n b = convert_to_fix_point(b.copy(), bit_precizion_bias)\n\n # We need to shift it to sum with result of multiplication\n b <<= bit_precizion_weights + (bit_precizion - bit_precizion_bias)\n\n if calc_type == 'slow':\n # Cycle by different batch images\n for sh0 in range(img.shape[0]):\n # input filters cycle\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, 0].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n # convolution\n for i in range(1, zero_pad.shape[0] - 1, strides[0]):\n for j in range(1, zero_pad.shape[1] - 1, strides[0]):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n # print((i - 1) // strides[0], (j - 1) // strides[1], wi)\n out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wj] = np.sum((sub*kernel).astype(np.int64))\n out[sh0, :, :, wj] += b[wj]\n elif calc_type == 'tf':\n out[...] = run_TF_Depthwise_Conv2D(img, w, b, strides, padding, 'int')\n\n # Shift it back to initial scale\n out = np.right_shift(out.astype(np.int64), bit_precizion_weights)\n\n return out\n\n\ndef mmDense_floating_point(layer, img, debug_info):\n config = layer.get_config()\n print(config)\n use_bias = config['use_bias']\n activation = config['activation']\n units = config['units']\n batch_size = img.shape[0]\n\n if use_bias:\n (w, b) = layer.get_weights()\n else:\n (w,) = layer.get_weights()\n\n print('Dense weights shape: {}'.format(w.shape))\n\n if activation != 'softmax':\n print('Activation {} is not supported'.format(activation))\n exit()\n\n if use_bias is True:\n print('Bias currently not supported!')\n exit()\n\n out = np.zeros((batch_size, units))\n for sh0 in range(batch_size):\n for i in range(w.shape[1]):\n for j in range(w.shape[0]):\n out[sh0, i] += img[sh0, j] * w[j, i]\n\n # Softmax activation part\n # We skip it here because we will use max at the end\n if 0:\n for sh0 in range(batch_size):\n maxy = out[sh0].max()\n out[sh0] = np.exp(out[sh0] - maxy)\n sum = out[sh0].sum()\n out[sh0] /= sum\n\n return out\n\n\ndef mmDense_fixed_point(layer, img, bit_precizion, bit_precizion_weights, debug_info):\n config = layer.get_config()\n if debug_info is True:\n print(config)\n use_bias = config['use_bias']\n activation = config['activation']\n units = config['units']\n batch_size = img.shape[0]\n\n if use_bias:\n (w, b) = layer.get_weights()\n else:\n (w,) = layer.get_weights()\n\n if use_bias is True:\n print('Bias currently not supported!')\n exit()\n\n if debug_info is True:\n print('Dense weights shape: {}'.format(w.shape))\n\n if activation != 'softmax':\n print('Activation {} is not supported'.format(activation))\n exit()\n\n w = convert_to_fix_point(w.copy(), bit_precizion_weights)\n\n out = np.zeros((batch_size, units))\n for sh0 in range(batch_size):\n for i in range(w.shape[1]):\n for j in range(w.shape[0]):\n out[sh0, i] += img[sh0, j] * w[j, i]\n\n # Divide by 2^bp\n out = np.right_shift(out.astype(np.int64), bit_precizion_weights)\n\n if out[out > 2 ** bit_precizion].any() or out[out < - 2 ** bit_precizion].any():\n if out[out > 2 ** bit_precizion].any():\n print('Warning overflow on current level! {}'.format(out[out > 2 ** bit_precizion]))\n else:\n print('Warning overflow on current level! {}'.format(out[out < - 2 ** bit_precizion]))\n print('Max is {}'.format(2 ** bit_precizion))\n\n # We don't need to find softmax here, since we only need the\n # position of max value, which will be the same\n\n return out\n\n\n# bit_precizion - fixed point accuracy in bits\ndef go_mat_model(model, images, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info=True):\n\n level_out = dict()\n level_out_reduced = dict()\n print_pixel_calc = False\n\n # Hack before we solve problem with exact 1.0 value\n one_value = (2 ** bit_precizion - 1) / (2 ** bit_precizion)\n\n for level_id in range(len(model.layers)):\n layer = model.layers[level_id]\n layer_type = layer.__class__.__name__\n if debug_info:\n print('Layer name: {} Layer type: {}'.format(layer.name, layer_type))\n if level_id > 0:\n print('Input shape: {}'.format(level_out[level_id-1].shape))\n\n if layer_type == 'InputLayer':\n level_out[level_id] = images.copy()\n level_out_reduced[level_id] = convert_to_fix_point(images.copy(), bit_precizion)\n\n elif layer_type == 'ZeroPadding2D':\n level_out[level_id] = mmZeroPadding2D_floating_point(layer, level_out[level_id - 1].copy())\n level_out_reduced[level_id] = mmZeroPadding2D_fixed_point(layer, level_out_reduced[level_id - 1].copy())\n\n elif layer_type == 'Conv2D':\n level_out[level_id] = mmConv2D_floating_point(layer, level_out[level_id - 1].copy(), debug_info)\n level_out_reduced[level_id] = mmConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info)\n\n elif layer_type == 'DepthwiseConv2D':\n level_out[level_id] = mmDepthwiseConv2D_floating_point(layer, level_out[level_id - 1].copy(), debug_info)\n level_out_reduced[level_id] = mmDepthwiseConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info)\n\n elif layer_type == 'Activation':\n level_out[level_id] = mmActivation_floating_point(layer, level_out[level_id - 1].copy(), one_value=one_value, debug_info=debug_info)\n level_out_reduced[level_id] = mmActivation_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, debug_info)\n\n elif layer_type == 'ReLU':\n level_out[level_id] = mmReLU_floating_point(layer, level_out[level_id - 1].copy(), one_value=one_value, debug_info=debug_info)\n level_out_reduced[level_id] = mmReLU_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, debug_info)\n\n elif layer_type == 'GlobalAveragePooling2D':\n level_out[level_id] = mmGlobalAveragePooling2D_floating_point(level_out[level_id - 1].copy())\n level_out_reduced[level_id] = mmGlobalAveragePooling2D_fixed_point(level_out_reduced[level_id - 1].copy())\n\n elif layer_type == 'Dense':\n level_out[level_id] = mmDense_floating_point(layer, level_out[level_id - 1].copy(), debug_info)\n level_out_reduced[level_id] = mmDense_fixed_point(layer, level_out_reduced[level_id - 1].copy(),\n bit_precizion, bit_precizion_weights, debug_info)\n\n # Convert back to float for comparison\n checker_tmp = from_fix_point_to_float(level_out_reduced[level_id], bit_precizion)\n compare_outputs(level_out[level_id], checker_tmp, debug_info)\n\n if debug_info:\n print('')\n\n if level_id > 1000:\n exit()\n\n if layer.name == 'conv_dw_2_bn_':\n exit()\n\n print(level_out[len(model.layers) - 1].shape)\n print(level_out[len(model.layers) - 1])\n print(level_out_reduced[len(model.layers) - 1].shape)\n print(level_out_reduced[len(model.layers) - 1])\n pred_float = np.argmax(level_out[len(model.layers) - 1], axis=1)\n pred_fixed = np.argmax(level_out_reduced[len(model.layers) - 1], axis=1)\n error_rate = (pred_float != pred_fixed).sum() / level_out[len(model.layers) - 1].shape[0]\n\n return error_rate, pred_float, pred_fixed\n\n\ndef get_error_rate(a1, a2):\n miss = 0\n for i in range(len(a1)):\n if a1[i] != a2[i]:\n miss += 1\n print('Error rate: {}%'.format(round(100*miss/len(a1), 2)))\n return miss\n\n\ndef preproc_input_mathmodel(x):\n x -= 127.5\n x /= 128.\n return x\n\n\ndef load_oid_data_optimal(type):\n valid = pd.read_csv(CACHE_PATH + 'oid_validation_{}.csv'.format(type))\n X_valid = valid['id'].values\n Y_valid = valid['target'].values\n return X_valid, Y_valid\n\n\ndef get_image_set(type, image_limit, preproc_type='keras'):\n from keras.applications.mobilenet import preprocess_input\n from r03_mobilenet_v1_reduce_and_scale_model import process_single_item\n from a01_oid_utils import read_single_image, DATASET_PATH\n\n input_size = 128\n X_test, Y_test = load_oid_data_optimal(type)\n condition1 = (Y_test == 0)\n print(X_test.shape, Y_test.shape)\n X_test = np.concatenate((\n X_test[condition1][:image_limit // 2],\n X_test[~condition1][:image_limit // 2],\n ))\n Y_test = np.concatenate((\n Y_test[condition1][:image_limit // 2],\n Y_test[~condition1][:image_limit // 2],\n ))\n\n print(X_test.shape)\n uni = np.unique(Y_test, return_counts=True)\n print('Targets: {}'.format(uni))\n\n img_list = []\n for i in range(len(X_test)):\n img = process_single_item(X_test[i], input_size)\n img_list.append(img)\n img_list = np.array(img_list, dtype=np.float32)\n if preproc_type == 'keras':\n img_list = preprocess_input(img_list)\n else:\n img_list = preproc_input_mathmodel(img_list)\n print(\"Image limit: {} Images shape: {}\".format(image_limit, img_list.shape))\n return img_list, Y_test\n\n\ndef find_conv_overflow_bit_values(model):\n max_w = -1000000000\n max_b = -1000000000\n for level_id in range(len(model.layers)):\n layer = model.layers[level_id]\n layer_type = layer.__class__.__name__\n if layer_type == 'Conv2D' or layer_type == 'DepthwiseConv2D':\n print('Go for layer: {}'.format(layer.name))\n config = layer.get_config()\n w, b = layer.get_weights()\n print('Weights range: {} - {}'.format(w.min(), w.max()))\n print('Bias range: {} - {}'.format(w.min(), w.max()))\n if w.max() > max_w:\n max_w = w.max()\n if np.abs(w.min()) > max_w:\n max_w = np.abs(w.min())\n if b.max() > max_b:\n max_b = b.max()\n if np.abs(b.min()) > max_b:\n max_b = np.abs(b.min())\n print('Maximum weight in covolution overall: {}'.format(max_w))\n print('Maximum bias in covolution overall: {}'.format(max_b))\n max_w_bit = math.ceil(math.log(max_w, 2))\n max_b_bit = math.ceil(math.log(max_b, 2))\n print('Overflow for conv weights w: {} bits b: {} bits'.format(max_w_bit, max_b_bit))\n\n return max_w_bit, max_b_bit\n\n\n# This function works slow, so it should be run once to find optimal bit\ndef get_optimal_bit_for_weights(type, model_path, image_limit, acceptable_error_rate, use_cache):\n cache_path = CACHE_PATH + 'optimal_bit_{}_{}.pklz'.format(type, image_limit)\n if not os.path.isfile(cache_path) or use_cache is not True:\n print('Read model...')\n # We read already reduced weights. We don't need to fix them any way\n model = get_model(model_path)\n print(model.summary())\n convW, convB = find_conv_overflow_bit_values(model)\n\n # We doing preprocessing a little bit different because values shouldn't goes to -1 and 1 values (it will lead to overflow).\n # It can reduce accuracy a little bit. Probably we should initially train with this preproc\n images, answers = get_image_set(type, image_limit, 'math')\n\n print('Classify images...')\n keras_out = model.predict(images)\n res_keras_array = []\n acc = 0.\n for i in range(keras_out.shape[0]):\n res_keras_array.append(np.argmax(keras_out[i]))\n if res_keras_array[-1] == answers[i]:\n acc += 1.\n print('Keras result raw: ', keras_out)\n print('Keras result pos: ', res_keras_array)\n print('Accuracy: {}'.format(acc / keras_out.shape[0]))\n\n image_bit_precision = 8\n weight_bit_precision = 16\n bias_bit_precision = 16\n\n if 1:\n print('First run')\n while 1:\n print('\\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision))\n error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True)\n print('Error rate: {:.6f}'.format(error_rate))\n print(res_keras_array)\n print(pred_float)\n print(pred_fixed)\n image_bit_precision += 1\n if error_rate < acceptable_error_rate or image_bit_precision > 36:\n break\n\n if image_bit_precision > 32:\n return -1, -1, -1, -1, -1\n\n print('Second run. Decrease weights bitsize')\n while 1:\n weight_bit_precision -= 1\n # bias_bit_precision = image_bit_precision\n print('\\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision))\n error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True)\n print('Error rate: {:.6f}'.format(error_rate))\n print(res_keras_array)\n print(pred_float)\n print(pred_fixed)\n if error_rate > acceptable_error_rate:\n weight_bit_precision += 1\n break\n\n print('Third run. Decrease bias bitsize')\n while 1:\n bias_bit_precision -= 1\n print('\\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision,\n weight_bit_precision,\n bias_bit_precision))\n error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision,\n weight_bit_precision, bias_bit_precision,\n debug_info=True)\n print('Error rate: {:.6f}'.format(error_rate))\n print(res_keras_array)\n print(pred_float)\n print(pred_fixed)\n if error_rate > acceptable_error_rate:\n bias_bit_precision += 1\n break\n\n if 0:\n print('Single debug run')\n print('\\nStart error precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision,\n weight_bit_precision,\n bias_bit_precision))\n error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision,\n weight_bit_precision, bias_bit_precision,\n debug_info=True)\n print('Error rate: {:.6f}'.format(error_rate))\n print(res_keras_array)\n print(pred_float)\n print(pred_fixed)\n\n save_in_file((image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB), cache_path)\n return image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB\n else:\n return load_from_file(cache_path)\n\n\nif __name__ == '__main__':\n if 0:\n use_cache = False\n acceptable_error_rate = 0.005 # 0.5%\n image_limit = 3000\n type = 'people'\n model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5'\n\n if 0:\n use_cache = False\n acceptable_error_rate = 0.005 # 0.5%\n image_limit = 3000\n type = 'cars'\n model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5'\n\n if 1:\n use_cache = False\n acceptable_error_rate = 0.005 # 0.5%\n image_limit = 3000\n type = 'animals'\n model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5'\n\n\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights(type, model_path_rescaled, image_limit, acceptable_error_rate, use_cache)\n if image_bit_precision > 0:\n print('Optimal bit size for image and feature maps (sign bit is not included) is: {}'.format(image_bit_precision))\n print('Optimal bit size for weights: {}'.format(weight_bit_precision))\n print('Optimal bit size for bias: {}'.format(bias_bit_precision))\n print('Bit overflows. Weights {} Bias: {}'.format(convW, convB))\n else:\n print('Impossible to find optimal bit!')\n sess.close()\n\n'''\nMax error rate: 0.5%\nweights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5\nOptimal 12, 11, 10, 7, 3\nweights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5\nOptimal 10, 9, 8, 7, 3\nweights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5\nOptimal 12, 11, 10, 7, 3\n'''" }, { "path": "r05_gen_weights_in_verilog_format.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n'''\nGenerate weights with optimal bit size in verilog format \n'''\n\nif __name__ == '__main__':\n import os\n\n # Block to choose backend\n gpu_use = 4\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n\nfrom r04_find_optimal_bit_for_weights import *\n\n\nSTORAGE_COUNT_WEIGHTS = 0\nSTORAGE_COUNT_BIAS = 0\n\n\n# Note: We suppose that every Conv2D layer has type \"same\"\n# In Tensorflow weight matrices already transposed\ndef my_convolve(input, kernel):\n output = np.zeros((input.shape[0], input.shape[1]))\n zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = input\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n for i in range(1, zero_pad.shape[0] - 1):\n for j in range(1, zero_pad.shape[1] - 1):\n sub = zero_pad[i-1:i+2, j-1:j+2]\n output[i-1, j-1] = np.sum(sub*kernel)\n return output\n\n\ndef my_convolve_fixed_point(input, kernel, bit):\n output = np.zeros((input.shape[0], input.shape[1]))\n zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = input\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n for i in range(1, zero_pad.shape[0] - 1):\n for j in range(1, zero_pad.shape[1] - 1):\n sub = zero_pad[i-1:i+2, j-1:j+2]\n output[i-1, j-1] = np.sum((sub*kernel).astype(np.int64))\n return output\n\n\ndef preprocess_forward(arr, val):\n arr1 = arr.copy().astype(np.float32)\n arr1 /= val\n return arr1\n\n\ndef convert_to_fix_point(arr1, bit):\n arr2 = arr1.copy().astype(np.float32)\n arr2[arr2 < 0] = 0.0\n arr2 = np.round(np.abs(arr2) * (2 ** bit))\n arr3 = arr1.copy().astype(np.float32)\n arr3[arr3 > 0] = 0.0\n arr3 = -np.round(np.abs(-arr3) * (2 ** bit))\n arr4 = arr2 + arr3\n return arr4.astype(np.int64)\n\n\ndef from_fix_point_to_float(arr, bit):\n return arr / (2 ** bit)\n\n\ndef compare_outputs(s1, s2, debug_info=True):\n if s1.shape != s2.shape:\n print('Shape of arrays is different! {} != {}'.format(s1.shape, s2.shape))\n s = np.abs(s1 - s2)\n size = 1\n for dim in np.shape(s): size *= dim\n if debug_info:\n print('Max difference: {}'.format(s.max()))\n print('Avg difference: {}'.format(s.mean()/size))\n print('Value range float: {} - {}'.format(s1.min(), s1.max()))\n print('Value range fixed: {} - {}'.format(s2.min(), s2.max()))\n\n\ndef dump_memory_structure_conv(arr, out_file):\n print('Dump memory structure in file: {}'.format(out_file))\n out = open(out_file, \"w\")\n total = 0\n for a in range(arr.shape[2]):\n for i in range(arr.shape[0]):\n for j in range(arr.shape[1]):\n out.write(str(total) + \" LVL: {} X: {} Y: {} \".format(a, i, j) + str(arr[i, j, a]) + '\\n')\n total += 1\n\n out.close()\n\n\ndef dump_memory_structure_dense(arr, out_file):\n print('Dump memory structure for dense layer in file: {}'.format(out_file))\n out = open(out_file, \"w\")\n total = 0\n print('Shape:', arr.shape)\n for j in range(arr.shape[0]):\n out.write(str(total) + \" POS: {} \".format(j) + str(arr[j]) + '\\n')\n total += 1\n\n out.close()\n\n\ndef print_first_pixel_detailed_calculation_dense(previous_layer_output, wgt_bit, bit_precizion):\n i = 10\n conv_my = 0\n for j in range(0, previous_layer_output.shape[0]):\n print('Pixel {}: {}'.format(j, int(previous_layer_output[j])))\n print('Weight {}: {}'.format(j, wgt_bit[j][i]))\n conv_my += np.right_shift((previous_layer_output[j]*wgt_bit[j][i]).astype(np.int64), bit_precizion)\n if j > 0 and j % 9 == 8:\n print('Current conv_my: {}'.format(conv_my))\n print('Result first pixel: {}'.format(conv_my))\n exit()\n\n\ndef print_first_pixel_detailed_calculation(previous_layer_output, wgt_bit, bit_precizion):\n i = 0\n x = 0\n y = 0\n conv_my = 0\n print('Point: {} X: {} Y: {}'.format(i, x, y))\n print('Weights shape: {}'.format(wgt_bit.shape))\n for j in range(wgt_bit.shape[2]):\n full_image = previous_layer_output[:, :, j]\n zero_pad = np.zeros((full_image.shape[0] + 2, full_image.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = full_image\n pics = zero_pad[x+1-1:x+1+2, y+1-1:y+1+2].astype(np.int64)\n print('Pixel area 3x3 for [{}, {}]:'.format(x, y), pics)\n kernel = wgt_bit[:, :, j, i].copy()\n # Не надо переворачивать для TensorFlow\n # kernel = np.flipud(kernel)\n # kernel = np.fliplr(kernel)\n print('Weights {}: {}'.format(j, kernel))\n res = np.sum(np.right_shift((pics*kernel).astype(np.int64), bit_precizion))\n print('Convolution result {}: {}'.format(j, res))\n conv_my += res\n\n print('Overall result: {}'.format(conv_my))\n if conv_my[conv_my > 2 ** bit_precizion].any() or conv_my[conv_my < - 2 ** bit_precizion].any():\n print('Overflow! {}'.format(conv_my[conv_my > 2 ** bit_precizion]))\n exit()\n if conv_my < 0:\n conv_my = 0\n exit()\n\n\ndef convert_to_normalized_form(value, precision, required_precision=None):\n sign = 0\n ret = value\n if ret < 0:\n sign = 1\n ret = abs(ret)\n\n # down = ret - math.floor(ret)\n # print(ret, down)\n normed = int(round(ret * 2**(precision-1)))\n #if sign == 1 and normed != 0:\n # Complement code for negative numbers\n #normed = 2**(precision) - normed\n down_binary_str = \"{:0b}\".format(normed)\n if required_precision is None:\n required_precision = precision\n for j in range(len(down_binary_str), required_precision):\n down_binary_str = '0' + down_binary_str\n return sign, down_binary_str\n\n\ndef convert_to_normalized_form_array(value, precision):\n ret = np.abs(value)\n normed = np.round(ret * 2**(precision - 1)).astype(np.int64)\n return normed\n\n\ndef convert_to_normalized_form_v2(value, precision):\n sign = 0\n ret = value\n if ret < 0:\n sign = 1\n ret = abs(ret)\n\n normed = ret\n #if sign == 1 and normed != 0:\n # Complement code for negative numbers\n #normed = 2**(precision) - normed\n down_binary_str = \"{:b}\".format(normed)\n for j in range(len(down_binary_str), precision):\n down_binary_str = '0' + down_binary_str\n return sign, down_binary_str\n\n\ndef get_shape_string(w):\n r = str(w.shape)[1:-1]\n r = r.replace(',', '')\n r = r.replace(' ', '_')\n return r\n\n\ndef gen_convolution_weights(level_id, layer, bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias):\n global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS\n\n # Convolution with fixed point\n config = layer.get_config()\n use_bias = config['use_bias']\n kernel_size = config['kernel_size']\n requred_mem_in_bits = 0\n\n if kernel_size != (3, 3) and kernel_size != (1, 1):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n # w = convert_to_fix_point(w.copy(), bit_precizion)\n\n # Check that everything is fine with weights\n if w[w > 2 ** convW].any() or w[w < -2 ** convW].any():\n print('Overflow for conv weights!')\n exit()\n\n # Check that everything is fine with bias\n if b[b > 2 ** convB].any() or b[b < -2 ** convB].any():\n print('Overflow for conv bias!')\n exit()\n\n precisionW = weight_bit_precision + 1 + convW\n precisionB = bias_bit_precision + 1 + convB\n print('Initial bits weights: {} bias: {}'.format(precisionW, precisionB))\n\n w_check = convert_to_normalized_form_array(w, weight_bit_precision + 1)\n w_check_max = w_check.max()\n precisionW = np.log2(w_check_max).astype(np.int64) + 1 + 1\n b_check = convert_to_normalized_form_array(b, bias_bit_precision + 1)\n b_check_max = b_check.max()\n precisionB = np.log2(b_check_max).astype(np.int64) + 1 + 1\n print('Max value to store weights: {} bias: {}'.format(w_check_max, b_check_max))\n print('Reduced bits weights: {} bias: {}'.format(precisionW, precisionB))\n\n print('Go for: {} Shape: {}'.format(layer.name, w.shape))\n\n tp1 = 'bin'\n\n s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} {} {} Shape: {}\\n\\n'.format(level_id, layer.name, layer.__class__.__name__,\n bit_precizion + 1,\n weight_bit_precision + 1 + convW,\n bias_bit_precision + 1 + convB,\n get_shape_string(w))\n out_weights.write(s1)\n out_bias.write(s1)\n\n # Cycle by outputs\n for i in range(w.shape[3]):\n # Cycle by inputs\n for j in range(w.shape[2]):\n # Cycle by conv 3x3\n for k in range(w.shape[1]):\n for l in range(w.shape[0]):\n sign, bin1 = convert_to_normalized_form(w[k, l, j, i].copy(), weight_bit_precision + 1, precisionW)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n dec_verilog = int(bin1, 2)\n if sign == 1:\n dec_verilog = -dec_verilog\n if tp1 == 'hex':\n hx = hex(int(bin1, 2))[2:].upper()\n out_weights.write(\n \"storage[{}] = {}{}'h{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, hx, dec_verilog, w[k, l, j, i]))\n else:\n out_weights.write(\n \"storage[{}] = {}{}'b{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, bin1, dec_verilog, w[k, l, j, i]))\n requred_mem_in_bits += precisionW\n STORAGE_COUNT_WEIGHTS += 1\n if w.shape[1] > 1:\n out_weights.write('\\n')\n out_weights.write('\\n')\n\n # Cycle by outputs\n for i in range(w.shape[3]):\n sign, bin1 = convert_to_normalized_form(b[i].copy(), bias_bit_precision + 1, precisionB)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n dec_verilog = int(bin1, 2)\n if sign == 1:\n dec_verilog = -dec_verilog\n if tp1 == 'hex':\n hx = hex(int(bin1, 2))[2:].upper()\n out_bias.write(\n \"storage_bias[{}] = {}{}'h{}; // {} {}\\n\".format(STORAGE_COUNT_BIAS, sgn, precisionB, hx, dec_verilog, b[i]))\n else:\n out_bias.write(\n \"storage_bias[{}] = {}{}'b{}; // {} {}\\n\".format(STORAGE_COUNT_BIAS, sgn, precisionB, bin1, dec_verilog, b[i]))\n requred_mem_in_bits += precisionB\n STORAGE_COUNT_BIAS += 1\n out_bias.write('\\n')\n\n return requred_mem_in_bits\n\n\ndef gen_depthwise_convolution_weights(level_id, layer, bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias):\n global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS\n\n config = layer.get_config()\n use_bias = config['use_bias']\n kernel_size = config['kernel_size']\n requred_mem_in_bits = 0\n\n if kernel_size != (3, 3) and kernel_size != (1, 1):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n # Check that everything is fine with weights\n if w[w > 2 ** convW].any() or w[w < -2 ** convW].any():\n print('Overflow for conv weights!')\n exit()\n\n # Check that everything is fine with bias\n if b[b > 2 ** convB].any() or b[b < -2 ** convB].any():\n print('Overflow for conv bias!')\n exit()\n\n precisionW = weight_bit_precision + 1 + convW\n precisionB = bias_bit_precision + 1 + convB\n print('Initial bits weights: {} bias: {}'.format(precisionW, precisionB))\n\n w_check = convert_to_normalized_form_array(w, weight_bit_precision + 1)\n w_check_max = w_check.max()\n precisionW = np.log2(w_check_max).astype(np.int64) + 1 + 1\n b_check = convert_to_normalized_form_array(b, bias_bit_precision + 1)\n b_check_max = b_check.max()\n precisionB = np.log2(b_check_max).astype(np.int64) + 1 + 1\n print('Max value to store weights: {} bias: {}'.format(w_check_max, b_check_max))\n print('Reduced bits weights: {} bias: {}'.format(precisionW, precisionB))\n\n print('Go for: {} Shape: {}'.format(layer.name, w.shape))\n\n s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} {} {} Shape: {}\\n\\n'.format(level_id, layer.name, layer.__class__.__name__,\n bit_precizion + 1,\n weight_bit_precision + 1 + convW,\n bias_bit_precision + 1 + convB,\n get_shape_string(w))\n out_weights.write(s1)\n out_bias.write(s1)\n\n tp1 = 'bin'\n # Cycle by inputs. Output is always 1\n for i in range(w.shape[2]):\n # Cycle by conv 3x3\n for k in range(w.shape[1]):\n for l in range(w.shape[0]):\n sign, bin1 = convert_to_normalized_form(w[k, l, i, 0].copy(), weight_bit_precision + 1, precisionW)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n dec_verilog = int(bin1, 2)\n if sign == 1:\n dec_verilog = -dec_verilog\n if tp1 == 'hex':\n hx = hex(int(bin1, 2))[2:].upper()\n out_weights.write(\n \"storage[{}] = {}{}'h{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, hx, dec_verilog, w[k, l, i, 0]))\n else:\n out_weights.write(\n \"storage[{}] = {}{}'b{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, bin1, dec_verilog, w[k, l, i, 0]))\n requred_mem_in_bits += precisionW\n STORAGE_COUNT_WEIGHTS += 1\n out_weights.write('\\n')\n\n # Cycle by inputs. Output is always 1\n for i in range(w.shape[2]):\n sign, bin1 = convert_to_normalized_form(b[i].copy(), bias_bit_precision + 1, precisionB)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n dec_verilog = int(bin1, 2)\n if sign == 1:\n dec_verilog = -dec_verilog\n if tp1 == 'hex':\n hx = hex(int(bin1, 2))[2:].upper()\n out_bias.write(\n \"storage_bias[{}] = {}{}'h{}; // {} {}\\n\".format(STORAGE_COUNT_BIAS, sgn, precisionB, hx, dec_verilog,\n w[k, l, i, 0]))\n else:\n out_bias.write(\n \"storage_bias[{}] = {}{}'b{}; // {} {}\\n\".format(STORAGE_COUNT_BIAS, sgn, precisionB, bin1, dec_verilog,\n w[k, l, i, 0]))\n requred_mem_in_bits += precisionB\n STORAGE_COUNT_BIAS += 1\n out_bias.write('\\n')\n\n return requred_mem_in_bits\n\n\ndef gen_dense_weights(level_id, layer, bit_precizion, out_weights):\n global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS\n\n config = layer.get_config()\n use_bias = config['use_bias']\n requred_mem_in_bits = 0\n\n if use_bias:\n print('Bias currently unsupported!')\n exit()\n\n (w,) = layer.get_weights()\n\n # Check that everything is fine with weights\n if w[w > 1].any() or w[w < -1].any():\n print('Overflow for depthwise conv weights!')\n exit()\n\n print('Go for: {} Shape: {}'.format(layer.name, w.shape))\n\n s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} Shape: {}\\n\\n'.format(level_id, layer.name, layer.__class__.__name__,\n bit_precizion + 1,\n get_shape_string(w))\n out_weights.write(s1)\n\n tp1 = 'bin'\n precision = bit_precizion + 1\n # Cycle by outputs\n for i in range(w.shape[1]):\n # Cycle by inputs\n for j in range(w.shape[0]):\n sign, bin1 = convert_to_normalized_form(w[j, i].copy(), precision)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n dec_verilog = int(bin1, 2)\n if sign == 1:\n dec_verilog = -dec_verilog\n if tp1 == 'hex':\n hx = hex(int(bin1, 2))[2:].upper()\n out_weights.write(\n \"storage[{}] = {}{}'h{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precision, hx, dec_verilog, w[j, i]))\n else:\n out_weights.write(\n \"storage[{}] = {}{}'b{}; // {} {}\\n\".format(STORAGE_COUNT_WEIGHTS, sgn, precision, bin1, dec_verilog, w[j, i]))\n STORAGE_COUNT_WEIGHTS += 1\n requred_mem_in_bits += precision\n out_weights.write('\\n')\n\n return requred_mem_in_bits\n\n\ndef generate_weights_for_layers(model, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_dir):\n global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS\n\n STORAGE_COUNT_WEIGHTS = 0\n STORAGE_COUNT_BIAS = 0\n weights_required_memory = 0\n out_weights = open(out_dir + 'storage.v', 'w')\n out_bias = open(out_dir + 'storage_bias.v', 'w')\n\n for level_id in range(len(model.layers)):\n layer = model.layers[level_id]\n layer_type = layer.__class__.__name__\n req_mem = 0\n\n if layer_type == 'Conv2D':\n req_mem = gen_convolution_weights(level_id, layer, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias)\n elif layer_type == 'DepthwiseConv2D':\n req_mem = gen_depthwise_convolution_weights(level_id, layer, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias)\n elif layer_type == 'Dense':\n req_mem = gen_dense_weights(level_id, layer, weight_bit_precision, out_weights)\n else:\n continue\n\n print('Required weights memory: {} bit'.format(req_mem))\n weights_required_memory += req_mem\n\n out_weights.close()\n out_bias.close()\n print('Overall weights memory requirements: {} bit ({:.2f} MB)'.format(weights_required_memory, weights_required_memory / (1024*1024)))\n\n\nif __name__ == '__main__':\n type = 'animals'\n model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5'\n acceptable_error_rate = 0.005 # 0.5%\n image_limit = 3000\n\n if 0:\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights(type, model_path, image_limit, acceptable_error_rate, use_cache=True)\n else:\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3\n\n out_dir = CACHE_PATH + type + '/'\n if not os.path.isdir(out_dir):\n os.mkdir(out_dir)\n\n model = get_model(model_path)\n generate_weights_for_layers(model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB, out_dir)\n" }, { "path": "r06_generate_debug_data.py", "content": "# coding: utf-8\n__author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS'\n\n\n'''\nThis code takes one image run it through the network and store all intermediate feature maps \nin fixed point representation in separate files. Also detailed first pixel calculation is \ngenerated. It used later to check generated verilog on correctness.\n'''\n\nif __name__ == '__main__':\n import os\n\n # Block to choose backend and GPU to run\n gpu_use = 4\n os.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\n os.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\n\nfrom r04_find_optimal_bit_for_weights import *\nimport math\n\n\ndef convert_to_normalized_form_v2(value, precision):\n sign = 0\n ret = value\n if ret < 0:\n sign = 1\n ret = abs(ret)\n\n normed = ret\n #if sign == 1 and normed != 0:\n # Complement code for negative numbers\n #normed = 2**(precision) - normed\n down_binary_str = \"{:b}\".format(normed)\n for j in range(len(down_binary_str), precision):\n down_binary_str = '0' + down_binary_str\n return sign, down_binary_str\n\n\ndef store_layer_result(level_id, layer, layer_type, bp, res):\n r = str(res.shape[1:])[1:-1]\n r = r.replace(',', '')\n r = r.replace(' ', '_')\n out_file = INTERMEDIATE_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}_shape_{}.txt'.format(level_id, layer.name, bp+1, r)\n print('Write to {}'.format(out_file))\n out = open(out_file, 'w')\n\n if layer_type != 'Conv2D' and layer_type != 'DepthwiseConv2D':\n if np.abs(res).max() >= 2 ** bp:\n print('Some layer result problem here! ({} > {})'.format(np.abs(res).max(), 2 ** bp))\n exit()\n else:\n if np.abs(res).max() >= 2 ** bp:\n print('Overflow on {} layer! ({} > {}). It is expected, increase bit space!'.format(layer_type, np.abs(res).max(), 2 ** bp))\n\n precision = bp + 1\n # Possible overflow. It's fine\n bit_max = math.ceil(math.log(np.abs(res).max() + 1, 2)) + 1\n if bit_max > precision:\n precision = bit_max\n\n total = 0\n if len(res.shape) == 4:\n if 1:\n # Start from channels\n for i in range(res.shape[3]):\n for j in range(res.shape[1]):\n for k in range(res.shape[2]):\n sign, bin1 = convert_to_normalized_form_v2(res[0, j, k, i].copy(), precision)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n out.write(\"pixel[{}] = {}{}'b{}; // {}\\n\".format(total, sgn, precision, bin1, res[0, j, k, i]))\n total += 1\n out.write('\\n')\n elif len(res.shape) == 2:\n for i in range(res.shape[1]):\n sign, bin1 = convert_to_normalized_form_v2(res[0, i].copy(), precision)\n sgn = ' '\n if sign == 1:\n sgn = '-'\n out.write(\"pixel[{}] = {}{}'b{}; // {}\\n\".format(total, sgn, precision, bin1, res[0, i]))\n total += 1\n else:\n print('Shape problem!')\n exit()\n\n out.close()\n\n\ndef print_convolution_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision, bias_bit_precision):\n config = layer.get_config()\n filters = config['filters']\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2\n sh2 -= 2\n\n if kernel_size != (3, 3) and kernel_size != (1, 1):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name, image_bit_precizion + 1)\n print('Write to {}'.format(out_file))\n out = open(out_file, 'w')\n w = convert_to_fix_point(w.copy(), weight_bit_precision)\n b = convert_to_fix_point(b.copy(), bias_bit_precision)\n\n i = 0\n x = 0\n y = 0\n # Output filter number\n wi = i\n # Batch image number\n sh0 = 0\n out.write('Point: {} X: {} Y: {}\\n'.format(i, x, y))\n\n # input filters cycle\n value = 0\n for wj in range(w.shape[-2]):\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n\n # Convolution for single output pixel\n i = x*strides[0] + 1\n j = y*strides[1] + 1\n if kernel_size == (3, 3):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n vv = np.sum((sub * kernel).astype(np.int64))\n elif kernel_size == (1, 1):\n sub = zero_pad[i, j]\n vv = (sub * kernel[0, 0]).astype(np.int64)\n\n out.write('Input kernel number: {}\\n'.format(wj))\n out.write('Kernel:\\n{}\\n'.format(kernel))\n out.write('Part:\\n{}\\n'.format(sub))\n out.write('Current result: {}\\n\\n'.format(vv))\n value += vv\n\n b[wi] <<= weight_bit_precision + (image_bit_precizion - bias_bit_precision)\n out.write('Add bias: {}\\n'.format(b[wi]))\n value += b[wi]\n out.write('Overall result before shift: {}\\n'.format(value))\n # Divide by 2^bp\n value = np.right_shift(value, weight_bit_precision)\n out.write('Overall result after shift: {}\\n'.format(value))\n out.close()\n\n\ndef print_depthwise_conv_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision, bias_bit_precision):\n config = layer.get_config()\n use_bias = config['use_bias']\n strides = config['strides']\n padding = config['padding']\n kernel_size = config['kernel_size']\n\n sh1 = img.shape[1]\n sh2 = img.shape[2]\n if padding == 'valid':\n sh1 -= 2\n sh2 -= 2\n\n if kernel_size != (3, 3):\n print('Unsupported kernel size: {}'.format(kernel_size))\n exit()\n\n (w, b) = layer.get_weights()\n\n out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name, image_bit_precizion+1)\n print('Write to {}'.format(out_file))\n out = open(out_file, 'w')\n w = convert_to_fix_point(w.copy(), weight_bit_precision)\n b = convert_to_fix_point(b.copy(), bias_bit_precision)\n\n i = 0\n x = 0\n y = 0\n # Output filter number\n wj = i\n wi = 0\n # Batch image number\n sh0 = 0\n out.write('Point: {} X: {} Y: {}\\n'.format(i, x, y))\n\n # input filters cycle\n value = 0\n kernel = w[:, :, wj, wi].copy()\n slice = img[sh0, :, :, wj]\n\n if padding == 'same':\n zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2))\n zero_pad[1:-1, 1:-1] = slice\n elif padding == 'valid':\n zero_pad = slice.copy()\n else:\n print('Unknown padding: {}'.format(padding))\n exit()\n\n # Convolution for single output pixel\n i = x*strides[0] + 1\n j = y*strides[1] + 1\n if kernel_size == (3, 3):\n sub = zero_pad[i - 1:i + 2, j - 1:j + 2]\n vv = np.sum((sub * kernel).astype(np.int64))\n elif kernel_size == (1, 1):\n sub = zero_pad[i, j]\n vv = (sub * kernel[0, 0]).astype(np.int64)\n\n value = vv\n out.write('Input kernel number: {}\\n'.format(wj))\n out.write('Kernel:\\n{}\\n'.format(kernel))\n out.write('Part:\\n{}\\n'.format(sub))\n b[wj] <<= weight_bit_precision + (image_bit_precizion - bias_bit_precision)\n out.write('Add bias: {}\\n'.format(b[wj]))\n value += b[wj]\n out.write('Overall result before shift: {}\\n'.format(value))\n # Divide by 2^bp\n value = np.right_shift(value, weight_bit_precision)\n out.write('Overall result after shift: {}\\n'.format(value))\n out.close()\n\n\ndef print_dense_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision):\n config = layer.get_config()\n use_bias = config['use_bias']\n activation = config['activation']\n\n if use_bias:\n (w, b) = layer.get_weights()\n else:\n (w,) = layer.get_weights()\n\n if use_bias is True:\n print('Bias currently not supported!')\n exit()\n\n if activation != 'softmax':\n print('Activation {} is not supported'.format(activation))\n exit()\n\n w = convert_to_fix_point(w.copy(), weight_bit_precision)\n\n out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name,\n weight_bit_precision + 1)\n print('Write to {}'.format(out_file))\n out = open(out_file, 'w')\n\n i = 0\n x = 0\n # Batch image number\n sh0 = 0\n out.write('Point: {} X: {}\\n'.format(i, x))\n value = 0\n for j in range(w.shape[0]):\n out.write('Weight {}: {}\\n'.format(j, w[j, i]))\n vv = img[sh0, j] * w[j, i]\n value += vv\n out.write('Current intermediate result: {} [Accumulate: {}]\\n'.format(vv, value))\n\n out.write('Overall result before shift: {}\\n'.format(value))\n # Divide by 2^bp\n value = np.right_shift(value.astype(np.int64), weight_bit_precision)\n out.write('Overall result after shift: {}\\n'.format(value))\n out.close()\n\n\ndef get_filters_size(arr):\n a = np.prod(np.array(arr.shape).astype(np.int64))\n return a\n\n\ndef generate_layer_results(model, images, image_bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB):\n\n if images.shape[0] > 1:\n print('Only one image must be in batch for debug!')\n exit()\n\n level_out_reduced = dict()\n debug_info = False\n prev_filters_space = -1\n next_filters_space = -1\n max_filter_space = -1\n critical_layer = -1\n\n for level_id in range(len(model.layers)):\n layer = model.layers[level_id]\n layer_type = layer.__class__.__name__\n print('Layer num: {} Layer name: {} Layer type: {}'.format(level_id, layer.name, layer_type))\n if level_id == 0:\n next_filters_space = get_filters_size(images[0]) * (image_bit_precizion + 1)\n\n if level_id > 0:\n print('Input shape: {}'.format(level_out_reduced[level_id-1].shape))\n prev_filters_space = next_filters_space.copy()\n next_filters_space = get_filters_size(level_out_reduced[level_id-1][0]) * (image_bit_precizion + 1)\n if prev_filters_space + next_filters_space > max_filter_space:\n max_filter_space = prev_filters_space + next_filters_space\n critical_layer = level_id\n\n if layer_type == 'InputLayer':\n level_out_reduced[level_id] = convert_to_fix_point(images.copy(), image_bit_precizion)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'ZeroPadding2D':\n level_out_reduced[level_id] = mmZeroPadding2D_fixed_point(layer, level_out_reduced[level_id - 1].copy())\n\n elif layer_type == 'Conv2D':\n level_out_reduced[level_id] = mmConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision, debug_info)\n print_convolution_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'DepthwiseConv2D':\n level_out_reduced[level_id] = mmDepthwiseConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision, debug_info)\n print_depthwise_conv_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'Activation':\n level_out_reduced[level_id] = mmActivation_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, debug_info)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'ReLU':\n level_out_reduced[level_id] = mmReLU_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, debug_info)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'GlobalAveragePooling2D':\n level_out_reduced[level_id] = mmGlobalAveragePooling2D_fixed_point(level_out_reduced[level_id - 1].copy())\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n elif layer_type == 'Dense':\n level_out_reduced[level_id] = mmDense_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, debug_info)\n print_dense_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision)\n store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id])\n\n print('Required space to store intermediate results of calculations: {} bits ({:.2f} MB)'.format(max_filter_space, max_filter_space / (1024 * 1024)))\n print('Critical layer number: {}'.format(critical_layer))\n\n\ndef get_debug_image():\n img = cv2.imread(CACHE_PATH + 'image.png')\n img_list = []\n img_list.append(img.copy())\n img_list = np.array(img_list, dtype=np.float32)\n img_list = preproc_input_mathmodel(img_list)\n print(img_list.shape, img_list.max(), img_list.min())\n return img_list\n\n\ndef generate_layer_results_for_image(type, model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB):\n print(model.summary())\n\n # Get only one image\n try:\n a = 10/0\n # If OID dataset exists\n images, answers = get_image_set(type, 2, 'math')\n images = images[0:1]\n print('Use OID images')\n except:\n images = np.zeros((1, 128, 128, 3), dtype=np.float32)\n images[...] = 255\n images = preproc_input_mathmodel(images)\n print('No OID images found. Use generated image')\n\n generate_layer_results(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB)\n\n\nif __name__ == '__main__':\n problem_type = 'people'\n\n INTERMEDIATE_OUTPUT_PATH = CACHE_PATH + 'intermediate_{}/'.format(problem_type)\n if not os.path.isdir(INTERMEDIATE_OUTPUT_PATH):\n os.mkdir(INTERMEDIATE_OUTPUT_PATH)\n FIRST_PIXEL_OUTPUT_PATH = CACHE_PATH + 'first_pixel_{}/'.format(problem_type)\n if not os.path.isdir(FIRST_PIXEL_OUTPUT_PATH):\n os.mkdir(FIRST_PIXEL_OUTPUT_PATH)\n\n if problem_type == 'people':\n model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5')\n # bit_precision - without sign, so we need to add 1 to it to store sign as well\n # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights()\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3\n elif problem_type == 'cars':\n model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5')\n # bit_precision - without sign, so we need to add 1 to it to store sign as well\n # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights()\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 10, 9, 8, 7, 3\n elif problem_type == 'animals':\n model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5')\n # bit_precision - without sign, so we need to add 1 to it to store sign as well\n # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights()\n image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3\n\n generate_layer_results_for_image(problem_type, model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB)\n" }, { "path": "r07_generate_verilog_for_mobilenet.py", "content": "# coding: utf-8\n__author__ = 'Alex Kustov, IPPM RAS'\n\nimport os\n\ngpu_use = 0\nos.environ[\"KERAS_BACKEND\"] = \"tensorflow\"\nos.environ[\"CUDA_VISIBLE_DEVICES\"] = \"{}\".format(gpu_use)\n\nfrom r04_find_optimal_bit_for_weights import *\n\n\ndef addressRAM(directory, steps_count, max_address_value):\n f = open(directory + \"addressRAM.v\", 'w')\n\n bit_steps_count = len(bin(steps_count)) - 2\n bit_max_address_value = len(bin(max_address_value)) - 2\n\n f.write(\"module addressRAM(\\n\")\n f.write(\"\tinput [\"+str(bit_steps_count-1)+\":0] step,\\n\")\n f.write(\"\toutput reg re_weights,\\n\")\n f.write(\"\toutput reg re_bias,\\n\")\n f.write(\"\toutput reg [\"+str(bit_max_address_value-1)+\":0] firstaddr, lastaddr\\n\")\n f.write(\");\\n\")\n f.write(\"parameter convolution_size = 9;\\n\")\n f.write(\"parameter conv1 = 1*8*3 * convolution_size;\\n\")\n f.write(\"parameter conv2_1 = 8 * convolution_size + conv1;\\n\")\n f.write(\"parameter conv2_2 = (8*8*2) + conv2_1;\\n\")\n f.write(\"parameter conv3_1 = 16 * convolution_size + conv2_2;\\n\")\n f.write(\"parameter conv3_2 = (16*16*2) + conv3_1;\\n\")\n f.write(\"parameter conv4_1 = 32 * convolution_size + conv3_2;\\n\")\n f.write(\"parameter conv4_2 = (32*32) + conv4_1;\\n\")\n f.write(\"parameter conv5_1 = 32 * convolution_size + conv4_2;\\n\")\n f.write(\"parameter conv5_2 = (32*32*2) + conv5_1;\\n\")\n f.write(\"parameter conv6_1 = 64 * convolution_size + conv5_2;\\n\")\n f.write(\"parameter conv6_2 = (64*64) + conv6_1;\\n\")\n f.write(\"parameter conv7_1 = 64 * convolution_size + conv6_2;\\n\")\n f.write(\"parameter conv7_2 = (64*64*2) + conv7_1;\\n\")\n f.write(\"parameter conv8_1 = 128 * convolution_size + conv7_2;\\n\")\n f.write(\"parameter conv8_2 = (128*128) + conv8_1;\\n\")\n f.write(\"parameter conv9_1 = 128 * convolution_size + conv8_2;\\n\")\n f.write(\"parameter conv9_2 = (128*128) + conv9_1;\\n\")\n f.write(\"parameter conv10_1 = 128 * convolution_size + conv9_2;\\n\")\n f.write(\"parameter conv10_2 = (128*128) + conv10_1;\\n\")\n f.write(\"parameter conv11_1 = 128 * convolution_size + conv10_2;\\n\")\n f.write(\"parameter conv11_2 = (128*128) + conv11_1;\\n\")\n f.write(\"parameter conv12_1 = 128 * convolution_size + conv11_2;\\n\")\n f.write(\"parameter conv12_2 = (128*128) + conv12_1;\\n\")\n f.write(\"parameter conv13_1 = 128 * convolution_size + conv12_2;\\n\")\n f.write(\"parameter conv13_2 = (128*128*2) + conv13_1;\\n\")\n f.write(\"parameter conv14_1 = 256 * convolution_size + conv13_2;\\n\")\n f.write(\"parameter conv14_2_1 = ((256*256)>>1) + conv14_1;\\n\")\n f.write(\"parameter conv14_2_2 = ((256*256)>>1) + conv14_2_1;\\n\")\n f.write(\"parameter predict = 512 + conv14_2_2;\\n\")\n f.write(\"\\n\")\n f.write(\"\\n\")\n f.write(\"parameter bias1 = 8;\\n\")\n f.write(\"parameter bias2_1 = (8)+8;\\n\")\n f.write(\"parameter bias2_2 = (16)+16;\\n\")\n f.write(\"parameter bias3_1 = (32)+16;\\n\")\n f.write(\"parameter bias3_2 = (48)+32;\\n\")\n f.write(\"parameter bias4_1 = (80)+32;\\n\")\n f.write(\"parameter bias4_2 = (112)+32;\\n\")\n f.write(\"parameter bias5_1 = (144)+32;\\n\")\n f.write(\"parameter bias5_2 = (176)+64;\\n\")\n f.write(\"parameter bias6_1 = (240)+64;\\n\")\n f.write(\"parameter bias6_2 = (304)+64;\\n\")\n f.write(\"parameter bias7_1 = (368)+64;\\n\")\n f.write(\"parameter bias7_2 = (432)+128;\\n\")\n f.write(\"parameter bias8_1 = (560)+128;\\n\")\n f.write(\"parameter bias8_2 = (688)+128;\\n\")\n f.write(\"parameter bias9_1 = (816)+128;\\n\")\n f.write(\"parameter bias9_2 = (944)+128;\\n\")\n f.write(\"parameter bias10_1 = (1072)+128;\\n\")\n f.write(\"parameter bias10_2 = (1200)+128;\\n\")\n f.write(\"parameter bias11_1 = (1328)+128;\\n\")\n f.write(\"parameter bias11_2 = (1456)+128;\\n\")\n f.write(\"parameter bias12_1 = (1584)+128;\\n\")\n f.write(\"parameter bias12_2 = (1712)+128;\\n\")\n f.write(\"parameter bias13_1 = (1840)+128;\\n\")\n f.write(\"parameter bias13_2 = (1968)+256;\\n\")\n f.write(\"parameter bias14_1 = (2224)+256;\\n\")\n f.write(\"parameter bias14_2_1 = (2480)+(256>>1);\\n\")\n f.write(\"parameter bias14_2_2 = (2608)+(256>>1);\\n\")\n f.write(\"\\n\")\n f.write(\"\\n\")\n f.write(\"always @(step)\\n\")\n f.write(\"case (step) \\n\")\n f.write(\"8'd1: begin //weights conv1 \\n\")\n f.write(\"\t\tfirstaddr = 0;\\n\")\n f.write(\"\t\tlastaddr = conv1;\\n\")\n f.write(\"\t\tre_weights = 1;\\n\")\n f.write(\"\t\tre_bias = 0;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd2: begin\t//bias conv1\\n\")\n f.write(\"\t\tfirstaddr = 0;\\n\")\n f.write(\"\t\tlastaddr = bias1;\\n\")\n f.write(\"\t\tre_weights = 0;\\n\")\n f.write(\"\t\tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd4: begin //weights conv2 dw 1\\n\")\n f.write(\"\t\tfirstaddr = conv1;\\n\")\n f.write(\"\t\tlastaddr = conv2_1;\\n\")\n f.write(\"\t\tre_weights = 1;\\n\")\n f.write(\"\t\tre_bias = 0;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd5: begin\t//bias conv2 dw\\n\")\n f.write(\"\t\tfirstaddr = bias1;\\n\")\n f.write(\"\t\tlastaddr = bias2_1;\\n\")\n f.write(\"\t\tre_weights = 0;\\n\")\n f.write(\"\t\tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd7: begin //weights conv2 1x1\\n\")\n f.write(\"\t\tfirstaddr = conv2_1;\\n\")\n f.write(\"\t\tlastaddr = conv2_2;\\n\")\n f.write(\"\t\tre_weights = 1;\\n\")\n f.write(\"\t\tre_bias = 0;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd8: begin //bias conv2 1x1\\n\")\n f.write(\"\t\tfirstaddr = bias2_1;\\n\")\n f.write(\"\t\tlastaddr = bias2_2;\\n\")\n f.write(\"\t\tre_weights = 0;\\n\")\n f.write(\"\t\tre_bias = 1;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd10: begin //weights conv3 dw 2\\n\")\n f.write(\"\t\tfirstaddr = conv2_2;\\n\")\n f.write(\"\t\tlastaddr = conv3_1;\\n\")\n f.write(\"\t\tre_weights = 1;\\n\")\n f.write(\"\t\tre_bias = 0;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd11: begin //bias conv3 DW\\n\")\n f.write(\"\t\tfirstaddr = bias2_2;\\n\")\n f.write(\"\t\tlastaddr = bias3_1;\\n\")\n f.write(\"\t\tre_weights = 0;\\n\")\n f.write(\"\t\tre_bias = 1;\\n\")\n f.write(\"\t end\\n\")\n f.write(\"8'd13: begin //weights conv3 1x1\\n\")\n f.write(\" \tfirstaddr = conv3_1;\\n\")\n f.write(\" \tlastaddr = conv3_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd14: begin //bias conv\\n\")\n f.write(\" \tfirstaddr = bias3_1;\\n\")\n f.write(\" \tlastaddr = bias3_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd16: begin\\n\")\n f.write(\" \tfirstaddr = conv3_2; // dw 3\\n\")\n f.write(\" \tlastaddr = conv4_1;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd17: begin\\n\")\n f.write(\" \tfirstaddr = bias3_2;\\n\")\n f.write(\" \tlastaddr = bias4_1;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd19: begin\\n\")\n f.write(\" \tfirstaddr = conv4_1;\\n\")\n f.write(\" \tlastaddr = conv4_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd20: begin\\n\")\n f.write(\" \tfirstaddr = bias4_1;\\n\")\n f.write(\" \tlastaddr = bias4_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd22: begin\\n\")\n f.write(\" \tfirstaddr = conv4_2; // dw 4\\n\")\n f.write(\" \tlastaddr = conv5_1;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd23: begin\\n\")\n f.write(\" \tfirstaddr = bias4_2;\\n\")\n f.write(\" \tlastaddr = bias5_1;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd25: begin\\n\")\n f.write(\" \tfirstaddr = conv5_1;\\n\")\n f.write(\" \tlastaddr = conv5_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd26: begin\\n\")\n f.write(\" \tfirstaddr = bias5_1;\\n\")\n f.write(\" \tlastaddr = bias5_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd28: begin\\n\")\n f.write(\" \tfirstaddr = conv5_2; // dw 5\\n\")\n f.write(\" \tlastaddr = conv6_1;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd29: begin\\n\")\n f.write(\" \tfirstaddr = bias5_2;\\n\")\n f.write(\" \tlastaddr = bias6_1;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd31: begin\\n\")\n f.write(\" \tfirstaddr = conv6_1;\\n\")\n f.write(\" \tlastaddr = conv6_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd32: begin\\n\")\n f.write(\" \tfirstaddr = bias6_1;\\n\")\n f.write(\" \tlastaddr = bias6_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd34: begin\\n\")\n f.write(\" \tfirstaddr = conv6_2; // dw 6\\n\")\n f.write(\" \tlastaddr = conv7_1;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd35: begin\\n\")\n f.write(\" \tfirstaddr = bias6_2;\\n\")\n f.write(\" \tlastaddr = bias7_1;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd37: begin\\n\")\n f.write(\" \tfirstaddr = conv7_1;\\n\")\n f.write(\" \tlastaddr = conv7_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd38: begin\\n\")\n f.write(\" \tfirstaddr = bias7_1;\\n\")\n f.write(\" \tlastaddr = bias7_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd40: begin\\n\")\n f.write(\" \tfirstaddr = conv7_2; // dw 7\\n\")\n f.write(\" \tlastaddr = conv8_1;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd41: begin\\n\")\n f.write(\" \tfirstaddr = bias7_2;\\n\")\n f.write(\" \tlastaddr = bias8_1;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd43: begin\\n\")\n f.write(\" \tfirstaddr = conv8_1;\\n\")\n f.write(\" \tlastaddr = conv8_2;\\n\")\n f.write(\" \tre_weights = 1;\\n\")\n f.write(\" \tre_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd44: begin\\n\")\n f.write(\" \tfirstaddr = bias8_1;\\n\")\n f.write(\" \tlastaddr = bias8_2;\\n\")\n f.write(\" \tre_weights = 0;\\n\")\n f.write(\" \tre_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd46: begin\\n\")\n f.write(\"\t firstaddr = conv8_2; // dw 8\\n\")\n f.write(\"\t lastaddr = conv9_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd47: begin\\n\")\n f.write(\"\t firstaddr = bias8_2;\\n\")\n f.write(\"\t lastaddr = bias9_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd49: begin\\n\")\n f.write(\"\t firstaddr = conv9_1;\\n\")\n f.write(\"\t lastaddr = conv9_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd50: begin\\n\")\n f.write(\"\t firstaddr = bias9_1;\\n\")\n f.write(\"\t lastaddr = bias9_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd52: begin\\n\")\n f.write(\"\t firstaddr = conv9_2; // dw 9\\n\")\n f.write(\"\t lastaddr = conv10_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd53: begin\\n\")\n f.write(\"\t firstaddr = bias9_2;\\n\")\n f.write(\"\t lastaddr = bias10_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd55: begin\\n\")\n f.write(\"\t firstaddr = conv10_1;\\n\")\n f.write(\"\t lastaddr = conv10_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd56: begin\\n\")\n f.write(\"\t firstaddr = bias10_1;\\n\")\n f.write(\"\t lastaddr = bias10_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd58: begin\\n\")\n f.write(\"\t firstaddr = conv10_2; // dw 10\\n\")\n f.write(\"\t lastaddr = conv11_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd59: begin\\n\")\n f.write(\"\t firstaddr = bias10_2;\\n\")\n f.write(\"\t lastaddr = bias11_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd61: begin\\n\")\n f.write(\"\t firstaddr = conv11_1;\\n\")\n f.write(\"\t lastaddr = conv11_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd62: begin\\n\")\n f.write(\"\t firstaddr = bias11_1;\\n\")\n f.write(\"\t lastaddr = bias11_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd64: begin\\n\")\n f.write(\"\t firstaddr = conv11_2; // dw 11\\n\")\n f.write(\"\t lastaddr = conv12_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd65: begin\\n\")\n f.write(\"\t firstaddr = bias11_2;\\n\")\n f.write(\"\t lastaddr = bias12_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd67: begin\\n\")\n f.write(\"\t firstaddr = conv12_1;\\n\")\n f.write(\"\t lastaddr = conv12_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd68: begin\\n\")\n f.write(\"\t firstaddr = bias12_1;\\n\")\n f.write(\"\t lastaddr = bias12_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd70: begin\\n\")\n f.write(\"\t firstaddr = conv12_2; // dw 12\\n\")\n f.write(\"\t lastaddr = conv13_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd71: begin\\n\")\n f.write(\"\t firstaddr = bias12_2;\\n\")\n f.write(\"\t lastaddr = bias13_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd73: begin\\n\")\n f.write(\"\t firstaddr = conv13_1;\\n\")\n f.write(\"\t lastaddr = conv13_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd74: begin\\n\")\n f.write(\"\t firstaddr = bias13_1;\\n\")\n f.write(\"\t lastaddr = bias13_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd76: begin\\n\")\n f.write(\"\t firstaddr = conv13_2; // dw 13\\n\")\n f.write(\"\t lastaddr = conv14_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd77: begin\\n\")\n f.write(\"\t firstaddr = bias13_2;\\n\")\n f.write(\"\t lastaddr = bias14_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd79: begin\\n\")\n f.write(\"\t firstaddr = conv14_1;\\n\")\n f.write(\"\t lastaddr = conv14_2_1;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd80: begin\\n\")\n f.write(\"\t firstaddr = bias14_1;\\n\")\n f.write(\"\t lastaddr = bias14_2_1;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd82: begin\\n\")\n f.write(\"\t firstaddr = conv14_2_1;\\n\")\n f.write(\"\t lastaddr = conv14_2_2;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd83: begin\\n\")\n f.write(\"\t firstaddr = bias14_2_1;\\n\")\n f.write(\"\t lastaddr = bias14_2_2;\\n\")\n f.write(\"\t re_weights = 0;\\n\")\n f.write(\"\t re_bias = 1;\\n\")\n f.write(\" end\\n\")\n f.write(\"8'd85: begin\\n\")\n f.write(\"\t firstaddr = conv14_2_2;\\n\")\n f.write(\"\t lastaddr = predict;\\n\")\n f.write(\"\t re_weights = 1;\\n\")\n f.write(\"\t re_bias = 0;\\n\")\n f.write(\" end\\n\")\n f.write(\"default:\\n\")\n f.write(\"\t\tbegin\\n\")\n f.write(\"\t\t\tre_weights = 0;\\n\")\n f.write(\"\t\t\tre_bias = 0;\\n\")\n f.write(\"\t\tend\\n\")\n f.write(\"endcase\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef border(directory, razmer):\n f = open(directory + \"border.v\",'w')\n\n bit_matrix = len(bin(razmer))-2\n bit_matrix_2=len(bin(razmer*razmer))-2\n\n f.write(\"module border(\\n\")\n f.write(\" input clk, go,\\n\")\n f.write(\" input [\"+str(bit_matrix_2-1)+\":0] i,\\n\")\n f.write(\" input [\"+str(bit_matrix-1)+\":0] matrix,\\n\")\n f.write(\" output reg [1:0] prov\\n\")\n f.write(\");\\n\")\n f.write(\"\talways @(posedge clk)\\n\")\n f.write(\"\tbegin\t\\n\")\n f.write(\"\t\tif (go == 1)\\n\")\n f.write(\"\t\tbegin\\n\")\n f.write(\"\t\t\tprov = 0;\\n\")\n for i in range(128):\n f.write(\"\t\t\t\tif ((i == \"+str(i+1)+\"*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\\n\")\n f.write(\"\\n\")\n for i in range(128+1):\n f.write(\" if ((i == \"+str(i)+\"*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\\n\")\n f.write(\"\t\tend\\n\")\n f.write(\"\t\telse\\n\")\n f.write(\"\t\t\tprov = 0;\\n\")\n f.write(\"\tend\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef conv_block(directory,razmer):\n f = open(directory + \"conv.v\",'w')\n\n bit_matrix = len(bin(razmer)) - 2\n bit_matrix_2 = len(bin(razmer*razmer)) - 2\n\n f.write(\"module conv(clk,Y1,prov,matrix,matrix2,i,up_perm,down_perm,p1,p2,p3,w1,w2,w3,conv_en,dense_en,stride_plus_prov);\\n\")\n f.write(\"\\n\")\n f.write(\"parameter SIZE=0;\\n\")\n f.write(\"parameter SIZE_address_pix=18;\\n\")\n f.write(\"parameter SIZE_weights=0;\\n\")\n f.write(\"\\n\")\n f.write(\"input clk;\\n\")\n f.write(\"output reg signed [32-1:0] Y1;\\n\")\n f.write(\"input [1:0] prov;\\n\")\n f.write(\"input [\"+str(bit_matrix-1)+\":0] matrix;\\n\")\n f.write(\"input [\"+str(bit_matrix_2-1)+\":0] matrix2;\\n\")\n f.write(\"input [\"+str(bit_matrix_2-1)+\":0] i;\\n\")\n f.write(\"input up_perm,down_perm;\\n\")\n f.write(\"input signed [SIZE-1:0] p1,p2,p3;\\n\")\n f.write(\"input signed [SIZE_weights-1:0] w1,w2,w3;\\n\")\n f.write(\"input conv_en;\\n\")\n f.write(\"input dense_en;\\n\")\n f.write(\"input [SIZE_address_pix-1:0] stride_plus_prov;\\n\")\n f.write(\"\\n\")\n f.write(\"wire up,down;\\n\")\n f.write(\"\\n\")\n f.write(\"assign up = (((i+stride_plus_prov)<=matrix-1'b1)&&(up_perm))?1'b1:1'b0;\\n\")\n f.write(\"assign down = (((i+stride_plus_prov)>=matrix2-matrix)&&(down_perm))?1'b1:1'b0;\\n\")\n f.write(\"\\n\")\n f.write(\"always @(posedge clk)\\n\")\n f.write(\" begin\\n\")\n f.write(\"\t\tif (conv_en==1)\\n\")\n f.write(\"\t\t\tbegin\\n\")\n f.write(\"\t\t\t\tY1=0;\\n\")\n f.write(\"\t\t\t\tif ((prov!=2'b11)&&(!up)&&(!down)) Y1 = Y1+(p1*w1);\\n\")\n f.write(\"\t\t\t\tif ((!up)&&(!down)) Y1 = Y1+(p2*w2);\\n\")\n f.write(\"\t\t\t\tif ((prov!=2'b10)&&(!up)&&(!down)) Y1 = Y1+(p3*w3);\\n\")\n f.write(\"\t\t\tend\\n\")\n f.write(\" end\\n\")\n f.write(\"\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef conv_TOP(directory, razmer, max_conv_input_size, max_conv_output_size, num_conv, steps_count, sizeI, sizeW):\n f = open(directory + \"conv_TOP.v\", 'w')\n\n bit_matrix=len(bin(razmer))-2\n bit_matrix_2=len(bin(razmer*razmer))-2\n bit_max_conv_input_size = len(bin(max_conv_input_size)) - 2\n bit_max_conv_output_size = len(bin(max_conv_output_size)) - 2\n bit_razmer_2 = len(bin(razmer * razmer)) - 2\n bit_steps_count = len(bin(steps_count)) - 2\n Y=''\n w=''\n p=''\n res_out=''\n res=''\n res_old=''\n glob_average_perem=''\n glob_average_perem_1=''\n res_bias_check=''\n data_bias=''\n for i in range(num_conv):\n Y = Y + \"Y\" + str(i + 1) + \",\"\n w = w + \"w\"+str(i+1)+\"1,w\"+str(i+1)+\"2,w\"+str(i+1)+\"3,\"\n p = p + \"p\" + str(i) + \"_1,p\" + str(i) + \"_2,p\" + str(i) + \"_3,\"\n res_out = res_out + \"res_out_\" +str(i+1) + \",\"\n res = res + \"res\"+ str(i+1) + \",\"\n res_old = res_old + \"res_old_\" + str(i+1) + \",\"\n glob_average_perem = glob_average_perem + \"glob_average_perem_\" + str(i+1) + \",\"\n glob_average_perem_1 = glob_average_perem_1 + \"glob_average_perem_\" + str(i + 1) + \"_1,\"\n res_bias_check = res_bias_check + \"res_bias_check_\" + str(i+1) + \",\"\n data_bias = data_bias + \"data_bias_\" + str(i+1) + \",\"\n\n f.write(\"module conv_TOP(clk,conv_en,STOP,memstartp,memstartw,memstartzap,read_addressp,write_addressp,read_addresstp,write_addresstp,read_addressw,we,re_wb,re,we_t,re_t,qp,qtp,qw,dp,dtp,prov,matrix,matrix2,i_to_prov,lvl,slvl,mem,\")\n f.write(Y)\n f.write(w)\n f.write(p)\n f.write(\"go,up_perm,down_perm,num,filt,bias,glob_average_en,step,stride,depthwise,onexone,q_bias,read_addressb,memstartb,stride_plus_prov);\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"parameter SIZE_\"+str(i+1)+\"=0;\\n\")\n f.write(\"parameter SIZE_address_pix=13;\\n\")\n f.write(\"parameter SIZE_address_pix_t=12;\\n\")\n f.write(\"parameter SIZE_address_wei=13;\\n\")\n f.write(\"parameter SIZE_weights=0;\\n\")\n f.write(\"parameter SIZE_bias=0;\\n\")\n f.write(\"\\n\")\n f.write(\"input clk,conv_en,glob_average_en;\\n\")\n f.write(\"input [1:0] prov;\\n\")\n f.write(\"input [\"+str(bit_matrix-1)+\":0] matrix;\\n\")\n f.write(\"input [\"+str(bit_matrix_2-1)+\":0] matrix2;\\n\")\n f.write(\"input [SIZE_address_pix-1:0] memstartp;\\n\")\n f.write(\"input [SIZE_address_wei-1:0] memstartw;\\n\")\n f.write(\"input [SIZE_address_pix-1:0] memstartzap;\\n\")\n f.write(\"input [10:0]\t\t\t\t memstartb;\\n\")\n f.write(\"input [\"+str(bit_max_conv_input_size-1)+\":0] lvl;\\n\")\n f.write(\"input [8:0] slvl;\\n\")\n f.write(\"output reg [SIZE_address_pix-1:0] read_addressp;\\n\")\n f.write(\"output reg [SIZE_address_pix_t-1:0] read_addresstp;\\n\")\n f.write(\"output reg [SIZE_address_wei-1:0] read_addressw;\\n\")\n f.write(\"output reg [10:0]\t\t\t\t read_addressb;\\n\")\n f.write(\"output reg [SIZE_address_pix-1:0] write_addressp;\\n\")\n f.write(\"output reg [SIZE_address_pix_t-1:0] write_addresstp;\\n\")\n f.write(\"output reg we,re,re_wb;\\n\")\n f.write(\"output reg we_t,re_t;\\n\")\n f.write(\"input signed [SIZE_\"+str(num_conv)+\"-1:0] qp;\\n\")\n f.write(\"input signed [32*\"+str(num_conv)+\"-1:0] qtp;\\n\")\n f.write(\"input signed [SIZE_weights*9-1:0] qw;\\n\")\n f.write(\"input signed [SIZE_bias-1:0] q_bias;\\n\")\n f.write(\"output signed [SIZE_\"+str(num_conv)+\"-1:0] dp;\\n\")\n f.write(\"output signed [32*\"+str(num_conv)+\"-1:0] dtp;\\n\")\n f.write(\"output reg STOP;\\n\")\n f.write(\"output reg [\"+str(bit_razmer_2-1)+\":0] i_to_prov;\\n\")\n f.write(\"input signed [32-1:0] \"+Y[:-1]+\";\\n\")\n f.write(\"output reg signed [SIZE_weights-1:0] \"+w[:-1]+\";\\n\")\n f.write(\"output reg signed [SIZE_1-1:0] \"+p[:-1]+\";\\n\")\n f.write(\"output reg go;\\n\")\n f.write(\"output reg up_perm,down_perm;\\n\")\n f.write(\"input [2:0] num;\\n\")\n f.write(\"input [\"+str(bit_max_conv_output_size-1)+\":0] mem;\\n\")\n f.write(\"input [\"+str(bit_max_conv_input_size-1)+\":0] filt;\\n\")\n f.write(\"input bias;\\n\")\n f.write(\"input [\"+str(bit_steps_count-1)+\":0] step;\\n\")\n f.write(\"input [1:0] stride;\\n\")\n f.write(\"output reg [SIZE_address_pix-1:0] stride_plus_prov;\\n\")\n f.write(\"\\n\")\n f.write(\"input depthwise,onexone;\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"reg signed [SIZE_weights-1:0] w\" + str(i + 1) + \"1_pre,w\" + str(i + 1) + \"2_pre,w\" + str(i + 1) + \"3_pre,w\" + str(i + 1) + \"4_pre,w\" + str(i + 1) + \"5_pre,w\" + str(i + 1) + \"6_pre,w\" + str(i + 1) + \"7_pre,w\" + str(i + 1) + \"8_pre,w\" + str(i + 1) + \"9_pre;\\n\")\n f.write(\"reg signed [SIZE_1-1:0]\")\n for i in range(int(num_conv/4)):\n f.write(\"p\" + str(0+8*i) + \"_pre,p\" + str(1+8*i) + \"_pre,p\" + str(2+8*i) + \"_pre,p\" + str(3+8*i) + \"_pre,p\" + str(4+8*i) + \"_pre,p\" + str(5+8*i) + \"_pre,p\" + str(6+8*i) + \"_pre,p\" + str(7+8*i) + \"_pre\")\n if ((i+1)==(int(num_conv/4))): f.write(\";\")\n else: f.write(\",\")\n f.write(\"\\n\")\n f.write(\"reg signed [SIZE_1-1:0] \"+res_out[:-1]+\";\\n\")\n f.write(\"reg signed [32-1:0] \"+res[:-1]+\";\\n\")\n f.write(\"reg signed [32-1:0] \"+res_old[:-1]+\";\\n\")\n f.write(\"reg signed [21:0] \"+glob_average_perem[:-1]+\";\\n\")\n f.write(\"wire signed [SIZE_1-1:0] \"+glob_average_perem_1[:-1]+\";\\n\")\n f.write(\"\\n\")\n f.write(\"reg signed [SIZE_1-1:0]\")\n for i in range(num_conv):\n f.write(\"buff\" + str(i) + \"_0 [2:0]\")\n if (i != (num_conv-1)): f.write(\", \")\n else: f.write(\";\\n\")\n f.write(\"reg signed [SIZE_1-1:0]\")\n for i in range(num_conv):\n f.write(\"buff\" + str(i) + \"_1 [2:0]\")\n if (i != (num_conv-1)): f.write(\", \")\n else: f.write(\";\\n\")\n f.write(\"reg signed [SIZE_1-1:0]\")\n for i in range(num_conv):\n f.write(\"buff\" + str(i) + \"_2 [2:0]\")\n if (i != (num_conv-1)): f.write(\", \")\n else: f.write(\";\\n\")\n f.write(\"\\n\")\n f.write(\"reg [4:0] marker;\\n\")\n f.write(\"reg zagryzka_weight;\\n\")\n f.write(\"reg [15:0] i;\\n\")\n f.write(\"reg [15:0] i_onexone,i_onexone_1;\\n\")\n f.write(\"wire [15:0] i_onexone_plus1;\\n\")\n f.write(\"assign i_onexone_plus1 = i_onexone + 1'b1;\\n\")\n f.write(\"reg [SIZE_address_pix-1:0] stride_plus,next_number,next_number_prov;\\n\")\n f.write(\"\\n\")\n f.write(\"reg signed [19-1:0] \"+res_bias_check[:-1]+\";\\n\")\n f.write(\"\\n\")\n f.write(\"reg signed [SIZE_bias-1:0] \" + data_bias[:-1]+\";\\n\")\n f.write(\"\\n\")\n f.write(\"initial zagryzka_weight=0;\\n\")\n f.write(\"initial marker=0;\\n\")\n f.write(\"\\n\")\n f.write(\"wire [15:0] line_stride;\\n\")\n f.write(\"\\n\")\n f.write(\"assign line_stride=matrix>>(stride-1);\\n\")\n f.write(\"\\n\")\n f.write(\"always @(posedge clk)\\n\")\n f.write(\"begin\\n\")\n f.write(\"if (conv_en==1)\\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\tif (zagryzka_weight==0)\\n\")\n f.write(\"\t\tbegin\\n\")\n f.write(\"\t\t next_number = matrix;\\n\")\n f.write(\"\t\t next_number_prov = matrix;\\n\")\n f.write(\"\t\t if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus=0;\\n\")\n f.write(\"\t\t else stride_plus=matrix;\\n\")\n f.write(\"\t\t if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus_prov=0;\\n\")\n f.write(\"\t\t else stride_plus_prov=matrix;\\n\")\n f.write(\"\t\t case (marker)\\n\")\n\n for i in range(num_conv+2):\n f.write(\"\t\t\t\t\"+str(i)+\": begin\\n\")\n if (i==0): f.write(\"\t\t\t\t re_wb=1;\\n\")\n if (i < num_conv):\n f.write(\"\t\t\t\t read_addressw=memstartw+\" + str(i) + \"*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\\n\")\n f.write(\"\t\t\t\t read_addressb=memstartb+\" + str(i) + \";\\n\")\n if ((i=2)):\n for j in range(9):\n f.write(\"\t\t\t\t w\"+str(i-1)+str(j+1)+\"_pre=qw[SIZE_weights*\"+str(j+1)+\"-1:\")\n if (j==0): f.write(\"0\")\n else: f.write(\"SIZE_weights*\"+str(j))\n f.write(\"]; \\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t data_bias_\" + str(i-1) + \" = q_bias;\\n\")\n if (i == num_conv + 1): f.write(\"\t\t\t\t zagryzka_weight=1; re_wb=0; marker=-1;\\n\")\n f.write(\"\t\t\t\tend\\n\")\n f.write(\"\t\t\t\tdefault: \\n\")\n f.write(\"\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\tread_addressw=0;\\n\")\n f.write(\"\t\t\t\t\t\tread_addressb=0;\\n\")\n f.write(\"\t\t\t\t\t\tre_wb=0;\\n\")\n f.write(\"\t\t\t\t\t\t$display(\\\"Check zagryzka_weight\\\");\\n\")\n f.write(\"\t\t\t\t\tend\\n\")\n f.write(\"\t\tendcase\\n\")\n f.write(\"\t\tmarker=marker+1;\\n\")\n f.write(\"\t\tend\\n\")\n f.write(\"\t\telse\\n\")\n f.write(\"\t\tbegin\\n\")\n f.write(\"\t\t\tre=1;\\n\")\n f.write(\"\t\t\tcase (marker)\\n\")\n f.write(\"\t\t\t\t0: begin\t\\n\")\n f.write(\"\t\t\t\t\t\t\t\tre_t=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif ((stride==2)&&(i==next_number))\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tstride_plus=stride_plus+matrix;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tnext_number = matrix+next_number;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse read_addressp=i+memstartp+stride_plus;\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_1=p6_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_2=p7_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_3=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (depthwise)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_2[2]=qp[SIZE_\" + str(num_conv-i) + \"-1:\")\n if (num_conv==(i+1)): f.write(\"0\")\n else: f.write(\"SIZE_\"+ str(num_conv-i-1))\n f.write(\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tif (((i+stride_plus-1)1):\n if (i==0):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t if\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t else if\")\n f.write(\" ({\"+lvl[1:]+\"}==\"+str(len(bin(num_conv))-3)+\"'d\"+str(i)+\") \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_2[2]=qp[\"+one_size+\"-1:\"+two_size+\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"2[2]=qp[SIZE_1-1:0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_2[2]=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_1=buff\" + str(i) + \"_2[0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_2=buff\" + str(i) + \"_2[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_3=buff\" + str(i) + \"_2[2];\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\\n\")\n\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"1=(onexone)?w\" + str(i+1) + \"3_pre:w\" + str(i+1) + \"3_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"2=(onexone)?w\" + str(i+1) + \"2_pre:w\" + str(i+1) + \"2_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"3=(onexone)?w\" + str(i+1) + \"1_pre:w\" + str(i+1) + \"1_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tup_perm=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) down_perm=0; else down_perm=1;\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tres\" + str(i+1) + \"=Y\" + str(i+1) + \";\\n\")\n f.write(\"\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t1: begin\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse\tif ((i+stride_plus)>=matrix-1)\tread_addressp=i-matrix+memstartp+stride_plus;\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tres\" + str(i+1) + \"=res\" + str(i+1) + \"+Y\" + str(i+1) + \";\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1))) \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tres_old_\" + str(i+1) + \"=qtp[32*\" + str(num_conv-i) + \"-1:32*\")\n if (num_conv==(i+1)): f.write(\"0\")\n else: f.write(str(num_conv-i-1))\n f.write(\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\tgo=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\ti_to_prov=i_to_prov+1'b1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif ((stride==2)&&(i_to_prov==next_number_prov)) \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tstride_plus_prov=stride_plus_prov+matrix;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tnext_number_prov = matrix+next_number_prov;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_2[0]=buff\" + str(i) + \"_2[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_1[0]=buff\" + str(i) + \"_1[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_0[0]=buff\" + str(i) + \"_0[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_2[1]=buff\" + str(i) + \"_2[2];\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_1[1]=buff\" + str(i) + \"_1[2];\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_0[1]=buff\" + str(i) + \"_0[2];\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t2: begin\\n\")\n f.write(\"\t\t\t\t\t\t\tif (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\\n\")\n f.write(\"\t\t\t\t\t\t\telse\tif ((i+stride_plus)1):\n if (i==0):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tif\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\telse if\")\n f.write(\" ({\"+lvl[1:]+\"}==\"+str(len(bin(num_conv))-3)+\"'d\"+str(i)+\") \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_1[2]=qp[\"+one_size+\"-1:\"+two_size+\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"1[2]=qp[SIZE_1-1:0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tend\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_1=buff\" + str(i) + \"_1[0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_2=buff\" + str(i) + \"_1[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_3=buff\" + str(i) + \"_1[2];\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tend\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"1=(onexone)?w\" + str(i+1) + \"9_pre:w\" + str(i+1) + \"6_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"2=(onexone)?w\" + str(i+1) + \"8_pre:w\" + str(i+1) + \"5_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"3=(onexone)?w\" + str(i+1) + \"7_pre:w\" + str(i+1) + \"4_pre;\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tgo=1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tup_perm=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tdown_perm=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1)))\\n\")\n f.write(\"\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) write_addresstp=i_onexone-2;\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse write_addresstp=(i>>(stride-1))-1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (glob_average_en) write_addressp=memstartzap;\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (onexone)\twrite_addressp=memstartzap+i_onexone-2;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\telse\t\t\twrite_addressp=memstartzap+((i-2)>>(stride-1));\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (((onexone && (i_onexone_1 == 0)) || !onexone)&&(!bias)) we_t=1;\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tres\" + str(i+1) + \"=res\" + str(i+1) + \"+Y\" + str(i+1) + \";\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif ((lvl!=0)&&(!depthwise))\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tres\" + str(i+1) + \"=res\" + str(i+1) + \"+res_old_\" + str(i+1) + \";\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (bias)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tres\" + str(i+1) + \"=res\" + str(i+1) + \"+(data_bias_\" + str(i+1) + \"<<\"+str(sizeI+1)+\");\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (res\" + str(i+1) + \"<0) res\" + str(i+1) + \"=0; //RELU\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tres_bias_check_\" + str(i+1) + \"=res\" + str(i+1) + \"[\"+ str(sizeI+sizeW+2) +\"-1-2:SIZE_1-2];\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (res_bias_check_\" + str(i+1) + \">(2**(SIZE_1-1))-1) res_out_\" + str(i+1) + \"=(2**(SIZE_1-1))-1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\telse res_out_\" + str(i+1) + \"=res\" + str(i+1) + \"[SIZE_1+SIZE_1-2-2:SIZE_1-2];\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif ((glob_average_en)&&(i_onexone_1 == 0))\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_\" + str(i+1) + \" = glob_average_perem_\" + str(i+1) + \" + res_out_\" + str(i+1) + \";\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif ((onexone && (i_onexone_1 == 0)) || !onexone) we=1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t3: begin\\n\")\n f.write(\"\t\t\t\t\t\t\t\tre_t=1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) read_addresstp=i_onexone-1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse read_addresstp=(i>>(stride-1))-1;\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n if (num_conv<8):\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(num_conv+i) + \"_pre = qp[SIZE_\" + str(num_conv-i) + \"-1:\")\n if (num_conv==(i+1)): f.write(\"0\")\n else: f.write(\"SIZE_\" + str(num_conv-i-1))\n f.write(\"];\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_1=p3_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_2=p4_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_3=p5_pre;\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (depthwise)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_0[2]=qp[SIZE_\" + str(num_conv-i) + \"-1:\")\n if (num_conv==(i+1)): f.write(\"0\")\n else: f.write(\"SIZE_\" + str(num_conv-i-1))\n f.write(\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tif ((i+stride_plus)>=matrix-1)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n\n lvl=''\n for i in range(len(bin(num_conv))-3):\n lvl = \",lvl[\"+str(i)+\"]\" + lvl\n for i in range(num_conv):\n one_size=\"SIZE_\"+str(num_conv-i)\n if ((num_conv-i-1)==0): two_size=\"0\"\n else: two_size=\"SIZE_\"+str(num_conv-i-1)\n if (num_conv>1):\n if (i==0):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tif\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\telse if\")\n f.write(\" ({\"+lvl[1:]+\"}==\"+str(len(bin(num_conv))-3)+\"'d\"+str(i)+\") \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_0[2]=qp[\"+one_size+\"-1:\"+two_size+\"];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n else:\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"0[2]=qp[SIZE_1-1:0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\telse\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff\" + str(i) + \"_0[2]=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_1=buff\" + str(i) + \"_0[0];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_2=buff\" + str(i) + \"_0[1];\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tp\" + str(i) + \"_3=buff\" + str(i) + \"_0[2];\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tend\\n\")\n for i in range(num_conv):\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"1=(onexone)?w\" + str(i+1) + \"6_pre:w\" + str(i+1) + \"9_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"2=(onexone)?w\" + str(i+1) + \"5_pre:w\" + str(i+1) + \"8_pre;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tw\" + str(i+1) + \"3=(onexone)?w\" + str(i+1) + \"4_pre:w\" + str(i+1) + \"7_pre;\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\t\t\t\t\t\tif (onexone) up_perm=0; else up_perm=1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tdown_perm=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\twe_t=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\twe=0;\\n\")\n f.write(\"\t\t\t\t\tend\t\t\\n\")\n f.write(\"\t\t\tdefault: $display(\\\"Check case conv_TOP\\\");\\n\")\n f.write(\"\t\t\tendcase\\n\")\n f.write(\"\\n\")\n f.write(\"\t\t\tif (marker!=3) marker=marker+1;\\n\")\n f.write(\"\t\t\telse begin \\n\")\n f.write(\"\t\t\t\t\tmarker=0; \\n\")\n f.write(\"\t\t\t\t\tif (((i>2)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\ti_onexone = i_onexone + 1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\ti_onexone_1 = 0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\telse\ti_onexone_1 = i_onexone_1 + 1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\telse STOP=1; \\n\")\n f.write(\"\t\t\t\t end\\n\")\n f.write(\"\t\tend\\n\")\n f.write(\"\tend\\n\")\n f.write(\"else \\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\ti=0;\\n\")\n f.write(\"\t\ti_to_prov=-2;\\n\")\n f.write(\"\t\tstride_plus=0;\\n\")\n f.write(\"\t\tnext_number=matrix;\\n\")\n f.write(\"\t\tzagryzka_weight=0;\\n\")\n f.write(\"\t\tSTOP=0;\\n\")\n f.write(\"\t\tre=0;\\n\")\n f.write(\"\t\tre_t=0;\\n\")\n f.write(\"\t\tgo=0;\\n\")\n f.write(\"\t\tmarker=0;\\n\")\n for i in range(num_conv):\n f.write(\"\t\tglob_average_perem_\"+str(i+1)+\"=0;\\n\")\n f.write(\"\t\ti_onexone = 0;\\n\")\n f.write(\"\t\ti_onexone_1 = 0;\\n\")\n f.write(\"\t\tread_addressw=0;\\n\")\n f.write(\"\t\tread_addressb=0;\\n\")\n f.write(\"\t\tre_wb=0;\\n\")\n f.write(\"\tend\\n\")\n f.write(\"end\\n\")\n for i in range(num_conv):\n f.write(\"assign glob_average_perem_\" + str(i+1) + \"_1=glob_average_perem_\" + str(i+1) + \">>4;\\n\")\n f.write(\"assign dp={\")\n for i in range(num_conv):\n f.write(\"(glob_average_en?glob_average_perem_\" + str(i+1) + \"_1:res_out_\" + str(i+1) + \")\")\n if ((i+1)!=num_conv): f.write(\",\")\n f.write(\"\\n\")\n f.write(\"};\\n\")\n f.write(\"assign dtp={\" + str(res[:-1]) + \"};\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef dense(directory, in_dense_razmer, out_dense_razmer, num_conv, sizeI, sizeW):\n file = open(directory + \"dense.v\", 'w')\n\n bit_in = len(bin(in_dense_razmer)) - 2\n bit_out = len(bin(out_dense_razmer)) - 2\n Y=''\n w=''\n p=''\n Ypl=''\n Y_use=''\n Y_use_pl=''\n for i in range(num_conv):\n Y=Y+\" Y\"+str(i+1)+\",\"\n Y_use=Y_use+\" Y\"+str(i+1)+\"_use,\"\n Y_use_pl = Y_use_pl + \" Y\" + str(i + 1) + \"_use+\"\n Ypl = Ypl + \" (Y\" + str(i + 1) + \"_use?Y\" + str(i + 1) + \":0)+\"\n w=w+\" w\"+str(i+1)+\"1, w\"+str(i+1)+\"2, w\"+str(i+1)+\"3,\"\n p=p+\" p\"+str(i+1)+\"1, p\"+str(i+1)+\"2, p\"+str(i+1)+\"3,\"\n\n file.write(\"module dense(clk, dense_en, STOP, in, out, we, re_p, re_w, read_addressp, read_addressw, write_addressp, memstartp, memstartzap, qp, qw, res,\"+Y+w+p+\" go, nozero);\\n\\n\")\n file.write(\"parameter num_conv=0;\\n\")\n file.write(\"\\n\")\n for i in range(num_conv):\n file.write(\"parameter SIZE_\"+str(i+1)+\"=0;\\n\")\n file.write(\"parameter SIZE_address_pix=0;\\n\")\n file.write(\"parameter SIZE_address_wei=0;\\n\")\n file.write(\"parameter SIZE_weights=0;\\n\")\n file.write(\"\\n\")\n file.write(\"input clk,dense_en;\\n\")\n file.write(\"output reg STOP;\\n\")\n file.write(\"input [\"+str(bit_in-1)+\":0] in;\\n\")\n file.write(\"input [\"+str(bit_out-1)+\":0] out;\\n\")\n file.write(\"output reg we,re_p,re_w;\\n\")\n file.write(\"output reg [SIZE_address_pix-1:0] read_addressp;\\n\")\n file.write(\"output reg [SIZE_address_wei-1:0] read_addressw;\\n\")\n file.write(\"output reg [SIZE_address_pix-1:0] write_addressp;\\n\")\n file.write(\"input [SIZE_address_pix-1:0] memstartp,memstartzap;\\n\")\n file.write(\"input signed [SIZE_\"+str(num_conv)+\"-1:0] qp;\\n\")\n file.write(\"input signed [SIZE_weights*9-1:0] qw;\\n\")\n file.write(\"output reg signed [SIZE_\"+str(num_conv)+\"-1:0] res;\\n\")\n file.write(\"input signed [32-1:0]\"+Y[:-1]+\";\\n\")\n file.write(\"output reg signed [SIZE_weights - 1:0]\"+w[:-1]+\";\\n\")\n file.write(\"output reg signed [SIZE_1-1:0]\"+p[:-1]+\";\\n\")\n file.write(\"output reg go;\\n\")\n file.write(\"input nozero;\\n\")\n file.write(\"\\n\")\n for i in range(num_conv):\n file.write(\"reg signed[SIZE_weights - 1:0] w\"+str(i+1)+\"1_pre, w\"+str(i+1)+\"2_pre, w\"+str(i+1)+\"3_pre, w\"+str(i+1)+\"4_pre, w\"+str(i+1)+\"5_pre, w\"+str(i+1)+\"6_pre, w\"+str(i+1)+\"7_pre, w\"+str(i+1)+\"8_pre, w\"+str(i+1)+\"9_pre;\\n\")\n file.write(\"\\n\")\n for i in range(num_conv):\n file.write(\"reg signed[SIZE_1 - 1:0] p\"+str(i+1)+\"1_pre, p\"+str(i+1)+\"2_pre, p\"+str(i+1)+\"3_pre, p\"+str(i+1)+\"4_pre, p\"+str(i+1)+\"5_pre, p\"+str(i+1)+\"6_pre, p\"+str(i+1)+\"7_pre, p\"+str(i+1)+\"8_pre, p\"+str(i+1)+\"9_pre;\\n\")\n file.write(\"reg [3:0] marker;\\n\")\n file.write(\"reg [6:0] lvl;\\n\")\n file.write(\"reg [8:0] i;\\n\")\n file.write(\"reg [8:0] j;\\n\")\n\n bit_sh=len(bin(num_conv)) - 4\n if (bit_sh>0): sh=\"[\"+str(bit_sh)+\":0]\"\n else: sh=''\n\n file.write(\"reg \"+sh+\" sh;\\n\")\n file.write(\"reg signed [32-1:0] dp;\\n\") ###[(SIZE_2)*\"+str(num_conv)+\"-1:0]\n file.write(\"reg signed [SIZE_1-1:0] dp_shift;\\n\")\n file.write(\"reg signed [19-1:0]dp_check;\\n\\n\")\n file.write(\"always @(posedge clk)\\n\")\n file.write(\"begin\\n\")\n file.write(\" if (dense_en==1)\\n\")\n file.write(\" begin\\n\")\n file.write(\" re_p=1;\\n\")\n file.write(\" case (marker)\\n\") \n\n k1=1\n k2=1\n k3=1\n k4=1\n k7=1\n k8=1\n k9=1\n k10=1\n\n i=2\n STOP=0\n while (STOP==0):\n\n file.write(str(i)+\":begin\\n\")\n file.write(\" if (i>(in>>\"+str(len(bin(num_conv))-3)+\")+1) begin\\n\")\n file.write(\" \")\n for j in range(num_conv):\n file.write(\" p\"+str(k1)+str(k2)+\"_pre = 0;\")\n if (k2==9):\n k2=1\n k1+=1\n else: k2+=1\n\n file.write(\"\\n end\\n\")\n file.write(\" else begin\\n\")\n file.write(\" \")\n for j in range(num_conv):\n one=\"SIZE_\"+str(num_conv-j)\n if (num_conv-j-1==0): two=\"0\"\n else: two = \"SIZE_\"+str(num_conv - j - 1)\n file.write(\" p\"+str(k3)+str(k4)+\"_pre = qp[\"+one+\" - 1:\"+two+\"];\")\n if (k4==9):\n k4=1\n k3+=1\n else: k4+=1\n file.write(\"\\n end\\n\")\n\n file.write(\" \")\n if (((i>=2)|((i<2)&((i+num_conv)<=num_conv)))&(i<(num_conv+2))):\n k6=9\n for k5 in range(9):\n if (i<2): m=(num_conv*1+1)\n else: m=0\n file.write(\"w\"+str(i-1+m)+str(k5+1)+\"_pre=qw[SIZE_weights*\"+str(k6)+\"-1:SIZE_weights*\")\n if ((k6-1)==0): file.write(\"0]; \")\n else: file.write(str(k6-1)+\"]; \")\n k6-=1\n file.write(\"\\n\")\n\n if (i(in>>\"+str(len(bin(num_conv))-3)+\")+4)&&(marker==4))\\n\")\n file.write(\" begin\\n\")\n file.write(\" \t write_addressp=memstartzap+(lvl>>(num_conv>>1));\\n\")\n file.write(\" dp_check=dp[\"+str(sizeI+sizeW+2)+\"-1-2:SIZE_1-2];\\n\")\n file.write(\" if ((dp_shift<0)&&(nozero==0)) dp_shift=0;\\n\")\n file.write(\"\t\t if (dp_check>2**(SIZE_1-1)-1) dp_shift=2**(SIZE_1-1)-1;\\n\")\n file.write(\" else dp_shift=dp_check;\\n\")\n for i in range(num_conv):\n file.write(\" if (sh == \"+str(i)+\") begin\")\n if (i==0): file.write(\" res=0;\")\n file.write(\" res[SIZE_\"+str(num_conv-i)+\"-1:\")\n if (num_conv-i-1==0): file.write(\"0\")\n else: file.write(\"SIZE_\"+str(num_conv-i-1))\n file.write(\"]=dp_shift; end\\n\")\n file.write(\" lvl=lvl+1;\\n\")\n file.write(\" i=0; \\n\")\n file.write(\" j=0; \\n\")\n file.write(\" dp=0; \\n\")\n file.write(\" marker=0;\\n\")\n file.write(\" sh=sh+1; if (sh==num_conv) sh=0; \\n\")\n file.write(\"\t\t if ((sh==0)||(lvl==out)) we=1;\\n\")\n file.write(\" if (lvl==out) STOP=1;\\n\")\n file.write(\" end\\n\")\n file.write(\"end\\n\")\n file.write(\"else\\n\")\n file.write(\"begin\\n\")\n file.write(\" marker=0;\\n\")\n file.write(\" i=0;\\n\")\n file.write(\" j=0;\\n\")\n file.write(\" sh=0;\\n\")\n file.write(\" we=0;\\n\")\n file.write(\" dp=0;\\n\")\n file.write(\" res=0;\\n\")\n file.write(\" re_p=0;\\n\")\n file.write(\" re_w=0;\\n\")\n file.write(\" STOP=0;\\n\")\n file.write(\" lvl=0;\\n\")\n file.write(\"end\\n\")\n file.write(\"end\\n\")\n file.write(\"endmodule\\n\")\n\n file.close()\n\ndef RAM(directory, max_weights_per_layer, num_conv):\n f = open(directory + \"RAM.v\", 'w')\n\n f.write(\"module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk,clk_RAM_w,q_bias,d_bias,we_bias,re_bias,write_address_bias,read_address_bias);\\n\")\n f.write(\"parameter picture_size=0;\t\\n\")\n for i in range(num_conv):\n f.write(\"parameter SIZE_\"+str(i+1)+\"=0;\\n\")\n f.write(\"parameter SIZE_address_pix=13;\\n\")\n f.write(\"parameter SIZE_address_pix_t=12;\\n\")\n f.write(\"parameter SIZE_address_wei=13;\\n\")\n f.write(\"parameter SIZE_address_image=16;\\n\")\n f.write(\"parameter SIZE_weights=0;\\n\")\n f.write(\"parameter SIZE_bias=0;\\n\")\n f.write(\"\\n\")\n f.write(\"output reg signed [SIZE_\"+str(num_conv)+\"-1:0] qp; //read data\\n\")\n f.write(\"output reg signed [32*\"+str(num_conv)+\"-1:0] qtp; //read data\\n\")\n f.write(\"output reg signed [SIZE_weights*9-1:0] qw; //read weight\\n\")\n f.write(\"output reg signed [SIZE_bias-1:0] q_bias;\\n\")\n f.write(\"input signed [SIZE_1*\"+str(num_conv)+\"-1:0] dp; //write data\\n\")\n f.write(\"input signed [32*\"+str(num_conv)+\"-1:0] dtp; //write data\\n\")\n f.write(\"input signed [SIZE_weights*9-1:0] dw; //write weight\\n\")\n f.write(\"input signed [SIZE_bias-1:0] d_bias;\\n\")\n f.write(\"input [SIZE_address_pix-1:0] write_addressp, read_addressp;\\n\")\n f.write(\"input [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;\\n\")\n f.write(\"input [SIZE_address_wei-1:0] write_addressw, read_addressw;\\n\")\n f.write(\"input [10:0] write_address_bias,read_address_bias;\\n\")\n f.write(\"input we_p;\\n\")\n f.write(\"input we_tp;\\n\")\n f.write(\"input we_w;\\n\")\n f.write(\"input we_bias;\\n\")\n f.write(\"input re_p;\\n\")\n f.write(\"input re_tp;\\n\")\n f.write(\"input re_w;\\n\")\n f.write(\"input re_bias;\\n\")\n f.write(\"input clk,clk_RAM_w;\\n\")\n f.write(\"\\n\")\n f.write(\"reg signed [SIZE_1*\"+str(num_conv)+\"-1:0] mem [0:128*128*\"+str(int(4/num_conv))+\"+4096*\"+str(num_conv)+\"-1];\\n\")\n f.write(\"reg signed [32*\"+str(num_conv)+\"-1:0] mem_t [0:4096-1];\\n\")\n f.write(\"reg signed [SIZE_weights*9-1:0] weight [0:4095]; \\n\")\n f.write(\"reg signed [SIZE_bias-1:0] mem_bias [0:256];\\n\")\n f.write(\"always @ (posedge clk) \\n\")\n f.write(\" begin\\n\")\n f.write(\" if (we_p) mem[write_addressp] <= dp;\\n\")\n f.write(\"\t\tif (we_tp) mem_t[write_addresstp] <= dtp;\\n\")\n f.write(\" end\\n\")\n f.write(\"always @ (posedge clk_RAM_w)\\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\tif (we_w) weight[write_addressw] <= dw;\\n\")\n f.write(\"\t\tif (we_bias) mem_bias[write_address_bias] <= d_bias;\\n\")\n f.write(\"\tend\\n\")\n f.write(\"always @ (posedge clk)\\n\")\n f.write(\" begin\\n\")\n f.write(\" if (re_p) qp <= mem[read_addressp];\\n\")\n f.write(\"\t\tif (re_tp)qtp <= mem_t[read_addresstp];\\n\")\n f.write(\" if (re_w) qw <= weight[read_addressw];\\n\")\n f.write(\"\t\tif (re_bias) q_bias <= mem_bias[read_address_bias];\\n\")\n f.write(\" end\\n\")\n f.write(\"\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef RAMtoMEM(directory, max_address_value, steps_count, in_dense_razmer, conv_block_size, num_conv):\n f = open(directory + \"RAMtoMEM.v\", 'w')\n\n bit_max_address_value = len(bin(max_address_value)) - 2\n bit_weight_case = len(bin(conv_block_size*conv_block_size)) - 2\n bit_steps_count = len(bin(steps_count)) - 2\n bit_in_dense_razmer = len(bin(in_dense_razmer)) - 2\n\n f.write(\"module memorywork(clk_RAM_w,data,data_bias,address,we_w,re_weights,re_bias,nextstep,dw,addrw,step_out,GO,in_dense,load_weights,onexone,address_bias,d_bias,load_bias,we_bias,write_address_bias);\\n\")\n f.write(\"\\n\")\n f.write(\"parameter num_conv=0;\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"parameter SIZE_\"+str(i+1)+\"=0;\\n\")\n f.write(\"parameter SIZE_address_pix=0;\\n\")\n f.write(\"parameter SIZE_address_wei=0;\\n\")\n f.write(\"parameter SIZE_weights=0;\\n\")\n f.write(\"parameter SIZE_bias=0;\\n\")\n f.write(\"\\n\")\n f.write(\"input clk_RAM_w;\\n\")\n f.write(\"input signed [SIZE_weights-1:0] data;\\n\")\n f.write(\"input signed [SIZE_bias-1:0] data_bias;\\n\")\n f.write(\"output [23:0] address;\\n\")\n f.write(\"output reg we_w;\\n\")\n f.write(\"output re_weights,re_bias;\\n\")\n f.write(\"input nextstep;\\n\")\n f.write(\"output reg signed [SIZE_weights*9-1:0] dw;\\n\")\n f.write(\"output reg [SIZE_address_wei-1:0] addrw;\\n\")\n f.write(\"output [\"+str(bit_steps_count-1)+\":0] step_out;\\n\")\n f.write(\"input GO;\\n\")\n f.write(\"input [\"+str(bit_in_dense_razmer-1)+\":0] in_dense;\\n\")\n f.write(\"input load_weights,load_bias;\\n\")\n f.write(\"\\n\")\n f.write(\"output reg signed [SIZE_bias-1:0] d_bias;\\n\")\n f.write(\"output reg we_bias;\\n\")\n f.write(\"output reg [10:0] write_address_bias;\\n\")\n f.write(\"output [11:0] address_bias;\\n\")\n f.write(\"\\n\")\n f.write(\"input onexone; \\n\")\n f.write(\"\\n\")\n f.write(\"reg [SIZE_address_pix-1:0] addr;\\n\")\n f.write(\"wire [\"+str(bit_max_address_value-1)+\":0] firstaddr,lastaddr;\\n\")\n f.write(\"\\n\")\n f.write(\"wire [18:0] razn_addr;\\n\")\n f.write(\"assign razn_addr = lastaddr-firstaddr;\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_steps_count-1)+\":0] step;\\n\")\n f.write(\"reg [\"+str(bit_steps_count-1)+\":0] step_n;\\n\")\n f.write(\"reg [\"+str(bit_weight_case-1)+\":0] weight_case;\\n\")\n f.write(\"reg [SIZE_weights*9-1:0] buff;\\n\")\n f.write(\"reg [\"+str(bit_max_address_value-1)+\":0] i;\\n\")\n f.write(\"reg [\"+str(bit_max_address_value-1)+\":0] i_d;\\n\")\n f.write(\"reg [\"+str(bit_max_address_value-1)+\":0] i1;\\n\")\n f.write(\"addressRAM inst_1(.step(step_out),.re_weights(re_weights),.re_bias(re_bias),.firstaddr(firstaddr),.lastaddr(lastaddr)); \\n\")\n f.write(\"initial weight_case=0;\\n\")\n f.write(\"initial i=0;\\n\")\n f.write(\"initial i_d=0;\\n\")\n f.write(\"initial i1=0;\\n\")\n f.write(\"\\n\")\n f.write(\"always @(negedge clk_RAM_w)\\n\")\n f.write(\"\tif ( (step_out==1)||(step_out==2)\\n\")\n f.write(\"\t\t||(step_out==4)||(step_out==5)\\n\")\n f.write(\"\t\t||(step_out==7)||(step_out==8)\\n\")\n f.write(\"\t\t||(step_out==10)||(step_out==11)\\n\")\n f.write(\"\t\t||(step_out==13)||(step_out==14)\\n\")\n f.write(\"\t\t||(step_out==16)||(step_out==17)\\n\")\n f.write(\"\t\t||(step_out==19)||(step_out==20)\\n\")\n f.write(\"\t\t||(step_out==22)||(step_out==23)\\n\")\n f.write(\"\t\t||(step_out==25)||(step_out==26)\\n\")\n f.write(\"\t\t||(step_out==28)||(step_out==29)\\n\")\n f.write(\"\t\t||(step_out==31)||(step_out==32)\\n\")\n f.write(\"\t\t||(step_out==34)||(step_out==35)\\n\")\n f.write(\"\t\t||(step_out==37)||(step_out==38)\\n\")\n f.write(\"\t\t||(step_out==40)||(step_out==41)\\n\")\n f.write(\"\t\t||(step_out==43)||(step_out==44)\\n\")\n f.write(\"\t\t||(step_out==46)||(step_out==47)\\n\")\n f.write(\"\t\t||(step_out==49)||(step_out==50)\\n\")\n f.write(\"\t\t||(step_out==52)||(step_out==53)\\n\")\n f.write(\"\t\t||(step_out==55)||(step_out==56)\\n\")\n f.write(\"\t\t||(step_out==58)||(step_out==59)\\n\")\n f.write(\"\t\t||(step_out==61)||(step_out==62)\\n\")\n f.write(\"\t\t||(step_out==64)||(step_out==65)\\n\")\n f.write(\"\t\t||(step_out==67)||(step_out==68)\\n\")\n f.write(\"\t\t||(step_out==70)||(step_out==71)\\n\")\n f.write(\"\t\t||(step_out==73)||(step_out==74)\\n\")\n f.write(\"\t\t||(step_out==76)||(step_out==77)\\n\")\n f.write(\"\t\t||(step_out==79)||(step_out==80)\\n\")\n f.write(\"\t\t||(step_out==82)||(step_out==83)\\n\")\n f.write(\"\t\t||(step_out==85)\\n\")\n f.write(\"\t\t)\\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\tif ((i<=razn_addr+1)&&(re_weights)) addr=i1;\\n\")\n f.write(\"\t\tif ((i<=razn_addr+1)&&(re_bias))\taddr=i;\\n\")\n f.write(\"\tend\\n\")\n f.write(\"\\n\")\n f.write(\"always @(posedge clk_RAM_w or posedge GO)\\n\")\n f.write(\"\tif (GO) step=1;\\n\")\n f.write(\"\telse\\n\")\n f.write(\" begin\\n\")\n f.write(\"\t\t\tcase (step_out)\\n\")\n f.write(\"\t\t\t\t8'd1,8'd4,8'd7,8'd10,8'd13,8'd16,8'd19,8'd22,8'd25,8'd28,8'd31,8'd34,8'd37,8'd40,8'd43,8'd46,8'd49,8'd52,8'd55,8'd58,8'd61,8'd64,8'd67,8'd70,8'd73,8'd76,8'd79,8'd82,8'd85:\\n\")\n f.write(\"\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\tif (i<=razn_addr+3)\\n\")\n f.write(\" begin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\twe_w=0;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\taddrw=addr;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1) i=i+1; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (step_out==85) if (i_d==((in_dense)+1)) begin dw=buff; we_w=1; weight_case=1; i_d=1; i1=i1+1; end\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tcase (weight_case)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t0: ;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t1: begin buff=0; buff[SIZE_weights*9-1:SIZE_weights*8]=data[SIZE_weights-1:0]; end \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t2: buff[SIZE_weights*8-1:SIZE_weights*7]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t3: buff[SIZE_weights*7-1:SIZE_weights*6]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t4: buff[SIZE_weights*6-1:SIZE_weights*5]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t5: buff[SIZE_weights*5-1:SIZE_weights*4]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t6: buff[SIZE_weights*4-1:SIZE_weights*3]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t7: buff[SIZE_weights*3-1:SIZE_weights*2]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t8: buff[SIZE_weights*2-1:SIZE_weights]=data[SIZE_weights-1:0]; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t9: begin buff[SIZE_weights-1:0]=data[SIZE_weights-1:0]; end\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tdefault: $display(\\\"Check weight_case\\\");\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tendcase\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1) i_d=i_d+1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1)\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\tif ((weight_case==9)||((onexone)&&(weight_case==8))) \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbegin \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tweight_case=1; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tdw=buff; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\twe_w=1; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\ti1=i1+1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tend \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\telse \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\t\tweight_case=weight_case+1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\t\tend\\n\")\n f.write(\" end\\n\")\n f.write(\"\t\t\t\t\tif (i>razn_addr+3)\\n\")\n f.write(\" begin\\n\")\n f.write(\" step=step+1; //next step\\n\")\n f.write(\" i=0;\\n\")\n f.write(\"\t\t\t\t\t\ti_d=0;\\n\")\n f.write(\"\t\t\t\t\t\ti1=0;\\n\")\n f.write(\"\t\t\t\t\t\tweight_case=0;\\n\")\n f.write(\" end\\n\")\n f.write(\" end\\n\")\n f.write(\"\t\t\t8'd2,8'd5,8'd8,8'd11,8'd14,8'd17,8'd20,8'd23,8'd26,8'd29,8'd32,8'd35,8'd38,8'd41,8'd44,8'd47,8'd50,8'd53,8'd56,8'd59,8'd62,8'd65,8'd68,8'd71,8'd74,8'd77,8'd80,8'd83:\\n\")\n f.write(\"\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\tif (i<=razn_addr)\\n\")\n f.write(\"\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\twe_bias=1;\\n\")\n f.write(\"\t\t\t\t\t\t\twrite_address_bias=addr;\\n\")\n f.write(\"\t\t\t\t\t\t\tif (load_bias==1'b1) i=i+1;\\n\")\n f.write(\"\t\t\t\t\t\t\td_bias=data_bias;\\n\")\n f.write(\"\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\telse\t\\n\")\n f.write(\"\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\tstep=step+1;\\n\")\n f.write(\"\t\t\t\t\t\t\ti=0;\\n\")\n f.write(\"\t\t\t\t\t\t\twe_bias=0;\\n\")\n f.write(\"\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\tend\\n\")\n f.write(\"\t\t\tdefault:\\n\")\n f.write(\"\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\twe_w=0;\\n\")\n f.write(\"\t\t\t\t\twe_bias=0;\\n\")\n f.write(\"\t\t\t\t\ti=0;\\n\")\n f.write(\"\t\t\t\t\ti_d=0;\\n\")\n f.write(\"\t\t\t\t\ti1=0;\\n\")\n f.write(\"\t\t\t\tend\\n\")\n f.write(\"\t\tendcase\\n\")\n f.write(\" end\\n\")\n f.write(\"always @(posedge nextstep) if (GO==1) step_n=0; else step_n=step_n+1;\\n\")\n f.write(\"assign step_out=step+step_n;\\n\")\n f.write(\"assign address=(re_weights)?(firstaddr+i):0;\\n\")\n f.write(\"assign address_bias=(re_bias)?(firstaddr+i):0;\\n\")\n f.write(\"endmodule\\n\")\n\n f.close()\n\ndef result(directory,output_neurons_count,num_conv):\n f = open(directory + \"result.v\", 'w')\n\n bit_output_neurons_count = len(bin(output_neurons_count))-2\n bit_marker_chislo = len(bin(output_neurons_count+2)) - 2\n\n f.write(\"module result(clk,enable,STOP,memstartp,read_addressp,qp,re,RESULT);\\n\")\n f.write(\"\\n\")\n for i in range(num_conv):\n f.write(\"parameter SIZE_\"+str(i+1)+\"=0;\\n\")\n f.write(\"parameter SIZE_address_pix=0;\\n\")\n f.write(\"\\n\")\n f.write(\"input clk,enable;\\n\")\n f.write(\"output reg STOP;\\n\")\n f.write(\"input [SIZE_address_pix-1:0] memstartp;\\n\")\n f.write(\"input [SIZE_\"+str(num_conv)+\"-1:0] qp;\\n\")\n f.write(\"output reg re;\\n\")\n f.write(\"output reg [SIZE_address_pix-1:0] read_addressp;\\n\")\n f.write(\"output reg [\"+str(bit_output_neurons_count-1)+\":0] RESULT;\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_marker_chislo-1)+\":0] marker;\\n\")\n f.write(\"wire signed [SIZE_1-1:0] p1,p2;\\n\")\n f.write(\"always @(posedge clk)\\n\")\n f.write(\"begin\\n\")\n f.write(\"if (enable==1)\\n\")\n f.write(\"begin\\n\")\n f.write(\"re=1;\\n\")\n f.write(\"case (marker)\\n\")\n f.write(\"\t0: read_addressp=memstartp;\\n\")\n f.write(\"\t1: ;\\n\")\n f.write(\"\t2: begin\\n\")\n f.write(\"\t\tRESULT=0; \\n\")\n f.write(\"\t\tif (p2>=p1) RESULT=1; \\n\")\n f.write(\"\t\telse RESULT=0; \\n\")\n f.write(\"\t\tSTOP=1; \\n\")\n f.write(\"\t\tend\\n\")\n f.write(\"\tdefault: $display(\\\"Check case result\\\");\\n\")\n f.write(\"endcase\\n\")\n f.write(\"marker=marker+1;\\n\")\n f.write(\"end\\n\")\n f.write(\"else \\n\")\n f.write(\"begin\\n\")\n f.write(\"re=0;\\n\")\n f.write(\"marker=0;\\n\")\n f.write(\"STOP=0;\\n\")\n f.write(\"end\\n\")\n f.write(\"end\\n\")\n f.write(\"\\n\")\n f.write(\"assign p1=qp[SIZE_\" + str(num_conv) + \"-1:SIZE_\" + str(num_conv-1) + \"];\\n\")\n f.write(\"assign p2=qp[SIZE_\" + str(num_conv-1) + \"-1:\")\n if (num_conv-2!=0): f.write(\"SIZE_\" + str(num_conv-2))\n else: f.write(\"0\")\n f.write(\"];\\n\")\n f.write(\"endmodule\\n\")\n\ndef TOP(directory, sizeI, sizeW, sizeB, razmer, max_address_value, output_neurons_count, max_weights_per_layer,\n total_conv_layers_number, max_conv_input_size, in_dense_razmer,\n out_dense_razmer, max_conv_output_size, layers, num_conv, steps_count):\n f = open(directory + \"TOP.v\", 'w')\n\n bit_max_address_value = len(bin(max_address_value)) - 2\n bit_output_neurons_count = len(bin(output_neurons_count)) - 2\n bit_address_pix = len(bin(razmer*razmer*8+razmer*razmer)) - 2\n bit_address_pix_t = len(bin(razmer*razmer*4)) - 2\n bit_max_weights_per_layer = len(bin(max_weights_per_layer)) - 2\n bit_total_conv_layers_number = len(bin(total_conv_layers_number)) - 2\n bit_max_conv_input_size = len(bin(max_conv_input_size)) - 2\n bit_razmer = len(bin(razmer)) - 2\n bit_razmer_2 = len(bin(razmer*razmer)) - 2\n bit_in_dense_razmer = len(bin(in_dense_razmer)) - 2\n bit_out_dense_razmer = len(bin(out_dense_razmer)) - 2\n bit_max_conv_output_size = len(bin(max_conv_output_size)) - 2\n bit_steps_count = len(bin(steps_count)) - 2\n Y=''\n p=''\n w=''\n p_d=''\n w_c=''\n w_d=''\n for i in range(num_conv):\n Y=Y+\"Y\"+str(i+1)+\",\"\n w_c=w_c+\"w\"+str(i+1)+\"1_c,w\"+str(i+1)+\"2_c,w\"+str(i+1)+\"3_c,w\"+str(i+1)+\"4_c,w\"+str(i+1)+\"5_c,w\"+str(i+1)+\"6_c,w\"+str(i+1)+\"7_c,w\"+str(i+1)+\"8_c,w\"+str(i+1)+\"9_c,\"\n w_d=w_d+\"w\"+str(i+1)+\"1_d,w\"+str(i+1)+\"2_d,w\"+str(i+1)+\"3_d,w\"+str(i+1)+\"4_d,w\"+str(i+1)+\"5_d,w\"+str(i+1)+\"6_d,w\"+str(i+1)+\"7_d,w\"+str(i+1)+\"8_d,w\"+str(i+1)+\"9_d,\"\n p_d=p_d+\"p\"+str(i+1)+\"1_d,p\"+str(i+1)+\"2_d,p\"+str(i+1)+\"3_d,p\"+str(i+1)+\"4_d,p\"+str(i+1)+\"5_d,p\"+str(i+1)+\"6_d,p\"+str(i+1)+\"7_d,p\"+str(i+1)+\"8_d,p\"+str(i+1)+\"9_d,\"\n p = p + \"p\" + str(i + 1) + \"1,p\" + str(i + 1) + \"2,p\" + str(i + 1) + \"3,p\" + str(i + 1) + \"4,p\" + str(i + 1) + \"5,p\" + str(i + 1) + \"6,p\" + str(i + 1) + \"7,p\" + str(i + 1) + \"8,p\" + str(i + 1) + \"9,\"\n w = w + \"w\" + str(i + 1) + \"1,w\" + str(i + 1) + \"2,w\" + str(i + 1) + \"3,w\" + str(i + 1) + \"4,w\" + str(i + 1) + \"5,w\" + str(i + 1) + \"6,w\" + str(i + 1) + \"7,w\" + str(i + 1) + \"8,w\" + str(i + 1) + \"9,\"\n\n f.write(\"module TOP(\\n\")\n f.write(\"clk,\\n\")\n f.write(\"clk_RAM_w,\\n\")\n f.write(\"clk_RAM_p,\\n\")\n f.write(\"GO,\\n\")\n f.write(\"RESULT,\\n\")\n f.write(\"STOP,\\n\")\n f.write(\"\\n\")\n f.write(\"re_weights,\\n\")\n f.write(\"load_weights,\\n\")\n f.write(\"dp_weights,\\n\")\n f.write(\"address_weights,\\n\")\n f.write(\"\\n\")\n f.write(\"re_bias,\\n\")\n f.write(\"load_bias,\\n\")\n f.write(\"dp_bias,\\n\")\n f.write(\"address_bias,\\n\")\n f.write(\"\\n\")\n f.write(\"we_image,\\n\")\n f.write(\"dp_image,\\n\")\n f.write(\"address_image,\\n\")\n f.write(\"step\\n\")\n f.write(\");\\n\")\n f.write(\"\\n\")\n f.write(\"parameter num_conv=\"+str(num_conv)+\";\\n\")\n f.write(\"parameter SIZE_weights = \"+str(sizeW+1)+\";\\n\")\n f.write(\"parameter SIZE_bias = \"+str(sizeB+1)+\";\\n\")\n for i in range(num_conv):\n f.write(\"parameter SIZE_\"+ str(i+1) +\"=\" + str((sizeI + 1)*(i+1)) + \";\\n\")\n f.write(\"parameter SIZE_address_pix=\"+str(bit_address_pix)+\";\\n\")\n f.write(\"parameter SIZE_address_pix_t=\"+str(bit_address_pix_t)+\";\\n\")\n f.write(\"parameter SIZE_address_wei=\"+str(bit_max_weights_per_layer)+\";\\n\")\n f.write(\"parameter SIZE_address_image=16;\\n\")\n f.write(\"parameter picture_size = \"+str(razmer)+\";\\n\")\n f.write(\"parameter picture_storage_limit = 0;\\n\")\n f.write(\"parameter razmpar = picture_size >> 1;\\n\")\n f.write(\"parameter razmpar2 = picture_size >> 2;\\n\")\n f.write(\"parameter picture_storage_limit_2 = picture_size*picture_size;\\n\")\n f.write(\"input clk,clk_RAM_w,clk_RAM_p;\\n\")\n f.write(\"input GO;\\n\")\n f.write(\"output [\"+str(bit_output_neurons_count-1)+\":0] RESULT;\\n\")\n f.write(\"input signed [SIZE_weights-1:0] dp_weights;\\n\")\n f.write(\"input signed [SIZE_bias-1:0] dp_bias;\\n\")\n f.write(\"output [23:0] address_weights;\\n\")\n f.write(\"output [11:0] address_bias;\\n\")\n f.write(\"input load_weights,load_bias;\\n\")\n f.write(\"input signed [SIZE_1-1:0] dp_image;\\n\")\n f.write(\"input [SIZE_address_image-1:0] address_image;\\n\")\n f.write(\"input we_image;\\n\")\n f.write(\"output reg STOP;\\n\")\n f.write(\"output re_weights,re_bias;\\n\")\n f.write(\"output [\"+str(bit_steps_count-1)+\":0] step;\\n\")\n f.write(\"\\n\")\n f.write(\"wire [SIZE_address_image-1:0] address_image_1;\\n\")\n f.write(\"\\n\")\n f.write(\"reg conv_en;\\n\")\n f.write(\"wire STOP_conv;\\n\")\n f.write(\"\\n\")\n f.write(\"reg dense_en;\\n\")\n f.write(\"wire STOP_dense;\\n\")\n f.write(\"\\n\")\n f.write(\"reg result_en;\\n\")\n f.write(\"wire STOP_res;\t\\n\")\n f.write(\"wire [\"+str(bit_output_neurons_count-1)+\":0] res_out;\\n\")\n f.write(\"\\n\")\n f.write(\"reg bias,glob_average_en;\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_total_conv_layers_number-1)+\":0] TOPlvl_conv;\\n\")\n f.write(\"wire [\"+str(bit_total_conv_layers_number-1)+\":0] TOPlvl;\\n\")\n f.write(\"reg [8:0] lvl;\\n\")\n f.write(\"reg [8:0] slvl;\\n\")\n f.write(\"reg [2:0] num;\\n\")\n f.write(\"reg [SIZE_address_pix-1:0] memstartp;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] memstartp_lvl;\\n\")\n f.write(\"reg [SIZE_address_wei-1:0] memstartw;\\n\")\n f.write(\"wire [SIZE_address_wei-1:0] memstartw_lvl;\\n\")\n f.write(\"reg [SIZE_address_pix-1:0] memstartzap;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] memstartzap_num;\\n\")\n f.write(\"wire [10:0] \t\t\t\tmemstartb;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] read_addressp;\\n\")\n f.write(\"wire [SIZE_address_image-1:0] read_addressp_init;\\n\")\n f.write(\"wire [SIZE_address_pix_t-1:0] read_addresstp;\\n\")\n f.write(\"wire [SIZE_address_wei-1:0] read_addressw;\\n\")\n f.write(\"wire [10:0]\t\t\t\t\tread_address_bias; \\n\")\n f.write(\"wire [SIZE_address_pix-1:0] read_addressp_conv;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] read_addressp_dense;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] read_addressp_res;\\n\")\n f.write(\"wire [SIZE_address_wei-1:0] read_addressw_conv;\\n\")\n f.write(\"wire [SIZE_address_wei-1:0] read_addressw_dense;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] write_addressp;\\n\")\n f.write(\"wire [SIZE_address_pix_t-1:0] write_addresstp;\\n\")\n f.write(\"wire [SIZE_address_wei-1:0] write_addressw;\\n\")\n f.write(\"wire [10:0]\t\t\t\t\twrite_address_bias; \\n\")\n f.write(\"wire [SIZE_address_pix-1:0] write_addressp_zagr;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] write_addressp_conv;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] write_addressp_dense;\\n\")\n f.write(\"wire we_p,we_tp,we_w;\\n\")\n f.write(\"wire re_p,re_tp,re_w,re_p_init;\\n\")\n f.write(\"wire re_bias_RAM;\\n\")\n f.write(\"wire we_p_zagr;\\n\")\n f.write(\"wire we_conv,re_wb_conv,re_conv;\\n\")\n f.write(\"wire we_dense,re_p_dense,re_w_dense;\\n\")\n f.write(\"wire we_bias;\\n\")\n f.write(\"wire re_p_res;\\n\")\n f.write(\"wire signed [SIZE_\"+str(num_conv)+\"-1:0] qp;\\n\")\n f.write(\"wire signed [32*\"+str(num_conv)+\"-1:0] qtp;\\n\")\n f.write(\"wire signed [SIZE_weights*9-1:0] qw;\\n\")\n f.write(\"wire signed [SIZE_bias-1:0]\tq_bias;\\n\")\n f.write(\"wire signed [SIZE_\"+str(num_conv)+\"-1:0] dp;\\n\")\n f.write(\"wire signed [32*\"+str(num_conv)+\"-1:0] dtp;\\n\")\n f.write(\"wire signed [SIZE_weights*9-1:0] dw;\\n\")\n f.write(\"wire signed [SIZE_\"+str(num_conv)+\"-1:0] dp_conv;\\n\")\n f.write(\"wire signed [SIZE_\"+str(num_conv)+\"-1:0] dp_dense;\\n\")\n f.write(\"wire signed [SIZE_\"+str(num_conv)+\"-1:0] dp_zagr;\\n\")\n f.write(\"wire signed [SIZE_bias-1:0] d_bias;\\n\")\n f.write(\"\\n\")\n f.write(\"wire [1:0] prov;\\n\")\n f.write(\"wire [\"+str(bit_razmer_2-1)+\":0] i_conv;\\n\")\n f.write(\"wire signed [32-1:0] \")\n for i in range(num_conv):\n f.write(\"Y\"+str(i+1))\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"\\n\")\n f.write(\"wire signed [SIZE_weights-1:0] \")\n for i in range(num_conv):\n f.write(\"w\"+str(i+1)+\"1,w\"+str(i+1)+\"2,w\"+str(i+1)+\"3\")\n if (i!=num_conv-1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire signed [SIZE_weights-1:0] \")\n for i in range(num_conv):\n f.write(\"w\"+str(i+1)+\"1_c,w\"+str(i+1)+\"2_c,w\"+str(i+1)+\"3_c\")\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire signed [SIZE_weights-1:0] \")\n for i in range(num_conv):\n f.write(\"w\"+str(i+1)+\"1_d,w\"+str(i+1)+\"2_d,w\"+str(i+1)+\"3_d\")\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire signed [SIZE_1-1:0] \")\n for i in range(num_conv):\n f.write(\"p\"+str(i+1)+\"1,p\"+str(i+1)+\"2,p\"+str(i+1)+\"3\")\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire signed [SIZE_1-1:0] \")\n for i in range(num_conv):\n f.write(\"p\"+str(i+1)+\"1_c,p\"+str(i+1)+\"2_c,p\"+str(i+1)+\"3_c\")\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire signed [SIZE_1-1:0] \")\n for i in range(num_conv):\n f.write(\"p\"+str(i+1)+\"1_d,p\"+str(i+1)+\"2_d,p\"+str(i+1)+\"3_d\")\n if (i != num_conv - 1): f.write(\",\")\n f.write(\";\\n\")\n f.write(\"wire go_conv;\\n\")\n f.write(\"wire go_conv_TOP;\\n\")\n f.write(\"wire go_dense;\\n\")\n f.write(\"\\n\")\n f.write(\"reg nextstep;\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_razmer-1)+\":0] matrix;\\n\")\n f.write(\"wire [\"+str(bit_razmer_2-1)+\":0] matrix2; //razmer*razmer\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_max_conv_output_size-1)+\":0] mem;\\n\")\n f.write(\"reg [\"+str(bit_max_conv_input_size-1)+\":0] filt;\\n\")\n f.write(\"reg [1:0] stride;\\n\")\n f.write(\"reg depthwise;\\n\")\n f.write(\"reg onexone;\\n\")\n f.write(\"\\n\")\n f.write(\"reg [\"+str(bit_in_dense_razmer-1)+\":0] in_dense;\\n\")\n f.write(\"reg [\"+str(bit_out_dense_razmer-1)+\":0] out_dense;\\n\")\n f.write(\"reg nozero_dense;\\n\")\n f.write(\"\\n\")\n f.write(\"wire clk_RAM;\\n\")\n f.write(\"\\n\")\n f.write(\"wire up_perm,down_perm;\\n\")\n f.write(\"wire [SIZE_address_pix-1:0] stride_plus_prov;\\n\")\n f.write(\"\\n\")\n f.write(\"conv_TOP #(\\n\")\n for i in range(num_conv):\n f.write(\"\tSIZE_\"+ str(i+1) +\",\\n\")\n f.write(\"\tSIZE_address_pix,\\n\")\n f.write(\"\tSIZE_address_pix_t,\\n\")\n f.write(\"\tSIZE_address_wei,\\n\")\n f.write(\"\tSIZE_weights,\\n\")\n f.write(\"\tSIZE_bias\\n\")\n f.write(\") conv_TOP (\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t\t(clk),\\n\")\n f.write(\"\t.conv_en\t\t\t\t\t\t(conv_en),\\n\")\n f.write(\"\t.STOP\t\t\t\t\t\t\t(STOP_conv),\\n\")\n f.write(\"\t.memstartp\t\t\t\t\t(memstartp_lvl),\\n\")\n f.write(\"\t.memstartw\t\t\t\t\t(memstartw_lvl),\\n\")\n f.write(\"\t.memstartb\t\t\t\t\t(memstartb),\\n\")\n f.write(\"\t.memstartzap\t\t\t\t(memstartzap_num),\\n\")\n f.write(\"\t.read_addressp\t\t\t\t(read_addressp_conv),\\n\")\n f.write(\"\t.write_addressp\t\t\t (write_addressp_conv),\\n\")\n f.write(\"\t.read_addresstp\t\t\t (read_addresstp),\\n\")\n f.write(\"\t.write_addresstp\t\t\t(write_addresstp),\\n\")\n f.write(\"\t.read_addressb\t\t\t\t(read_address_bias),\\n\")\n f.write(\" .read_addressw\t\t\t\t(read_addressw_conv),\\n\")\n f.write(\"\t.we\t\t\t\t\t\t\t(we_conv),\\n\")\n f.write(\"\t.re_wb\t\t\t\t\t\t(re_wb_conv),\\n\")\n f.write(\"\t.re\t\t\t\t\t\t\t(re_conv),\\n\")\n f.write(\"\t.we_t\t\t\t\t\t\t(we_tp),\\n\")\n f.write(\"\t.re_t\t\t\t\t\t\t(re_tp),\\n\")\n f.write(\"\t.qp\t\t\t\t\t\t\t(qp),\\n\")\n f.write(\"\t.qtp\t\t\t\t\t\t(qtp),\\n\")\n f.write(\"\t.qw\t\t\t\t\t\t\t(qw),\\n\")\n f.write(\"\t.q_bias\t\t\t\t\t\t(q_bias),\\n\")\n f.write(\"\t.dp\t\t\t\t\t\t\t(dp_conv),\\n\")\n f.write(\"\t.dtp\t\t\t\t\t\t(dtp),\\n\")\n f.write(\"\t.prov\t\t\t\t\t\t(prov),\\n\")\n f.write(\"\t.matrix\t\t\t\t\t\t(matrix),\\n\")\n f.write(\"\t.matrix2\t\t\t\t\t(matrix2),\\n\")\n f.write(\"\t.i_to_prov\t\t\t\t\t(i_conv),\\n\")\n f.write(\"\t.lvl\t\t\t\t\t\t(lvl),\\n\")\n f.write(\"\t.slvl\t\t\t\t\t\t(slvl),\\n\")\n for i in range(num_conv):\n f.write(\"\t.Y\"+str(i+1)+\"\t\t\t\t\t\t\t(Y\"+str(i+1)+\"),\\n\")\n for i in range(num_conv):\n for j in range(3):\n f.write(\"\t.w\"+str(i+1)+str(j+1)+\"\t\t\t\t\t\t\t(w\"+str(i+1)+str(j+1)+\"_c),\\n\")\n for i in range(num_conv):\n for j in range(3):\n f.write(\"\t.p\"+str(i)+\"_\"+str(j+1)+\"\t\t\t\t\t\t\t(p\"+str(i+1)+str(j+1)+\"_c),\\n\")\n f.write(\"\t.go\t\t\t\t\t\t\t(go_conv_TOP),\\n\")\n f.write(\"\t.up_perm\t\t\t\t\t(up_perm),\\n\")\n f.write(\"\t.down_perm\t\t\t\t\t(down_perm),\\n\")\n f.write(\"\t.stride_plus_prov\t\t\t(stride_plus_prov),\\n\")\n f.write(\"\t.num\t\t\t\t\t\t(num),\\n\")\n f.write(\"\t.filt\t\t\t\t\t\t(filt),\\n\")\n f.write(\"\t.mem\t\t\t\t\t\t(mem),\\n\")\n f.write(\"\t.bias\t\t\t\t\t\t(bias),\\n\")\n f.write(\"\t.glob_average_en\t\t\t(glob_average_en),\\n\")\n f.write(\"\t.step\t\t\t\t\t\t(step),\\n\")\n f.write(\"\t.stride\t\t\t\t\t\t(stride),\\n\")\n f.write(\"\t.depthwise\t\t\t\t\t(depthwise),\\n\")\n f.write(\"\t.onexone\t\t\t\t\t(onexone)\\n\")\n f.write(\");\\n\")\n f.write(\"memorywork #(\\n\")\n f.write(\"\tnum_conv,\\n\")\n for i in range(num_conv):\n f.write(\"\tSIZE_\"+ str(i+1) +\",\\n\")\n f.write(\"\tSIZE_address_pix,\\n\")\n f.write(\"\tSIZE_address_wei,\\n\")\n f.write(\"\tSIZE_weights,\\n\")\n f.write(\"\tSIZE_bias\\n\")\n f.write(\") block (\\n\")\n f.write(\"\t.clk_RAM_w\t\t\t\t\t(clk_RAM_w),\\n\")\n f.write(\"\t.we_w\t\t\t\t\t\t(we_w),\\n\")\n f.write(\"\t.re_weights\t\t\t\t\t(re_weights),\\n\")\n f.write(\"\t.re_bias\t\t\t\t\t(re_bias),\\n\")\n f.write(\"\t.load_weights\t\t\t\t(load_weights),\\n\")\n f.write(\"\t.addrw\t\t\t\t\t\t(write_addressw),\\n\")\n f.write(\"\t.dw\t\t\t\t\t\t\t(dw),\\n\")\n f.write(\"\t.step_out\t\t\t\t\t(step),\\n\")\n f.write(\"\t.nextstep\t\t\t\t\t(nextstep),\\n\")\n f.write(\"\t.data\t\t\t\t\t\t(dp_weights),\\n\")\n f.write(\"\t.address\t\t\t\t\t(address_weights),\\n\")\n f.write(\"\t.GO\t\t\t\t\t\t\t(GO),\\n\")\n f.write(\"\t.in_dense\t\t\t\t\t(in_dense),\\n\")\n f.write(\"\t.onexone\t\t\t\t\t(onexone),\\n\")\n f.write(\"\t.data_bias\t\t\t\t\t(dp_bias),\\n\")\n f.write(\"\t.load_bias\t\t\t\t\t(load_bias),\\n\")\n f.write(\"\t.address_bias\t\t\t\t(address_bias),\\n\")\n f.write(\"\t.write_address_bias\t\t (write_address_bias),\\n\")\n f.write(\"\t.we_bias\t\t\t\t\t(we_bias),\\n\")\n f.write(\"\t.d_bias\t\t\t\t\t\t(d_bias)\\n\")\n f.write(\");\\n\")\n f.write(\"RAM #(\\n\")\n f.write(\"\tpicture_size,\\n\")\n for i in range(num_conv):\n f.write(\"\tSIZE_\"+ str(i+1) +\",\\n\")\n f.write(\"\tSIZE_address_pix,\\n\")\n f.write(\"\tSIZE_address_pix_t,\\n\")\n f.write(\"\tSIZE_address_wei,\\n\")\n f.write(\"\tSIZE_address_image,\\n\")\n f.write(\"\tSIZE_weights,\\n\")\n f.write(\"\tSIZE_bias\\n\")\n f.write(\") memory (\\n\")\n f.write(\"\t.qp\t\t\t\t\t\t\t(qp),\\n\")\n f.write(\"\t.qtp\t\t\t\t\t\t(qtp),\\n\")\n f.write(\"\t.qw\t\t\t\t\t\t\t(qw),\\n\")\n f.write(\"\t.dp\t\t\t\t\t\t\t(dp),\\n\")\n f.write(\"\t.dtp\t\t\t\t\t\t(dtp),\\n\")\n f.write(\"\t.dw\t\t\t\t\t\t\t(dw),\\n\")\n f.write(\"\t.write_addressp\t\t\t (write_addressp),\\n\")\n f.write(\"\t.read_addressp\t\t\t\t(read_addressp),\\n\")\n f.write(\"\t.write_addresstp\t\t\t(write_addresstp),\\n\")\n f.write(\"\t.read_addresstp\t\t\t (read_addresstp),\\n\")\n f.write(\"\t.write_addressw\t\t\t (write_addressw),\\n\")\n f.write(\"\t.read_addressw\t\t\t\t(read_addressw),\\n\")\n f.write(\"\t.we_p\t\t\t\t\t\t(we_p),\\n\")\n f.write(\"\t.we_tp\t\t\t\t\t\t(we_tp),\\n\")\n f.write(\"\t.we_w\t\t\t\t\t\t(we_w),\\n\")\n f.write(\"\t.re_p\t\t\t\t\t\t(re_p),\\n\")\n f.write(\"\t.re_tp\t\t\t\t\t\t(re_tp),\\n\")\n f.write(\"\t.re_w\t\t\t\t\t\t(re_w),\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t(clk_RAM),\\n\")\n f.write(\"\t.clk_RAM_w\t\t\t\t\t(clk_RAM_w),\\n\")\n f.write(\"\t.q_bias\t\t\t\t\t\t(q_bias),\\n\")\n f.write(\"\t.d_bias\t\t\t\t\t\t(d_bias),\\n\")\n f.write(\"\t.we_bias\t\t\t\t\t(we_bias),\\n\")\n f.write(\"\t.re_bias\t\t\t\t\t(re_bias_RAM),\\n\")\n f.write(\"\t.write_address_bias\t\t (write_address_bias),\\n\")\n f.write(\"\t.read_address_bias\t\t (read_address_bias)\\n\")\n f.write(\");\\n\")\n f.write(\"border border(\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t(clk),\\n\")\n f.write(\"\t.go\t\t\t\t\t\t\t(conv_en && (!onexone)),\\n\")\n f.write(\"\t.i\t\t\t\t\t\t\t(i_conv),\\n\")\n f.write(\"\t.matrix\t\t\t\t\t\t(matrix),\\n\")\n f.write(\"\t.prov\t\t\t\t\t\t(prov)\\n\")\n f.write(\");\\n\")\n f.write(\"dense #(\\n\")\n f.write(\"\tnum_conv,\\n\")\n for i in range(num_conv):\n f.write(\"\tSIZE_\"+ str(i+1) +\",\\n\")\n f.write(\"\tSIZE_address_pix,\\n\")\n f.write(\"\tSIZE_address_wei,\\n\")\n f.write(\"\tSIZE_weights\\n\")\n f.write(\") dense (\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t(clk),\\n\")\n f.write(\"\t.dense_en\t\t\t\t\t(dense_en),\\n\")\n f.write(\"\t.STOP\t\t\t\t\t\t(STOP_dense),\\n\")\n f.write(\"\t.in\t\t\t\t\t\t\t(in_dense),\\n\")\n f.write(\"\t.out\t\t\t\t\t\t(out_dense),\\n\")\n f.write(\"\t.we\t\t\t\t\t\t\t(we_dense),\\n\")\n f.write(\"\t.re_p\t\t\t\t\t\t(re_p_dense),\\n\")\n f.write(\"\t.re_w\t\t\t\t\t\t(re_w_dense),\\n\")\n f.write(\"\t.read_addressp\t\t\t\t(read_addressp_dense),\\n\")\n f.write(\"\t.read_addressw\t\t\t\t(read_addressw_dense),\\n\")\n f.write(\"\t.write_addressp\t\t\t (write_addressp_dense),\\n\")\n f.write(\"\t.memstartp\t\t\t\t\t(memstartp_lvl),\\n\")\n f.write(\"\t.memstartzap\t\t\t\t(memstartzap_num),\\n\")\n f.write(\"\t.qp\t\t\t\t\t\t\t(qp),\\n\")\n f.write(\"\t.qw\t\t\t\t\t\t\t(qw),\\n\")\n f.write(\"\t.res\t\t\t\t\t\t(dp_dense),\\n\")\n for i in range(num_conv):\n f.write(\"\t.Y\"+str(i+1)+\"\t\t\t\t\t\t\t(Y\"+str(i+1)+\"),\\n\")\n for i in range(num_conv):\n f.write(\"\t.w\"+str(i+1)+\"1\t\t\t\t\t\t(w\"+str(i+1)+\"1_d),\\n\")\n f.write(\"\t.w\"+str(i+1)+\"2\t\t\t\t\t\t(w\"+str(i+1)+\"2_d),\\n\")\n f.write(\"\t.w\"+str(i+1)+\"3\t\t\t\t\t\t(w\"+str(i+1)+\"3_d),\\n\")\n for i in range(num_conv):\n f.write(\"\t.p\" + str(i + 1) + \"1\t\t\t\t\t\t(p\" + str(i + 1) + \"1_d),\\n\")\n f.write(\"\t.p\" + str(i + 1) + \"2\t\t\t\t\t\t(p\" + str(i + 1) + \"2_d),\\n\")\n f.write(\"\t.p\" + str(i + 1) + \"3\t\t\t\t\t\t(p\" + str(i + 1) + \"3_d),\\n\")\n f.write(\"\t.go\t\t\t\t\t\t\t(go_dense),\\n\")\n f.write(\"\t.nozero\t\t\t\t\t\t(nozero_dense)\\n\")\n f.write(\");\\n\")\n f.write(\"result #(\\n\")\n for i in range(num_conv):\n f.write(\"\tSIZE_\"+ str(i+1) +\",\\n\")\n f.write(\"\tSIZE_address_pix\\n\")\n f.write(\") result (\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t(clk),\\n\")\n f.write(\"\t.enable\t\t\t\t\t\t(result_en),\\n\")\n f.write(\"\t.STOP\t\t\t\t\t\t(STOP_res),\\n\")\n f.write(\"\t.memstartp\t\t\t\t\t(memstartp_lvl),\\n\")\n f.write(\"\t.read_addressp\t\t\t\t(read_addressp_res),\\n\")\n f.write(\"\t.qp\t\t\t\t\t\t\t(qp),\\n\")\n f.write(\"\t.re\t\t\t\t\t\t\t(re_p_res),\\n\")\n f.write(\"\t.RESULT\t\t\t\t\t\t(res_out)\\n\")\n f.write(\");\\n\")\n for i in range(num_conv):\n f.write(\"conv #(\\n\")\n f.write(\"\tSIZE_1,\\n\")\n f.write(\"\tSIZE_address_pix,\\n\")\n f.write(\"\tSIZE_weights\\n\")\n f.write(\") conv\"+str(i+1)+\" (\\n\")\n f.write(\"\t.clk\t\t\t\t\t\t(clk),\\n\")\n f.write(\"\t.Y1\t\t\t\t\t\t\t(Y\"+str(i+1)+\"),\\n\")\n f.write(\"\t.prov\t\t\t\t\t\t(prov),\\n\")\n f.write(\"\t.matrix\t\t\t\t\t\t(matrix),\\n\")\n f.write(\"\t.matrix2\t\t\t\t\t(matrix2),\\n\")\n f.write(\"\t.i\t\t\t\t\t\t\t(i_conv),\\n\")\n f.write(\"\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\\n\")\n f.write(\"\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\\n\")\n f.write(\"\t.p1\t\t\t\t\t\t\t(p\"+str(i+1)+\"1),\\n\")\n f.write(\"\t.p2\t\t\t\t\t\t\t(p\"+str(i+1)+\"2),\\n\")\n f.write(\"\t.p3\t\t\t\t\t\t\t(p\"+str(i+1)+\"3),\\n\")\n f.write(\"\t.w1\t\t\t\t\t\t\t(w\"+str(i+1)+\"1),\\n\")\n f.write(\"\t.w2\t\t\t\t\t\t\t(w\"+str(i+1)+\"2),\\n\")\n f.write(\"\t.w3\t\t\t\t\t\t\t(w\"+str(i+1)+\"3),\\n\")\n f.write(\"\t.conv_en\t\t\t\t\t(go_conv),\\n\")\n f.write(\"\t.dense_en\t\t\t\t\t((onexone||dense_en)),\\n\")\n f.write(\"\t.stride_plus_prov\t\t\t(stride_plus_prov)\\n\")\n f.write(\");\\n\")\n f.write(\"always @(posedge clk )\\n\")\n f.write(\"begin\\n\")\n f.write(\"if (GO==1)\\n\")\n f.write(\"begin\\n\")\n f.write(\"STOP=0;\\n\")\n f.write(\"nextstep=1;\\n\")\n f.write(\"glob_average_en=0;\\n\")\n f.write(\"result_en=0;\\n\")\n f.write(\"end\\n\")\n f.write(\"else nextstep=0;\\n\")\n f.write(\"if (STOP==0)\\n\")\n f.write(\"begin\\n\")\n\n TOPlvl = 1\n step = 0\n start = 1\n start_me = 0\n onexone = 0\n ZeroPadding2D = 0\n GlobalAveragePooling2D = 0\n one = \"picture_storage_limit\"\n two = \"picture_storage_limit_2\"\n for i in range(len(layers)):\n layer = str(layers[i].__class__.__name__)\n #print(layer,layers[i].input_shape,layers[i].output_shape)\n if 'Conv2D' in layer:\n if (str(layers[i+2].__class__.__name__) == 'GlobalAveragePooling2D'): GlobalAveragePooling2D=1\n else: GlobalAveragePooling2D=0\n for j in range(1+GlobalAveragePooling2D):\n mem = int(layers[i].output_shape[3]/(1+GlobalAveragePooling2D)-1)\n filt = layers[i].input_shape[3]-1\n\n if (start == 0):\n f.write(\"\t if ((TOPlvl==\"+str(TOPlvl)+\")&&(step==\"+str(step)+\")) \\n\")\n f.write(\" begin\\n\")\n f.write(\" nextstep = 1;\\n\")\n f.write(\" onexone = \" + str(onexone) + \";\\n\")\n f.write(\" end\\n\")\n else: start = 0\n\n step += 3\n\n f.write(\"\t if ((TOPlvl==\"+str(TOPlvl)+\")&&(step==\"+str(step)+\"))\\n\")\n f.write(\"\t\t begin\\n\")\n if (ZeroPadding2D): f.write(\"\t\t\t matrix = \"+str(layers[i].input_shape[1] - 1)+\";\\n\")\n else: f.write(\"\t\t\t matrix = \"+str(layers[i].input_shape[1])+\";\\n\")\n f.write(\"\t\t\t memstartp = \"+str(one)+\";\\n\")\n f.write(\"\t\t\t memstartw = 0;\\n\")\n if (GlobalAveragePooling2D): f.write(\"\t\t\t memstartzap = \"+str(two)+ \"+\" + str(j*int(128/num_conv)) + \";\\n\")\n else: f.write(\"\t\t\t memstartzap = \"+str(two)+\";\\n\")\n f.write(\"\t\t\t conv_en = 1;\\n\")\n f.write(\"\t\t\t dense_en=0;\\n\")\n if (start_me == 0):\n f.write(\"\t\t\t mem = \"+str(mem)+\";\\n\")\n f.write(\"\t\t\t filt = \"+str(filt)+\";\\n\")\n else:\n f.write(\"\t\t\t mem = \"+str(filt)+\";\\n\")\n f.write(\"\t\t\t filt = \"+str(mem)+\";\\n\")\n f.write(\"\t\t\t stride=\" + str(layers[i].strides[0]) + \";\\n\")\n f.write(\"\t\t\t onexone=\" + str(onexone) + \";\\n\")\n if (layer == 'DepthwiseConv2D'):\n f.write(\"\t\t\t depthwise=1;\\n\")\n if (GlobalAveragePooling2D == 0): onexone = 1\n else:\n f.write(\"\t\t\t depthwise=0;\\n\")\n if (GlobalAveragePooling2D == 0): onexone = 0\n if (GlobalAveragePooling2D): f.write(\"\t\t\t glob_average_en=1;\\n\")\n else: f.write(\"\t\t\t glob_average_en=0;\\n\")\n f.write(\" end\\n\")\n\n if (j == GlobalAveragePooling2D):\n one_t=one\n two_t=two\n two=one_t\n one=two_t\n TOPlvl += 1\n start_me = 1\n ZeroPadding2D=0\n\n if 'ZeroPadding2D' in layer: ZeroPadding2D = 1\n if 'Dense' in layer:\n\n f.write(\"\t if ((TOPlvl==\" + str(TOPlvl) + \")&&(step==\" + str(step) + \")) \\n\")\n f.write(\" begin\\n\")\n f.write(\"\t\t\t nextstep=1;\\n\")\n f.write(\"\t\t\t onexone=0;\\n\")\n f.write(\"\t\t\t in_dense=\"+str(layers[i].input_shape[1])+\";\\n\")\n f.write(\"\t\t\t out_dense=\"+str(layers[i].output_shape[1])+\";\\n\")\n f.write(\"\t\t\tend\\n\")\n\n step += 2\n\n f.write(\"\t if ((TOPlvl==\"+str(TOPlvl)+\")&&(step==\"+str(step)+\"))\\n\")\n f.write(\" begin\\n\")\n f.write(\"\t\t\t memstartp= \" + str(one) + \";\\n\")\n f.write(\"\t\t\t memstartzap = \" + str(two) + \";\\n\")\n f.write(\"\t\t\t conv_en=0;\\n\")\n f.write(\"\t\t\t dense_en=1;\\n\")\n f.write(\"\t\t\t nozero_dense=1;\\n\")\n f.write(\"\t\t\t depthwise=0;\\n\")\n f.write(\"\t\t\tend\\n\")\n\n one_t=one\n two_t=two\n two=one_t\n one=two_t\n TOPlvl += 1\n if (i == len(layers)-1):\n step += 1\n f.write(\"\t if ((TOPlvl==\"+str(TOPlvl-1)+\")&&(STOP_dense==0)&&(step==\"+str(step)+\"))\\n\")\n f.write(\"\t\t begin\\n\")\n f.write(\"\t\t\t memstartp = \"+str(one)+\";\\n\")\n f.write(\"\t\t \tresult_en = 1;\\n\")\n f.write(\"\t\t end\\n\")\n\n f.write(\"\tif ((depthwise)||(lvl==filt)||((onexone)&&(mem==((lvl+1)*8)-1))) bias=1; else bias=0;\\n\")\n f.write(\"\tif ((STOP_conv)&&(conv_en==1)) conv_en=0;\\n\")\n f.write(\"\tif (STOP_dense==1) begin dense_en=0; nextstep=1; end\\n\")\n f.write(\"\tif ((STOP_res==1)&&(result_en==1))\\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\tresult_en=0;\\n\")\n f.write(\"\t\tSTOP=1;\\n\")\n f.write(\"\tend\\n\")\n f.write(\"end\\n\")\n f.write(\"end\\n\")\n f.write(\"\\n\")\n f.write(\"always @(negedge STOP_conv or posedge GO)\\n\")\n f.write(\"\tbegin\\n\")\n f.write(\"\t\tif (GO)\\n\")\n f.write(\"\t\t\tbegin\\n\")\n f.write(\"\t\t\t\tlvl=0;\\n\")\n f.write(\"\t\t\t\tslvl=0;\\n\")\n f.write(\"\t\t\t\tTOPlvl_conv=1;\\n\")\n f.write(\"\t\t\t\tnum=0;\\n\")\n f.write(\"\t\t\tend\\n\")\n f.write(\"\t\telse\\n\")\n f.write(\"\t\t\tbegin\\n\")\n f.write(\"\t\t\t\tif (lvl==(filt)||((lvl==filt>>\"+ str(len(bin(num_conv))-3) +\")&&(depthwise))||((lvl==((mem+1)>>3)-1)&&(onexone)))\\n\")\n f.write(\"\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\tlvl=0;\\n\")\n f.write(\"\t\t\t\t\t\tif ((num!=\")\n if (num_conv<=4): f.write(\"4-num_conv\")\n else: f.write(\"0\")\n f.write(\")&&(!depthwise)) num=num+1; else num=0;\\n\")\n f.write(\"\t\t\t\t\t\tif ((num==0)||(depthwise))\\n\")\n f.write(\"\t\t\t\t\t\tbegin \\n\")\n f.write(\"\t\t\t\t\t\t\tif ((depthwise)||((!onexone)&&(mem==(\"+str(num_conv)+\"+(slvl*\"+str(num_conv)+\"))-1))||((onexone)&&(filt==(\"+str(num_conv)+\"+(slvl*\"+str(num_conv)+\"))-1))) \\n\")\n f.write(\"\t\t\t\t\t\t\t\tbegin\\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tslvl=0; \\n\")\n f.write(\"\t\t\t\t\t\t\t\t\tTOPlvl_conv=TOPlvl_conv+1'b1;\\n\")\n f.write(\"\t\t\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\t\t\telse slvl = slvl + 1'b1;\\n\")\n f.write(\"\t\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\t\tend\\n\")\n f.write(\"\t\t\t\telse\\n\")\n f.write(\"\t\t\t\tlvl=lvl+1;\\n\")\n f.write(\"\t\t\tend\\n\")\n f.write(\"\tend\\n\")\n f.write(\"\\n\")\n f.write(\"assign address_image_1 = address_image[\")\n if (num_conv<3): f.write(str(bit_razmer_2-len(bin(num_conv))+3))\n else: f.write(str(13))\n f.write(\":0]+1;\t\\n\")\n f.write(\"\\n\")\n f.write(\"assign memstartw_lvl=memstartw+((onexone?num*(((mem+1)>>3)-1)+lvl:(depthwise?lvl*num_conv:lvl))+(((!depthwise)&&(!onexone))?(slvl*(4*(filt+1))):(1'b0))+((!onexone)?(num*(filt+1)):num+slvl*((mem+1)\")\n if (num_conv<=4): f.write(\">>\"+str(len(bin(8-num_conv))-3))\n else: f.write(\"<<\"+str(len(bin(num_conv-8))-3))\n f.write(\")));\\n\")\n f.write(\"assign memstartzap_num = memstartzap+((glob_average_en)?(num+slvl*1):0)+(((conv_en==1)&&(!glob_average_en))?(num*((matrix>>(stride-1))*(matrix>>(stride-1)))+slvl*((matrix>>(stride-1))*(matrix>>(stride-1)))\")\n if (num_conv<=4): f.write(\"*(5-num_conv)\")\n f.write(\"+((depthwise)?lvl*((matrix>>(stride-1))*(matrix>>(stride-1))):0)):0);\\n\")\n f.write(\"assign memstartp_lvl=memstartp+(onexone?((lvl\")\n if (num_conv>4): f.write(\"[8:\"+str(len(bin(num_conv))-6)+\"]\")\n f.write(\")*matrix2\")\n if (num_conv<=4): f.write(\"*(8>>2)\")\n f.write(\"):(depthwise?(lvl*matrix2):((lvl>>num_conv-1)*matrix2))); \\n\")\n f.write(\"assign memstartb=slvl*\"+str(num_conv)+\"+num+(depthwise?lvl*num_conv:0)+1;\\n\")\n f.write(\"\\n\")\n f.write(\"assign re_p=GO?1'b1:((conv_en==1)?re_conv:((dense_en==1)?re_p_dense:((result_en==1)?re_p_res:0)));\\n\")\n f.write(\"assign re_w=(conv_en==1)?re_wb_conv:((dense_en==1)?re_w_dense:0);\\n\")\n f.write(\"assign re_bias_RAM=(conv_en==1)?re_wb_conv:0;\\n\")\n f.write(\"assign read_addressp=GO?address_image_1[\")\n if (num_conv < 3):\n f.write(str(bit_razmer_2 - len(bin(num_conv)) + 3))\n else:\n f.write(str(13))\n f.write(\":0]:((conv_en==1)?read_addressp_conv:((dense_en==1)?read_addressp_dense:((result_en==1)?read_addressp_res:0)));\\n\")\n f.write(\"assign we_p=GO?we_image:((conv_en==1)?we_conv:((dense_en==1)?we_dense:0));\\n\")\n f.write(\"assign dp=GO?\")\n n = 0\n for i in range(3): #ИСПРАВИТЬ НА ЗАВИСИМОСТЬ (картинка 3-х цветная)\n f.write(\"((address_image<128*128*\" + str(i+1) + \")?\")\n f.write(\"{\")\n for j in range(num_conv):\n if (j==n): f.write(\"dp_image\")\n elif ((j>i)|(j==num_conv-1)): f.write(str(sizeI+1)+\"'d0\")\n else: f.write(\"qp[SIZE_\"+str(num_conv-j)+\"-1:SIZE_\"+str(num_conv-j-1)+\"]\")\n if (j+1!=num_conv): f.write(\",\")\n if (n max_weights_per_layer:\n max_weights_per_layer = max_weights_per_layer_1\n elif 'Dense' in str(layer.__class__.__name__):\n w = layer.get_weights()\n total_dense_layers_number += 1\n dense_inputs.append(layer.input_shape[1])\n dense_outputs.append(layer.output_shape[1])\n max_address_value += len(layer.get_weights()[0][0]) * len(w[0])\n max_weights_per_layer_1 = int(len(w[0][0]) * len(w[0])/(conv_block_size_1*conv_block_size_2)) + 1\n if max_weights_per_layer_1 > max_weights_per_layer:\n max_weights_per_layer = max_weights_per_layer_1\n if i == len(model.layers) - 1:\n # Number of neurons on final classification layer.\n output_neurons_count = layer.output_shape[1]\n\n if 'ZeroPadding2D' in str(layer.__class__.__name__):\n ZeroPadding2D = 1\n\n # Maximum size of image for neural net. Equal to 128.\n max_input_image_size = max(conv_inputs)\n # Number of steps in neural net. Step means any action like loading data, processing convolution layer.\n steps_count = 2 + (total_conv_layers_number*3) + (total_dense_layers_number*2) + 1\n # Bit size of input data for dense layer\n in_dense_size = max(dense_inputs)\n # Bit size of output data for dense layer\n out_dense_size = max(dense_outputs)\n # Size of convolution block.\n conv_block_size = max(conv_blocks)\n # Maximum number of input feature maps for all convolution layers\n max_conv_input_size = max(conv_filt)\n # Maximum number of output feature maps for all convolution layers\n max_conv_output_size = max(conv_mem)\n max_address_value += input\n\n print(\"Make addressRAM file\")\n addressRAM(output_directory, steps_count, max_address_value)\n\n print(\"Make border file\")\n border(output_directory, max_input_image_size)\n\n print(\"Make conv_block file\")\n conv_block(output_directory,max_input_image_size)\n\n print(\"Make conv_TOP file\")\n conv_TOP(output_directory, max_input_image_size, max_conv_input_size, max_conv_output_size, num_conv, steps_count,image_bit_precision,weight_bit_precision+convW)\n\n print(\"Make dense file\")\n dense(output_directory, in_dense_size, out_dense_size, num_conv, image_bit_precision, weight_bit_precision+convW)\n\n print(\"Make RAM file\")\n RAM(output_directory, max_weights_per_layer, num_conv)\n\n print(\"Make RAMtoMEM file\")\n RAMtoMEM(output_directory, max_address_value, steps_count, in_dense_size, conv_block_size, num_conv)\n\n print(\"Make result file\")\n result(output_directory, output_neurons_count, num_conv)\n\n TOP(output_directory, image_bit_precision, weight_bit_precision+convW, bias_bit_precision+convB, max_input_image_size, max_address_value, output_neurons_count,\n max_weights_per_layer, total_conv_layers_number, max_conv_input_size,\n in_dense_size, out_dense_size, max_conv_output_size, model.layers, num_conv, steps_count)\n\n\n" }, { "path": "r08_generate_weights_file_for_FPGA.py", "content": "# coding: utf-8\n__author__ = 'Alex Kustov, IPPM RAS'\n\ndef load_cache_file(f):\n file = open(f,'r')\n result_list = []\n for i in file:\n if ((i[:2] != '//') & (i != '\\n')):\n result_list.append(i)\n file.close()\n return result_list\n\nif __name__ == '__main__':\n nn_type = 'people'\n\n f_w = 'cache/{}/storage.v'.format(nn_type)\n f_b = 'cache/{}/storage_bias.v'.format(nn_type)\n f_r = 'cache/{}/weights.txt'.format(nn_type)\n\n weights = load_cache_file(f_w)\n bias = load_cache_file(f_b)\n\n file = open(f_r,'w')\n for i in range(len(weights)):\n for j in range(len(weights[i])):\n file.write(weights[i][j])\n for i in range(3):\n file.write('storage[0] = 12\\'b000000000000; // 0 0\\n')\n for i in range(len(bias)):\n for j in range(len(bias[i])):\n file.write(bias[i][j])\n file.close()" }, { "path": "utils/data_uart_to_fpga.py", "content": "import serial\nfrom tqdm import tqdm\n\nWEIGHT_FILE_TO_USE = 'weights/weights_cars.txt'\n\n\nif __name__ == '__main__':\n ser = serial.Serial(port='COM4', baudrate=115200, bytesize=8, timeout=0)\n ser.write(bytes([255]))\n\n file = open(WEIGHT_FILE_TO_USE, 'r')\n k = 0\n j = 0\n l = 0\n for i in file:\n k += 1\n file.close()\n\n file = open(WEIGHT_FILE_TO_USE, 'r')\n for i in tqdm(range(k)):\n string_current = file.readline()\n if ((string_current.split(\" \")[0] != \"\\n\") & (string_current.split(\" \")[0] != \"//\")):\n if string_current.split(\" \")[2] == '':\n data_current = string_current.split(\" \")[3][4:-1]\n minus = '0'\n else:\n data_current = string_current.split(\" \")[2][5:-1]\n minus = '1'\n\n while len(data_current) != 21:\n data_current = \"0\" + data_current\n\n ser.write(bytes([int('00' + data_current[15] + data_current[16] + data_current[17] + data_current[18] + data_current[19] + data_current[20], 2)]))\n ser.write(bytes([int('00' + data_current[9] + data_current[10] + data_current[11] + data_current[12] + data_current[13] + data_current[14], 2)]))\n ser.write(bytes([int('00' + data_current[3] + data_current[4] + data_current[5] + data_current[6] + data_current[7] + data_current[8], 2)]))\n ser.write(bytes([int('0000' + minus + data_current[0] + data_current[1] + data_current[2], 2)]))\n l += 1\n\n for i in range(3):\n ser.write(bytes([191]))\n for i in range(3):\n ser.write(bytes([0]))\n file.close()\n\n print(\"Counter numbers: \" + str(l))" }, { "path": "verilog/CAMERA/camera_controller.v", "content": "module camera_contoller(\n\toutput\t\t\tCMOS_SCLK,\t//cmos i2c clock\n\tinout\t\t\t\tCMOS_SDAT,\t//cmos i2c data\n\tinput\t\t\t\tCMOS_VSYNC,\t//cmos vsync\n\tinput\t\t\t\tCMOS_HREF,\t//cmos hsync refrence\n\tinput\t\t\t\tCMOS_PCLK,\t//cmos pxiel clock\n\toutput\t\t\tCMOS_XCLK,\t//cmos externl clock\n\tinput\t[7:0]\t CMOS_DB,\t\t//cmos data\n\toutput\t\t\tcmos_rst_n,\t//cmos reset\n\toutput\t\t\tcmos_pwdn,\t//cmos pwer down\n);\n\nwire clk_camera;\nwire clk_vga;\t\t//vga clock\nwire clk_ref;\t\t//sdram ctrl clock\nwire clk_refout;\t\t//sdram clock output\nwire clk_25M;\n \nwire sys_rst_n;\t\t//global reset\n \nwire\t\t\tsys_we;\t\t\t//system data write enable\nwire\t[15:0] sys_data_in; //system data input\nwire\t\t\tsdram_init_done; //sdram init done\n \n\nwire initial_en; \nwire locked;\n\n\n//pll pll_inst(clk, tft_clk, clk_10khz, clk_camera, locked);\npll_test pll_test ( .refclk\t(clk), // refclk.clk\n\t\t\t .rst\t\t(1'b0), // reset.reset\n\t\t\t .outclk_0\t(tft_clk), // outclk0.clk\n\t\t\t .outclk_1 (), // outclk1.clk\n\t\t\t .outclk_2 (clk_camera), // outclk2.clk\n\t\t\t .locked\t(locked) // locked.export\n\t);\n\nreg [9:0] delay_cnt;\nreg delay_done;\n\nalways @(posedge tft_clk or negedge rst_n)\nbegin\n\tif(!rst_n)\n\t\tbegin\n\t\tdelay_cnt <= 0;\n\t\tdelay_done <= 1'b0;\n\t\tend\n\telse\n\t\tbegin\n\t\t if (delay_cnt== 1000)\n\t\t\t delay_done <= 1'b1;\n else\n delay_cnt <= delay_cnt +1'b1;\n\t\tend\nend\n\nassign sys_rst_n=delay_done;\n \n //上电延迟部分\npower_on_delay\tpower_on_delay_inst(\n\t.clk_50M (clk_camera),\n\t.reset_n (sys_rst_n),\t\n\t.camera_rstn (cmos_rst_n),\n\t.camera_pwnd (cmos_pwdn),\n\t.initial_en (initial_en)\t\t\n);\n\n//Camera初始化部分,Camera LED FLASH control\nreg_config\treg_config_inst(\n\t.clk_25M (clk_camera),\n\t.camera_rstn (cmos_rst_n),\n\t.initial_en (initial_en),\t\t\n\t.i2c_sclk (CMOS_SCLK),\n\t.i2c_sdat (CMOS_SDAT),\n\t.reg_conf_done (Config_Done),\n\t.strobe_flash (),\n\t.reg_index (),\n\t.clock_20k (),\n\t.key1 (KEY1)\n);\n \n//----------------------------------------------- \nwire\t\t\tframe_valid;\t\t//data valid, or address restart\nwire\t[7:0] cmos_fps_data;\t\t//cmos frame rate\nCMOS_Capture\tu_CMOS_Capture\n(\n\t//Global Clock\n\t.iCLK\t\t\t\t(clk_camera),\t\t//24MHz\n\t.iRST_N\t\t\t\t(sys_rst_n),\t//global reset\n\t\n\t//I2C Initilize Done\n\t.Init_Done\t\t\t(Config_Done /*& sdram_init_done*/),\t//Init Done\n\t\n\t//Sensor Interface\n\t.CMOS_XCLK\t\t\t(CMOS_XCLK),\t\t//cmos\n\t.CMOS_PCLK\t\t\t(CMOS_PCLK),\t\t//24MHz\n\t.CMOS_iDATA\t\t\t(CMOS_DB), \t//CMOS Data\n\t.CMOS_VSYNC\t\t\t(CMOS_VSYNC), \t \t//L: Vaild\n\t.CMOS_HREF\t\t\t(CMOS_HREF), \t\t//H: Vaild\n\t \n\t//Ouput Sensor Data \n\t.CMOS_oCLK\t\t\t(sys_we),\t\t\t//Data PCLK\n\t.CMOS_oDATA\t\t\t(sys_data_in), \t//16Bits RGB\n\t.CMOS_VALID\t\t\t(frame_valid),\t\t//Data Enable\n\t.CMOS_FPS_DATA\t\t({LED[7],LED[6],LED[5],LED[4],LED[3],LED[2],LED[1],LED[0]})//(cmos_fps_data)\t\t//cmos frame rate\n);\n\nendmodule\n" }, { "path": "verilog/CAMERA/cmos_i2c_ov5640/CMOS_Capture.v", "content": "/*-------------------------------------------------------------------------\nDescription\t\t\t:\t\tsdram test with uart interface.\nModification History\t:\nData\t\t\tBy\t\t\tVersion\t\t\tChange Description\n===========================================================================\n\n--------------------------------------------------------------------------*/\n\n`timescale 1ns/1ns\nmodule CMOS_Capture\n(\n\t//Global Clock\n\tinput\t\t\t\tiCLK,\t\t\t//24MHz\n\tinput\t\t\t\tiRST_N,\n\n\t//I2C Initilize Done\n\tinput\t\t\t\tInit_Done,\t\t//Init Done\n\t\n\t//Sensor Interface\n\toutput\t\t\t\tCMOS_XCLK,\t\t//24MHz\n\tinput\t\t\t\tCMOS_PCLK,\t\t//24MHz\n\tinput\t[7:0]\t\tCMOS_iDATA,\t\t//CMOS Data\n\tinput\t\t\t\tCMOS_VSYNC,\t\t//L: Vaild\n\tinput\t\t\t\tCMOS_HREF,\t\t//H: Vaild\n\t\n\t//Ouput Sensor Data\n\toutput\treg\t\t\tCMOS_oCLK,\t\t//1/2 PCLK\n\toutput\treg\t[15:0]\tCMOS_oDATA,\t\t//16Bits RGB\t\t\n\toutput\treg\t\t\tCMOS_VALID,\t\t//Data Enable\n\toutput\treg\t[7:0]\tCMOS_FPS_DATA\t//cmos fps\n);\n\nassign\tCMOS_XCLK = iCLK;\t\t//24MHz XCLK\n\n\n//-----------------------------------------------------\n//ͬ//Sensor HS & VS Vaild Capture\n/**************************************************\n________\t\t\t\t\t\t\t ________\nVS\t\t|_________________________________|\nHS\t\t\t _______\t \t _______\n_____________| |__...___| |____________\n**************************************************/\n\n/*\n//----------------------------------------------\nreg\t\tmCMOS_HREF;\t\t//ͬߵƽЧ\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tmCMOS_HREF <= 0;\n\telse\n\t\tmCMOS_HREF <= CMOS_HREF;\t\t\nend\nwire\tCMOS_HREF_over = ({mCMOS_HREF,CMOS_HREF} == 2'b10) ? 1'b1 : 1'b0;\t\t//HREF ½ؽ\n*/\n\n//----------------------------------------------\nreg\t\tmCMOS_VSYNC;\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tmCMOS_VSYNC <= 1;\n\telse\n\t\tmCMOS_VSYNC <= CMOS_VSYNC;\t\t//ͬ͵ƽЧ\nend\nwire\tCMOS_VSYNC_over = ({mCMOS_VSYNC,CMOS_VSYNC} == 2'b01) ? 1'b1 : 1'b0;\t//VSYNCؽ\n\n\n/*\n//--------------------------------------------\n//Counter the HS & VS Pixel\nlocalparam\t\tH_DISP\t=\t12'd640;\nlocalparam\t\tV_DISP\t=\t12'd480;\nreg\t\t[11:0]\tX_Cont;\t//640\nreg\t\t[11:0]\tY_Cont;\t//480\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tX_Cont <= 0;\n\telse if(~CMOS_VSYNC & CMOS_HREF)\t\t\t//źЧ\n\t\tX_Cont <= (byte_state == 1'b1) ? X_Cont + 1'b1 : X_Cont;\n\telse\n\t\tX_Cont <= 0;\nend\n\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tY_Cont <= 0;\n\telse if(CMOS_VSYNC == 1'b0)\n\t\tbegin\n\t\tif(CMOS_HREF_over == 1'b1)\t\t//HREF½ һн\n\t\t\tY_Cont <= Y_Cont + 1'b1;\n\t\tend\n\telse\n\t\tY_Cont <= 0;\nend\n*/\n\n//-----------------------------------------------------\n//Change the sensor data from 8 bits to 16 bits.\nreg\t\t\tbyte_state;\t\t//byte state count\nreg [7:0] \tPre_CMOS_iDATA;\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tbegin\n\t\tbyte_state <= 0;\n\t\tPre_CMOS_iDATA <= 8'd0;\n\t\tCMOS_oDATA <= 16'd0;\n\t\tend\n\telse\n\t\tbegin\n\t\tif(~CMOS_VSYNC & CMOS_HREF)\t\t\t//гЧ{first_byte, second_byte} \n\t\t\tbegin\n\t\t\tbyte_state <= byte_state + 1'b1;\t//RGB565 = {first_byte, second_byte}\n\t\t\tcase(byte_state)\n\t\t\t1'b0 :\tPre_CMOS_iDATA[7:0] <= CMOS_iDATA;\n\t\t\t1'b1 : \tCMOS_oDATA[15:0] <= {Pre_CMOS_iDATA[7:0], CMOS_iDATA[7:0]};\n\t\t\tendcase\n\t\t\tend\n\t\telse\n\t\t\tbegin\n\t\t\tbyte_state <= 0;\n\t\t\tPre_CMOS_iDATA <= 8'd0;\n\t\t\tCMOS_oDATA <= CMOS_oDATA;\n\t\t\tend\n\t\tend\nend\n\n\n//--------------------------------------------\n//Wait for Sensor output Data valid 10 Franme\nreg\t[3:0] \tFrame_Cont;\nreg \t\tFrame_valid;\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tbegin\n\t\tFrame_Cont <= 0;\n\t\tFrame_valid <= 0;\n\t\tend\n\telse if(Init_Done)\t\t\t\t\t//CMOS I2Cʼ\n\t\tbegin\n\t\tif(CMOS_VSYNC_over == 1'b1)\t\t//VSأ1֡д\n\t\t\tbegin\n\t\t\tif(Frame_Cont < 12)\n\t\t\t\tbegin\n\t\t\t\tFrame_Cont\t<=\tFrame_Cont + 1'b1;\n\t\t\t\tFrame_valid <= 1'b0;\n\t\t\t\tend\n\t\t\telse\n\t\t\t\tbegin\n\t\t\t\tFrame_Cont\t<=\tFrame_Cont;\n\t\t\t\tFrame_valid <= 1'b1;\t\t//Ч\n\t\t\t\tend\n\t\t\tend\n\t\tend\nend\n\n//-----------------------------------------------------\n//CMOS_DATAͬʹʱ\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tCMOS_oCLK <= 0;\n\telse if(Frame_valid == 1'b1 && byte_state)//(X_Cont >= 12'd1 && X_Cont <= H_DISP))\n\t\tCMOS_oCLK <= ~CMOS_oCLK;\n\telse\n\t\tCMOS_oCLK <= 0;\nend\n\n//----------------------------------------------------\n//ЧCMOS_VALID\nalways@(posedge CMOS_PCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tCMOS_VALID <= 0;\n\telse if(Frame_valid == 1'b1)\n\t\tCMOS_VALID <= ~CMOS_VSYNC;\n\telse\n\t\tCMOS_VALID <= 0;\nend\n\n\n/************************************************************\n\tCaculate Frame Rate per second\n*************************************************************/\n//-----------------------------------------------------\n//\t2s ʱ\nreg\t[25:0]\tdelay_cnt;\t//25_000000 * 2\nalways@(posedge iCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tdelay_cnt <= 0;\n\telse if(Frame_valid)\n\t\tbegin\n\t\tif(delay_cnt < 26'd50_000000)\n\t\t\tdelay_cnt <= delay_cnt + 1'b1;\n\t\telse\n\t\t\tdelay_cnt <= 0;\n\t\tend\n\telse\n\t\tdelay_cnt <= 0;\nend\nwire\tdelay_2s = (delay_cnt == 26'd50_000000) ? 1'b1 : 1'b0;\n\n//-------------------------------------------\n//֡ʲ\nreg\t\t\tfps_state;\nreg\t[7:0]\tfps_data;\nalways@(posedge iCLK or negedge iRST_N)\nbegin\n\tif(!iRST_N)\n\t\tbegin\n\t\tfps_data <= 0;\n\t\tfps_state <= 0;\n\t\tCMOS_FPS_DATA <= 0;\n\t\tend\n\telse if(Frame_valid)\n\t\tbegin\n\t\tcase(fps_state)\n\t\t0:\tbegin\n\t\t\tCMOS_FPS_DATA <= CMOS_FPS_DATA;\n\t\t\tif(delay_2s == 0)\n\t\t\t\tbegin\n\t\t\t\tfps_state <= 0;\n\t\t\t\tif(CMOS_VSYNC_over == 1'b1)\t\t//VSأ1֡д\n\t\t\t\t\tfps_data <= fps_data + 1'b1;\n\t\t\t\tend\n\t\t\telse\n\t\t\t\tfps_state <= 1;\n\t\t\tend\n\t\t1:\tbegin\n\t\t\tfps_state <= 0;\n\t\t\tfps_data <= 0;\n\t\t\tCMOS_FPS_DATA <= fps_data >>1;\n\t\t\tend\n\t\tendcase\n\t\tend\n\telse\n\t\tbegin\n\t\tfps_data <= 0;\n\t\tfps_state <= 0;\n\t\tCMOS_FPS_DATA <= 0;\n\t\tend\nend\n\n\nendmodule\n\n\n\n" }, { "path": "verilog/CAMERA/cmos_i2c_ov5640/i2c_com.v", "content": " //sclksdinݴʱ루i2cдƴ룩\nmodule i2c_com(clock_i2c, //i2cƽӿڴʱӣ0-400khz˴Ϊ20khz\n camera_rstn, \n ack, //Ӧź\n i2c_data, //sdinӿڴ32λ\n start, //ʼ־\n tr_end, //־\n i2c_sclk, //FPGAcamera iicʱӽӿ\n i2c_sdat); //FPGAcamera iicݽӿ\n input [31:0]i2c_data;\n input camera_rstn;\n input clock_i2c;\n output ack;\n input start;\n output tr_end;\n output i2c_sclk;\n inout i2c_sdat;\n reg [5:0] cyc_count;\n reg reg_sdat;\n reg sclk;\n reg ack1,ack2,ack3;\n reg tr_end;\n \n \n wire i2c_sclk;\n wire i2c_sdat;\n wire ack;\n \n assign ack=ack1|ack2|ack3;\n assign i2c_sclk=sclk|(((cyc_count>=4)&(cyc_count<=39))?~clock_i2c:0);\n assign i2c_sdat=reg_sdat?1'bz:0;\n \n \n always@(posedge clock_i2c or negedge camera_rstn)\n begin\n if(!camera_rstn)\n cyc_count<=6'b111111;\n else \n\t\t begin\n if(start==0)\n cyc_count<=0;\n else if(cyc_count<6'b111111)\n cyc_count<=cyc_count+1;\n end\n end\n\t \n\t \n always@(posedge clock_i2c or negedge camera_rstn)\n begin\n if(!camera_rstn)\n begin\n tr_end<=0;\n ack1<=1;\n ack2<=1;\n ack3<=1;\n sclk<=1;\n reg_sdat<=1;\n end\n else\n case(cyc_count)\n 0:begin ack1<=1;ack2<=1;ack3<=1;tr_end<=0;sclk<=1;reg_sdat<=1;end\n 1:reg_sdat<=0; //ʼ\n 2:sclk<=0;\n 3:reg_sdat<=i2c_data[31];\n 4:reg_sdat<=i2c_data[30];\n 5:reg_sdat<=i2c_data[29];\n 6:reg_sdat<=i2c_data[28];\n 7:reg_sdat<=i2c_data[27];\n 8:reg_sdat<=i2c_data[26];\n 9:reg_sdat<=i2c_data[25];\n 10:reg_sdat<=i2c_data[24];\n 11:reg_sdat<=1; //Ӧź\n 12:begin reg_sdat<=i2c_data[23];ack1<=i2c_sdat;end\n 13:reg_sdat<=i2c_data[22];\n 14:reg_sdat<=i2c_data[21];\n 15:reg_sdat<=i2c_data[20];\n 16:reg_sdat<=i2c_data[19];\n 17:reg_sdat<=i2c_data[18];\n 18:reg_sdat<=i2c_data[17];\n 19:reg_sdat<=i2c_data[16];\n 20:reg_sdat<=1; //Ӧź \n 21:begin reg_sdat<=i2c_data[15];ack1<=i2c_sdat;end\n 22:reg_sdat<=i2c_data[14];\n 23:reg_sdat<=i2c_data[13];\n 24:reg_sdat<=i2c_data[12];\n 25:reg_sdat<=i2c_data[11];\n 26:reg_sdat<=i2c_data[10];\n 27:reg_sdat<=i2c_data[9];\n 28:reg_sdat<=i2c_data[8];\n 29:reg_sdat<=1; //Ӧź \n 30:begin reg_sdat<=i2c_data[7];ack2<=i2c_sdat;end\n 31:reg_sdat<=i2c_data[6];\n 32:reg_sdat<=i2c_data[5];\n 33:reg_sdat<=i2c_data[4];\n 34:reg_sdat<=i2c_data[3];\n 35:reg_sdat<=i2c_data[2];\n 36:reg_sdat<=i2c_data[1];\n 37:reg_sdat<=i2c_data[0];\n 38:reg_sdat<=1; //Ӧź \n 39:begin ack3<=i2c_sdat;sclk<=0;reg_sdat<=0;end\n 40:sclk<=1;\n 41:begin reg_sdat<=1;tr_end<=1;end\n endcase\n \nend\nendmodule\n\n" }, { "path": "verilog/CAMERA/cmos_i2c_ov5640/ov5640_cfg.v", "content": "module ov5640_cfg(\n \n);\n\n\n\nendmodule" }, { "path": "verilog/CAMERA/cmos_i2c_ov5640/power_on_delay.v", "content": "//camera power on timing requirement\nmodule power_on_delay(clk_50M,reset_n,camera_rstn,camera_pwnd,initial_en); \ninput clk_50M;\ninput reset_n;\noutput camera_rstn;\noutput camera_pwnd;\noutput initial_en;\nreg [18:0]cnt1;\nreg [15:0]cnt2;\nreg [19:0]cnt3;\nreg initial_en;\nreg camera_rstn_reg;\nreg camera_pwnd_reg;\n\nassign camera_rstn=camera_rstn_reg;\nassign camera_pwnd=camera_pwnd_reg;\n\n//5ms, delay from sensor power up stable to Pwdn pull down\nalways@(posedge clk_50M)\nbegin\n if(reset_n==1'b0) begin\n\t cnt1<=0;\n\t\t camera_pwnd_reg<=1'b1; \n end\n else if(cnt1<18'h40000) begin\n cnt1<=cnt1+1'b1;\n camera_pwnd_reg<=1'b1;\n end\n else\n camera_pwnd_reg<=1'b0; \nend\n\n//1.3ms, delay from pwdn low to resetb pull up\nalways@(posedge clk_50M)\nbegin\n if(camera_pwnd_reg==1) begin\n\t cnt2<=0;\n\t\t camera_rstn_reg<=1'b0; \n end\n else if(cnt2<16'hffff) begin\n cnt2<=cnt2+1'b1;\n camera_rstn_reg<=1'b0;\n end\n else\n camera_rstn_reg<=1'b1; \nend\n\n//21ms, delay from resetb pul high to SCCB initialization\nalways@(posedge clk_50M)\nbegin\n if(camera_rstn_reg==0) begin\n cnt3<=0;\n initial_en<=1'b0;\n end\n else if(cnt3<20'hfffff) begin\n cnt3<=cnt3+1'b1;\n initial_en<=1'b0;\n end\n else\n initial_en<=1'b1; \nend\n\nendmodule\n" }, { "path": "verilog/CAMERA/cmos_i2c_ov5640/reg_config.v", "content": "//camera�мĴ��������ó���\n module reg_config( \n\t\t input clk_25M,\n\t\t input camera_rstn,\n\t\t input initial_en,\n\t\t output reg strobe_flash,\n\t\t output reg_conf_done,\n\t\t output i2c_sclk,\n\t\t inout i2c_sdat,\n\t\t output reg clock_20k,\n\t\t output reg [8:0]reg_index,\n\t\t input key1\n\t );\n\n \n \n reg [15:0]clock_20k_cnt;\n reg [1:0]config_step;\n\t \n reg [31:0]i2c_data;\n reg [23:0]reg_data;\n reg start;\n\t reg reg_conf_done_reg;\n reg [15:0] on_counter;\n\t reg [15:0] off_counter;\n\t reg key_on, key_off;\n\t \n i2c_com u1(.clock_i2c(clock_20k),\n .camera_rstn(camera_rstn),\n .ack(ack),\n .i2c_data(i2c_data),\n .start(start),\n .tr_end(tr_end),\n .i2c_sclk(i2c_sclk),\n .i2c_sdat(i2c_sdat));\n\nassign reg_conf_done=reg_conf_done_reg;\n//����i2c����ʱ��-20khz \nalways@(posedge clk_25M or negedge camera_rstn) \nbegin\n if(!camera_rstn) begin\n clock_20k<=0;\n clock_20k_cnt<=0;\n end\n else if(clock_20k_cnt<1249)\n clock_20k_cnt<=clock_20k_cnt+1'b1;\n else begin\n clock_20k<=!clock_20k;\n clock_20k_cnt<=0;\n end\nend\n\n//��ť��������\t\nalways @(posedge clock_20k or negedge camera_rstn)\n if (!camera_rstn) begin\n\t on_counter<=0;\n off_counter<=0;\t\n\t\t key_on<=1'b0;\n\t\t key_off<=1'b0;\n\t end\n\telse begin\n\t if (key1==1'b1) //������ťû�а��£��Ĵ���Ϊ0\n\t on_counter<=0;\n\t else if ((key1==1'b0)& (on_counter<=16'h00c8)) //������ť���²�����ʱ������10ms,���� \n on_counter<=on_counter+1'b1;\n \t \n if (on_counter==16'h00c7) //һ�ΰ�ť������Ч\n\t\t\t key_on<=1'b1;\n\t\t else\n\t\t\t key_on<=1'b0;\n\t\t\t\t\n\t if (key1==1'b0) //������ťû���ͷţ��Ĵ���Ϊ0\n\t off_counter<=0;\n\t else if ((key1==1'b1)& (off_counter<=16'h00c8)) //������ť�ͷŲ�ʱ������10ms,���� \n off_counter<=off_counter+1'b1;\n \t \n if (off_counter==16'h00c7) //һ�ΰ�ť�ɿ���Ч\n\t\t\t key_off<=1'b1;\n\t\t else\n\t\t\t key_off<=1'b0;\t\t\t\t\n\t\t\t\t\n end \n\n\n////iic�Ĵ������ù��̿��� \nalways@(posedge clock_20k or negedge camera_rstn) \nbegin\n if(!camera_rstn) begin\n config_step<=0;\n start<=0;\n reg_index<=0;\n\t\t reg_conf_done_reg<=0;\n\t\t strobe_flash<=1'b0;\n end\n else begin\n if(reg_conf_done_reg==1'b0) begin //����camera��ʼ��δ����\n\t\t\t // if(reg_index<251) begin\n\t\t\t if(reg_index<302) begin\n\t\t\t\t\t case(config_step)\n\t\t\t\t\t 0:begin\n\t\t\t\t\t\ti2c_data<={8'h78,reg_data}; //IIC Device address is 0x78 \n\t\t\t\t\t\tstart<=1;\n\t\t\t\t\t\tconfig_step<=1;\n\t\t\t\t\t end\n\t\t\t\t\t 1:begin\n\t\t\t\t\t\tif(tr_end) begin //IIC���ͽ��� \t\t\t\t\t\n\t\t\t\t\t\t\t start<=0;\n\t\t\t\t\t\t\t config_step<=2;\n\t\t\t\t\t\tend\n\t\t\t\t\t end\n\t\t\t\t\t 2:begin\n\t\t\t\t\t\t reg_index<=reg_index+1'b1;\n\t\t\t\t\t\t config_step<=0;\n\t\t\t\t\t end\n\t\t\t\t\t endcase\n\t\t\t\tend\n\t\t\t else \n\t\t\t\treg_conf_done_reg<=1'b1;\n end\n else begin //����camera��ʼ��������\n\t case(config_step)\n 0:begin\n\t\t\t\t \tif(key_on==1'b1) begin //��������,���üĴ���ʹ���������\n\t\t\t\t\t\tconfig_step<=1;\n\t\t\t\t\t\treg_index<=302; //�ӵ�302��ʼд�Ĵ���\n\t\t\t\t\t\tstrobe_flash<=1'b1;\n\t\t\t\t\tend\n\t\t\t\t\telse if (key_off==1'b1) begin //�����ɿ�,���üĴ���ʹ���������\n\t\t\t\t\t\tconfig_step<=1;\n\t\t\t\t\t\treg_index<=303; //�ӵ�303��ʼд�Ĵ���\n\t\t\t\t\t\tstrobe_flash<=1'b0;\n\t\t\t\t\tend\n end\t\t\t\t\t\n 1:begin\t\t\t\n\t\t\t\t\t\ti2c_data<={8'h78,reg_data}; //IIC Device address is 0x78 \n\t\t\t\t\t\tstart<=1;\t\t\t\t\t\t\n\t\t\t\t\t\tconfig_step<=2;\n end\n 2:begin\n if(tr_end) begin //IIC���ͽ��� \t\t\t\t\t\n\t\t\t\t\t start<=0;\n config_step<=3;\n end\n end\n 3:begin\n config_step<=0;\n\t\t\t\t\t reg_index<=300;\t \n end\n endcase\n\t\t end\n end\n end\n\t\t\t\n////iic��Ҫ���õļĴ���ֵ \t\t\t\nalways@(reg_index) \n begin\n case(reg_index)\n\t 0:reg_data<=24'h310311;// system clock from pad, bit[1]\n\t 1:reg_data<=24'h300882;// software reset, bit[7]// delay 5ms \n\t 2:reg_data<=24'h300842;// software power down, bit[6]\n\t 3:reg_data<=24'h310303;// system clock from PLL, bit[1]\n\t 4:reg_data<=24'h3017ff;// FREX, Vsync, HREF, PCLK, D[9:6] output enable\n\t 5:reg_data<=24'h3018ff;// D[5:0], GPIO[1:0] output enable\n\t 6:reg_data<=24'h30341A;// MIPI 10-bit\n\t 7:reg_data<=24'h303713;// PLL root divider, bit[4], PLL pre-divider, bit[3:0]\n\t 8:reg_data<=24'h310801;// PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] // SCLK root divider, bit[1:0] \n\t 9:reg_data<=24'h363036;\n\t 10:reg_data<=24'h36310e;\n\t 11:reg_data<=24'h3632e2;\n\t 12:reg_data<=24'h363312;\n\t 13:reg_data<=24'h3621e0;\n\t 14:reg_data<=24'h3704a0;\n\t 15:reg_data<=24'h37035a;\n\t 16:reg_data<=24'h371578;\n\t 17:reg_data<=24'h371701;\n\t 18:reg_data<=24'h370b60;\n\t 19:reg_data<=24'h37051a;\n \n\t 20:reg_data<=24'h390502;\n\t 21:reg_data<=24'h390610;\n\t 22:reg_data<=24'h39010a;\n\t 23:reg_data<=24'h373112;\n\t 24:reg_data<=24'h360008;// VCM control\n\t 25:reg_data<=24'h360133;// VCM control\n\t 26:reg_data<=24'h302d60;// system control\n\t 27:reg_data<=24'h362052;\n\t 28:reg_data<=24'h371b20;\n\t 29:reg_data<=24'h471c50;\n \n\t 30:reg_data<=24'h3a1343;// pre-gain = 1.047x\n\t 31:reg_data<=24'h3a1800;// gain ceiling\n\t 32:reg_data<=24'h3a19f8;// gain ceiling = 15.5x\n\t 33:reg_data<=24'h363513;\n\t 34:reg_data<=24'h363603;\n\t 35:reg_data<=24'h363440;\n\t 36:reg_data<=24'h362201; // 50/60Hz detection 50/60Hz 灯光条纹过滤\n\t 37:reg_data<=24'h3c0134;// Band auto, bit[7]\n\t 38:reg_data<=24'h3c0428;// threshold low sum\t \n\t 39:reg_data<=24'h3c0598;// threshold high sum\n \n\t 40:reg_data<=24'h3c0600;// light meter 1 threshold[15:8]\n\t 41:reg_data<=24'h3c0708;// light meter 1 threshold[7:0]\n\t 42:reg_data<=24'h3c0800;// light meter 2 threshold[15:8]\n\t 43:reg_data<=24'h3c091c;// light meter 2 threshold[7:0]\n\t 44:reg_data<=24'h3c0a9c;// sample number[15:8]\n\t 45:reg_data<=24'h3c0b40;// sample number[7:0]\n\t 46:reg_data<=24'h381000;// Timing Hoffset[11:8]\n\t 47:reg_data<=24'h381100;//10;// Timing Hoffset[7:0]\n\t 48:reg_data<=24'h381200;// Timing Voffset[10:8] \n\t 49:reg_data<=24'h370864;\n \n\t 50:reg_data<=24'h400102;// BLC start from line 2\n\t 51:reg_data<=24'h40051a;// BLC always update\n\t 52:reg_data<=24'h300000;// enable blocks\n\t 53:reg_data<=24'h3004ff;// enable clocks \n\t 54:reg_data<=24'h300e58;// MIPI power down, DVP enable\n\t 55:reg_data<=24'h302e00;\n\t 56:reg_data<=24'h430060;// RGB565\n\t 57:reg_data<=24'h501f01;// ISP RGB \n\t 58:reg_data<=24'h440e00;\n\t 59:reg_data<=24'h5000a7; // Lenc on, raw gamma on, BPC on, WPC on, CIP on // AEC target 自动曝光控制\n \n\t 60:reg_data<=24'h3a0f30;// stable range in high\n\t 61:reg_data<=24'h3a1028;// stable range in low\n\t 62:reg_data<=24'h3a1b30;// stable range out high\n\t 63:reg_data<=24'h3a1e26;// stable range out low\n\t 64:reg_data<=24'h3a1160;// fast zone high\n\t 65:reg_data<=24'h3a1f14;// fast zone low// Lens correction for ? 镜头补偿\n\t 66:reg_data<=24'h580023;\n\t 67:reg_data<=24'h580114;\n\t 68:reg_data<=24'h58020f;\n\t 69:reg_data<=24'h58030f;\n \n\t 70:reg_data<=24'h580412;\n\t 71:reg_data<=24'h580526;\n\t 72:reg_data<=24'h58060c;\n\t 73:reg_data<=24'h580708;\n\t 74:reg_data<=24'h580805;\n\t 75:reg_data<=24'h580905;\n\t 76:reg_data<=24'h580a08;\n\t 77:reg_data<=24'h580b0d;\n\t 78:reg_data<=24'h580c08;\n\t 79:reg_data<=24'h580d03;\n \n\t 80:reg_data<=24'h580e00;\n\t 81:reg_data<=24'h580f00;\n\t 82:reg_data<=24'h581003;\n\t 83:reg_data<=24'h581109;\n\t 84:reg_data<=24'h581207;\n\t 85:reg_data<=24'h581303;\n\t 86:reg_data<=24'h581400;\n\t 87:reg_data<=24'h581501;\n\t 88:reg_data<=24'h581603;\n\t 89:reg_data<=24'h581708;\n \n\t 90:reg_data<=24'h58180d;\n\t 91:reg_data<=24'h581908;\n\t 92:reg_data<=24'h581a05;\n\t 93:reg_data<=24'h581b06;\n\t 94:reg_data<=24'h581c08;\n\t 95:reg_data<=24'h581d0e;\n\t 96:reg_data<=24'h581e29;\n\t 97:reg_data<=24'h581f17;\n\t 98:reg_data<=24'h582011;\n\t 99:reg_data<=24'h582111;\n \n\t 100:reg_data<=24'h582215;\n\t 101:reg_data<=24'h582328;\n\t 102:reg_data<=24'h582446;\n\t 103:reg_data<=24'h582526;\n\t 104:reg_data<=24'h582608;\n\t 105:reg_data<=24'h582726;\n\t 106:reg_data<=24'h582864;\n\t 107:reg_data<=24'h582926;\n\t 108:reg_data<=24'h582a24;\n\t 109:reg_data<=24'h582b22;\n \n\t 110:reg_data<=24'h582c24;\n\t 111:reg_data<=24'h582d24;\n\t 112:reg_data<=24'h582e06;\n\t 113:reg_data<=24'h582f22;\n\t 114:reg_data<=24'h583040;\n\t 115:reg_data<=24'h583142;\n\t 116:reg_data<=24'h583224;\n\t 117:reg_data<=24'h583326;\n\t 118:reg_data<=24'h583424;\n\t 119:reg_data<=24'h583522;\n \n\t 120:reg_data<=24'h583622;\n\t 121:reg_data<=24'h583726;\n\t 122:reg_data<=24'h583844;\n\t 123:reg_data<=24'h583924;\n\t 124:reg_data<=24'h583a26;\n\t 125:reg_data<=24'h583b28;\n\t 126:reg_data<=24'h583c42;\n\t 127:reg_data<=24'h583dce;// lenc BR offset // AWB 自动白平衡\n\t 128:reg_data<=24'h5180ff;// AWB B block\n\t 129:reg_data<=24'h5181f2;// AWB control \n \n \n\t 130:reg_data<=24'h518200;// [7:4] max local counter, [3:0] max fast counter\n\t 131:reg_data<=24'h518314;// AWB advanced \n\t 132:reg_data<=24'h518425;\n\t 133:reg_data<=24'h518524;\n\t 134:reg_data<=24'h518609;\n\t 135:reg_data<=24'h518709;\n\t 136:reg_data<=24'h518809;\n\t 137:reg_data<=24'h518975;\n\t 138:reg_data<=24'h518a54;\n\t 139:reg_data<=24'h518be0;\n \n \n\t 140:reg_data<=24'h518cb2;\n\t 141:reg_data<=24'h518d42;\n\t 142:reg_data<=24'h518e3d;\n\t 143:reg_data<=24'h518f56;\n\t 144:reg_data<=24'h519046;\n\t 145:reg_data<=24'h5191f8;// AWB top limit\n\t 146:reg_data<=24'h519204;// AWB bottom limit\n\t 147:reg_data<=24'h519370;// red limit\n\t 148:reg_data<=24'h5194f0;// green limit\n\t 149:reg_data<=24'h5195f0;// blue limit\n \n \n\t 150:reg_data<=24'h519603;// AWB control\n\t 151:reg_data<=24'h519701;// local limit \n\t 152:reg_data<=24'h519804;\n\t 153:reg_data<=24'h519912;\n\t 154:reg_data<=24'h519a04;\n\t 155:reg_data<=24'h519b00;\n\t 156:reg_data<=24'h519c06;\n\t 157:reg_data<=24'h519d82;\n\t 158:reg_data<=24'h519e38;// AWB control // Gamma 伽玛曲线\n\t 159:reg_data<=24'h548001;// Gamma bias plus on, bit[0] \n \n \n\t 160:reg_data<=24'h548108;\n\t 161:reg_data<=24'h548214;\n\t 162:reg_data<=24'h548328;\n\t 163:reg_data<=24'h548451;\n\t 164:reg_data<=24'h548565;\n\t 165:reg_data<=24'h548671;\n\t 166:reg_data<=24'h54877d;\n\t 167:reg_data<=24'h548887;\n\t 168:reg_data<=24'h548991;\n\t 169:reg_data<=24'h548a9a;\n \n \n\t 170:reg_data<=24'h548baa;\n\t 171:reg_data<=24'h548cb8;\n\t 172:reg_data<=24'h548dcd;\n\t 173:reg_data<=24'h548edd;\n\t 174:reg_data<=24'h548fea;\n\t 175:reg_data<=24'h54901d;// color matrix 色彩矩阵\n\t 176:reg_data<=24'h53811e;// CMX1 for Y\n\t 177:reg_data<=24'h53825b;// CMX2 for Y\n\t 178:reg_data<=24'h538308;// CMX3 for Y\n\t 179:reg_data<=24'h53840a;// CMX4 for U\n \n \n\t 180:reg_data<=24'h53857e;// CMX5 for U\n\t 181:reg_data<=24'h538688;// CMX6 for U\n\t 182:reg_data<=24'h53877c;// CMX7 for V\n\t 183:reg_data<=24'h53886c;// CMX8 for V\n\t 184:reg_data<=24'h538910;// CMX9 for V\n\t 185:reg_data<=24'h538a01;// sign[9]\n\t 186:reg_data<=24'h538b98; // sign[8:1] // UV adjust UV色彩饱和度调整\n\t 187:reg_data<=24'h558006;// saturation on, bit[1]\n\t 188:reg_data<=24'h558340;\n\t 189:reg_data<=24'h558410;\n \n \n\t 190:reg_data<=24'h558910;\n\t 191:reg_data<=24'h558a00;\n\t 192:reg_data<=24'h558bf8;\n\t 193:reg_data<=24'h501d40;// enable manual offset of contrast// CIP 锐化和降噪 \n\t 194:reg_data<=24'h530008;// CIP sharpen MT threshold 1\n\t 195:reg_data<=24'h530130;// CIP sharpen MT threshold 2\n\t 196:reg_data<=24'h530210;// CIP sharpen MT offset 1\n\t 197:reg_data<=24'h530300;// CIP sharpen MT offset 2\n\t 198:reg_data<=24'h530408;// CIP DNS threshold 1\n\t 199:reg_data<=24'h530530;// CIP DNS threshold 2\n \n \n\t 200:reg_data<=24'h530608;// CIP DNS offset 1\n\t 201:reg_data<=24'h530716;// CIP DNS offset 2 \n\t 202:reg_data<=24'h530908;// CIP sharpen TH threshold 1\n\t 203:reg_data<=24'h530a30;// CIP sharpen TH threshold 2\n\t 204:reg_data<=24'h530b04;// CIP sharpen TH offset 1\n\t 205:reg_data<=24'h530c06;// CIP sharpen TH offset 2\n\t 206:reg_data<=24'h502500;\n\t 207:reg_data<=24'h300802; // wake up from standby, bit[6]\n\t 208:reg_data<=24'h303511;// PLL //640x480 30帧/秒, night mode 5fps, input clock =24Mhz, PCLK =56Mhz\n\t 209:reg_data<=24'h303646;// PLL\n \n \n\t 210:reg_data<=24'h3c0708;// light meter 1 threshold [7:0]\n\t 211:reg_data<=24'h382041;// Sensor flip off, ISP flip on\n\t 212:reg_data<=24'h382107;// Sensor mirror on, ISP mirror on, H binning on\n\t 213:reg_data<=24'h381431;// X INC \n\t 214:reg_data<=24'h381531;// Y INC\n\t 215:reg_data<=24'h380000;// HS: X address start high byte\n\t 216:reg_data<=24'h380100;// HS: X address start low byte\n\t 217:reg_data<=24'h380200;// VS: Y address start high byte\n\t 218:reg_data<=24'h380304;// VS: Y address start low byte \n\t 219:reg_data<=24'h38040a;// HW (HE) \n\n \n\t 220:reg_data<=24'h38053f;// HW (HE)\n\t 221:reg_data<=24'h380607;// VH (VE) \n\t 222:reg_data<=24'h38079b;// VH (VE) \n\t 223:reg_data<=24'h380803;// DVPHO \n\t 224:reg_data<=24'h380920;// DVPHO\n\t 225:reg_data<=24'h380a02;// DVPVO\n\t 226:reg_data<=24'h380b58;// DVPVO\n\t 227:reg_data<=24'h380c07;// HTS //Total horizontal size 800\n\t 228:reg_data<=24'h380d68;// HTS\n\t 229:reg_data<=24'h380e03;// VTS //total vertical size 500\n \n \n\t 230:reg_data<=24'h380fd8;// VTS \n\t 231:reg_data<=24'h381306;// Timing Voffset \n\t 232:reg_data<=24'h361800;\n\t 233:reg_data<=24'h361229;\n\t 234:reg_data<=24'h370952;\n\t 235:reg_data<=24'h370c03; \n\t 236:reg_data<=24'h3a0217;// 60Hz max exposure, night mode 5fps\n\t 237:reg_data<=24'h3a0310;// 60Hz max exposure // banding filters are calculated automatically in camera driver\n 238:reg_data<=24'h3a1417;// 50Hz max exposure, night mode 5fps\n\t 239:reg_data<=24'h3a1510;// 50Hz max exposure \n\t //reg_data<=24'h3a0801;// B50 step\n\t //reg_data<=24'h3a0927;// B50 step\n\t //reg_data<=24'h3a0a00;// B60 step\n\t //reg_data<=24'h3a0bf6;// B60 step\n\t //reg_data<=24'h3a0e03;// 50Hz max band\n\t //reg_data<=24'h3a0d04;// 60Hz max band\n\t \n\t 240:reg_data<=24'h400402;// BLC 2 lines \n\t 241:reg_data<=24'h30021c;// reset JFIFO, SFIFO, JPEG\n\t 242:reg_data<=24'h3006c3;// disable clock of JPEG2x, JPEG\n\t 243:reg_data<=24'h471303;// JPEG mode 3\n\t 244:reg_data<=24'h440704;// Quantization scale \n\t 245:reg_data<=24'h460b35;\n\t 246:reg_data<=24'h460c22;\n\t 247:reg_data<=24'h483722; // DVP CLK divider\n\t 248:reg_data<=24'h382402; // DVP CLK divider \n\t 249:reg_data<=24'h5001a3; // SDE on, scale on, UV average off, color matrix on, AWB on\n \n\t \n\t \n\t //set OV5640 to video mode 720p \n 250:reg_data<=24'h350300; // AEC/AGC on \n\t 251:reg_data<=24'h303521;// PLL input clock =24Mhz, PCLK =84Mhz\n\t 252:reg_data<=24'h303669;// PLL\n\t 253:reg_data<=24'h3c0707; // lightmeter 1 threshold[7:0]\n\t 254:reg_data<=24'h382047; // flip\n\t 255:reg_data<=24'h382100;//07; // mirror\n\t 256:reg_data<=24'h381431; // timing X inc\n\t 257:reg_data<=24'h381531; // timing Y inc\n\t 258:reg_data<=24'h380000; // HS\n\t 259:reg_data<=24'h380100; // HS\n \n\t 260:reg_data<=24'h380200; // VS\n\t 261:reg_data<=24'h380300;//fa; // VS\n\t 262:reg_data<=24'h38040a; // HW (HE)\n\t 263:reg_data<=24'h38053f; // HW (HE)\n\t 264:reg_data<=24'h380607;//06; // VH (VE)\n\t 265:reg_data<=24'h38079f;//a9; // VH (VE)\n\t 266:reg_data<=24'h380801; //320\n\t 267:reg_data<=24'h380940;\n\t 268:reg_data<=24'h380a00; //240\n\t 269:reg_data<=24'h380bf0;\n \n \n\t 270:reg_data<=24'h380c0c;//07; // HTS\n\t 271:reg_data<=24'h380d80;//64; // HTS\n\t 272:reg_data<=24'h380e07;//02; // VTS\n\t 273:reg_data<=24'h380fd0;//e4; // VTS\n\t 274:reg_data<=24'h381300;//04; // timing V offset\n\t 275:reg_data<=24'h361800;\n\t 276:reg_data<=24'h361229;\n\t 277:reg_data<=24'h370952;\n\t 278:reg_data<=24'h370c03;\n\t 279:reg_data<=24'h3a0202; // 60Hz max exposure\n \n \n\t 280:reg_data<=24'h3a03e0; // 60Hz max exposure\n\t 281:reg_data<=24'h3a0800; // B50 step\n\t 282:reg_data<=24'h3a096f; // B50 step\n\t 283:reg_data<=24'h3a0a00; // B60 step\n\t 284:reg_data<=24'h3a0b5c; // B60 step\n\t 285:reg_data<=24'h3a0e06; // 50Hz max band\n\t 286:reg_data<=24'h3a0d08; // 60Hz max band\n\t 287:reg_data<=24'h3a1402; // 50Hz max exposure\n\t 288:reg_data<=24'h3a15e0; // 50Hz max exposure\n\t 289:reg_data<=24'h400402; // BLC line number\n \n\t 290:reg_data<=24'h30021c; // reset JFIFO, SFIFO, JPG\n\t 291:reg_data<=24'h3006c3; // disable clock of JPEG2x, JPEG\n\t 292:reg_data<=24'h471303; // JPEG mode 3\n\t 293:reg_data<=24'h440704; // Quantization sacle\n\t 294:reg_data<=24'h460b37;\n\t 295:reg_data<=24'h460c20;\n\t 296:reg_data<=24'h483716; // MIPI global timing\n\t 297:reg_data<=24'h382404; // PCLK manual divider\n\t 298:reg_data<=24'h5001a3;//83; // SDE on, CMX on, AWB on\n\t 299:reg_data<=24'h350300; // AEC/AGC on \n\t 300:reg_data<=24'h301602; //Strobe output enable\n\t 301:reg_data<=24'h3b070a; //FREX strobe mode1\t\n\t //strobe flash and frame exposure \t \n//\t 302:reg_data<=24'h3b0083; //STROBE CTRL: strobe request ON, Strobe mode: LED3 \n//\t 303:reg_data<=24'h3b0000; //STROBE CTRL: strobe request OFF \n\t \n\t302:reg_data<=24'h503d80; //reg_data<=24'h503d80; test pattern selection control, 80:color bar,00: test disable\n\t303:reg_data<=24'h474101; //reg_data<=24'h47401; test pattern enable, Test pattern 8-bit\t \n\t default:reg_data<=24'h000000;\n endcase \nend\t \n\n\n\nendmodule\n\n" }, { "path": "verilog/CAMERA/sdram_ov5640_vga.v", "content": "/*-------------------------------------------------------------------------\nFilename\t\t\t:\t\tsdram_ov5640_vga.v\nDescription\t\t\t:\t\tsdram vga controller with ov5640 display 1024 * 768.\nModification History\t:\nData\t\t\tBy\t\t\tVersion\t\t\tChange Description\n===========================================================================\n15/02/1\n--------------------------------------------------------------------------*/\n`timescale 1ns / 1ps\nmodule ov5640\n(\n\t//global clock 50MHz\n\tinput\t\t\tCLOCK,\t\n\tinput\t\t\trst_n, //global reset\n\t\n\t/*//sdram control\n\toutput\t\t\tS_CLK,\t\t//sdram clock\n\toutput\t\t\tS_CKE,\t\t//sdram clock enable\n\toutput\t\t\tS_NCS,\t\t//sdram chip select\n\toutput\t\t\tS_NWE,\t\t//sdram write enable\n\toutput\t\t\tS_NCAS,\t //sdram column address strobe\n\toutput\t\t\tS_NRAS,\t //sdram row address strobe\n\toutput [1 :0] \t S_DQM,\t\t//sdram data enable \n\toutput\t[1 :0]\t S_BA,\t\t//sdram bank address\n\toutput\t[12:0]\t S_A,\t\t//sdram address\n\tinout\t[15:0]\t S_DB,\t\t//sdram data\n\t\n\t//VGA port\t\t\t\n\toutput\t\t\tVGA_HSYNC, //horizontal sync \n\toutput\t\t\tVGA_VSYNC, //vertical sync\n\toutput\t[15:0]\tlcd_rgb,\t\t//VGA data*/\n\t\n\t//cmos interface\n\toutput\t\t\tCMOS_SCLK,\t//cmos i2c clock\n\tinout\t\t\tCMOS_SDAT,\t//cmos i2c data\n\tinput\t\t\tCMOS_VSYNC,\t//cmos vsync\n\tinput\t\t\tCMOS_HREF,\t//cmos hsync refrence\n\tinput\t\t\tCMOS_PCLK,\t//cmos pxiel clock\n\toutput\t\t\tCMOS_XCLK,\t//cmos externl clock\n\tinput\t[7:0]\t CMOS_DB,\t//cmos data\n\toutput\t\t\tcmos_rst_n,\t//cmos reset\n\toutput\t\t\tcmos_pwdn,\t//cmos pwer down\n\t\n\toutput\t\tsys_we,\t\t\t//system data write enable\n\toutput\t[15:0] sys_data_in, //system data input\n\toutput\t\t\tframe_valid,\t\t//data valid, or address restart\n\n input KEY1, //KEY1 input\n\toutput\t[3:0]\t LED,\t\t//led data input\t\n\tinput clk24\n);\n\n//---------------------------------------------\nwire clk_vga;\t\t//vga clock\nwire clk_ref;\t\t//sdram ctrl clock\nwire clk_refout;\t\t//sdram clock output\nwire clk_25M;\n \nwire sys_rst_n;\t\t//global reset\n \nwire\t\t\tsdram_init_done; //sdram init done\n\n\nsystem_ctrl\tu_system_ctrl\n(\n\t.clk\t\t\t\t(CLOCK), //global clock 50MHZ\n\t.rst_n\t\t\t\t(rst_n), //external reset\n\t\n\t.sys_rst_n\t\t\t(sys_rst_n),\t//global reset\n\t.clk_c1\t\t\t\t(CLOCK)\n\n);\n \n\nwire initial_en; \nwire Config_Done;\n \n //�ϵ��ӳٲ���\npower_on_delay\tpower_on_delay_inst(\n\t.clk_50M (clk24),\n\t.reset_n (sys_rst_n),\t\n\t.camera_rstn (cmos_rst_n),\n\t.camera_pwnd (cmos_pwdn),\n\t.initial_en (initial_en)\t\t\n);\n\n//Camera��ʼ������,Camera LED FLASH control\nreg_config\treg_config_inst(\n\t.clk_25M (clk24),\n\t.camera_rstn (cmos_rst_n),\n\t.initial_en (initial_en),\t\t\n\t.i2c_sclk (CMOS_SCLK),\n\t.i2c_sdat (CMOS_SDAT),\n\t.reg_conf_done (Config_Done),\n\t.strobe_flash (),\n\t.reg_index (),\n\t.clock_20k (),\n\t.key1 (KEY1)\n);\n \n//----------------------------------------------- \nwire\t[7:0] cmos_fps_data;\t\t//cmos frame rate\nCMOS_Capture\tu_CMOS_Capture\n(\n\t//Global Clock\n\t.iCLK\t\t\t\t(clk24),\t\t//24MHz\n\t.iRST_N\t\t\t\t(sys_rst_n),\t//global reset\n\t\n\t//I2C Initilize Done\n\t.Init_Done\t\t\t(Config_Done /*& sdram_init_done*/),\t//Init Done\n\t\n\t//Sensor Interface\n\t.CMOS_XCLK\t\t\t(CMOS_XCLK),\t\t//cmos\n\t.CMOS_PCLK\t\t\t(CMOS_PCLK),\t\t//24MHz\n\t.CMOS_iDATA\t\t\t(CMOS_DB), \t//CMOS Data\n\t.CMOS_VSYNC\t\t\t(CMOS_VSYNC), \t \t//L: Vaild\n\t.CMOS_HREF\t\t\t(CMOS_HREF), \t\t//H: Vaild\n\t \n\t//Ouput Sensor Data \n\t.CMOS_oCLK\t\t\t(sys_we),\t\t\t//Data PCLK\n\t.CMOS_oDATA\t\t\t(sys_data_in), \t//16Bits RGB\n\t.CMOS_VALID\t\t\t(frame_valid),\t\t//Data Enable\n\t.CMOS_FPS_DATA\t\t ()//(cmos_fps_data)\t\t//cmos frame rate\n);\n\n\n\nendmodule\n" }, { "path": "verilog/CAMERA/system_ctrl.v", "content": "/*-------------------------------------------------------------------------\nDescription\t\t\t:\t\tsdram vga controller with ov7670 display.\n===========================================================================\n15/02/1\n--------------------------------------------------------------------------*/\n`timescale 1 ns / 1 ns\nmodule system_ctrl\n(\n\tinput \t\tclk,\t\t//50MHz\n\tinput \t\trst_n,\t\t//global reset\n\n\toutput \t\tsys_rst_n,\t//system reset\t\t\n\tinput \t\tclk_c1,\n\toutput\t\tclk_c2,\t//-75deg\n\toutput\t\tclk_c3\t//-75deg\n\n);\n\n//----------------------------------------------\nreg [9:0] delay_cnt;\nreg delay_done;\nalways @(posedge clk_c1 or negedge rst_n)\nbegin\n\tif(!rst_n)\n\t\tbegin\n\t\tdelay_cnt <= 0;\n\t\tdelay_done <= 1'b0;\n\t\tend\n\telse\n\t\tbegin\n\t\t if (delay_cnt== 1000)\n\t\t\t delay_done <= 1'b1;\n else\n delay_cnt <= delay_cnt +1'b1;\n\t\tend\nend\n\nassign sys_rst_n=delay_done;\n//----------------------------------------------\n//Component instantiation\nwire clk_50;\nwire clk_c2_oddr,clk_c0_oddr;\t\n\n\n/*\nODDR2 #(\n .DDR_ALIGNMENT(\"NONE\"), // Sets output alignment to \"NONE\", \"C0\" or \"C1\" \n .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1\n .SRTYPE(\"SYNC\") // Specifies \"SYNC\" or \"ASYNC\" set/reset\n ) U_ODDR2_c2\n(\n .Q(clk_c2), // 1-bit DDR output data\n .C0(clk_c2_oddr), // 1-bit clock input\n .C1(~clk_c2_oddr), // 1-bit clock input\n .CE(1'b1), // 1-bit clock enable input\n .D0(1'b1), // 1-bit data input (associated with C0)\n .D1(1'b0), // 1-bit data input (associated with C1)\n .R(1'b0), // 1-bit reset input\n .S(1'b0) // 1-bit set input\n);*/\n\n/*\nODDR2 #(\n .DDR_ALIGNMENT(\"NONE\"), // Sets output alignment to \"NONE\", \"C0\" or \"C1\" \n .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1\n .SRTYPE(\"SYNC\") // Specifies \"SYNC\" or \"ASYNC\" set/reset\n ) U_ODDR2_c0\n(\n .Q(clk_c0), // 1-bit DDR output data\n .C0(clk_c0_oddr), // 1-bit clock input\n .C1(~clk_c0_oddr), // 1-bit clock input\n .CE(1'b1), // 1-bit clock enable input\n .D0(1'b1), // 1-bit data input (associated with C0)\n .D1(1'b0), // 1-bit data input (associated with C1)\n .R(1'b0), // 1-bit reset input\n .S(1'b0) // 1-bit set input\n);\n*/\n\nendmodule\n" }, { "path": "verilog/GENERAL.qsf", "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 2018 Intel Corporation. All rights reserved.\n# Your use of Intel Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Intel Program License \n# Subscription Agreement, the Intel Quartus Prime License Agreement,\n# the Intel FPGA IP License Agreement, or other applicable license\n# agreement, including, without limitation, that your use is for\n# the sole purpose of programming logic devices manufactured by\n# Intel and sold by Intel or its authorized distributors. Please\n# refer to the applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus Prime\n# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition\n# Date created = 15:25:52 July 27, 2019\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\tGENERAL_assignment_defaults.qdf\n# If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n# file is updated automatically by the Quartus Prime software\n# and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone V\"\nset_global_assignment -name DEVICE 5CGXFC9D6F27C7\nset_global_assignment -name TOP_LEVEL_ENTITY GENERAL\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"15:25:52 JULY 27, 2019\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"18.0.0 Lite Edition\"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CLOCK_50\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to KEY[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to KEY[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to KEY[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to KEY[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to KEY\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to LED[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to LED[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to LED[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to LED[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to LED\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to UART_CTS\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to UART_RTS\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to UART_RX\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to UART_TX\nset_location_assignment PIN_W25 -to UART_CTS\nset_location_assignment PIN_W26 -to UART_RTS\nset_location_assignment PIN_P22 -to UART_RX\nset_location_assignment PIN_P21 -to UART_TX\nset_location_assignment PIN_U20 -to LED[0]\nset_location_assignment PIN_T19 -to LED[1]\nset_location_assignment PIN_Y24 -to LED[2]\nset_location_assignment PIN_Y23 -to LED[3]\nset_location_assignment PIN_M21 -to KEY[0]\nset_location_assignment PIN_K25 -to KEY[1]\nset_location_assignment PIN_K26 -to KEY[2]\nset_location_assignment PIN_G26 -to KEY[3]\nset_location_assignment PIN_R20 -to CLOCK_50\nset_location_assignment PIN_T8 -to HEX0[0]\nset_location_assignment PIN_P26 -to HEX0[1]\nset_location_assignment PIN_V8 -to HEX0[2]\nset_location_assignment PIN_U7 -to HEX0[3]\nset_location_assignment PIN_U25 -to HEX0[4]\nset_location_assignment PIN_W8 -to HEX0[5]\nset_location_assignment PIN_U26 -to HEX0[6]\nset_location_assignment PIN_N25 -to HEX1[6]\nset_location_assignment PIN_W21 -to HEX1[5]\nset_location_assignment PIN_Y9 -to HEX1[4]\nset_location_assignment PIN_AC22 -to HEX1[3]\nset_location_assignment PIN_AB6 -to HEX1[2]\nset_location_assignment PIN_W20 -to HEX1[1]\nset_location_assignment PIN_T7 -to HEX1[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX0\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to HEX1\nset_location_assignment PIN_H14 -to tft_sdo\nset_location_assignment PIN_G17 -to tft_sck\nset_location_assignment PIN_J12 -to tft_dc\nset_location_assignment PIN_C20 -to tft_reset\nset_location_assignment PIN_J11 -to tft_sdi\nset_location_assignment PIN_B19 -to tft_cs\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_sdo\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_sdi\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_sck\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_dc\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to cmos_rst_n\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_reset\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to tft_cs\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to cmos_pwdn\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_XCLK\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_VSYNC\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_SDAT\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_SCLK\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_PCLK\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_HREF\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to CMOS_DB\nset_location_assignment PIN_C14 -to CMOS_SCLK\nset_location_assignment PIN_B15 -to CMOS_SDAT\nset_location_assignment PIN_D15 -to CMOS_PCLK\nset_location_assignment PIN_C15 -to CMOS_VSYNC\nset_location_assignment PIN_D21 -to CMOS_DB[3]\nset_location_assignment PIN_A19 -to CMOS_DB[2]\nset_location_assignment PIN_D20 -to CMOS_DB[7]\nset_location_assignment PIN_A18 -to CMOS_DB[6]\nset_location_assignment PIN_E20 -to CMOS_XCLK\nset_location_assignment PIN_B22 -to CMOS_HREF\nset_location_assignment PIN_E19 -to CMOS_DB[0]\nset_location_assignment PIN_A21 -to CMOS_DB[4]\nset_location_assignment PIN_E18 -to CMOS_DB[5]\nset_location_assignment PIN_C23 -to CMOS_DB[1]\nset_location_assignment PIN_F18 -to cmos_rst_n\nset_location_assignment PIN_C22 -to cmos_pwdn\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/TOP.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/result.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/RAMtoMEM.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/RAM.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/dense.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/conv_TOP.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/conv.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/border.v\nset_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/addressRAM.v\nset_global_assignment -name VERILOG_FILE scale_picture.v\nset_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/reg_config.v\nset_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/power_on_delay.v\nset_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/ov5640_cfg.v\nset_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/i2c_com.v\nset_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/CMOS_Capture.v\nset_global_assignment -name VERILOG_FILE UART/serialGPIO.v\nset_global_assignment -name VERILOG_FILE UART/async.v\nset_global_assignment -name VERILOG_FILE GENERAL.v\nset_global_assignment -name VERILOG_FILE RAM.v\nset_global_assignment -name VERILOG_FILE Seg7.v\nset_global_assignment -name VERILOG_FILE CAMERA/system_ctrl.v\nset_global_assignment -name VERILOG_FILE CAMERA/sdram_ov5640_vga.v\nset_global_assignment -name SYSTEMVERILOG_FILE ili9341/tft_ili9341_spi.sv\nset_global_assignment -name SYSTEMVERILOG_FILE ili9341/tft_ili9341.sv\nset_global_assignment -name QIP_FILE pll_24_100.qip\nset_global_assignment -name SIP_FILE pll_24_100.sip\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top" }, { "path": "verilog/GENERAL.v", "content": "module GENERAL(\ninput CLOCK_50,\n\n//////////// ILI9341 //////////////\n\ninput \t\t\t\t\t\t\ttft_sdo, \noutput \t\t\t\t\t\t\ttft_sck, \noutput\t\t\t\t\t\t\ttft_sdi, \noutput\t\t\t\t\t\t\ttft_dc, \noutput\t\t\t\t\t\t\ttft_reset, \noutput\t\t\t\t\t\t\ttft_cs,\n\n//////////// CAMERA ///////////\noutput\t\t\tCMOS_SCLK,\t//cmos i2c clock\ninout\t\t\t\tCMOS_SDAT,\t//cmos i2c data\ninput\t\t\t\tCMOS_VSYNC,\t//cmos vsync\ninput\t\t\t\tCMOS_HREF,\t//cmos hsync refrence\ninput\t\t\t\tCMOS_PCLK,\t//cmos pxiel clock\noutput\t\t\tCMOS_XCLK,\t//cmos externl clock\ninput\t[7:0]\t CMOS_DB,\t\t//cmos data\noutput\t\t\tcmos_rst_n,\t//cmos reset\noutput\t\t\tcmos_pwdn,\t//cmos pwer down\n\ninput UART_RX,\noutput UART_TX,\ninput UART_CTS,\noutput UART_RTS,\n\noutput\t\t [6:0]\t\tHEX0,\noutput\t\t [6:0]\t\tHEX1,\n\ninput [3:0] KEY,\noutput [3:0] LED\n);\n\nwire [7:0] step;\n\nreg [15:0] x;\nwire [15:0] data_camera,currentPixel;\nreg [9:0] x_tft,y_tft,x_in,y_in,x_neuro_image,y_neuro_image;\nreg enable_image;\n\n//neuroset\nreg GO_neuroset,start_neuroset;\nreg [1:0] RESULT;\nreg [2:0] step_image;\n//scale_image\nwire [7:0] r_out_scale,g_out_scale,b_out_scale;\nwire [16:0] addr_out_scale;\nwire signed [12:0] r_out_scale_13,g_out_scale_13,b_out_scale_13;\nwire [15:0] ram_data;\nwire valid_data_out_scale;\nwire [18:0] addr_tft;\n//scale_image\nreg new_go,new_image,sh,sh_1,da;\nwire [18:0] addr_new_image;\nwire [23:0] data_scale_ram;\n\nwire [3:0] RESULT_neuroset;\nreg [3:0] res;\nwire [20:0] test1;\nwire [20:0] test2;\nwire\ttest2_en;\nwire signed [20:0] data_in_weights;\nwire signed [20:0] data_out_weights;\nreg signed [20:0] delete;\nreg delete2,delete3;\nwire [23:0] address_in_weights;\nwire [23:0] address_out_weights;\nwire [11:0] address_out_bias;\n\nreg clk25;\nwire clk100;\nreg [1:0] pre_button;\nreg trigger;\nreg start_wr;\n\nreg [1:0] sh_result;\nreg RESULT_0,RESULT_1,RESULT_2;\n// / //////////////////////////////////////////////\n// reset_n and start_n control\nreg [31:0] cont;\nalways@(posedge CLOCK_50)\ncont<=(cont==32'd4_000_001)?32'd0:cont+1'b1;\n\nreg[4:0] sample;\nalways@(posedge CLOCK_50)\nbegin\n\tif(cont==32'd4_000_000)\n\t\tsample[4:0]={sample[3:0],KEY[0] || KEY[3]};\n\telse \n\t\tsample[4:0]=sample[4:0];\nend\n\nassign test_software_reset_n=(sample[1:0]==2'b10)?1'b0:1'b1;\nassign test_global_reset_n =(sample[3:2]==2'b10)?1'b0:1'b1;\nassign test_start_n =(sample[4:3]==2'b01)?1'b0:1'b1;\n\n//////////////////////////////////////////////////\npll_24_100 pll_24_100\n(\n\t.refclk\t(CLOCK_50),\n\t.rst\t\t(1'b0/*~rst_n*/),\n\t.locked\t(),\n\t\t\t\n\t.outclk_0 (clk24), //24Mhz\n\t.outclk_1 (clk100), //100Mhz\n\t.outclk_2\t\t(clk60)\n\n);\n\nalways @(posedge CLOCK_50 or negedge KEY[0]) \nif (!KEY[0]) \n\tbegin\n\t\tclk25=0;\n\t\tpre_button <= 2'b11;\n\t\ttrigger <= 1'b0;\n\tend\nelse \n\tbegin\n\t\tclk25=!clk25;\n\t\tpre_button <= {pre_button[0], test_start_n};\n\t\ttrigger <= !pre_button[0] && pre_button[1];\n\t\tif (trigger) start_wr=1;\n\tend\n\nov5640 ov5640\n(\n\t.CLOCK\t\t\t(CLOCK_50),\t\n\t.rst_n\t\t\t(KEY[0]), \n\t.clk24\t\t\t(clk24),\n\t\n\t.CMOS_SCLK\t\t(CMOS_SCLK),\t//cmos i2c clock\n\t.CMOS_SDAT\t\t(CMOS_SDAT),\t//cmos i2c data\n\t.CMOS_VSYNC\t\t(CMOS_VSYNC),\t//cmos vsync\n\t.CMOS_HREF\t\t(CMOS_HREF),\t//cmos hsync refrence\n\t.CMOS_PCLK\t\t(CMOS_PCLK),\t//cmos pxiel clock\n\t.CMOS_XCLK\t\t(CMOS_XCLK),\t//cmos externl clock\n\t.CMOS_DB\t\t\t(CMOS_DB),\t//cmos data\n\t.cmos_rst_n\t\t(cmos_rst_n),\t//cmos reset\n\t.cmos_pwdn\t\t(cmos_pwdn),\t//cmos pwer down\n\t\n\t.sys_we\t\t\t(clk_camera),\t\t\t//system data write enable\n\t.sys_data_in\t(data_camera), //system data input\n\t.frame_valid\t(valid_data_camera)\t//data valid, or address restart\n);\nalways @(posedge CMOS_PCLK or negedge KEY[0])\n\tbegin\n\t\tif (!KEY[0])\t\n\t\t\tbegin\n\t\t\t\tnew_go=0;\n\t\t\t\tnew_image=0;\n\t\t\t\tx_in=0;\n\t\t\t\ty_in=0;\n\t\t\t\tsh=0;\n\t\t\t\tsh_1=0;\n\t\t\t\tda=0;\n\t\t\tend\n\t\telse\t\n\t\tbegin\n\t\tif ((!GO_neuroset) && da) sh=sh+1;\n\t\tda=GO_neuroset;\n\t\tif (((new_image==0)&&(new_go==0)&&(!GO_neuroset)&&(sh_1!=sh))) \n\t\t\tbegin\n\t\t\t\tnew_go = 1'b1;\n\t\t\t\tsh_1=sh;\n\t\t\tend\n\t\tif ((new_image==0)&&(new_go==1)&&(x_in==0)&&(y_in==0)) \n\t\t\tbegin\n\t\t\t\tnew_go = 0;\n\t\t\t\tnew_image = 1;\n\t\t\tend\n\t\tif ((clk_camera)&&(valid_data_camera)) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tif (x_in < (320-1)) x_in = x_in+1'b1;\n\t\t\t\t\t\telse \n\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\tx_in = 0;\n\t\t\t\t\t\t\t\tif (y_in < 240-1) y_in = y_in+1'b1;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\ty_in=0;\n\t\t\t\t\t\t\t\t\t\tnew_image=0;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\tif (!valid_data_camera) \n\t\t\tbegin\n\t\t\t\tx_in=0;\n\t\t\tend\n\t\tend\nend\nassign addr_new_image=x_in+y_in*320;\n\ntft_ili9341 #(.INPUT_CLK_MHZ(100)) tft(\n\t.clk\t\t\t\t\t(clk100), \n\t.tft_sdo\t\t\t\t(tft_sdo), \n\t.tft_sck\t\t\t\t(tft_sck), \n\t.tft_sdi\t\t\t\t(tft_sdi), \n\t.tft_dc\t\t\t\t(tft_dc), \n\t.tft_reset\t\t\t(tft_reset), \n\t.tft_cs\t\t\t\t(tft_cs), \n\t.framebufferData\t(((x_tft<20)&&(y_tft<20))?(RESULT[0]?16'b1110000000000:16'b100):{currentPixel[7],currentPixel[6],currentPixel[5],currentPixel[4],currentPixel[3],currentPixel[2],currentPixel[1],currentPixel[0],currentPixel[15],currentPixel[14],currentPixel[13],currentPixel[12],currentPixel[11],currentPixel[10],currentPixel[9],currentPixel[8]}), \n\t.framebufferClk\t(fbClk)\n);\n\nalways @(posedge fbClk or negedge KEY[0])\n\tif (!KEY[0])\n\t\tbegin\n\t\t\tx_tft=0;\n\t\t\ty_tft=0;\n\t\tend\n\telse\n\t\tbegin\n\t\t\tif (x_tft<319) x_tft=x_tft+1;\n\t\t\telse\n\t\t\t\tbegin\n\t\t\t\t\tx_tft=0;\n\t\t\t\t\tif (y_tft<239) y_tft=y_tft+1;\n\t\t\t\t\telse y_tft=0;\n\t\t\t\tend\n\t\tend\n\t\t\nalways @(posedge CLOCK_50 or negedge KEY[0])\n\tif (!KEY[0])\n\t\tbegin\n\t\t\tx_neuro_image=0;\n\t\t\ty_neuro_image=0;\n\t\tend\n\telse\n\t\tbegin\n\t\t\tif (GO_neuroset)\n\t\t\t\tbegin\n\t\t\t\t\tif (x_neuro_image<128-1) x_neuro_image=x_neuro_image+1;\n\t\t\t\t\telse\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tx_neuro_image=0;\n\t\t\t\t\t\t\tif (y_neuro_image<128-1) y_neuro_image=y_neuro_image+1;\n\t\t\t\t\t\t\telse y_neuro_image=0;\n\t\t\t\t\t\tend\n\t\t\t\tend\n\t\tend\n\t\t\nalways @(posedge CLOCK_50 or negedge KEY[0])\n\tbegin\n\t\tif (!KEY[0])\n\t\t\tbegin\n\t\t\t\tstart_neuroset = 0;\n\t\t\t\tGO_neuroset = 0;\n\t\t\t\tstep_image = 0;\n\t\t\t\tRESULT = 0;\n\t\t\tend\n\t\telse\n\t\t\tbegin\n\t\t\t\tif (STOP_neuroset) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tstep_image = 1;\n\t\t\t\t\t\tif (sh_result<2) sh_result = sh_result+1'b1;\n\t\t\t\t\t\telse sh_result=0;\n\t\t\t\t\t\tif (sh==0) RESULT_0 = RESULT_neuroset[1:0];\n\t\t\t\t\t\tif (sh==1) RESULT_1 = RESULT_neuroset[1:0];\n\t\t\t\t\t\tif (sh==2) RESULT_2 = RESULT_neuroset[1:0];\n\t\t\t\t\t\tif (sh_result==0) \n\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\tif (RESULT_0==RESULT_1) RESULT = RESULT_0;\n\t\t\t\t\t\t\t\telse if (RESULT_0==RESULT_2) RESULT = RESULT_0;\n\t\t\t\t\t\t\t\telse if (RESULT_1==RESULT_2) RESULT = RESULT_1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tif (UART_stop) start_neuroset = 1;\n\t\t\t\tif ((start_neuroset)&&(step_image<4))\n\t\t\t\t\tbegin\n\t\t\t\t\t\tif ((y_neuro_image*128+x_neuro_image) == 0) step_image = step_image + 1;\n\t\t\t\t\t\tGO_neuroset = 1;\n\t\t\t\t\tend\n\t\t\t\telse \n\t\t\t\t\tGO_neuroset = 0;\n\t\t\tend\n\tend\nassign addr_tft = x_tft + y_tft*320;\n\nserialGPIO(\n .clk25\t\t(clk25),\n .RxD\t\t\t(UART_RX),\n .TxD\t\t\t(UART_TX),\n\t .reset\t\t(KEY[0]),\n\t \n\t .address\t(address_in_weights),\n\t .data\t\t(data_in_weights),\n\t .write_enable\t(we_weights),\n\t .start\t\t(UART_start),\n\t .stop\t\t(UART_stop),\n\t \n\t .data_tx\t(test2[15:8]),\n\t .enable_tx\t(test2_en && delete2)\n);\n\nscale_picture scale_picture(\n\t.clk\t\t\t\t\t(fbClk),\n\t.rst\t\t\t\t\t(KEY[0]),\n\t.valid_data\t\t\t(1), \n\t.r\t\t\t\t\t\t({currentPixel[4],currentPixel[3],currentPixel[2],currentPixel[1],currentPixel[0],1'b0,1'b0,1'b0}),\n\t.g\t\t\t\t\t\t({currentPixel[10],currentPixel[9],currentPixel[8],currentPixel[7],currentPixel[6],currentPixel[5],1'b0,1'b0}),\n\t.b\t\t\t\t\t\t({currentPixel[15],currentPixel[14],currentPixel[13],currentPixel[12],currentPixel[11],1'b0,1'b0,1'b0}),\n\t.x\t\t\t\t\t\t(x_tft),\n\t.y\t\t\t\t\t\t(y_tft), \n\t.r_out\t\t\t\t(r_out_scale),\n\t.g_out\t\t\t\t(g_out_scale),\n\t.b_out\t\t\t\t(b_out_scale),\n\t.addr_out\t\t\t(addr_out_scale),\n\t.valid_data_out\t(valid_data_out_scale)\n);\n\t\t\nassign r_out_scale_13 = (data_scale_ram[23:16]*2 - 255)*16;\nassign g_out_scale_13 = (data_scale_ram[15:8]*2 - 255)*16;\nassign b_out_scale_13 = (data_scale_ram[7:0]*2 - 255)*16;\n\n\nTOP neuroset(\n.clk\t\t\t\t\t(CLOCK_50),\n.clk_RAM_w\t\t\t(CLOCK_50), \n.clk_RAM_p\t\t\t(CLOCK_50), \n.GO\t\t\t\t\t(GO_neuroset),\n.RESULT\t\t\t\t(RESULT_neuroset),\n.STOP\t\t\t\t\t(STOP_neuroset),\n\n.re_weights\t\t\t(re_weights),\n.load_weights\t\t(re_weights && (!GO_neuroset)), \n.dp_weights\t\t\t(data_out_weights),\n.address_weights\t(address_out_weights),\n\n.re_bias\t\t\t\t(re_bias),\n.load_bias\t\t\t(re_bias),\n.dp_bias\t\t\t\t(data_out_weights),\n.address_bias\t\t(address_out_bias),\n\n.we_image\t\t\t(GO_neuroset),\n.dp_image\t\t\t((step_image==1)?(b_out_scale_13):((step_image==2)?(g_out_scale_13):((step_image==3)?(r_out_scale_13):0))), \n.address_image\t\t((x_neuro_image+y_neuro_image*128)+((step_image-1)*128*128)),\n\n.step\t\t\t\t\t(step)/*,\n.test1\t\t\t\t(test1),\n.test2\t\t\t\t(test2),\n.test2_en\t\t\t(test2_en)*/\n);\n\nRAM_general RAM_general(\n.clk_in (clk25),\n.clk_out (CLOCK_50),\n.clk_in_im (CMOS_PCLK),\n.clk_out_im (fbClk),\n.clk_in_im_scale (fbClk),\n.clk_out_im_scale (CLOCK_50),\n\n.data_in_im (data_camera),\n.data_out_im (currentPixel),\n.address_in_im (addr_new_image),\n.address_out_im (addr_tft),\n.we_image ((new_image)&&(clk_camera)&&(valid_data_camera)),\n.re_image (1),\n\n.data_in_im_scale ({r_out_scale,g_out_scale,b_out_scale}),\n.data_out_im_scale (data_scale_ram),\n.address_in_im_scale (addr_out_scale),\n.address_out_im_scale (x_neuro_image+y_neuro_image*128),\n.we_image_scale (valid_data_out_scale),\n.re_image_scale (GO_neuroset),\n\n.data_in_weights (data_in_weights),\n.data_out_weights (data_out_weights),\n.address_in_weights (address_in_weights),\n.address_out_weights ((re_weights)?address_out_weights:(208115 + address_out_bias)),\n.we_weights (we_weights),\n.re_weights\t((re_weights && (!GO_neuroset)) || re_bias),\n\n);\n\nreg [31:0] sh_cadr,res_sh_cadr;\nreg wait_cadr;\nreg [2:0] sh_show;\n\nassign LED[3] = new_image;\nassign LED[2] = sh;\nassign LED[1] = sh_1;\nassign LED[0] = sh_show[0];\n\nalways @(posedge CLOCK_50 or negedge KEY[0])\nif (!KEY[0])\n\tbegin\n\t\twait_cadr=0;\n\t\tsh_cadr=0;\n\t\tres_sh_cadr=0;\n\tend\nelse\n\tbegin\n\t\tif (GO_neuroset && (!STOP_neuroset) && (!wait_cadr)) \n\t\t\tbegin\n\t\t\t\tsh_cadr=0;\n\t\t\t\twait_cadr=1;\n\t\t\tend\n\t\telse sh_cadr=sh_cadr+1;\n\t\tif (/*!GO_neuroset*/STOP_neuroset && wait_cadr) \n\t\t\tbegin\n\t\t\t\tres_sh_cadr=sh_cadr;\n\t\t\t\twait_cadr=0;\n\t\t\tend\n\tend\n\t\nalways @(negedge KEY[3] or negedge KEY[0])\nif (!KEY[0])\tsh_show=0;\nelse\tif (sh_show<3) sh_show=sh_show+1;\n\t\telse sh_show=0;\n\nSeg7 seg7_0(\n\t.data\t\t(((sh_show==0)?res_sh_cadr[3:0]:((sh_show==1)?res_sh_cadr[11:8]:((sh_show==2)?res_sh_cadr[19:16]:((sh_show==3)?res_sh_cadr[27:24]:0))))),\n\t.hex\t\t(HEX0)\n);\n\nSeg7 seg7_1(\n\t.data\t\t(((sh_show==0)?res_sh_cadr[7:4]:((sh_show==1)?res_sh_cadr[15:12]:((sh_show==2)?res_sh_cadr[23:20]:((sh_show==3)?res_sh_cadr[31:28]:0))))),\n\t.hex\t\t(HEX1)\n);\n\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/RAM.v", "content": "module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk,clk_RAM_w,q_bias,d_bias,we_bias,re_bias,write_address_bias,read_address_bias);\nparameter picture_size=0;\t\nparameter SIZE_1=0;\nparameter SIZE_2=0;\nparameter SIZE_3=0;\nparameter SIZE_4=0;\nparameter SIZE_5=0;\nparameter SIZE_6=0;\nparameter SIZE_7=0;\nparameter SIZE_8=0;\nparameter SIZE_address_pix=13;\nparameter SIZE_address_pix_t=12;\nparameter SIZE_address_wei=13;\nparameter SIZE_address_image=16;\nparameter SIZE_weights=0;\nparameter SIZE_bias=0;\n\noutput reg signed [SIZE_8-1:0] qp; //read data\noutput reg signed [32*8-1:0] qtp; //read data\noutput reg signed [SIZE_weights*9-1:0] qw; //read weight\noutput reg signed [SIZE_bias-1:0] q_bias;\ninput signed [SIZE_1*8-1:0] dp; //write data\ninput signed [32*8-1:0] dtp; //write data\ninput signed [SIZE_weights*9-1:0] dw; //write weight\ninput signed [SIZE_bias-1:0] d_bias;\ninput [SIZE_address_pix-1:0] write_addressp, read_addressp;\ninput [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;\ninput [SIZE_address_wei-1:0] write_addressw, read_addressw;\ninput [10:0] write_address_bias,read_address_bias;\ninput we_p;\ninput we_tp;\ninput we_w;\ninput we_bias;\ninput re_p;\ninput re_tp;\ninput re_w;\ninput re_bias;\ninput clk,clk_RAM_w;\n\nreg signed [SIZE_1*8-1:0] mem [0:128*128*1+4096*2-1];\nreg signed [32*8-1:0] mem_t [0:4096-1];\nreg signed [SIZE_weights*9-1:0] weight [0:4095]; \nreg signed [SIZE_bias-1:0] mem_bias [0:256];\nalways @ (posedge clk) \n begin\n if (we_p) mem[write_addressp] <= dp;\n\t\tif (we_tp) mem_t[write_addresstp] <= dtp;\n end\nalways @ (posedge clk_RAM_w)\n\tbegin\n\t\tif (we_w) weight[write_addressw] <= dw;\n\t\tif (we_bias) mem_bias[write_address_bias] <= d_bias;\n\tend\nalways @ (posedge clk)\n begin\n if (re_p) qp <= mem[read_addressp];\n\t\tif (re_tp)qtp <= mem_t[read_addresstp];\n if (re_w) qw <= weight[read_addressw];\n\t\tif (re_bias) q_bias <= mem_bias[read_address_bias];\n end\n\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/RAMtoMEM.v", "content": "module memorywork(clk_RAM_w,data,data_bias,address,we_w,re_weights,re_bias,nextstep,dw,addrw,step_out,GO,in_dense,load_weights,onexone,address_bias,d_bias,load_bias,we_bias,write_address_bias);\n\nparameter num_conv=0;\n\nparameter SIZE_1=0;\nparameter SIZE_2=0;\nparameter SIZE_3=0;\nparameter SIZE_4=0;\nparameter SIZE_5=0;\nparameter SIZE_6=0;\nparameter SIZE_7=0;\nparameter SIZE_8=0;\nparameter SIZE_address_pix=0;\nparameter SIZE_address_wei=0;\nparameter SIZE_weights=0;\nparameter SIZE_bias=0;\n\ninput clk_RAM_w;\ninput signed [SIZE_weights-1:0] data;\ninput signed [SIZE_bias-1:0] data_bias;\noutput [23:0] address;\noutput reg we_w;\noutput re_weights,re_bias;\ninput nextstep;\noutput reg signed [SIZE_weights*9-1:0] dw;\noutput reg [SIZE_address_wei-1:0] addrw;\noutput [6:0] step_out;\ninput GO;\ninput [8:0] in_dense;\ninput load_weights,load_bias;\n\noutput reg signed [SIZE_bias-1:0] d_bias;\noutput reg we_bias;\noutput reg [10:0] write_address_bias;\noutput [11:0] address_bias;\n\ninput onexone; \n\nreg [SIZE_address_pix-1:0] addr;\nwire [17:0] firstaddr,lastaddr;\n\nwire [18:0] razn_addr;\nassign razn_addr = lastaddr-firstaddr;\n\nreg [6:0] step;\nreg [6:0] step_n;\nreg [3:0] weight_case;\nreg [SIZE_weights*9-1:0] buff;\nreg [17:0] i;\nreg [17:0] i_d;\nreg [17:0] i1;\naddressRAM inst_1(.step(step_out),.re_weights(re_weights),.re_bias(re_bias),.firstaddr(firstaddr),.lastaddr(lastaddr)); \ninitial weight_case=0;\ninitial i=0;\ninitial i_d=0;\ninitial i1=0;\n\nalways @(negedge clk_RAM_w)\n\tif ( (step_out==1)||(step_out==2)\n\t\t||(step_out==4)||(step_out==5)\n\t\t||(step_out==7)||(step_out==8)\n\t\t||(step_out==10)||(step_out==11)\n\t\t||(step_out==13)||(step_out==14)\n\t\t||(step_out==16)||(step_out==17)\n\t\t||(step_out==19)||(step_out==20)\n\t\t||(step_out==22)||(step_out==23)\n\t\t||(step_out==25)||(step_out==26)\n\t\t||(step_out==28)||(step_out==29)\n\t\t||(step_out==31)||(step_out==32)\n\t\t||(step_out==34)||(step_out==35)\n\t\t||(step_out==37)||(step_out==38)\n\t\t||(step_out==40)||(step_out==41)\n\t\t||(step_out==43)||(step_out==44)\n\t\t||(step_out==46)||(step_out==47)\n\t\t||(step_out==49)||(step_out==50)\n\t\t||(step_out==52)||(step_out==53)\n\t\t||(step_out==55)||(step_out==56)\n\t\t||(step_out==58)||(step_out==59)\n\t\t||(step_out==61)||(step_out==62)\n\t\t||(step_out==64)||(step_out==65)\n\t\t||(step_out==67)||(step_out==68)\n\t\t||(step_out==70)||(step_out==71)\n\t\t||(step_out==73)||(step_out==74)\n\t\t||(step_out==76)||(step_out==77)\n\t\t||(step_out==79)||(step_out==80)\n\t\t||(step_out==82)||(step_out==83)\n\t\t||(step_out==85)\n\t\t)\n\tbegin\n\t\tif ((i<=razn_addr+1)&&(re_weights)) addr=i1;\n\t\tif ((i<=razn_addr+1)&&(re_bias))\taddr=i;\n\tend\n\nalways @(posedge clk_RAM_w or posedge GO)\n\tif (GO) step=1;\n\telse\n begin\n\t\t\tcase (step_out)\n\t\t\t\t8'd1,8'd4,8'd7,8'd10,8'd13,8'd16,8'd19,8'd22,8'd25,8'd28,8'd31,8'd34,8'd37,8'd40,8'd43,8'd46,8'd49,8'd52,8'd55,8'd58,8'd61,8'd64,8'd67,8'd70,8'd73,8'd76,8'd79,8'd82,8'd85:\n\t\t\t\t\tbegin\n\t\t\t\t\t\tif (i<=razn_addr+3)\n begin\n\t\t\t\t\t\t\t\t\t\twe_w=0;\n\t\t\t\t\t\t\t\t\t\taddrw=addr;\n\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1) i=i+1; \n\t\t\t\t\t\t\t\t\t\tif (step_out==85) if (i_d==((in_dense)+1)) begin dw=buff; we_w=1; weight_case=1; i_d=1; i1=i1+1; end\n\t\t\t\t\t\t\t\t\t\tcase (weight_case)\n\t\t\t\t\t\t\t\t\t\t\t0: ;\n\t\t\t\t\t\t\t\t\t\t\t1: begin buff=0; buff[SIZE_weights*9-1:SIZE_weights*8]=data[SIZE_weights-1:0]; end \n\t\t\t\t\t\t\t\t\t\t\t2: buff[SIZE_weights*8-1:SIZE_weights*7]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t3: buff[SIZE_weights*7-1:SIZE_weights*6]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t4: buff[SIZE_weights*6-1:SIZE_weights*5]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t5: buff[SIZE_weights*5-1:SIZE_weights*4]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t6: buff[SIZE_weights*4-1:SIZE_weights*3]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t7: buff[SIZE_weights*3-1:SIZE_weights*2]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t8: buff[SIZE_weights*2-1:SIZE_weights]=data[SIZE_weights-1:0]; \n\t\t\t\t\t\t\t\t\t\t\t9: begin buff[SIZE_weights-1:0]=data[SIZE_weights-1:0]; end\n\t\t\t\t\t\t\t\t\t\t\tdefault: $display(\"Check weight_case\");\n\t\t\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1) i_d=i_d+1;\n\t\t\t\t\t\t\t\t\t\tif (load_weights==1'b1)\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tif ((weight_case==9)||((onexone)&&(weight_case==8))) \n\t\t\t\t\t\t\t\t\t\t\t\t\tbegin \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tweight_case=1; \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tdw=buff; \n\t\t\t\t\t\t\t\t\t\t\t\t\t\twe_w=1; \n\t\t\t\t\t\t\t\t\t\t\t\t\t\ti1=i1+1;\n\t\t\t\t\t\t\t\t\t\t\t\t\tend \n\t\t\t\t\t\t\t\t\t\t\t\telse \n\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tweight_case=weight_case+1;\n\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\tend\n end\n\t\t\t\t\tif (i>razn_addr+3)\n begin\n step=step+1; //next step\n i=0;\n\t\t\t\t\t\ti_d=0;\n\t\t\t\t\t\ti1=0;\n\t\t\t\t\t\tweight_case=0;\n end\n end\n\t\t\t8'd2,8'd5,8'd8,8'd11,8'd14,8'd17,8'd20,8'd23,8'd26,8'd29,8'd32,8'd35,8'd38,8'd41,8'd44,8'd47,8'd50,8'd53,8'd56,8'd59,8'd62,8'd65,8'd68,8'd71,8'd74,8'd77,8'd80,8'd83:\n\t\t\t\tbegin\n\t\t\t\t\tif (i<=razn_addr)\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\twe_bias=1;\n\t\t\t\t\t\t\twrite_address_bias=addr;\n\t\t\t\t\t\t\tif (load_bias==1'b1) i=i+1;\n\t\t\t\t\t\t\td_bias=data_bias;\n\t\t\t\t\t\tend\n\t\t\t\t\telse\t\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tstep=step+1;\n\t\t\t\t\t\t\ti=0;\n\t\t\t\t\t\t\twe_bias=0;\n\t\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tdefault:\n\t\t\t\tbegin\n\t\t\t\t\twe_w=0;\n\t\t\t\t\twe_bias=0;\n\t\t\t\t\ti=0;\n\t\t\t\t\ti_d=0;\n\t\t\t\t\ti1=0;\n\t\t\t\tend\n\t\tendcase\n end\nalways @(posedge nextstep) if (GO==1) step_n=0; else step_n=step_n+1;\nassign step_out=step+step_n;\nassign address=(re_weights)?(firstaddr+i):0;\nassign address_bias=(re_bias)?(firstaddr+i):0;\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/TOP.v", "content": "module TOP(\nclk,\nclk_RAM_w,\nclk_RAM_p,\nGO,\nRESULT,\nSTOP,\n\nre_weights,\nload_weights,\ndp_weights,\naddress_weights,\n\nre_bias,\nload_bias,\ndp_bias,\naddress_bias,\n\nwe_image,\ndp_image,\naddress_image,\nstep\n);\n\nparameter num_conv=8;\nparameter SIZE_weights = 19;\nparameter SIZE_bias = 14;\nparameter SIZE_1=13;\nparameter SIZE_2=26;\nparameter SIZE_3=39;\nparameter SIZE_4=52;\nparameter SIZE_5=65;\nparameter SIZE_6=78;\nparameter SIZE_7=91;\nparameter SIZE_8=104;\nparameter SIZE_address_pix=18;\nparameter SIZE_address_pix_t=17;\nparameter SIZE_address_wei=17;\nparameter SIZE_address_image=16;\nparameter picture_size = 128;\nparameter picture_storage_limit = 0;\nparameter razmpar = picture_size >> 1;\nparameter razmpar2 = picture_size >> 2;\nparameter picture_storage_limit_2 = picture_size*picture_size*1;\ninput clk,clk_RAM_w,clk_RAM_p;\ninput GO;\noutput [1:0] RESULT;\ninput signed [SIZE_weights-1:0] dp_weights;\ninput signed [SIZE_bias-1:0] dp_bias;\noutput [23:0] address_weights;\noutput [11:0] address_bias;\ninput load_weights,load_bias;\ninput signed [SIZE_1-1:0] dp_image;\ninput [SIZE_address_image-1:0] address_image;\ninput we_image;\noutput reg STOP;\noutput re_weights,re_bias;\noutput [6:0] step;\n\nwire [SIZE_address_image-1:0] address_image_1;\n\nreg conv_en;\nwire STOP_conv;\n\nreg dense_en;\nwire STOP_dense;\n\nreg result_en;\nwire STOP_res;\t\nwire [1:0] res_out;\n\nreg bias,glob_average_en;\n\nreg [4:0] TOPlvl_conv;\nwire [4:0] TOPlvl;\nreg [8:0] lvl;\nreg [8:0] slvl;\nreg [2:0] num;\nreg [SIZE_address_pix-1:0] memstartp;\nwire [SIZE_address_pix-1:0] memstartp_lvl;\nreg [SIZE_address_wei-1:0] memstartw;\nwire [SIZE_address_wei-1:0] memstartw_lvl;\nreg [SIZE_address_pix-1:0] memstartzap;\nwire [SIZE_address_pix-1:0] memstartzap_num;\nwire [10:0] \t\t\t\tmemstartb;\nwire [SIZE_address_pix-1:0] read_addressp;\nwire [SIZE_address_image-1:0] read_addressp_init;\nwire [SIZE_address_pix_t-1:0] read_addresstp;\nwire [SIZE_address_wei-1:0] read_addressw;\nwire [10:0]\t\t\t\t\tread_address_bias; \nwire [SIZE_address_pix-1:0] read_addressp_conv;\nwire [SIZE_address_pix-1:0] read_addressp_dense;\nwire [SIZE_address_pix-1:0] read_addressp_res;\nwire [SIZE_address_wei-1:0] read_addressw_conv;\nwire [SIZE_address_wei-1:0] read_addressw_dense;\nwire [SIZE_address_pix-1:0] write_addressp;\nwire [SIZE_address_pix_t-1:0] write_addresstp;\nwire [SIZE_address_wei-1:0] write_addressw;\nwire [10:0]\t\t\t\t\twrite_address_bias; \nwire [SIZE_address_pix-1:0] write_addressp_zagr;\nwire [SIZE_address_pix-1:0] write_addressp_conv;\nwire [SIZE_address_pix-1:0] write_addressp_dense;\nwire we_p,we_tp,we_w;\nwire re_p,re_tp,re_w,re_p_init;\nwire re_bias_RAM;\nwire we_p_zagr;\nwire we_conv,re_wb_conv,re_conv;\nwire we_dense,re_p_dense,re_w_dense;\nwire we_bias;\nwire re_p_res;\nwire signed [SIZE_8-1:0] qp;\nwire signed [32*8-1:0] qtp;\nwire signed [SIZE_weights*9-1:0] qw;\nwire signed [SIZE_bias-1:0]\tq_bias;\nwire signed [SIZE_8-1:0] dp;\nwire signed [32*8-1:0] dtp;\nwire signed [SIZE_weights*9-1:0] dw;\nwire signed [SIZE_8-1:0] dp_conv;\nwire signed [SIZE_8-1:0] dp_dense;\nwire signed [SIZE_8-1:0] dp_zagr;\nwire signed [SIZE_bias-1:0] d_bias;\n\nwire [1:0] prov;\nwire [14:0] i_conv;\nwire signed [32-1:0] Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8;\n\nwire signed [SIZE_weights-1:0] w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83;\nwire signed [SIZE_weights-1:0] w11_c,w12_c,w13_c,w21_c,w22_c,w23_c,w31_c,w32_c,w33_c,w41_c,w42_c,w43_c,w51_c,w52_c,w53_c,w61_c,w62_c,w63_c,w71_c,w72_c,w73_c,w81_c,w82_c,w83_c;\nwire signed [SIZE_weights-1:0] w11_d,w12_d,w13_d,w21_d,w22_d,w23_d,w31_d,w32_d,w33_d,w41_d,w42_d,w43_d,w51_d,w52_d,w53_d,w61_d,w62_d,w63_d,w71_d,w72_d,w73_d,w81_d,w82_d,w83_d;\nwire signed [SIZE_1-1:0] p11,p12,p13,p21,p22,p23,p31,p32,p33,p41,p42,p43,p51,p52,p53,p61,p62,p63,p71,p72,p73,p81,p82,p83;\nwire signed [SIZE_1-1:0] p11_c,p12_c,p13_c,p21_c,p22_c,p23_c,p31_c,p32_c,p33_c,p41_c,p42_c,p43_c,p51_c,p52_c,p53_c,p61_c,p62_c,p63_c,p71_c,p72_c,p73_c,p81_c,p82_c,p83_c;\nwire signed [SIZE_1-1:0] p11_d,p12_d,p13_d,p21_d,p22_d,p23_d,p31_d,p32_d,p33_d,p41_d,p42_d,p43_d,p51_d,p52_d,p53_d,p61_d,p62_d,p63_d,p71_d,p72_d,p73_d,p81_d,p82_d,p83_d;\nwire go_conv;\nwire go_conv_TOP;\nwire go_dense;\n\nreg nextstep;\n\nreg [7:0] matrix;\nwire [14:0] matrix2; //razmer*razmer\n\nreg [8:0] mem;\nreg [8:0] filt;\nreg [1:0] stride;\nreg depthwise;\nreg onexone;\n\nreg [8:0] in_dense;\nreg [1:0] out_dense;\nreg nozero_dense;\n\nwire clk_RAM;\n\nwire up_perm,down_perm;\nwire [SIZE_address_pix-1:0] stride_plus_prov;\n\nconv_TOP #(\n\tSIZE_1,\n\tSIZE_2,\n\tSIZE_3,\n\tSIZE_4,\n\tSIZE_5,\n\tSIZE_6,\n\tSIZE_7,\n\tSIZE_8,\n\tSIZE_address_pix,\n\tSIZE_address_pix_t,\n\tSIZE_address_wei,\n\tSIZE_weights,\n\tSIZE_bias\n) conv_TOP (\n\t.clk\t\t\t\t\t\t\t(clk),\n\t.conv_en\t\t\t\t\t\t(conv_en),\n\t.STOP\t\t\t\t\t\t\t(STOP_conv),\n\t.memstartp\t\t\t\t\t(memstartp_lvl),\n\t.memstartw\t\t\t\t\t(memstartw_lvl),\n\t.memstartb\t\t\t\t\t(memstartb),\n\t.memstartzap\t\t\t\t(memstartzap_num),\n\t.read_addressp\t\t\t\t(read_addressp_conv),\n\t.write_addressp\t\t\t (write_addressp_conv),\n\t.read_addresstp\t\t\t (read_addresstp),\n\t.write_addresstp\t\t\t(write_addresstp),\n\t.read_addressb\t\t\t\t(read_address_bias),\n .read_addressw\t\t\t\t(read_addressw_conv),\n\t.we\t\t\t\t\t\t\t(we_conv),\n\t.re_wb\t\t\t\t\t\t(re_wb_conv),\n\t.re\t\t\t\t\t\t\t(re_conv),\n\t.we_t\t\t\t\t\t\t(we_tp),\n\t.re_t\t\t\t\t\t\t(re_tp),\n\t.qp\t\t\t\t\t\t\t(qp),\n\t.qtp\t\t\t\t\t\t(qtp),\n\t.qw\t\t\t\t\t\t\t(qw),\n\t.q_bias\t\t\t\t\t\t(q_bias),\n\t.dp\t\t\t\t\t\t\t(dp_conv),\n\t.dtp\t\t\t\t\t\t(dtp),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i_to_prov\t\t\t\t\t(i_conv),\n\t.lvl\t\t\t\t\t\t(lvl),\n\t.slvl\t\t\t\t\t\t(slvl),\n\t.Y1\t\t\t\t\t\t\t(Y1),\n\t.Y2\t\t\t\t\t\t\t(Y2),\n\t.Y3\t\t\t\t\t\t\t(Y3),\n\t.Y4\t\t\t\t\t\t\t(Y4),\n\t.Y5\t\t\t\t\t\t\t(Y5),\n\t.Y6\t\t\t\t\t\t\t(Y6),\n\t.Y7\t\t\t\t\t\t\t(Y7),\n\t.Y8\t\t\t\t\t\t\t(Y8),\n\t.w11\t\t\t\t\t\t\t(w11_c),\n\t.w12\t\t\t\t\t\t\t(w12_c),\n\t.w13\t\t\t\t\t\t\t(w13_c),\n\t.w21\t\t\t\t\t\t\t(w21_c),\n\t.w22\t\t\t\t\t\t\t(w22_c),\n\t.w23\t\t\t\t\t\t\t(w23_c),\n\t.w31\t\t\t\t\t\t\t(w31_c),\n\t.w32\t\t\t\t\t\t\t(w32_c),\n\t.w33\t\t\t\t\t\t\t(w33_c),\n\t.w41\t\t\t\t\t\t\t(w41_c),\n\t.w42\t\t\t\t\t\t\t(w42_c),\n\t.w43\t\t\t\t\t\t\t(w43_c),\n\t.w51\t\t\t\t\t\t\t(w51_c),\n\t.w52\t\t\t\t\t\t\t(w52_c),\n\t.w53\t\t\t\t\t\t\t(w53_c),\n\t.w61\t\t\t\t\t\t\t(w61_c),\n\t.w62\t\t\t\t\t\t\t(w62_c),\n\t.w63\t\t\t\t\t\t\t(w63_c),\n\t.w71\t\t\t\t\t\t\t(w71_c),\n\t.w72\t\t\t\t\t\t\t(w72_c),\n\t.w73\t\t\t\t\t\t\t(w73_c),\n\t.w81\t\t\t\t\t\t\t(w81_c),\n\t.w82\t\t\t\t\t\t\t(w82_c),\n\t.w83\t\t\t\t\t\t\t(w83_c),\n\t.p0_1\t\t\t\t\t\t\t(p11_c),\n\t.p0_2\t\t\t\t\t\t\t(p12_c),\n\t.p0_3\t\t\t\t\t\t\t(p13_c),\n\t.p1_1\t\t\t\t\t\t\t(p21_c),\n\t.p1_2\t\t\t\t\t\t\t(p22_c),\n\t.p1_3\t\t\t\t\t\t\t(p23_c),\n\t.p2_1\t\t\t\t\t\t\t(p31_c),\n\t.p2_2\t\t\t\t\t\t\t(p32_c),\n\t.p2_3\t\t\t\t\t\t\t(p33_c),\n\t.p3_1\t\t\t\t\t\t\t(p41_c),\n\t.p3_2\t\t\t\t\t\t\t(p42_c),\n\t.p3_3\t\t\t\t\t\t\t(p43_c),\n\t.p4_1\t\t\t\t\t\t\t(p51_c),\n\t.p4_2\t\t\t\t\t\t\t(p52_c),\n\t.p4_3\t\t\t\t\t\t\t(p53_c),\n\t.p5_1\t\t\t\t\t\t\t(p61_c),\n\t.p5_2\t\t\t\t\t\t\t(p62_c),\n\t.p5_3\t\t\t\t\t\t\t(p63_c),\n\t.p6_1\t\t\t\t\t\t\t(p71_c),\n\t.p6_2\t\t\t\t\t\t\t(p72_c),\n\t.p6_3\t\t\t\t\t\t\t(p73_c),\n\t.p7_1\t\t\t\t\t\t\t(p81_c),\n\t.p7_2\t\t\t\t\t\t\t(p82_c),\n\t.p7_3\t\t\t\t\t\t\t(p83_c),\n\t.go\t\t\t\t\t\t\t(go_conv_TOP),\n\t.up_perm\t\t\t\t\t(up_perm),\n\t.down_perm\t\t\t\t\t(down_perm),\n\t.stride_plus_prov\t\t\t(stride_plus_prov),\n\t.num\t\t\t\t\t\t(num),\n\t.filt\t\t\t\t\t\t(filt),\n\t.mem\t\t\t\t\t\t(mem),\n\t.bias\t\t\t\t\t\t(bias),\n\t.glob_average_en\t\t\t(glob_average_en),\n\t.step\t\t\t\t\t\t(step),\n\t.stride\t\t\t\t\t\t(stride),\n\t.depthwise\t\t\t\t\t(depthwise),\n\t.onexone\t\t\t\t\t(onexone)\n);\nmemorywork #(\n\tnum_conv,\n\tSIZE_1,\n\tSIZE_2,\n\tSIZE_3,\n\tSIZE_4,\n\tSIZE_5,\n\tSIZE_6,\n\tSIZE_7,\n\tSIZE_8,\n\tSIZE_address_pix,\n\tSIZE_address_wei,\n\tSIZE_weights,\n\tSIZE_bias\n) block (\n\t.clk_RAM_w\t\t\t\t\t(clk_RAM_w),\n\t.we_w\t\t\t\t\t\t(we_w),\n\t.re_weights\t\t\t\t\t(re_weights),\n\t.re_bias\t\t\t\t\t(re_bias),\n\t.load_weights\t\t\t\t(load_weights),\n\t.addrw\t\t\t\t\t\t(write_addressw),\n\t.dw\t\t\t\t\t\t\t(dw),\n\t.step_out\t\t\t\t\t(step),\n\t.nextstep\t\t\t\t\t(nextstep),\n\t.data\t\t\t\t\t\t(dp_weights),\n\t.address\t\t\t\t\t(address_weights),\n\t.GO\t\t\t\t\t\t\t(GO),\n\t.in_dense\t\t\t\t\t(in_dense),\n\t.onexone\t\t\t\t\t(onexone),\n\t.data_bias\t\t\t\t\t(dp_bias),\n\t.load_bias\t\t\t\t\t(load_bias),\n\t.address_bias\t\t\t\t(address_bias),\n\t.write_address_bias\t\t (write_address_bias),\n\t.we_bias\t\t\t\t\t(we_bias),\n\t.d_bias\t\t\t\t\t\t(d_bias)\n);\nRAM #(\n\tpicture_size,\n\tSIZE_1,\n\tSIZE_2,\n\tSIZE_3,\n\tSIZE_4,\n\tSIZE_5,\n\tSIZE_6,\n\tSIZE_7,\n\tSIZE_8,\n\tSIZE_address_pix,\n\tSIZE_address_pix_t,\n\tSIZE_address_wei,\n\tSIZE_address_image,\n\tSIZE_weights,\n\tSIZE_bias\n) memory (\n\t.qp\t\t\t\t\t\t\t(qp),\n\t.qtp\t\t\t\t\t\t(qtp),\n\t.qw\t\t\t\t\t\t\t(qw),\n\t.dp\t\t\t\t\t\t\t(dp),\n\t.dtp\t\t\t\t\t\t(dtp),\n\t.dw\t\t\t\t\t\t\t(dw),\n\t.write_addressp\t\t\t (write_addressp),\n\t.read_addressp\t\t\t\t(read_addressp),\n\t.write_addresstp\t\t\t(write_addresstp),\n\t.read_addresstp\t\t\t (read_addresstp),\n\t.write_addressw\t\t\t (write_addressw),\n\t.read_addressw\t\t\t\t(read_addressw),\n\t.we_p\t\t\t\t\t\t(we_p),\n\t.we_tp\t\t\t\t\t\t(we_tp),\n\t.we_w\t\t\t\t\t\t(we_w),\n\t.re_p\t\t\t\t\t\t(re_p),\n\t.re_tp\t\t\t\t\t\t(re_tp),\n\t.re_w\t\t\t\t\t\t(re_w),\n\t.clk\t\t\t\t\t\t(clk_RAM),\n\t.clk_RAM_w\t\t\t\t\t(clk_RAM_w),\n\t.q_bias\t\t\t\t\t\t(q_bias),\n\t.d_bias\t\t\t\t\t\t(d_bias),\n\t.we_bias\t\t\t\t\t(we_bias),\n\t.re_bias\t\t\t\t\t(re_bias_RAM),\n\t.write_address_bias\t\t (write_address_bias),\n\t.read_address_bias\t\t (read_address_bias)\n);\nborder border(\n\t.clk\t\t\t\t\t\t(clk),\n\t.go\t\t\t\t\t\t\t(conv_en && (!onexone)),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.prov\t\t\t\t\t\t(prov)\n);\ndense #(\n\tnum_conv,\n\tSIZE_1,\n\tSIZE_2,\n\tSIZE_3,\n\tSIZE_4,\n\tSIZE_5,\n\tSIZE_6,\n\tSIZE_7,\n\tSIZE_8,\n\tSIZE_address_pix,\n\tSIZE_address_wei,\n\tSIZE_weights\n) dense (\n\t.clk\t\t\t\t\t\t(clk),\n\t.dense_en\t\t\t\t\t(dense_en),\n\t.STOP\t\t\t\t\t\t(STOP_dense),\n\t.in\t\t\t\t\t\t\t(in_dense),\n\t.out\t\t\t\t\t\t(out_dense),\n\t.we\t\t\t\t\t\t\t(we_dense),\n\t.re_p\t\t\t\t\t\t(re_p_dense),\n\t.re_w\t\t\t\t\t\t(re_w_dense),\n\t.read_addressp\t\t\t\t(read_addressp_dense),\n\t.read_addressw\t\t\t\t(read_addressw_dense),\n\t.write_addressp\t\t\t (write_addressp_dense),\n\t.memstartp\t\t\t\t\t(memstartp_lvl),\n\t.memstartzap\t\t\t\t(memstartzap_num),\n\t.qp\t\t\t\t\t\t\t(qp),\n\t.qw\t\t\t\t\t\t\t(qw),\n\t.res\t\t\t\t\t\t(dp_dense),\n\t.Y1\t\t\t\t\t\t\t(Y1),\n\t.Y2\t\t\t\t\t\t\t(Y2),\n\t.Y3\t\t\t\t\t\t\t(Y3),\n\t.Y4\t\t\t\t\t\t\t(Y4),\n\t.Y5\t\t\t\t\t\t\t(Y5),\n\t.Y6\t\t\t\t\t\t\t(Y6),\n\t.Y7\t\t\t\t\t\t\t(Y7),\n\t.Y8\t\t\t\t\t\t\t(Y8),\n\t.w11\t\t\t\t\t\t(w11_d),\n\t.w12\t\t\t\t\t\t(w12_d),\n\t.w13\t\t\t\t\t\t(w13_d),\n\t.w21\t\t\t\t\t\t(w21_d),\n\t.w22\t\t\t\t\t\t(w22_d),\n\t.w23\t\t\t\t\t\t(w23_d),\n\t.w31\t\t\t\t\t\t(w31_d),\n\t.w32\t\t\t\t\t\t(w32_d),\n\t.w33\t\t\t\t\t\t(w33_d),\n\t.w41\t\t\t\t\t\t(w41_d),\n\t.w42\t\t\t\t\t\t(w42_d),\n\t.w43\t\t\t\t\t\t(w43_d),\n\t.w51\t\t\t\t\t\t(w51_d),\n\t.w52\t\t\t\t\t\t(w52_d),\n\t.w53\t\t\t\t\t\t(w53_d),\n\t.w61\t\t\t\t\t\t(w61_d),\n\t.w62\t\t\t\t\t\t(w62_d),\n\t.w63\t\t\t\t\t\t(w63_d),\n\t.w71\t\t\t\t\t\t(w71_d),\n\t.w72\t\t\t\t\t\t(w72_d),\n\t.w73\t\t\t\t\t\t(w73_d),\n\t.w81\t\t\t\t\t\t(w81_d),\n\t.w82\t\t\t\t\t\t(w82_d),\n\t.w83\t\t\t\t\t\t(w83_d),\n\t.p11\t\t\t\t\t\t(p11_d),\n\t.p12\t\t\t\t\t\t(p12_d),\n\t.p13\t\t\t\t\t\t(p13_d),\n\t.p21\t\t\t\t\t\t(p21_d),\n\t.p22\t\t\t\t\t\t(p22_d),\n\t.p23\t\t\t\t\t\t(p23_d),\n\t.p31\t\t\t\t\t\t(p31_d),\n\t.p32\t\t\t\t\t\t(p32_d),\n\t.p33\t\t\t\t\t\t(p33_d),\n\t.p41\t\t\t\t\t\t(p41_d),\n\t.p42\t\t\t\t\t\t(p42_d),\n\t.p43\t\t\t\t\t\t(p43_d),\n\t.p51\t\t\t\t\t\t(p51_d),\n\t.p52\t\t\t\t\t\t(p52_d),\n\t.p53\t\t\t\t\t\t(p53_d),\n\t.p61\t\t\t\t\t\t(p61_d),\n\t.p62\t\t\t\t\t\t(p62_d),\n\t.p63\t\t\t\t\t\t(p63_d),\n\t.p71\t\t\t\t\t\t(p71_d),\n\t.p72\t\t\t\t\t\t(p72_d),\n\t.p73\t\t\t\t\t\t(p73_d),\n\t.p81\t\t\t\t\t\t(p81_d),\n\t.p82\t\t\t\t\t\t(p82_d),\n\t.p83\t\t\t\t\t\t(p83_d),\n\t.go\t\t\t\t\t\t\t(go_dense),\n\t.nozero\t\t\t\t\t\t(nozero_dense)\n);\nresult #(\n\tSIZE_1,\n\tSIZE_2,\n\tSIZE_3,\n\tSIZE_4,\n\tSIZE_5,\n\tSIZE_6,\n\tSIZE_7,\n\tSIZE_8,\n\tSIZE_address_pix\n) result (\n\t.clk\t\t\t\t\t\t(clk),\n\t.enable\t\t\t\t\t\t(result_en),\n\t.STOP\t\t\t\t\t\t(STOP_res),\n\t.memstartp\t\t\t\t\t(memstartp_lvl),\n\t.read_addressp\t\t\t\t(read_addressp_res),\n\t.qp\t\t\t\t\t\t\t(qp),\n\t.re\t\t\t\t\t\t\t(re_p_res),\n\t.RESULT\t\t\t\t\t\t(res_out)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv1 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y1),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p11),\n\t.p2\t\t\t\t\t\t\t(p12),\n\t.p3\t\t\t\t\t\t\t(p13),\n\t.w1\t\t\t\t\t\t\t(w11),\n\t.w2\t\t\t\t\t\t\t(w12),\n\t.w3\t\t\t\t\t\t\t(w13),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv2 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y2),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p21),\n\t.p2\t\t\t\t\t\t\t(p22),\n\t.p3\t\t\t\t\t\t\t(p23),\n\t.w1\t\t\t\t\t\t\t(w21),\n\t.w2\t\t\t\t\t\t\t(w22),\n\t.w3\t\t\t\t\t\t\t(w23),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv3 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y3),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p31),\n\t.p2\t\t\t\t\t\t\t(p32),\n\t.p3\t\t\t\t\t\t\t(p33),\n\t.w1\t\t\t\t\t\t\t(w31),\n\t.w2\t\t\t\t\t\t\t(w32),\n\t.w3\t\t\t\t\t\t\t(w33),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv4 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y4),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p41),\n\t.p2\t\t\t\t\t\t\t(p42),\n\t.p3\t\t\t\t\t\t\t(p43),\n\t.w1\t\t\t\t\t\t\t(w41),\n\t.w2\t\t\t\t\t\t\t(w42),\n\t.w3\t\t\t\t\t\t\t(w43),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv5 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y5),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p51),\n\t.p2\t\t\t\t\t\t\t(p52),\n\t.p3\t\t\t\t\t\t\t(p53),\n\t.w1\t\t\t\t\t\t\t(w51),\n\t.w2\t\t\t\t\t\t\t(w52),\n\t.w3\t\t\t\t\t\t\t(w53),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv6 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y6),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p61),\n\t.p2\t\t\t\t\t\t\t(p62),\n\t.p3\t\t\t\t\t\t\t(p63),\n\t.w1\t\t\t\t\t\t\t(w61),\n\t.w2\t\t\t\t\t\t\t(w62),\n\t.w3\t\t\t\t\t\t\t(w63),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv7 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y7),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p71),\n\t.p2\t\t\t\t\t\t\t(p72),\n\t.p3\t\t\t\t\t\t\t(p73),\n\t.w1\t\t\t\t\t\t\t(w71),\n\t.w2\t\t\t\t\t\t\t(w72),\n\t.w3\t\t\t\t\t\t\t(w73),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nconv #(\n\tSIZE_1,\n\tSIZE_address_pix,\n\tSIZE_weights\n) conv8 (\n\t.clk\t\t\t\t\t\t(clk),\n\t.Y1\t\t\t\t\t\t\t(Y8),\n\t.prov\t\t\t\t\t\t(prov),\n\t.matrix\t\t\t\t\t\t(matrix),\n\t.matrix2\t\t\t\t\t(matrix2),\n\t.i\t\t\t\t\t\t\t(i_conv),\n\t.up_perm\t\t\t\t\t((up_perm && (!dense_en))),\n\t.down_perm\t\t\t\t\t((down_perm && (!dense_en))),\n\t.p1\t\t\t\t\t\t\t(p81),\n\t.p2\t\t\t\t\t\t\t(p82),\n\t.p3\t\t\t\t\t\t\t(p83),\n\t.w1\t\t\t\t\t\t\t(w81),\n\t.w2\t\t\t\t\t\t\t(w82),\n\t.w3\t\t\t\t\t\t\t(w83),\n\t.conv_en\t\t\t\t\t(go_conv),\n\t.dense_en\t\t\t\t\t((onexone||dense_en)),\n\t.stride_plus_prov\t\t\t(stride_plus_prov)\n);\nalways @(posedge clk )\nbegin\nif (GO==1)\nbegin\nSTOP=0;\nnextstep=1;\nglob_average_en=0;\nresult_en=0;\nend\nelse nextstep=0;\nif (STOP==0)\nbegin\n\t if ((TOPlvl==1)&&(step==3))\n\t\t begin\n\t\t\t matrix = 128;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 7;\n\t\t\t filt = 2;\n\t\t\t stride=2;\n\t\t\t onexone=0;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==2)&&(step==3)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==2)&&(step==6))\n\t\t begin\n\t\t\t matrix = 64;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 7;\n\t\t\t filt = 7;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==3)&&(step==6)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==3)&&(step==9))\n\t\t begin\n\t\t\t matrix = 64;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 7;\n\t\t\t filt = 15;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==4)&&(step==9)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==4)&&(step==12))\n\t\t begin\n\t\t\t matrix = 64;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 15;\n\t\t\t filt = 15;\n\t\t\t stride=2;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==5)&&(step==12)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==5)&&(step==15))\n\t\t begin\n\t\t\t matrix = 32;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 15;\n\t\t\t filt = 31;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==6)&&(step==15)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==6)&&(step==18))\n\t\t begin\n\t\t\t matrix = 32;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 31;\n\t\t\t filt = 31;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==7)&&(step==18)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==7)&&(step==21))\n\t\t begin\n\t\t\t matrix = 32;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 31;\n\t\t\t filt = 31;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==8)&&(step==21)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==8)&&(step==24))\n\t\t begin\n\t\t\t matrix = 32;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 31;\n\t\t\t filt = 31;\n\t\t\t stride=2;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==9)&&(step==24)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==9)&&(step==27))\n\t\t begin\n\t\t\t matrix = 16;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 31;\n\t\t\t filt = 63;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==10)&&(step==27)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==10)&&(step==30))\n\t\t begin\n\t\t\t matrix = 16;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 63;\n\t\t\t filt = 63;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==11)&&(step==30)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==11)&&(step==33))\n\t\t begin\n\t\t\t matrix = 16;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 63;\n\t\t\t filt = 63;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==12)&&(step==33)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==12)&&(step==36))\n\t\t begin\n\t\t\t matrix = 16;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 63;\n\t\t\t filt = 63;\n\t\t\t stride=2;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==13)&&(step==36)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==13)&&(step==39))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 63;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==14)&&(step==39)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==14)&&(step==42))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==15)&&(step==42)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==15)&&(step==45))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==16)&&(step==45)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==16)&&(step==48))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==17)&&(step==48)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==17)&&(step==51))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==18)&&(step==51)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==18)&&(step==54))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==19)&&(step==54)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==19)&&(step==57))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==20)&&(step==57)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==20)&&(step==60))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==21)&&(step==60)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==21)&&(step==63))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==22)&&(step==63)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==22)&&(step==66))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==23)&&(step==66)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==23)&&(step==69))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==24)&&(step==69)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==24)&&(step==72))\n\t\t begin\n\t\t\t matrix = 8;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 127;\n\t\t\t stride=2;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==25)&&(step==72)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==25)&&(step==75))\n\t\t begin\n\t\t\t matrix = 4;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 127;\n\t\t\t filt = 255;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==26)&&(step==75)) \n begin\n nextstep = 1;\n onexone = 0;\n end\n\t if ((TOPlvl==26)&&(step==78))\n\t\t begin\n\t\t\t matrix = 4;\n\t\t\t memstartp = picture_storage_limit_2;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 255;\n\t\t\t filt = 255;\n\t\t\t stride=1;\n\t\t\t onexone=0;\n\t\t\t depthwise=1;\n\t\t\t glob_average_en=0;\n end\n\t if ((TOPlvl==27)&&(step==78)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==27)&&(step==81))\n\t\t begin\n\t\t\t matrix = 4;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2+0;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 255;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=1;\n end\n\t if ((TOPlvl==28)&&(step==81)) \n begin\n nextstep = 1;\n onexone = 1;\n end\n\t if ((TOPlvl==28)&&(step==84))\n\t\t begin\n\t\t\t matrix = 4;\n\t\t\t memstartp = picture_storage_limit;\n\t\t\t memstartw = 0;\n\t\t\t memstartzap = picture_storage_limit_2+16;\n\t\t\t conv_en = 1;\n\t\t\t dense_en=0;\n\t\t\t mem = 255;\n\t\t\t filt = 127;\n\t\t\t stride=1;\n\t\t\t onexone=1;\n\t\t\t depthwise=0;\n\t\t\t glob_average_en=1;\n end\n\t if ((TOPlvl==29)&&(step==84)) \n begin\n\t\t\t nextstep=1;\n\t\t\t onexone=0;\n\t\t\t in_dense=256;\n\t\t\t out_dense=2;\n\t\t\tend\n\t if ((TOPlvl==29)&&(step==86))\n begin\n\t\t\t memstartp= picture_storage_limit_2;\n\t\t\t memstartzap = picture_storage_limit;\n\t\t\t conv_en=0;\n\t\t\t dense_en=1;\n\t\t\t nozero_dense=1;\n\t\t\t depthwise=0;\n\t\t\tend\n\t if ((TOPlvl==29)&&(STOP_dense==0)&&(step==87))\n\t\t begin\n\t\t\t memstartp = picture_storage_limit;\n\t\t \tresult_en = 1;\n\t\t end\n\tif ((depthwise)||(lvl==filt)||((onexone)&&(mem==((lvl+1)*8)-1))) bias=1; else bias=0;\n\tif ((STOP_conv)&&(conv_en==1)) conv_en=0;\n\tif (STOP_dense==1) begin dense_en=0; nextstep=1; end\n\tif ((STOP_res==1)&&(result_en==1))\n\tbegin\n\t\tresult_en=0;\n\t\tSTOP=1;\n\tend\nend\nend\n\nalways @(negedge STOP_conv or posedge GO)\n\tbegin\n\t\tif (GO)\n\t\t\tbegin\n\t\t\t\tlvl=0;\n\t\t\t\tslvl=0;\n\t\t\t\tTOPlvl_conv=1;\n\t\t\t\tnum=0;\n\t\t\tend\n\t\telse\n\t\t\tbegin\n\t\t\t\tif (lvl==(filt)||((lvl==filt>>3)&&(depthwise))||((lvl==((mem+1)>>3)-1)&&(onexone)))\n\t\t\t\t\tbegin\n\t\t\t\t\t\tlvl=0;\n\t\t\t\t\t\tif ((num!=0)&&(!depthwise)) num=num+1; else num=0;\n\t\t\t\t\t\tif ((num==0)||(depthwise))\n\t\t\t\t\t\tbegin \n\t\t\t\t\t\t\tif ((depthwise)||((!onexone)&&(mem==(8+(slvl*8))-1))||((onexone)&&(filt==(8+(slvl*8))-1))) \n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tslvl=0; \n\t\t\t\t\t\t\t\t\tTOPlvl_conv=TOPlvl_conv+1'b1;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\telse slvl = slvl + 1'b1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\telse\n\t\t\t\tlvl=lvl+1;\n\t\t\tend\n\tend\n\nassign address_image_1 = address_image[13:0]+1;\t\n\nassign memstartw_lvl=memstartw+((onexone?num*(((mem+1)>>3)-1)+lvl:(depthwise?lvl*num_conv:lvl))+(((!depthwise)&&(!onexone))?(slvl*(4*(filt+1))):(1'b0))+((!onexone)?(num*(filt+1)):num+slvl*((mem+1)<<0)));\nassign memstartzap_num = memstartzap+((glob_average_en)?(num+slvl*1):0)+(((conv_en==1)&&(!glob_average_en))?(num*((matrix>>(stride-1))*(matrix>>(stride-1)))+slvl*((matrix>>(stride-1))*(matrix>>(stride-1)))+((depthwise)?lvl*((matrix>>(stride-1))*(matrix>>(stride-1))):0)):0);\nassign memstartp_lvl=memstartp+(onexone?((lvl[8:0])*matrix2):(depthwise?(lvl*matrix2):((lvl>>num_conv-1)*matrix2))); \nassign memstartb=slvl*8+num+(depthwise?lvl*num_conv:0)+1;\n\nassign re_p=GO?1'b1:((conv_en==1)?re_conv:((dense_en==1)?re_p_dense:((result_en==1)?re_p_res:0)));\nassign re_w=(conv_en==1)?re_wb_conv:((dense_en==1)?re_w_dense:0);\nassign re_bias_RAM=(conv_en==1)?re_wb_conv:0;\nassign read_addressp=GO?address_image_1[13:0]:((conv_en==1)?read_addressp_conv:((dense_en==1)?read_addressp_dense:((result_en==1)?read_addressp_res:0)));\nassign we_p=GO?we_image:((conv_en==1)?we_conv:((dense_en==1)?we_dense:0));\nassign dp=GO?((address_image<128*128*1)?{dp_image,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0}:((address_image<128*128*2)?{qp[SIZE_8-1:SIZE_7],dp_image,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0}:((address_image<128*128*3)?{qp[SIZE_8-1:SIZE_7],qp[SIZE_7-1:SIZE_6],dp_image,13'd0,13'd0,13'd0,13'd0,13'd0}:0))):((conv_en==1)?dp_conv:((dense_en==1)?dp_dense:0));\nassign write_addressp=GO?(address_image[13:0]):((conv_en==1)?write_addressp_conv:((dense_en==1)?write_addressp_dense:0));\nassign read_addressw=(conv_en==1)?read_addressw_conv:((dense_en==1)?read_addressw_dense:0);\n\nassign matrix2=matrix*matrix;\n\nassign clk_RAM=GO?clk_RAM_p:clk;\n\nassign p11=(conv_en==1)?p11_c:((dense_en==1)?p11_d:0);\nassign p12=(conv_en==1)?p12_c:((dense_en==1)?p12_d:0);\nassign p13=(conv_en==1)?p13_c:((dense_en==1)?p13_d:0);\nassign p21=(conv_en==1)?p21_c:((dense_en==1)?p21_d:0);\nassign p22=(conv_en==1)?p22_c:((dense_en==1)?p22_d:0);\nassign p23=(conv_en==1)?p23_c:((dense_en==1)?p23_d:0);\nassign p31=(conv_en==1)?p31_c:((dense_en==1)?p31_d:0);\nassign p32=(conv_en==1)?p32_c:((dense_en==1)?p32_d:0);\nassign p33=(conv_en==1)?p33_c:((dense_en==1)?p33_d:0);\nassign p41=(conv_en==1)?p41_c:((dense_en==1)?p41_d:0);\nassign p42=(conv_en==1)?p42_c:((dense_en==1)?p42_d:0);\nassign p43=(conv_en==1)?p43_c:((dense_en==1)?p43_d:0);\nassign p51=(conv_en==1)?p51_c:((dense_en==1)?p51_d:0);\nassign p52=(conv_en==1)?p52_c:((dense_en==1)?p52_d:0);\nassign p53=(conv_en==1)?p53_c:((dense_en==1)?p53_d:0);\nassign p61=(conv_en==1)?p61_c:((dense_en==1)?p61_d:0);\nassign p62=(conv_en==1)?p62_c:((dense_en==1)?p62_d:0);\nassign p63=(conv_en==1)?p63_c:((dense_en==1)?p63_d:0);\nassign p71=(conv_en==1)?p71_c:((dense_en==1)?p71_d:0);\nassign p72=(conv_en==1)?p72_c:((dense_en==1)?p72_d:0);\nassign p73=(conv_en==1)?p73_c:((dense_en==1)?p73_d:0);\nassign p81=(conv_en==1)?p81_c:((dense_en==1)?p81_d:0);\nassign p82=(conv_en==1)?p82_c:((dense_en==1)?p82_d:0);\nassign p83=(conv_en==1)?p83_c:((dense_en==1)?p83_d:0);\n\nassign w11=(conv_en==1)?w11_c:((dense_en==1)?w11_d:0);\nassign w12=(conv_en==1)?w12_c:((dense_en==1)?w12_d:0);\nassign w13=(conv_en==1)?w13_c:((dense_en==1)?w13_d:0);\nassign w21=(conv_en==1)?w21_c:((dense_en==1)?w21_d:0);\nassign w22=(conv_en==1)?w22_c:((dense_en==1)?w22_d:0);\nassign w23=(conv_en==1)?w23_c:((dense_en==1)?w23_d:0);\nassign w31=(conv_en==1)?w31_c:((dense_en==1)?w31_d:0);\nassign w32=(conv_en==1)?w32_c:((dense_en==1)?w32_d:0);\nassign w33=(conv_en==1)?w33_c:((dense_en==1)?w33_d:0);\nassign w41=(conv_en==1)?w41_c:((dense_en==1)?w41_d:0);\nassign w42=(conv_en==1)?w42_c:((dense_en==1)?w42_d:0);\nassign w43=(conv_en==1)?w43_c:((dense_en==1)?w43_d:0);\nassign w51=(conv_en==1)?w51_c:((dense_en==1)?w51_d:0);\nassign w52=(conv_en==1)?w52_c:((dense_en==1)?w52_d:0);\nassign w53=(conv_en==1)?w53_c:((dense_en==1)?w53_d:0);\nassign w61=(conv_en==1)?w61_c:((dense_en==1)?w61_d:0);\nassign w62=(conv_en==1)?w62_c:((dense_en==1)?w62_d:0);\nassign w63=(conv_en==1)?w63_c:((dense_en==1)?w63_d:0);\nassign w71=(conv_en==1)?w71_c:((dense_en==1)?w71_d:0);\nassign w72=(conv_en==1)?w72_c:((dense_en==1)?w72_d:0);\nassign w73=(conv_en==1)?w73_c:((dense_en==1)?w73_d:0);\nassign w81=(conv_en==1)?w81_c:((dense_en==1)?w81_d:0);\nassign w82=(conv_en==1)?w82_c:((dense_en==1)?w82_d:0);\nassign w83=(conv_en==1)?w83_c:((dense_en==1)?w83_d:0);\n\nassign TOPlvl=TOPlvl_conv;\n\nassign go_conv=(conv_en==1)?go_conv_TOP:((dense_en==1)?go_dense:0);\n\nassign RESULT=(STOP)?res_out:4'b1111;\n\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/addressRAM.v", "content": "module addressRAM(\n\tinput [6:0] step,\n\toutput reg re_weights,\n\toutput reg re_bias,\n\toutput reg [17:0] firstaddr, lastaddr\n);\nparameter convolution_size = 9;\nparameter conv1 = 1*8*3 * convolution_size;\nparameter conv2_1 = 8 * convolution_size + conv1;\nparameter conv2_2 = (8*8*2) + conv2_1;\nparameter conv3_1 = 16 * convolution_size + conv2_2;\nparameter conv3_2 = (16*16*2) + conv3_1;\nparameter conv4_1 = 32 * convolution_size + conv3_2;\nparameter conv4_2 = (32*32) + conv4_1;\nparameter conv5_1 = 32 * convolution_size + conv4_2;\nparameter conv5_2 = (32*32*2) + conv5_1;\nparameter conv6_1 = 64 * convolution_size + conv5_2;\nparameter conv6_2 = (64*64) + conv6_1;\nparameter conv7_1 = 64 * convolution_size + conv6_2;\nparameter conv7_2 = (64*64*2) + conv7_1;\nparameter conv8_1 = 128 * convolution_size + conv7_2;\nparameter conv8_2 = (128*128) + conv8_1;\nparameter conv9_1 = 128 * convolution_size + conv8_2;\nparameter conv9_2 = (128*128) + conv9_1;\nparameter conv10_1 = 128 * convolution_size + conv9_2;\nparameter conv10_2 = (128*128) + conv10_1;\nparameter conv11_1 = 128 * convolution_size + conv10_2;\nparameter conv11_2 = (128*128) + conv11_1;\nparameter conv12_1 = 128 * convolution_size + conv11_2;\nparameter conv12_2 = (128*128) + conv12_1;\nparameter conv13_1 = 128 * convolution_size + conv12_2;\nparameter conv13_2 = (128*128*2) + conv13_1;\nparameter conv14_1 = 256 * convolution_size + conv13_2;\nparameter conv14_2_1 = ((256*256)>>1) + conv14_1;\nparameter conv14_2_2 = ((256*256)>>1) + conv14_2_1;\nparameter predict = 512 + conv14_2_2;\n\n\nparameter bias1 = 8;\nparameter bias2_1 = (8)+8;\nparameter bias2_2 = (16)+16;\nparameter bias3_1 = (32)+16;\nparameter bias3_2 = (48)+32;\nparameter bias4_1 = (80)+32;\nparameter bias4_2 = (112)+32;\nparameter bias5_1 = (144)+32;\nparameter bias5_2 = (176)+64;\nparameter bias6_1 = (240)+64;\nparameter bias6_2 = (304)+64;\nparameter bias7_1 = (368)+64;\nparameter bias7_2 = (432)+128;\nparameter bias8_1 = (560)+128;\nparameter bias8_2 = (688)+128;\nparameter bias9_1 = (816)+128;\nparameter bias9_2 = (944)+128;\nparameter bias10_1 = (1072)+128;\nparameter bias10_2 = (1200)+128;\nparameter bias11_1 = (1328)+128;\nparameter bias11_2 = (1456)+128;\nparameter bias12_1 = (1584)+128;\nparameter bias12_2 = (1712)+128;\nparameter bias13_1 = (1840)+128;\nparameter bias13_2 = (1968)+256;\nparameter bias14_1 = (2224)+256;\nparameter bias14_2_1 = (2480)+(256>>1);\nparameter bias14_2_2 = (2608)+(256>>1);\n\n\nalways @(step)\ncase (step) \n8'd1: begin //weights conv1 \n\t\tfirstaddr = 0;\n\t\tlastaddr = conv1;\n\t\tre_weights = 1;\n\t\tre_bias = 0;\n\t end\n8'd2: begin\t//bias conv1\n\t\tfirstaddr = 0;\n\t\tlastaddr = bias1;\n\t\tre_weights = 0;\n\t\tre_bias = 1;\n end\n8'd4: begin //weights conv2 dw 1\n\t\tfirstaddr = conv1;\n\t\tlastaddr = conv2_1;\n\t\tre_weights = 1;\n\t\tre_bias = 0;\n\t end\n8'd5: begin\t//bias conv2 dw\n\t\tfirstaddr = bias1;\n\t\tlastaddr = bias2_1;\n\t\tre_weights = 0;\n\t\tre_bias = 1;\n end\n8'd7: begin //weights conv2 1x1\n\t\tfirstaddr = conv2_1;\n\t\tlastaddr = conv2_2;\n\t\tre_weights = 1;\n\t\tre_bias = 0;\n\t end\n8'd8: begin //bias conv2 1x1\n\t\tfirstaddr = bias2_1;\n\t\tlastaddr = bias2_2;\n\t\tre_weights = 0;\n\t\tre_bias = 1;\n\t end\n8'd10: begin //weights conv3 dw 2\n\t\tfirstaddr = conv2_2;\n\t\tlastaddr = conv3_1;\n\t\tre_weights = 1;\n\t\tre_bias = 0;\n\t end\n8'd11: begin //bias conv3 DW\n\t\tfirstaddr = bias2_2;\n\t\tlastaddr = bias3_1;\n\t\tre_weights = 0;\n\t\tre_bias = 1;\n\t end\n8'd13: begin //weights conv3 1x1\n \tfirstaddr = conv3_1;\n \tlastaddr = conv3_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd14: begin //bias conv\n \tfirstaddr = bias3_1;\n \tlastaddr = bias3_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd16: begin\n \tfirstaddr = conv3_2; // dw 3\n \tlastaddr = conv4_1;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd17: begin\n \tfirstaddr = bias3_2;\n \tlastaddr = bias4_1;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd19: begin\n \tfirstaddr = conv4_1;\n \tlastaddr = conv4_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd20: begin\n \tfirstaddr = bias4_1;\n \tlastaddr = bias4_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd22: begin\n \tfirstaddr = conv4_2; // dw 4\n \tlastaddr = conv5_1;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd23: begin\n \tfirstaddr = bias4_2;\n \tlastaddr = bias5_1;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd25: begin\n \tfirstaddr = conv5_1;\n \tlastaddr = conv5_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd26: begin\n \tfirstaddr = bias5_1;\n \tlastaddr = bias5_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd28: begin\n \tfirstaddr = conv5_2; // dw 5\n \tlastaddr = conv6_1;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd29: begin\n \tfirstaddr = bias5_2;\n \tlastaddr = bias6_1;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd31: begin\n \tfirstaddr = conv6_1;\n \tlastaddr = conv6_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd32: begin\n \tfirstaddr = bias6_1;\n \tlastaddr = bias6_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd34: begin\n \tfirstaddr = conv6_2; // dw 6\n \tlastaddr = conv7_1;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd35: begin\n \tfirstaddr = bias6_2;\n \tlastaddr = bias7_1;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd37: begin\n \tfirstaddr = conv7_1;\n \tlastaddr = conv7_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd38: begin\n \tfirstaddr = bias7_1;\n \tlastaddr = bias7_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd40: begin\n \tfirstaddr = conv7_2; // dw 7\n \tlastaddr = conv8_1;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd41: begin\n \tfirstaddr = bias7_2;\n \tlastaddr = bias8_1;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd43: begin\n \tfirstaddr = conv8_1;\n \tlastaddr = conv8_2;\n \tre_weights = 1;\n \tre_bias = 0;\n end\n8'd44: begin\n \tfirstaddr = bias8_1;\n \tlastaddr = bias8_2;\n \tre_weights = 0;\n \tre_bias = 1;\n end\n8'd46: begin\n\t firstaddr = conv8_2; // dw 8\n\t lastaddr = conv9_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd47: begin\n\t firstaddr = bias8_2;\n\t lastaddr = bias9_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd49: begin\n\t firstaddr = conv9_1;\n\t lastaddr = conv9_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd50: begin\n\t firstaddr = bias9_1;\n\t lastaddr = bias9_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd52: begin\n\t firstaddr = conv9_2; // dw 9\n\t lastaddr = conv10_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd53: begin\n\t firstaddr = bias9_2;\n\t lastaddr = bias10_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd55: begin\n\t firstaddr = conv10_1;\n\t lastaddr = conv10_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd56: begin\n\t firstaddr = bias10_1;\n\t lastaddr = bias10_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd58: begin\n\t firstaddr = conv10_2; // dw 10\n\t lastaddr = conv11_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd59: begin\n\t firstaddr = bias10_2;\n\t lastaddr = bias11_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd61: begin\n\t firstaddr = conv11_1;\n\t lastaddr = conv11_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd62: begin\n\t firstaddr = bias11_1;\n\t lastaddr = bias11_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd64: begin\n\t firstaddr = conv11_2; // dw 11\n\t lastaddr = conv12_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd65: begin\n\t firstaddr = bias11_2;\n\t lastaddr = bias12_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd67: begin\n\t firstaddr = conv12_1;\n\t lastaddr = conv12_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd68: begin\n\t firstaddr = bias12_1;\n\t lastaddr = bias12_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd70: begin\n\t firstaddr = conv12_2; // dw 12\n\t lastaddr = conv13_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd71: begin\n\t firstaddr = bias12_2;\n\t lastaddr = bias13_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd73: begin\n\t firstaddr = conv13_1;\n\t lastaddr = conv13_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd74: begin\n\t firstaddr = bias13_1;\n\t lastaddr = bias13_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd76: begin\n\t firstaddr = conv13_2; // dw 13\n\t lastaddr = conv14_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd77: begin\n\t firstaddr = bias13_2;\n\t lastaddr = bias14_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd79: begin\n\t firstaddr = conv14_1;\n\t lastaddr = conv14_2_1;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd80: begin\n\t firstaddr = bias14_1;\n\t lastaddr = bias14_2_1;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd82: begin\n\t firstaddr = conv14_2_1;\n\t lastaddr = conv14_2_2;\n\t re_weights = 1;\n\t re_bias = 0;\n end\n8'd83: begin\n\t firstaddr = bias14_2_1;\n\t lastaddr = bias14_2_2;\n\t re_weights = 0;\n\t re_bias = 1;\n end\n8'd85: begin\n\t firstaddr = conv14_2_2;\n\t lastaddr = predict;\n\t re_weights = 1;\n\t re_bias = 0;\n end\ndefault:\n\t\tbegin\n\t\t\tre_weights = 0;\n\t\t\tre_bias = 0;\n\t\tend\nendcase\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/border.v", "content": "module border(\n input clk, go,\n input [14:0] i,\n input [7:0] matrix,\n output reg [1:0] prov\n);\n\talways @(posedge clk)\n\tbegin\t\n\t\tif (go == 1)\n\t\tbegin\n\t\t\tprov = 0;\n\t\t\t\tif ((i == 1*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 2*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 3*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 4*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 5*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 6*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 7*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 8*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 9*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 10*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 11*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 12*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 13*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 14*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 15*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 16*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 17*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 18*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 19*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 20*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 21*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 22*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 23*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 24*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 25*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 26*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 27*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 28*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 29*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 30*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 31*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 32*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 33*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 34*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 35*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 36*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 37*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 38*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 39*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 40*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 41*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 42*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 43*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 44*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 45*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 46*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 47*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 48*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 49*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 50*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 51*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 52*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 53*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 54*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 55*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 56*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 57*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 58*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 59*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 60*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 61*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 62*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 63*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 64*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 65*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 66*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 67*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 68*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 69*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 70*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 71*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 72*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 73*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 74*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 75*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 76*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 77*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 78*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 79*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 80*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 81*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 82*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 83*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 84*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 85*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 86*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 87*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 88*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 89*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 90*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 91*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 92*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 93*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 94*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 95*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 96*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 97*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 98*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 99*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 100*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 101*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 102*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 103*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 104*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 105*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 106*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 107*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 108*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 109*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 110*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 111*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 112*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 113*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 114*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 115*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 116*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 117*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 118*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 119*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 120*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 121*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 122*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 123*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 124*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 125*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 126*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 127*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\t\t\t\tif ((i == 128*matrix-1'b1) && (prov != 2'b10))\tprov = 2'b10;\n\n if ((i == 0*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 1*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 2*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 3*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 4*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 5*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 6*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 7*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 8*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 9*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 10*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 11*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 12*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 13*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 14*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 15*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 16*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 17*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 18*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 19*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 20*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 21*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 22*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 23*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 24*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 25*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 26*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 27*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 28*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 29*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 30*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 31*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 32*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 33*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 34*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 35*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 36*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 37*matrix) && (prov != 2'b11))\t prov = 2'b11;\n if ((i == 38*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 39*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 40*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 41*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 42*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 43*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 44*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 45*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 46*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 47*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 48*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 49*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 50*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 51*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 52*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 53*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 54*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 55*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 56*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 57*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 58*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 59*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 60*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 61*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 62*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 63*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 64*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 65*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 66*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 67*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 68*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 69*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 70*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 71*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 72*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 73*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 74*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 75*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 76*matrix) && (prov != 2'b11))\t\t prov = 2'b11;\n if ((i == 77*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 78*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 79*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 80*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 81*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 82*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 83*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 84*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 85*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 86*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 87*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 88*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 89*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 90*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 91*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 92*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 93*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 94*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 95*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 96*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 97*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 98*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 99*matrix) && (prov != 2'b11))\t \tprov = 2'b11;\n if ((i == 100*matrix) && (prov != 2'b11))\t prov = 2'b11;\n if ((i == 101*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 102*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 103*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 104*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 105*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 106*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 107*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 108*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 109*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 110*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 111*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 112*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 113*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 114*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 115*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 116*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 117*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 118*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 119*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 120*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 121*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 122*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 123*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 124*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 125*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 126*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 127*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n if ((i == 128*matrix) && (prov != 2'b11))\t\tprov = 2'b11;\n\t\tend\n\t\telse\n\t\t\tprov = 0;\n\tend\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/conv.v", "content": "module conv(clk,Y1,prov,matrix,matrix2,i,up_perm,down_perm,p1,p2,p3,w1,w2,w3,conv_en,dense_en,stride_plus_prov);\n\nparameter SIZE=0;\nparameter SIZE_address_pix=18;\nparameter SIZE_weights=0;\n\ninput clk;\noutput reg signed [32-1:0] Y1;\ninput [1:0] prov;\ninput [7:0] matrix;\ninput [14:0] matrix2;\ninput [14:0] i;\ninput up_perm,down_perm;\ninput signed [SIZE-1:0] p1,p2,p3;\ninput signed [SIZE_weights-1:0] w1,w2,w3;\ninput conv_en;\ninput dense_en;\ninput [SIZE_address_pix-1:0] stride_plus_prov;\n\nwire up,down;\n\nassign up = (((i+stride_plus_prov)<=matrix-1'b1)&&(up_perm))?1'b1:1'b0;\nassign down = (((i+stride_plus_prov)>=matrix2-matrix)&&(down_perm))?1'b1:1'b0;\n\nalways @(posedge clk)\n begin\n\t\tif (conv_en==1)\n\t\t\tbegin\n\t\t\t\tY1=0;\n\t\t\t\tif ((prov!=2'b11)&&(!up)&&(!down)) Y1 = Y1+(p1*w1);\n\t\t\t\tif ((!up)&&(!down)) Y1 = Y1+(p2*w2);\n\t\t\t\tif ((prov!=2'b10)&&(!up)&&(!down)) Y1 = Y1+(p3*w3);\n\t\t\tend\n end\n\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/conv_TOP.v", "content": "module conv_TOP(clk,conv_en,STOP,memstartp,memstartw,memstartzap,read_addressp,write_addressp,read_addresstp,write_addresstp,read_addressw,we,re_wb,re,we_t,re_t,qp,qtp,qw,dp,dtp,prov,matrix,matrix2,i_to_prov,lvl,slvl,mem,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83,p0_1,p0_2,p0_3,p1_1,p1_2,p1_3,p2_1,p2_2,p2_3,p3_1,p3_2,p3_3,p4_1,p4_2,p4_3,p5_1,p5_2,p5_3,p6_1,p6_2,p6_3,p7_1,p7_2,p7_3,go,up_perm,down_perm,num,filt,bias,glob_average_en,step,stride,depthwise,onexone,q_bias,read_addressb,memstartb,stride_plus_prov);\n\nparameter SIZE_1=0;\nparameter SIZE_2=0;\nparameter SIZE_3=0;\nparameter SIZE_4=0;\nparameter SIZE_5=0;\nparameter SIZE_6=0;\nparameter SIZE_7=0;\nparameter SIZE_8=0;\nparameter SIZE_address_pix=13;\nparameter SIZE_address_pix_t=12;\nparameter SIZE_address_wei=13;\nparameter SIZE_weights=0;\nparameter SIZE_bias=0;\n\ninput clk,conv_en,glob_average_en;\ninput [1:0] prov;\ninput [7:0] matrix;\ninput [14:0] matrix2;\ninput [SIZE_address_pix-1:0] memstartp;\ninput [SIZE_address_wei-1:0] memstartw;\ninput [SIZE_address_pix-1:0] memstartzap;\ninput [10:0]\t\t\t\t memstartb;\ninput [8:0] lvl;\ninput [8:0] slvl;\noutput reg [SIZE_address_pix-1:0] read_addressp;\noutput reg [SIZE_address_pix_t-1:0] read_addresstp;\noutput reg [SIZE_address_wei-1:0] read_addressw;\noutput reg [10:0]\t\t\t\t read_addressb;\noutput reg [SIZE_address_pix-1:0] write_addressp;\noutput reg [SIZE_address_pix_t-1:0] write_addresstp;\noutput reg we,re,re_wb;\noutput reg we_t,re_t;\ninput signed [SIZE_8-1:0] qp;\ninput signed [32*8-1:0] qtp;\ninput signed [SIZE_weights*9-1:0] qw;\ninput signed [SIZE_bias-1:0] q_bias;\noutput signed [SIZE_8-1:0] dp;\noutput signed [32*8-1:0] dtp;\noutput reg STOP;\noutput reg [14:0] i_to_prov;\ninput signed [32-1:0] Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8;\noutput reg signed [SIZE_weights-1:0] w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83;\noutput reg signed [SIZE_1-1:0] p0_1,p0_2,p0_3,p1_1,p1_2,p1_3,p2_1,p2_2,p2_3,p3_1,p3_2,p3_3,p4_1,p4_2,p4_3,p5_1,p5_2,p5_3,p6_1,p6_2,p6_3,p7_1,p7_2,p7_3;\noutput reg go;\noutput reg up_perm,down_perm;\ninput [2:0] num;\ninput [8:0] mem;\ninput [8:0] filt;\ninput bias;\ninput [6:0] step;\ninput [1:0] stride;\noutput reg [SIZE_address_pix-1:0] stride_plus_prov;\n\ninput depthwise,onexone;\n\nreg signed [SIZE_weights-1:0] w11_pre,w12_pre,w13_pre,w14_pre,w15_pre,w16_pre,w17_pre,w18_pre,w19_pre;\nreg signed [SIZE_weights-1:0] w21_pre,w22_pre,w23_pre,w24_pre,w25_pre,w26_pre,w27_pre,w28_pre,w29_pre;\nreg signed [SIZE_weights-1:0] w31_pre,w32_pre,w33_pre,w34_pre,w35_pre,w36_pre,w37_pre,w38_pre,w39_pre;\nreg signed [SIZE_weights-1:0] w41_pre,w42_pre,w43_pre,w44_pre,w45_pre,w46_pre,w47_pre,w48_pre,w49_pre;\nreg signed [SIZE_weights-1:0] w51_pre,w52_pre,w53_pre,w54_pre,w55_pre,w56_pre,w57_pre,w58_pre,w59_pre;\nreg signed [SIZE_weights-1:0] w61_pre,w62_pre,w63_pre,w64_pre,w65_pre,w66_pre,w67_pre,w68_pre,w69_pre;\nreg signed [SIZE_weights-1:0] w71_pre,w72_pre,w73_pre,w74_pre,w75_pre,w76_pre,w77_pre,w78_pre,w79_pre;\nreg signed [SIZE_weights-1:0] w81_pre,w82_pre,w83_pre,w84_pre,w85_pre,w86_pre,w87_pre,w88_pre,w89_pre;\nreg signed [SIZE_1-1:0]p0_pre,p1_pre,p2_pre,p3_pre,p4_pre,p5_pre,p6_pre,p7_pre,p8_pre,p9_pre,p10_pre,p11_pre,p12_pre,p13_pre,p14_pre,p15_pre;\nreg signed [SIZE_1-1:0] res_out_1,res_out_2,res_out_3,res_out_4,res_out_5,res_out_6,res_out_7,res_out_8;\nreg signed [32-1:0] res1,res2,res3,res4,res5,res6,res7,res8;\nreg signed [32-1:0] res_old_1,res_old_2,res_old_3,res_old_4,res_old_5,res_old_6,res_old_7,res_old_8;\nreg signed [21:0] glob_average_perem_1,glob_average_perem_2,glob_average_perem_3,glob_average_perem_4,glob_average_perem_5,glob_average_perem_6,glob_average_perem_7,glob_average_perem_8;\nwire signed [SIZE_1-1:0] glob_average_perem_1_1,glob_average_perem_2_1,glob_average_perem_3_1,glob_average_perem_4_1,glob_average_perem_5_1,glob_average_perem_6_1,glob_average_perem_7_1,glob_average_perem_8_1;\n\nreg signed [SIZE_1-1:0]buff0_0 [2:0], buff1_0 [2:0], buff2_0 [2:0], buff3_0 [2:0], buff4_0 [2:0], buff5_0 [2:0], buff6_0 [2:0], buff7_0 [2:0];\nreg signed [SIZE_1-1:0]buff0_1 [2:0], buff1_1 [2:0], buff2_1 [2:0], buff3_1 [2:0], buff4_1 [2:0], buff5_1 [2:0], buff6_1 [2:0], buff7_1 [2:0];\nreg signed [SIZE_1-1:0]buff0_2 [2:0], buff1_2 [2:0], buff2_2 [2:0], buff3_2 [2:0], buff4_2 [2:0], buff5_2 [2:0], buff6_2 [2:0], buff7_2 [2:0];\n\nreg [4:0] marker;\nreg zagryzka_weight;\nreg [15:0] i;\nreg [15:0] i_onexone,i_onexone_1;\nwire [15:0] i_onexone_plus1;\nassign i_onexone_plus1 = i_onexone + 1'b1;\nreg [SIZE_address_pix-1:0] stride_plus,next_number,next_number_prov;\n\nreg signed [19-1:0] res_bias_check_1,res_bias_check_2,res_bias_check_3,res_bias_check_4,res_bias_check_5,res_bias_check_6,res_bias_check_7,res_bias_check_8;\n\nreg signed [SIZE_bias-1:0] data_bias_1,data_bias_2,data_bias_3,data_bias_4,data_bias_5,data_bias_6,data_bias_7,data_bias_8;\n\ninitial zagryzka_weight=0;\ninitial marker=0;\n\nwire [15:0] line_stride;\n\nassign line_stride=matrix>>(stride-1);\n\nalways @(posedge clk)\nbegin\nif (conv_en==1)\n\tbegin\n\t\tif (zagryzka_weight==0)\n\t\tbegin\n\t\t next_number = matrix;\n\t\t next_number_prov = matrix;\n\t\t if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus=0;\n\t\t else stride_plus=matrix;\n\t\t if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus_prov=0;\n\t\t else stride_plus_prov=matrix;\n\t\t case (marker)\n\t\t\t\t0: begin\n\t\t\t\t re_wb=1;\n\t\t\t\t read_addressw=memstartw+0*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+0;\n\t\t\t\tend\n\t\t\t\t1: begin\n\t\t\t\t read_addressw=memstartw+1*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+1;\n\t\t\t\tend\n\t\t\t\t2: begin\n\t\t\t\t read_addressw=memstartw+2*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+2;\n\t\t\t\t w11_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w12_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w13_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w14_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w15_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w16_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w17_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w18_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w19_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_1 = q_bias;\n\t\t\t\tend\n\t\t\t\t3: begin\n\t\t\t\t read_addressw=memstartw+3*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+3;\n\t\t\t\t w21_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w22_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w23_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w24_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w25_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w26_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w27_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w28_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w29_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_2 = q_bias;\n\t\t\t\tend\n\t\t\t\t4: begin\n\t\t\t\t read_addressw=memstartw+4*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+4;\n\t\t\t\t w31_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w32_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w33_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w34_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w35_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w36_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w37_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w38_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w39_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_3 = q_bias;\n\t\t\t\tend\n\t\t\t\t5: begin\n\t\t\t\t read_addressw=memstartw+5*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+5;\n\t\t\t\t w41_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w42_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w43_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w44_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w45_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w46_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w47_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w48_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w49_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_4 = q_bias;\n\t\t\t\tend\n\t\t\t\t6: begin\n\t\t\t\t read_addressw=memstartw+6*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+6;\n\t\t\t\t w51_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w52_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w53_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w54_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w55_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w56_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w57_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w58_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w59_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_5 = q_bias;\n\t\t\t\tend\n\t\t\t\t7: begin\n\t\t\t\t read_addressw=memstartw+7*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n\t\t\t\t read_addressb=memstartb+7;\n\t\t\t\t w61_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w62_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w63_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w64_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w65_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w66_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w67_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w68_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w69_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_6 = q_bias;\n\t\t\t\tend\n\t\t\t\t8: begin\n\t\t\t\t w71_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w72_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w73_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w74_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w75_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w76_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w77_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w78_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w79_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_7 = q_bias;\n\t\t\t\tend\n\t\t\t\t9: begin\n\t\t\t\t w81_pre=qw[SIZE_weights-1:0]; \n\t\t\t\t w82_pre=qw[SIZE_weights*2-1:SIZE_weights]; \n\t\t\t\t w83_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; \n\t\t\t\t w84_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; \n\t\t\t\t w85_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; \n\t\t\t\t w86_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; \n\t\t\t\t w87_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; \n\t\t\t\t w88_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; \n\t\t\t\t w89_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; \n\n\t\t\t\t data_bias_8 = q_bias;\n\t\t\t\t zagryzka_weight=1; re_wb=0; marker=-1;\n\t\t\t\tend\n\t\t\t\tdefault: \n\t\t\t\t\tbegin\n\t\t\t\t\t\tread_addressw=0;\n\t\t\t\t\t\tread_addressb=0;\n\t\t\t\t\t\tre_wb=0;\n\t\t\t\t\t\t$display(\"Check zagryzka_weight\");\n\t\t\t\t\tend\n\t\tendcase\n\t\tmarker=marker+1;\n\t\tend\n\t\telse\n\t\tbegin\n\t\t\tre=1;\n\t\t\tcase (marker)\n\t\t\t\t0: begin\t\n\t\t\t\t\t\t\t\tre_t=0;\n\t\t\t\t\t\t\t\tif ((stride==2)&&(i==next_number))\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tstride_plus=stride_plus+matrix;\n\t\t\t\t\t\t\t\t\t\tnext_number = matrix+next_number;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\n\t\t\t\t\t\t\t\telse read_addressp=i+memstartp+stride_plus;\n\n\t\t\t\t\t\t\t\tif (onexone)\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tp0_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp0_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp0_3=0;\n\t\t\t\t\t\t\t\t\t\tp1_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp1_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp1_3=0;\n\t\t\t\t\t\t\t\t\t\tp2_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp2_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp2_3=0;\n\t\t\t\t\t\t\t\t\t\tp3_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp3_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp3_3=0;\n\t\t\t\t\t\t\t\t\t\tp4_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp4_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp4_3=0;\n\t\t\t\t\t\t\t\t\t\tp5_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp5_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp5_3=0;\n\t\t\t\t\t\t\t\t\t\tp6_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp6_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp6_3=0;\n\t\t\t\t\t\t\t\t\t\tp7_1=p6_pre;\n\t\t\t\t\t\t\t\t\t\tp7_2=p7_pre;\n\t\t\t\t\t\t\t\t\t\tp7_3=0;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tif (depthwise)\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tbuff0_2[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff1_2[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff2_2[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff3_2[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff4_2[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff5_2[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff6_2[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff7_2[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tif (((i+stride_plus-1)=matrix-1)\tread_addressp=i-matrix+memstartp+stride_plus;\n\n\t\t\t\t\t\t\t\tres1=res1+Y1;\n\t\t\t\t\t\t\t\tres2=res2+Y2;\n\t\t\t\t\t\t\t\tres3=res3+Y3;\n\t\t\t\t\t\t\t\tres4=res4+Y4;\n\t\t\t\t\t\t\t\tres5=res5+Y5;\n\t\t\t\t\t\t\t\tres6=res6+Y6;\n\t\t\t\t\t\t\t\tres7=res7+Y7;\n\t\t\t\t\t\t\t\tres8=res8+Y8;\n\t\t\t\t\t\t\t\tif ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1))) \n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tres_old_1=qtp[32*8-1:32*7];\n\t\t\t\t\t\t\t\t\t\tres_old_2=qtp[32*7-1:32*6];\n\t\t\t\t\t\t\t\t\t\tres_old_3=qtp[32*6-1:32*5];\n\t\t\t\t\t\t\t\t\t\tres_old_4=qtp[32*5-1:32*4];\n\t\t\t\t\t\t\t\t\t\tres_old_5=qtp[32*4-1:32*3];\n\t\t\t\t\t\t\t\t\t\tres_old_6=qtp[32*3-1:32*2];\n\t\t\t\t\t\t\t\t\t\tres_old_7=qtp[32*2-1:32*1];\n\t\t\t\t\t\t\t\t\t\tres_old_8=qtp[32*1-1:32*0];\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tgo=0;\n\t\t\t\t\t\t\t\ti_to_prov=i_to_prov+1'b1;\n\t\t\t\t\t\t\t\tif ((stride==2)&&(i_to_prov==next_number_prov)) \n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tstride_plus_prov=stride_plus_prov+matrix;\n\t\t\t\t\t\t\t\t\t\tnext_number_prov = matrix+next_number_prov;\n\t\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\t\tbuff0_2[0]=buff0_2[1];\n\t\t\t\t\t\t\t\tbuff0_1[0]=buff0_1[1];\n\t\t\t\t\t\t\t\tbuff0_0[0]=buff0_0[1];\n\t\t\t\t\t\t\t\tbuff0_2[1]=buff0_2[2];\n\t\t\t\t\t\t\t\tbuff0_1[1]=buff0_1[2];\n\t\t\t\t\t\t\t\tbuff0_0[1]=buff0_0[2];\n\n\t\t\t\t\t\t\t\tbuff1_2[0]=buff1_2[1];\n\t\t\t\t\t\t\t\tbuff1_1[0]=buff1_1[1];\n\t\t\t\t\t\t\t\tbuff1_0[0]=buff1_0[1];\n\t\t\t\t\t\t\t\tbuff1_2[1]=buff1_2[2];\n\t\t\t\t\t\t\t\tbuff1_1[1]=buff1_1[2];\n\t\t\t\t\t\t\t\tbuff1_0[1]=buff1_0[2];\n\n\t\t\t\t\t\t\t\tbuff2_2[0]=buff2_2[1];\n\t\t\t\t\t\t\t\tbuff2_1[0]=buff2_1[1];\n\t\t\t\t\t\t\t\tbuff2_0[0]=buff2_0[1];\n\t\t\t\t\t\t\t\tbuff2_2[1]=buff2_2[2];\n\t\t\t\t\t\t\t\tbuff2_1[1]=buff2_1[2];\n\t\t\t\t\t\t\t\tbuff2_0[1]=buff2_0[2];\n\n\t\t\t\t\t\t\t\tbuff3_2[0]=buff3_2[1];\n\t\t\t\t\t\t\t\tbuff3_1[0]=buff3_1[1];\n\t\t\t\t\t\t\t\tbuff3_0[0]=buff3_0[1];\n\t\t\t\t\t\t\t\tbuff3_2[1]=buff3_2[2];\n\t\t\t\t\t\t\t\tbuff3_1[1]=buff3_1[2];\n\t\t\t\t\t\t\t\tbuff3_0[1]=buff3_0[2];\n\n\t\t\t\t\t\t\t\tbuff4_2[0]=buff4_2[1];\n\t\t\t\t\t\t\t\tbuff4_1[0]=buff4_1[1];\n\t\t\t\t\t\t\t\tbuff4_0[0]=buff4_0[1];\n\t\t\t\t\t\t\t\tbuff4_2[1]=buff4_2[2];\n\t\t\t\t\t\t\t\tbuff4_1[1]=buff4_1[2];\n\t\t\t\t\t\t\t\tbuff4_0[1]=buff4_0[2];\n\n\t\t\t\t\t\t\t\tbuff5_2[0]=buff5_2[1];\n\t\t\t\t\t\t\t\tbuff5_1[0]=buff5_1[1];\n\t\t\t\t\t\t\t\tbuff5_0[0]=buff5_0[1];\n\t\t\t\t\t\t\t\tbuff5_2[1]=buff5_2[2];\n\t\t\t\t\t\t\t\tbuff5_1[1]=buff5_1[2];\n\t\t\t\t\t\t\t\tbuff5_0[1]=buff5_0[2];\n\n\t\t\t\t\t\t\t\tbuff6_2[0]=buff6_2[1];\n\t\t\t\t\t\t\t\tbuff6_1[0]=buff6_1[1];\n\t\t\t\t\t\t\t\tbuff6_0[0]=buff6_0[1];\n\t\t\t\t\t\t\t\tbuff6_2[1]=buff6_2[2];\n\t\t\t\t\t\t\t\tbuff6_1[1]=buff6_1[2];\n\t\t\t\t\t\t\t\tbuff6_0[1]=buff6_0[2];\n\n\t\t\t\t\t\t\t\tbuff7_2[0]=buff7_2[1];\n\t\t\t\t\t\t\t\tbuff7_1[0]=buff7_1[1];\n\t\t\t\t\t\t\t\tbuff7_0[0]=buff7_0[1];\n\t\t\t\t\t\t\t\tbuff7_2[1]=buff7_2[2];\n\t\t\t\t\t\t\t\tbuff7_1[1]=buff7_1[2];\n\t\t\t\t\t\t\t\tbuff7_0[1]=buff7_0[2];\n\n\t\t\t\t\tend\n\t\t\t\t2: begin\n\t\t\t\t\t\t\tif (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\n\t\t\t\t\t\t\telse\tif ((i+stride_plus)=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1)))\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\tif (onexone) write_addresstp=i_onexone-2;\n\t\t\t\t\t\t\t\telse write_addresstp=(i>>(stride-1))-1;\n\t\t\t\t\t\t\t\tif (glob_average_en) write_addressp=memstartzap;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tif (onexone)\twrite_addressp=memstartzap+i_onexone-2;\n\t\t\t\t\t\t\t\t\t\telse\t\t\twrite_addressp=memstartzap+((i-2)>>(stride-1));\n\t\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\t\tif (((onexone && (i_onexone_1 == 0)) || !onexone)&&(!bias)) we_t=1;\n\n\t\t\t\t\t\t\t\tres1=res1+Y1;\n\t\t\t\t\t\t\t\tres2=res2+Y2;\n\t\t\t\t\t\t\t\tres3=res3+Y3;\n\t\t\t\t\t\t\t\tres4=res4+Y4;\n\t\t\t\t\t\t\t\tres5=res5+Y5;\n\t\t\t\t\t\t\t\tres6=res6+Y6;\n\t\t\t\t\t\t\t\tres7=res7+Y7;\n\t\t\t\t\t\t\t\tres8=res8+Y8;\n\n\t\t\t\t\t\t\t\tif ((lvl!=0)&&(!depthwise))\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tres1=res1+res_old_1;\n\t\t\t\t\t\t\t\t\t\tres2=res2+res_old_2;\n\t\t\t\t\t\t\t\t\t\tres3=res3+res_old_3;\n\t\t\t\t\t\t\t\t\t\tres4=res4+res_old_4;\n\t\t\t\t\t\t\t\t\t\tres5=res5+res_old_5;\n\t\t\t\t\t\t\t\t\t\tres6=res6+res_old_6;\n\t\t\t\t\t\t\t\t\t\tres7=res7+res_old_7;\n\t\t\t\t\t\t\t\t\t\tres8=res8+res_old_8;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (bias)\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tres1=res1+(data_bias_1<<13);\n\t\t\t\t\t\t\t\t\t\tres2=res2+(data_bias_2<<13);\n\t\t\t\t\t\t\t\t\t\tres3=res3+(data_bias_3<<13);\n\t\t\t\t\t\t\t\t\t\tres4=res4+(data_bias_4<<13);\n\t\t\t\t\t\t\t\t\t\tres5=res5+(data_bias_5<<13);\n\t\t\t\t\t\t\t\t\t\tres6=res6+(data_bias_6<<13);\n\t\t\t\t\t\t\t\t\t\tres7=res7+(data_bias_7<<13);\n\t\t\t\t\t\t\t\t\t\tres8=res8+(data_bias_8<<13);\n\n\t\t\t\t\t\t\t\t\t\tif (res1<0) res1=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res2<0) res2=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res3<0) res3=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res4<0) res4=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res5<0) res5=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res6<0) res6=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res7<0) res7=0; //RELU\n\t\t\t\t\t\t\t\t\t\tif (res8<0) res8=0; //RELU\n\n\t\t\t\t\t\t\t\t\t\tres_bias_check_1=res1[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_2=res2[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_3=res3[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_4=res4[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_5=res5[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_6=res6[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_7=res7[32-1-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tres_bias_check_8=res8[32-1-2:SIZE_1-2];\n\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_1>(2**(SIZE_1-1))-1) res_out_1=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_1=res1[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_2>(2**(SIZE_1-1))-1) res_out_2=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_2=res2[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_3>(2**(SIZE_1-1))-1) res_out_3=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_3=res3[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_4>(2**(SIZE_1-1))-1) res_out_4=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_4=res4[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_5>(2**(SIZE_1-1))-1) res_out_5=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_5=res5[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_6>(2**(SIZE_1-1))-1) res_out_6=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_6=res6[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_7>(2**(SIZE_1-1))-1) res_out_7=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_7=res7[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\t\t\t\t\t\t\t\t\t\tif (res_bias_check_8>(2**(SIZE_1-1))-1) res_out_8=(2**(SIZE_1-1))-1;\n\t\t\t\t\t\t\t\t\t\telse res_out_8=res8[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n\n\t\t\t\t\t\t\t\t\t\tif ((glob_average_en)&&(i_onexone_1 == 0))\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_1 = glob_average_perem_1 + res_out_1;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_2 = glob_average_perem_2 + res_out_2;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_3 = glob_average_perem_3 + res_out_3;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_4 = glob_average_perem_4 + res_out_4;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_5 = glob_average_perem_5 + res_out_5;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_6 = glob_average_perem_6 + res_out_6;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_7 = glob_average_perem_7 + res_out_7;\n\t\t\t\t\t\t\t\t\t\t\t\tglob_average_perem_8 = glob_average_perem_8 + res_out_8;\n\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\tif ((onexone && (i_onexone_1 == 0)) || !onexone) we=1;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t3: begin\n\t\t\t\t\t\t\t\tre_t=1;\n\t\t\t\t\t\t\t\tif (onexone) read_addresstp=i_onexone-1;\n\t\t\t\t\t\t\t\telse read_addresstp=(i>>(stride-1))-1;\n\n\t\t\t\t\t\t\t\tif (onexone)\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tp8_pre = qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\tp9_pre = qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\tp10_pre = qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\tp11_pre = qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\tp12_pre = qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\tp13_pre = qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\tp14_pre = qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\tp15_pre = qp[SIZE_1-1:0];\n\n\t\t\t\t\t\t\t\t\t\tp0_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp0_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp0_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp1_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp1_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp1_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp2_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp2_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp2_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp3_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp3_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp3_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp4_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp4_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp4_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp5_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp5_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp5_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp6_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp6_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp6_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\t\tp7_1=p3_pre;\n\t\t\t\t\t\t\t\t\t\tp7_2=p4_pre;\n\t\t\t\t\t\t\t\t\t\tp7_3=p5_pre;\n\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\tif (depthwise)\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\tif ((i+stride_plus)>=matrix-1)\n\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\tif ({lvl[2],lvl[1],lvl[0]}==3'd0) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_8-1:SIZE_7];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd1) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_7-1:SIZE_6];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd2) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_6-1:SIZE_5];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd3) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_5-1:SIZE_4];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd4) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_4-1:SIZE_3];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd5) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_3-1:SIZE_2];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd6) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_2-1:SIZE_1];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\t\telse if ({lvl[2],lvl[1],lvl[0]}==3'd7) \n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=qp[SIZE_1-1:0];\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff0_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff1_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff2_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff3_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff4_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff5_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff6_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tbuff7_0[2]=0;\n\t\t\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\tp0_1=buff0_0[0];\n\t\t\t\t\t\t\t\t\t\tp0_2=buff0_0[1];\n\t\t\t\t\t\t\t\t\t\tp0_3=buff0_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp1_1=buff1_0[0];\n\t\t\t\t\t\t\t\t\t\tp1_2=buff1_0[1];\n\t\t\t\t\t\t\t\t\t\tp1_3=buff1_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp2_1=buff2_0[0];\n\t\t\t\t\t\t\t\t\t\tp2_2=buff2_0[1];\n\t\t\t\t\t\t\t\t\t\tp2_3=buff2_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp3_1=buff3_0[0];\n\t\t\t\t\t\t\t\t\t\tp3_2=buff3_0[1];\n\t\t\t\t\t\t\t\t\t\tp3_3=buff3_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp4_1=buff4_0[0];\n\t\t\t\t\t\t\t\t\t\tp4_2=buff4_0[1];\n\t\t\t\t\t\t\t\t\t\tp4_3=buff4_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp5_1=buff5_0[0];\n\t\t\t\t\t\t\t\t\t\tp5_2=buff5_0[1];\n\t\t\t\t\t\t\t\t\t\tp5_3=buff5_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp6_1=buff6_0[0];\n\t\t\t\t\t\t\t\t\t\tp6_2=buff6_0[1];\n\t\t\t\t\t\t\t\t\t\tp6_3=buff6_0[2];\n\n\t\t\t\t\t\t\t\t\t\tp7_1=buff7_0[0];\n\t\t\t\t\t\t\t\t\t\tp7_2=buff7_0[1];\n\t\t\t\t\t\t\t\t\t\tp7_3=buff7_0[2];\n\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tw11=(onexone)?w16_pre:w19_pre;\n\t\t\t\t\t\t\t\tw12=(onexone)?w15_pre:w18_pre;\n\t\t\t\t\t\t\t\tw13=(onexone)?w14_pre:w17_pre;\n\n\t\t\t\t\t\t\t\tw21=(onexone)?w26_pre:w29_pre;\n\t\t\t\t\t\t\t\tw22=(onexone)?w25_pre:w28_pre;\n\t\t\t\t\t\t\t\tw23=(onexone)?w24_pre:w27_pre;\n\n\t\t\t\t\t\t\t\tw31=(onexone)?w36_pre:w39_pre;\n\t\t\t\t\t\t\t\tw32=(onexone)?w35_pre:w38_pre;\n\t\t\t\t\t\t\t\tw33=(onexone)?w34_pre:w37_pre;\n\n\t\t\t\t\t\t\t\tw41=(onexone)?w46_pre:w49_pre;\n\t\t\t\t\t\t\t\tw42=(onexone)?w45_pre:w48_pre;\n\t\t\t\t\t\t\t\tw43=(onexone)?w44_pre:w47_pre;\n\n\t\t\t\t\t\t\t\tw51=(onexone)?w56_pre:w59_pre;\n\t\t\t\t\t\t\t\tw52=(onexone)?w55_pre:w58_pre;\n\t\t\t\t\t\t\t\tw53=(onexone)?w54_pre:w57_pre;\n\n\t\t\t\t\t\t\t\tw61=(onexone)?w66_pre:w69_pre;\n\t\t\t\t\t\t\t\tw62=(onexone)?w65_pre:w68_pre;\n\t\t\t\t\t\t\t\tw63=(onexone)?w64_pre:w67_pre;\n\n\t\t\t\t\t\t\t\tw71=(onexone)?w76_pre:w79_pre;\n\t\t\t\t\t\t\t\tw72=(onexone)?w75_pre:w78_pre;\n\t\t\t\t\t\t\t\tw73=(onexone)?w74_pre:w77_pre;\n\n\t\t\t\t\t\t\t\tw81=(onexone)?w86_pre:w89_pre;\n\t\t\t\t\t\t\t\tw82=(onexone)?w85_pre:w88_pre;\n\t\t\t\t\t\t\t\tw83=(onexone)?w84_pre:w87_pre;\n\n\t\t\t\t\t\t\t\tif (onexone) up_perm=0; else up_perm=1;\n\t\t\t\t\t\t\t\tdown_perm=0;\n\t\t\t\t\t\t\t\twe_t=0;\n\t\t\t\t\t\t\t\twe=0;\n\t\t\t\t\tend\t\t\n\t\t\tdefault: $display(\"Check case conv_TOP\");\n\t\t\tendcase\n\n\t\t\tif (marker!=3) marker=marker+1;\n\t\t\telse begin \n\t\t\t\t\tmarker=0; \n\t\t\t\t\tif (((i>2)\n\t\t\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t\t\ti_onexone = i_onexone + 1;\n\t\t\t\t\t\t\t\t\t\t\ti_onexone_1 = 0;\n\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\telse\ti_onexone_1 = i_onexone_1 + 1;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\telse STOP=1; \n\t\t\t\t end\n\t\tend\n\tend\nelse \n\tbegin\n\t\ti=0;\n\t\ti_to_prov=-2;\n\t\tstride_plus=0;\n\t\tnext_number=matrix;\n\t\tzagryzka_weight=0;\n\t\tSTOP=0;\n\t\tre=0;\n\t\tre_t=0;\n\t\tgo=0;\n\t\tmarker=0;\n\t\tglob_average_perem_1=0;\n\t\tglob_average_perem_2=0;\n\t\tglob_average_perem_3=0;\n\t\tglob_average_perem_4=0;\n\t\tglob_average_perem_5=0;\n\t\tglob_average_perem_6=0;\n\t\tglob_average_perem_7=0;\n\t\tglob_average_perem_8=0;\n\t\ti_onexone = 0;\n\t\ti_onexone_1 = 0;\n\t\tread_addressw=0;\n\t\tread_addressb=0;\n\t\tre_wb=0;\n\tend\nend\nassign glob_average_perem_1_1=glob_average_perem_1>>4;\nassign glob_average_perem_2_1=glob_average_perem_2>>4;\nassign glob_average_perem_3_1=glob_average_perem_3>>4;\nassign glob_average_perem_4_1=glob_average_perem_4>>4;\nassign glob_average_perem_5_1=glob_average_perem_5>>4;\nassign glob_average_perem_6_1=glob_average_perem_6>>4;\nassign glob_average_perem_7_1=glob_average_perem_7>>4;\nassign glob_average_perem_8_1=glob_average_perem_8>>4;\nassign dp={(glob_average_en?glob_average_perem_1_1:res_out_1),\n(glob_average_en?glob_average_perem_2_1:res_out_2),\n(glob_average_en?glob_average_perem_3_1:res_out_3),\n(glob_average_en?glob_average_perem_4_1:res_out_4),\n(glob_average_en?glob_average_perem_5_1:res_out_5),\n(glob_average_en?glob_average_perem_6_1:res_out_6),\n(glob_average_en?glob_average_perem_7_1:res_out_7),\n(glob_average_en?glob_average_perem_8_1:res_out_8)\n};\nassign dtp={res1,res2,res3,res4,res5,res6,res7,res8};\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/dense.v", "content": "module dense(clk, dense_en, STOP, in, out, we, re_p, re_w, read_addressp, read_addressw, write_addressp, memstartp, memstartzap, qp, qw, res, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, w11, w12, w13, w21, w22, w23, w31, w32, w33, w41, w42, w43, w51, w52, w53, w61, w62, w63, w71, w72, w73, w81, w82, w83, p11, p12, p13, p21, p22, p23, p31, p32, p33, p41, p42, p43, p51, p52, p53, p61, p62, p63, p71, p72, p73, p81, p82, p83, go, nozero);\n\nparameter num_conv=0;\n\nparameter SIZE_1=0;\nparameter SIZE_2=0;\nparameter SIZE_3=0;\nparameter SIZE_4=0;\nparameter SIZE_5=0;\nparameter SIZE_6=0;\nparameter SIZE_7=0;\nparameter SIZE_8=0;\nparameter SIZE_address_pix=0;\nparameter SIZE_address_wei=0;\nparameter SIZE_weights=0;\n\ninput clk,dense_en;\noutput reg STOP;\ninput [8:0] in;\ninput [1:0] out;\noutput reg we,re_p,re_w;\noutput reg [SIZE_address_pix-1:0] read_addressp;\noutput reg [SIZE_address_wei-1:0] read_addressw;\noutput reg [SIZE_address_pix-1:0] write_addressp;\ninput [SIZE_address_pix-1:0] memstartp,memstartzap;\ninput signed [SIZE_8-1:0] qp;\ninput signed [SIZE_weights*9-1:0] qw;\noutput reg signed [SIZE_8-1:0] res;\ninput signed [32-1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8;\noutput reg signed [SIZE_weights - 1:0] w11, w12, w13, w21, w22, w23, w31, w32, w33, w41, w42, w43, w51, w52, w53, w61, w62, w63, w71, w72, w73, w81, w82, w83;\noutput reg signed [SIZE_1-1:0] p11, p12, p13, p21, p22, p23, p31, p32, p33, p41, p42, p43, p51, p52, p53, p61, p62, p63, p71, p72, p73, p81, p82, p83;\noutput reg go;\ninput nozero;\n\nreg signed[SIZE_weights - 1:0] w11_pre, w12_pre, w13_pre, w14_pre, w15_pre, w16_pre, w17_pre, w18_pre, w19_pre;\nreg signed[SIZE_weights - 1:0] w21_pre, w22_pre, w23_pre, w24_pre, w25_pre, w26_pre, w27_pre, w28_pre, w29_pre;\nreg signed[SIZE_weights - 1:0] w31_pre, w32_pre, w33_pre, w34_pre, w35_pre, w36_pre, w37_pre, w38_pre, w39_pre;\nreg signed[SIZE_weights - 1:0] w41_pre, w42_pre, w43_pre, w44_pre, w45_pre, w46_pre, w47_pre, w48_pre, w49_pre;\nreg signed[SIZE_weights - 1:0] w51_pre, w52_pre, w53_pre, w54_pre, w55_pre, w56_pre, w57_pre, w58_pre, w59_pre;\nreg signed[SIZE_weights - 1:0] w61_pre, w62_pre, w63_pre, w64_pre, w65_pre, w66_pre, w67_pre, w68_pre, w69_pre;\nreg signed[SIZE_weights - 1:0] w71_pre, w72_pre, w73_pre, w74_pre, w75_pre, w76_pre, w77_pre, w78_pre, w79_pre;\nreg signed[SIZE_weights - 1:0] w81_pre, w82_pre, w83_pre, w84_pre, w85_pre, w86_pre, w87_pre, w88_pre, w89_pre;\n\nreg signed[SIZE_1 - 1:0] p11_pre, p12_pre, p13_pre, p14_pre, p15_pre, p16_pre, p17_pre, p18_pre, p19_pre;\nreg signed[SIZE_1 - 1:0] p21_pre, p22_pre, p23_pre, p24_pre, p25_pre, p26_pre, p27_pre, p28_pre, p29_pre;\nreg signed[SIZE_1 - 1:0] p31_pre, p32_pre, p33_pre, p34_pre, p35_pre, p36_pre, p37_pre, p38_pre, p39_pre;\nreg signed[SIZE_1 - 1:0] p41_pre, p42_pre, p43_pre, p44_pre, p45_pre, p46_pre, p47_pre, p48_pre, p49_pre;\nreg signed[SIZE_1 - 1:0] p51_pre, p52_pre, p53_pre, p54_pre, p55_pre, p56_pre, p57_pre, p58_pre, p59_pre;\nreg signed[SIZE_1 - 1:0] p61_pre, p62_pre, p63_pre, p64_pre, p65_pre, p66_pre, p67_pre, p68_pre, p69_pre;\nreg signed[SIZE_1 - 1:0] p71_pre, p72_pre, p73_pre, p74_pre, p75_pre, p76_pre, p77_pre, p78_pre, p79_pre;\nreg signed[SIZE_1 - 1:0] p81_pre, p82_pre, p83_pre, p84_pre, p85_pre, p86_pre, p87_pre, p88_pre, p89_pre;\nreg [3:0] marker;\nreg [6:0] lvl;\nreg [8:0] i;\nreg [8:0] j;\nreg [2:0] sh;\nreg signed [32-1:0] dp;\nreg signed [SIZE_1-1:0] dp_shift;\nreg signed [19-1:0]dp_check;\n\nalways @(posedge clk)\nbegin\n if (dense_en==1)\n begin\n re_p=1;\n case (marker)\n2:begin\n if (i>(in>>3)+1) begin\n p11_pre = 0; p12_pre = 0; p13_pre = 0; p14_pre = 0; p15_pre = 0; p16_pre = 0; p17_pre = 0; p18_pre = 0;\n end\n else begin\n p11_pre = qp[SIZE_8 - 1:SIZE_7]; p12_pre = qp[SIZE_7 - 1:SIZE_6]; p13_pre = qp[SIZE_6 - 1:SIZE_5]; p14_pre = qp[SIZE_5 - 1:SIZE_4]; p15_pre = qp[SIZE_4 - 1:SIZE_3]; p16_pre = qp[SIZE_3 - 1:SIZE_2]; p17_pre = qp[SIZE_2 - 1:SIZE_1]; p18_pre = qp[SIZE_1 - 1:0];\n end\n go=0;\n w11_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w12_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w13_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w14_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w15_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w16_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w17_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w18_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w19_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 2 + j*8;\n end\n3:begin\n if (i>(in>>3)+1) begin\n p19_pre = 0; p21_pre = 0; p22_pre = 0; p23_pre = 0; p24_pre = 0; p25_pre = 0; p26_pre = 0; p27_pre = 0;\n end\n else begin\n p19_pre = qp[SIZE_8 - 1:SIZE_7]; p21_pre = qp[SIZE_7 - 1:SIZE_6]; p22_pre = qp[SIZE_6 - 1:SIZE_5]; p23_pre = qp[SIZE_5 - 1:SIZE_4]; p24_pre = qp[SIZE_4 - 1:SIZE_3]; p25_pre = qp[SIZE_3 - 1:SIZE_2]; p26_pre = qp[SIZE_2 - 1:SIZE_1]; p27_pre = qp[SIZE_1 - 1:0];\n end\n if (i!=3) dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp;\n w21_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w22_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w23_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w24_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w25_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w26_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w27_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w28_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w29_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 3 + j*8;\n end\n4:begin\n if (i>(in>>3)+1) begin\n p28_pre = 0; p29_pre = 0; p31_pre = 0; p32_pre = 0; p33_pre = 0; p34_pre = 0; p35_pre = 0; p36_pre = 0;\n end\n else begin\n p28_pre = qp[SIZE_8 - 1:SIZE_7]; p29_pre = qp[SIZE_7 - 1:SIZE_6]; p31_pre = qp[SIZE_6 - 1:SIZE_5]; p32_pre = qp[SIZE_5 - 1:SIZE_4]; p33_pre = qp[SIZE_4 - 1:SIZE_3]; p34_pre = qp[SIZE_3 - 1:SIZE_2]; p35_pre = qp[SIZE_2 - 1:SIZE_1]; p36_pre = qp[SIZE_1 - 1:0];\n end\n go=1;\n\n w31_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w32_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w33_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w34_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w35_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w36_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w37_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w38_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w39_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 4 + j*8;\n\tp11=p11_pre; p12=p12_pre; p13=p13_pre; \n p21=p14_pre; p22=p15_pre; p23=p16_pre; \n p31=p17_pre; p32=p18_pre; p33=p19_pre; \n p41=p21_pre; p42=p22_pre; p43=p23_pre; \n p51=p24_pre; p52=p25_pre; p53=p26_pre; \n p61=p27_pre; p62=p28_pre; p63=p29_pre; \n p71=p31_pre; p72=p32_pre; p73=p33_pre; \n p81=p34_pre; p82=p35_pre; p83=p36_pre; \n\n w11=w11_pre; w12=w12_pre; w13=w13_pre; \n w21=w14_pre; w22=w15_pre; w23=w16_pre; \n w31=w17_pre; w32=w18_pre; w33=w19_pre; \n w41=w21_pre; w42=w22_pre; w43=w23_pre; \n w51=w24_pre; w52=w25_pre; w53=w26_pre; \n w61=w27_pre; w62=w28_pre; w63=w29_pre; \n w71=w31_pre; w72=w32_pre; w73=w33_pre; \n w81=w34_pre; w82=w35_pre; w83=w36_pre; \n end\n5:begin\n if (i>(in>>3)+1) begin\n p37_pre = 0; p38_pre = 0; p39_pre = 0; p41_pre = 0; p42_pre = 0; p43_pre = 0; p44_pre = 0; p45_pre = 0;\n end\n else begin\n p37_pre = qp[SIZE_8 - 1:SIZE_7]; p38_pre = qp[SIZE_7 - 1:SIZE_6]; p39_pre = qp[SIZE_6 - 1:SIZE_5]; p41_pre = qp[SIZE_5 - 1:SIZE_4]; p42_pre = qp[SIZE_4 - 1:SIZE_3]; p43_pre = qp[SIZE_3 - 1:SIZE_2]; p44_pre = qp[SIZE_2 - 1:SIZE_1]; p45_pre = qp[SIZE_1 - 1:0];\n end\n go=0;\n w41_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w42_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w43_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w44_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w45_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w46_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w47_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w48_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w49_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 5 + j*8;\n end\n6:begin\n if (i>(in>>3)+1) begin\n p46_pre = 0; p47_pre = 0; p48_pre = 0; p49_pre = 0; p51_pre = 0; p52_pre = 0; p53_pre = 0; p54_pre = 0;\n end\n else begin\n p46_pre = qp[SIZE_8 - 1:SIZE_7]; p47_pre = qp[SIZE_7 - 1:SIZE_6]; p48_pre = qp[SIZE_6 - 1:SIZE_5]; p49_pre = qp[SIZE_5 - 1:SIZE_4]; p51_pre = qp[SIZE_4 - 1:SIZE_3]; p52_pre = qp[SIZE_3 - 1:SIZE_2]; p53_pre = qp[SIZE_2 - 1:SIZE_1]; p54_pre = qp[SIZE_1 - 1:0];\n end\n dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp;\n w51_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w52_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w53_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w54_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w55_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w56_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w57_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w58_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w59_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 6 + j*8;\n end\n7:begin\n if (i>(in>>3)+1) begin\n p55_pre = 0; p56_pre = 0; p57_pre = 0; p58_pre = 0; p59_pre = 0; p61_pre = 0; p62_pre = 0; p63_pre = 0;\n end\n else begin\n p55_pre = qp[SIZE_8 - 1:SIZE_7]; p56_pre = qp[SIZE_7 - 1:SIZE_6]; p57_pre = qp[SIZE_6 - 1:SIZE_5]; p58_pre = qp[SIZE_5 - 1:SIZE_4]; p59_pre = qp[SIZE_4 - 1:SIZE_3]; p61_pre = qp[SIZE_3 - 1:SIZE_2]; p62_pre = qp[SIZE_2 - 1:SIZE_1]; p63_pre = qp[SIZE_1 - 1:0];\n end\n go=1;\n w61_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w62_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w63_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w64_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w65_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w66_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w67_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w68_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w69_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 7 + j*8;\n\tp11=p37_pre; p12=p38_pre; p13=p39_pre; \n p21=p41_pre; p22=p42_pre; p23=p43_pre; \n p31=p44_pre; p32=p45_pre; p33=p46_pre; \n p41=p47_pre; p42=p48_pre; p43=p49_pre; \n p51=p51_pre; p52=p52_pre; p53=p53_pre; \n p61=p54_pre; p62=p55_pre; p63=p56_pre; \n p71=p57_pre; p72=p58_pre; p73=p59_pre; \n p81=p61_pre; p82=p62_pre; p83=p63_pre; \n\n w11=w37_pre; w12=w38_pre; w13=w39_pre; \n w21=w41_pre; w22=w42_pre; w23=w43_pre; \n w31=w44_pre; w32=w45_pre; w33=w46_pre; \n w41=w47_pre; w42=w48_pre; w43=w49_pre; \n w51=w51_pre; w52=w52_pre; w53=w53_pre; \n w61=w54_pre; w62=w55_pre; w63=w56_pre; \n w71=w57_pre; w72=w58_pre; w73=w59_pre; \n w81=w61_pre; w82=w62_pre; w83=w63_pre; \n end\n8:begin\n if (i>(in>>3)+1) begin\n p64_pre = 0; p65_pre = 0; p66_pre = 0; p67_pre = 0; p68_pre = 0; p69_pre = 0; p71_pre = 0; p72_pre = 0;\n end\n else begin\n p64_pre = qp[SIZE_8 - 1:SIZE_7]; p65_pre = qp[SIZE_7 - 1:SIZE_6]; p66_pre = qp[SIZE_6 - 1:SIZE_5]; p67_pre = qp[SIZE_5 - 1:SIZE_4]; p68_pre = qp[SIZE_4 - 1:SIZE_3]; p69_pre = qp[SIZE_3 - 1:SIZE_2]; p71_pre = qp[SIZE_2 - 1:SIZE_1]; p72_pre = qp[SIZE_1 - 1:0];\n end\n go=0;\n j=j+1;\n w71_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w72_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w73_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w74_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w75_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w76_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w77_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w78_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w79_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n end\n0:begin\n if (i>(in>>3)+1) begin\n p73_pre = 0; p74_pre = 0; p75_pre = 0; p76_pre = 0; p77_pre = 0; p78_pre = 0; p79_pre = 0; p81_pre = 0;\n end\n else begin\n p73_pre = qp[SIZE_8 - 1:SIZE_7]; p74_pre = qp[SIZE_7 - 1:SIZE_6]; p75_pre = qp[SIZE_6 - 1:SIZE_5]; p76_pre = qp[SIZE_5 - 1:SIZE_4]; p77_pre = qp[SIZE_4 - 1:SIZE_3]; p78_pre = qp[SIZE_3 - 1:SIZE_2]; p79_pre = qp[SIZE_2 - 1:SIZE_1]; p81_pre = qp[SIZE_1 - 1:0];\n end\n we=0;\n re_w=1;\n if (i!=0) dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp;\n w81_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w82_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w83_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w84_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w85_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w86_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w87_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w88_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w89_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; \n read_addressw = lvl*29 + 0 + j*8;\n end\n1:begin\n if (i>(in>>3)+1) begin\n p82_pre = 0; p83_pre = 0; p84_pre = 0; p85_pre = 0; p86_pre = 0; p87_pre = 0; p88_pre = 0; p89_pre = 0;\n end\n else begin\n p82_pre = qp[SIZE_8 - 1:SIZE_7]; p83_pre = qp[SIZE_7 - 1:SIZE_6]; p84_pre = qp[SIZE_6 - 1:SIZE_5]; p85_pre = qp[SIZE_5 - 1:SIZE_4]; p86_pre = qp[SIZE_4 - 1:SIZE_3]; p87_pre = qp[SIZE_3 - 1:SIZE_2]; p88_pre = qp[SIZE_2 - 1:SIZE_1]; p89_pre = qp[SIZE_1 - 1:0];\n end\n if (i!=1) go=1;\n p11=p64_pre; p12=p65_pre; p13=p66_pre; \n p21=p67_pre; p22=p68_pre; p23=p69_pre; \n p31=p71_pre; p32=p72_pre; p33=p73_pre; \n p41=p74_pre; p42=p75_pre; p43=p76_pre; \n p51=p77_pre; p52=p78_pre; p53=p79_pre; \n p61=p81_pre; p62=p82_pre; p63=p83_pre; \n p71=p84_pre; p72=p85_pre; p73=p86_pre; \n p81=p87_pre; p82=p88_pre; p83=p89_pre; \n\n w11=w64_pre; w12=w65_pre; w13=w66_pre; \n w21=w67_pre; w22=w68_pre; w23=w69_pre; \n w31=w71_pre; w32=w72_pre; w33=w73_pre; \n w41=w74_pre; w42=w75_pre; w43=w76_pre; \n w51=w77_pre; w52=w78_pre; w53=w79_pre; \n w61=w81_pre; w62=w82_pre; w63=w83_pre; \n w71=w84_pre; w72=w85_pre; w73=w86_pre; \n w81=w87_pre; w82=w88_pre; w83=w89_pre; \n\n \n read_addressw = lvl*29 + 1 + j*8;\n end\n default: $display(\"Check case dense\");\n endcase\n\n read_addressp=memstartp+i;\n\n if (marker!=8) marker=marker+1; else marker=0;\n i=i+1;\n if ((i>(in>>3)+4)&&(marker==4))\n begin\n \t write_addressp=memstartzap+(lvl>>(num_conv>>1));\n dp_check=dp[32-2:SIZE_1-2];\n if ((dp_shift<0)&&(nozero==0)) dp_shift=0;\n\t\t if (dp_check>2**(SIZE_1-1)-1) dp_shift=2**(SIZE_1-1)-1;\n else dp_shift=dp_check;\n if (sh ==0) begin res=0; res[SIZE_8-1:SIZE_7]=dp_shift; end\n if (sh ==1) begin res[SIZE_7-1:SIZE_6]=dp_shift; end\n if (sh ==2) begin res[SIZE_6-1:SIZE_5]=dp_shift; end\n if (sh ==3) begin res[SIZE_5-1:SIZE_4]=dp_shift; end\n if (sh ==4) begin res[SIZE_4-1:SIZE_3]=dp_shift; end\n if (sh ==5) begin res[SIZE_3-1:SIZE_2]=dp_shift; end\n if (sh ==6) begin res[SIZE_2-1:SIZE_1]=dp_shift; end\n if (sh ==7) begin res[SIZE_1-1:0]=dp_shift; end\n lvl=lvl+1;\n i=0; \n j=0; \n dp=0; \n marker=0;\n sh=sh+1; if (sh==num_conv) sh=0; \n\t\t if ((sh==0)||(lvl==out)) we=1;\n if (lvl==out) STOP=1;\n end\nend\nelse\nbegin\n marker=0;\n i=0;\n j=0;\n sh=0;\n we=0;\n dp=0;\n res=0;\n re_p=0;\n re_w=0;\n STOP=0;\n lvl=0;\nend\nend\nendmodule\n" }, { "path": "verilog/MobileNet_v3_conv_8_3x1/result.v", "content": "module result(clk,enable,STOP,memstartp,read_addressp,qp,re,RESULT);\n\nparameter SIZE_1=0;\nparameter SIZE_2=0;\nparameter SIZE_3=0;\nparameter SIZE_4=0;\nparameter SIZE_5=0;\nparameter SIZE_6=0;\nparameter SIZE_7=0;\nparameter SIZE_8=0;\nparameter SIZE_address_pix=0;\n\ninput clk,enable;\noutput reg STOP;\ninput [SIZE_address_pix-1:0] memstartp;\ninput [SIZE_8-1:0] qp;\noutput reg re;\noutput reg [SIZE_address_pix-1:0] read_addressp;\noutput reg [1:0] RESULT;\n\nreg [2:0] marker;\nreg signed [SIZE_1-1:0] p1,p2;\nalways @(posedge clk)\nbegin\nif (enable==1)\nbegin\nre=1;\ncase (marker)\n\t0: \tbegin\n\t\tread_addressp=memstartp+0;\n\t\tend\n\t1: \tbegin\n\t\tend\n\t2: \tbegin\n\t\tp1=qp[SIZE_8-1:SIZE_7];\n\t\tp2=qp[SIZE_7-1:SIZE_6];\n\t\tRESULT=0; \n\t\tif (p2>=p1) RESULT=1; \n\t\telse RESULT=0; \n\t\tSTOP=1; \n\t\tend\n\tdefault: $display(\"Check case result\");\nendcase\nmarker=marker+1;\nend\nelse \nbegin\nre=0;\nmarker=0;\nSTOP=0;\nend\nend\n\nendmodule\n" }, { "path": "verilog/OpenVino_MobileNet.qpf", "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 2018 Intel Corporation. All rights reserved.\n# Your use of Intel Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Intel Program License \n# Subscription Agreement, the Intel Quartus Prime License Agreement,\n# the Intel FPGA IP License Agreement, or other applicable license\n# agreement, including, without limitation, that your use is for\n# the sole purpose of programming logic devices manufactured by\n# Intel and sold by Intel or its authorized distributors. Please\n# refer to the applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus Prime\n# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition\n# Date created = 15:25:52 July 27, 2019\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"18.0\"\nDATE = \"15:25:52 July 27, 2019\"\n\n# Revisions\n\nPROJECT_REVISION = \"GENERAL\"\n" }, { "path": "verilog/RAM.v", "content": "module RAM_general(\ninput clk_in,\ninput clk_out,\ninput clk_in_im,\ninput clk_out_im,\ninput clk_in_im_scale,\ninput clk_out_im_scale,\n\ninput [15:0] data_in_im,\noutput reg [15:0] data_out_im,\ninput [18:0] address_in_im,\ninput [18:0] address_out_im,\ninput we_image,\ninput re_image,\n\ninput [23:0] data_in_im_scale,\noutput reg [23:0] data_out_im_scale,\ninput [15:0] address_in_im_scale,\ninput [15:0] address_out_im_scale,\ninput we_image_scale,\ninput re_image_scale,\n\ninput [20:0] data_in_weights,\noutput reg [20:0] data_out_weights,\ninput [23:0] address_in_weights,\ninput [23:0] address_out_weights,\ninput we_weights,\ninput re_weights\n\n);\n\nreg signed [15:0] ram_image [0:70800-1];\nreg signed [23:0] ram_scale_image [0:128*128-1];\nreg signed [20:0] ram_weights [0:(208115+2736)];\n\nalways @(posedge clk_in)\tif (we_weights) ram_weights[address_in_weights] = data_in_weights;\n\nalways @(posedge clk_out)\tif (re_weights) data_out_weights = ram_weights[address_out_weights];\n\nalways @(posedge clk_in_im) if (we_image)\tram_image[address_in_im] = data_in_im;\n\nalways @(posedge clk_out_im) if (re_image) data_out_im = ram_image[address_out_im];\n\nalways @(posedge clk_in_im_scale) if (we_image_scale)\tram_scale_image[address_in_im_scale] = data_in_im_scale;\n\nalways @(posedge clk_out_im_scale) if (re_image_scale) data_out_im_scale = ram_scale_image[address_out_im_scale];\n\nendmodule\n" }, { "path": "verilog/Seg7.v", "content": "module Seg7 (data,hex);\n\ninput [3:0] data;\n\noutput [6:0] hex;\n\nassign hex[0] = !(((data==0)||(data==2)||(data==3)||(data==5)||(data==6)||(data==7)||(data==8)||(data==9)||(data==10)||(data==12)||(data==14)||(data==15))?1'b1:1'b0);\nassign hex[1] = !(((data==0)||(data==1)||(data==2)||(data==3)||(data==4)||(data==7)||(data==8)||(data==9)||(data==10)||(data==13))?1'b1:1'b0);\nassign hex[2] = !(((data==0)||(data==1)||(data==3)||(data==4)||(data==5)||(data==6)||(data==7)||(data==8)||(data==9)||(data==10)||(data==11)||(data==13))?1'b1:1'b0);\nassign hex[3] = !(((data==0)||(data==2)||(data==3)||(data==5)||(data==6)||(data==8)||(data==9)||(data==11)||(data==12)||(data==13)||(data==14))?1'b1:1'b0);\nassign hex[4] = !(((data==0)||(data==2)||(data==6)||(data==8)||(data==10)||(data==11)||(data==12)||(data==13)||(data==14)||(data==15))?1'b1:1'b0);\nassign hex[5] = !(((data==0)||(data==4)||(data==5)||(data==6)||(data==8)||(data==9)||(data==10)||(data==11)||(data==12)||(data==14)||(data==15))?1'b1:1'b0);\nassign hex[6] = !(((data==2)||(data==3)||(data==4)||(data==5)||(data==6)||(data==8)||(data==9)||(data==10)||(data==11)||(data==13)||(data==14)||(data==15))?1'b1:1'b0);\n\nendmodule" }, { "path": "verilog/UART/async.v", "content": "////////////////////////////////////////////////////////\n// RS-232 RX and TX module\n// (c) fpga4fun.com & KNJN LLC - 2003 to 2016\n\n// The RS-232 settings are fixed\n// TX: 8-bit data, 2 stop, no-parity\n// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)\n\n//`define SIMULATION // in this mode, TX outputs one bit per clock cycle\n // and RX receives one bit per clock cycle (for fast simulations)\n\n////////////////////////////////////////////////////////\nmodule async_transmitter(\n\tinput clk,\n\tinput TxD_start,\n\tinput [7:0] TxD_data,\n\toutput TxD,\n\toutput TxD_busy\n);\n\n// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data\n// TxD_data is latched so that it doesn't have to stay valid while it is being sent\n\nparameter ClkFrequency = 25000000;\t// 25MHz\nparameter Baud = 115200;\n\ngenerate\n\tif(ClkFrequency> 1);\n\n\tcase(TxD_state)\n\t\t4'b0000: if(TxD_start) TxD_state <= 4'b0100;\n\t\t4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit\n\t\t4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0\n\t\t4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1\n\t\t4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2\n\t\t4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3\n\t\t4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4\n\t\t4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5\n\t\t4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6\n\t\t4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7\n\t\t4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1\n\t\t4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2\n\t\tdefault: if(BitTick) TxD_state <= 4'b0000;\n\tendcase\nend\n\nassign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits\nendmodule\n\n\n////////////////////////////////////////////////////////\nmodule async_receiver(\n\tinput clk,\n\tinput RxD,\n\toutput reg RxD_data_ready = 0,\n\toutput reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted\n\n\t// We also detect if a gap occurs in the received stream of characters\n\t// That can be useful if multiple characters are sent in burst\n\t// so that multiple characters can be treated as a \"packet\"\n\toutput RxD_idle, // asserted when no data has been received for a while\n\toutput reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)\n);\n\nparameter ClkFrequency = 25000000; // 25MHz\nparameter Baud = 115200;\n\nparameter Oversampling = 8; // needs to be a power of 2\n// we oversample the RxD line at a fixed rate to capture each RxD data bit at the \"right\" time\n// 8 times oversampling by default, use 16 for higher quality reception\n\ngenerate\n\tif(ClkFrequency>log2) log2=log2+1; end endfunction\nlocalparam l2o = log2(Oversampling);\nreg [l2o-2:0] OversamplingCnt = 0;\nalways @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;\nwire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);\n`endif\n\n// now we can accumulate the RxD bits in a shift-register\nalways @(posedge clk)\ncase(RxD_state)\n\t4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?\n\t4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow\n\t4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0\n\t4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1\n\t4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2\n\t4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3\n\t4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4\n\t4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5\n\t4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6\n\t4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7\n\t4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit\n\tdefault: RxD_state <= 4'b0000;\nendcase\n\nalways @(posedge clk)\nif(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};\n\n//reg RxD_data_error = 0;\nalways @(posedge clk)\nbegin\n\tRxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received\n\t//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received\nend\n\n`ifdef SIMULATION\nassign RxD_idle = 0;\n`else\nreg [l2o+1:0] GapCnt = 0;\nalways @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;\nassign RxD_idle = GapCnt[l2o+1];\nalways @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];\n`endif\n\nendmodule\n\n\n////////////////////////////////////////////////////////\n// dummy module used to be able to raise an assertion in Verilog\nmodule ASSERTION_ERROR();\nendmodule\n\n\n////////////////////////////////////////////////////////\nmodule BaudTickGen(\n\tinput clk, enable,\n\toutput tick // generate a tick at the specified baud rate * oversampling\n);\nparameter ClkFrequency = 25000000;\nparameter Baud = 115200;\nparameter Oversampling = 1;\n\nfunction integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction\nlocalparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte\nreg [AccWidth:0] Acc = 0;\nlocalparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow\nlocalparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);\nalways @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];\nassign tick = Acc[AccWidth];\nendmodule\n\n\n////////////////////////////////////////////////////////\n" }, { "path": "verilog/UART/serialGPIO.v", "content": "module serialGPIO(\n input clk25,\n input RxD,\n output TxD,\n\t \n\t input reset,\n\t output\treg [23:0] address,\n\t output reg signed [20:0] data,\n\t output reg write_enable,\n\t output reg start,\n\t output reg stop,\n\t \n\t output RxD_data_ready,\n\t \n\t input signed [20:0] data_tx,\n\t input enable_tx\n\t \n);\n\nreg [7:0] GPout;\n\nreg [1:0] sh;\n\nwire [7:0] RxD_data;\n\nasync_receiver RX(.clk(clk25), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));\nalways @(posedge clk25) if(RxD_data_ready) GPout <= RxD_data;\n\nasync_transmitter TX(.clk(clk25), .TxD(TxD), .TxD_start(enable_tx), .TxD_data(data_tx[7:0]));\n\nalways @(posedge RxD_data_ready or negedge reset)\n\tif (!reset)\n\tbegin\n\t\t\taddress = -1;\n\t\t\tstart=0;\n\t\t\tsh=0;\n\t\t\twrite_enable=0;\n\t\t\tdata=0;\n\t\t\tstop=0;\n\tend \n\telse\n\tbegin\n\t\n\n\t\tif ((!(GPout == 255))&&(sh==0)) address = address + 1'b1;\n\t\t\n\t\tif (GPout == 191) \n\t\t\tbegin\n\t\t\t\tstart = 0;\n\t\t\t\tstop = 1;\n\t\t\t\tsh=0;\n\t\t\t\twrite_enable=0;\n\t\t\tend\n\t\n\t\tif (start)\n\t\t\tbegin\t\t\n\t\t\t\tif (sh==0) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tdata=0;\n\t\t\t\t\t\tdata[5:0]=GPout[5:0];\n\t\t\t\t\t\twrite_enable=0;\n\t\t\t\t\tend\n\t\t\t\tif (sh==1) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tdata[11:6]=GPout[5:0];\n\t\t\t\t\tend\n\t\t\t\tif (sh==2) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tdata[17:12]=GPout[5:0];\n\t\t\t\t\tend\n\t\t\t\tif (sh==3) \n\t\t\t\t\tbegin\n\t\t\t\t\t\tdata[19:18]=GPout[1:0]; //minus,data\n\t\t\t\t\t\tif (GPout[3]) data=-data;\n\t\t\t\t\t\twrite_enable = 1'b1;\n\t\t\t\t\tend\n\t\t\t\tsh=sh+1;\n\t\t\tend\n\t\t\t\n\t\tif (GPout == 255) \n\t\t\tbegin\n\t\t\t\taddress = -1;\n\t\t\t\tstart=1;\n\t\t\t\tsh=0;\n\t\t\t\twrite_enable=0;\n\t\t\t\tdata=0;\n\t\t\t\tstop=0;\n\t\t\tend\n\tend\n\t\nendmodule " }, { "path": "verilog/ili9341/tft_ili9341.sv", "content": "/** Simple frame-buffer based driver for the ILI9341 TFT module */\nmodule tft_ili9341(\n\t\tinput clk,\n\t\tinput tft_sdo, output wire tft_sck, output wire tft_sdi, \n\t\toutput wire tft_dc, output reg tft_reset, output wire tft_cs,\n\t\tinput[15:0] framebufferData, output wire framebufferClk\n\t);\n\t\n\tparameter INPUT_CLK_MHZ = 120; /* recommended */\n\t\n\t// Initial assignments\n\tinitial tft_reset = 1'b1;\n\n\t// Assign pins and modules\n\treg[8:0] spiData; \n\treg spiDataSet = 1'b0;\n\twire spiIdle;\n\t\n\treg frameBufferLowNibble = 1'b1;\n\tassign framebufferClk = !frameBufferLowNibble;\n\t\n\ttft_ili9341_spi spi(\n\t\t.spiClk(clk), \n\t\t.data(spiData), .dataAvailable(spiDataSet),\n\t\t.tft_sck(tft_sck), .tft_sdi(tft_sdi), .tft_dc(tft_dc), .tft_cs(tft_cs),\n\t\t.idle(spiIdle));\n\t\n\t// Init Sequence Data (based upon https://github.com/notro/fbtft/blob/master/fb_ili9341.c)\n\tlocalparam INIT_SEQ_LEN = 64;\n\treg[6:0] initSeqCounter = 7'b0;\n\treg[8:0] INIT_SEQ [0:INIT_SEQ_LEN-1] = '{\n\t\t// Turn off Display\n\t\t{1'b0, 8'h28},\n\t\t// Init (??)\n\t\t{1'b0, 8'hCF}, {1'b1, 8'h00}, {1'b1, 8'h83}, {1'b1, 8'h30}, \n\t\t{1'b0, 8'hED}, {1'b1, 8'h64}, {1'b1, 8'h03}, {1'b1, 8'h12}, {1'b1, 8'h81},\n\t\t{1'b0, 8'hE8}, {1'b1, 8'h85}, {1'b1, 8'h01}, {1'b1, 8'h79}, \n\t\t{1'b0, 8'hCB}, {1'b1, 8'h39}, {1'b1, 8'h2C}, {1'b1, 8'h00}, {1'b1, 8'h34}, {1'b1, 8'h02},\n\t\t{1'b0, 8'hF7}, {1'b1, 8'h20},\n\t\t{1'b0, 8'hEA}, {1'b1, 8'h00}, {1'b1, 8'h00},\n\t\t// Power Control\n\t\t{1'b0, 8'hC0}, {1'b1, 8'h26},\n\t\t{1'b0, 8'hC1}, {1'b1, 8'h11},\n\t\t// VCOM\n\t\t{1'b0, 8'hC5}, {1'b1, 8'h35}, {1'b1, 8'h3E},\n\t\t{1'b0, 8'hC7}, {1'b1, 8'hBE},\n\t\t// Memory Access Control\n\t\t{1'b0, 8'h3A}, {1'b1, 8'h55},\n\t\t{1'b0, 8'h2A}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'h01}, {1'b1, 8'h3F},\n\t\t{1'b0, 8'h2B}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'hEF},\n\t\t{1'b0, 8'h36}, {1'b1, 8'hE0},\n\t\t// Frame Rate\n\t\t{1'b0, 8'hB1}, {1'b1, 8'h00}, {1'b1, 8'h1B},\n\t\t// Gamma\n\t\t{1'b0, 8'h26}, {1'b1, 8'h01},\n\t\t// Brightness\n\t\t{1'b0, 8'h51}, {1'b1, 8'hFF},\n\t\t// Display\n\t\t{1'b0, 8'hB7}, {1'b1, 8'h07},\n\t\t{1'b0, 8'hB6}, {1'b1, 8'h0A}, {1'b1, 8'h82}, {1'b1, 8'h27}, {1'b1, 8'h00},\n\t\t\n\t\t{1'b0, 8'h29}, // Enable Display\n\t\t{1'b0, 8'h2C} // Start Memory-Write\n\t};\n\t\n\t\n\t// state machine with delay + idle support (used for initialization)\n\treg[23:0] remainingDelayTicks = 24'b0;\n\tenum logic[2:0] { START, HOLD_RESET, WAIT_FOR_POWERUP, SEND_INIT_SEQ, LOOP} state = START;\n\talways @ (posedge clk) begin\n\t\t// clear data flag first\n\t\tspiDataSet <= 1'b0; \n\t\t\n\t\t// always decrement delay ticks\n\t\tif (remainingDelayTicks > 0) begin\n\t\t\tremainingDelayTicks <= remainingDelayTicks - 1'b1;\n\t\tend\n\t\telse if (spiIdle && !spiDataSet) begin\n\t\t\t// advance state machine to next state, but only do this if we\n\t\t\t// didn't just clock in the last byte (since idle is not yet updated)\n\t\t\tcase (state)\n\t\t\t\t// initialize all pins in START mode; reset the LCD\n\t\t\t\tSTART: begin\n\t\t\t\t\ttft_reset <= 1'b0;\n\t\t\t\t\tremainingDelayTicks <= 24'(INPUT_CLK_MHZ * 10); // min: 10us\n\t\t\t\t\tstate <= HOLD_RESET;\n\t\t\t\tend\n\t\t\t\t\n\t\t\t\t// wait for RESET to kick in; then release pin & wait for power up\n\t\t\t\tHOLD_RESET: begin\n\t\t\t\t\ttft_reset <= 1'b1; // release pin\n\t\t\t\t\tremainingDelayTicks <= 24'(INPUT_CLK_MHZ * 120000); // min: 120ms\n\t\t\t\t\tstate <= WAIT_FOR_POWERUP;\n\t\t\t\t\tframeBufferLowNibble <= 1'b0; // request first pixel\n\t\t\t\tend\n\t\t\t\t\n\t\t\t\t// if power up is completed -> sw reset\n\t\t\t\tWAIT_FOR_POWERUP: begin\n\t\t\t\t\tspiData <= {1'b0, 8'h11}; // take out of sleep mode\n\t\t\t\t\tspiDataSet <= 1'b1;\n\t\t\t\t\tremainingDelayTicks <= 24'(INPUT_CLK_MHZ * 5000); // min: 5ms\n\t\t\t\t\tstate <= SEND_INIT_SEQ;\n\t\t\t\t\tframeBufferLowNibble <= 1'b1;\n\t\t\t\tend\n\t\t\t\t\n\t\t\t\t// setup the LCD by sending the init sequence\n\t\t\t\tSEND_INIT_SEQ: begin\n\t\t\t\t\tif (initSeqCounter < INIT_SEQ_LEN) begin\n\t\t\t\t\t\tspiData <= INIT_SEQ[initSeqCounter];\n\t\t\t\t\t\tspiDataSet <= 1'b1;\n\t\t\t\t\t\tinitSeqCounter <= initSeqCounter + 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tstate <= LOOP;\n\t\t\t\t\t\tremainingDelayTicks <= 24'(INPUT_CLK_MHZ * 10000); // min: 10ms\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\t\n\t\t\t\t// frame buffer loop\n\t\t\t\tdefault: begin\n\t\t\t\t\tspiData <= !frameBufferLowNibble ? {1'b1, framebufferData[15:8]} :{1'b1, framebufferData[7:0]};\n\t\t\t\t\tspiDataSet <= 1'b1;\n\t\t\t\t\tframeBufferLowNibble <= !frameBufferLowNibble;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule" }, { "path": "verilog/ili9341/tft_ili9341_spi.sv", "content": "// --- Byte-wise SPI + DC implementation\n// * Will copy data into internal buffer\n// * 'Idle' will be set to 0 once buffer copy is complete\n// * Data is only copied if 'dataAvailable' is set to 1\n// * SPI CLK will stop (high state) if no data is being sent\nmodule tft_ili9341_spi(\n\t\tinput spiClk, input[8:0] data, input dataAvailable,\n\t\toutput wire tft_sck, output reg tft_sdi, output reg tft_dc, output wire tft_cs,\n\t\toutput reg idle\n\t);\n\n\t// Registers\n\treg[0:2] counter = 3'b0;\n\treg[8:0] internalData;\n\treg internalSck;\n\treg cs;\n\t\n\tinitial internalSck <= 1'b1;\n\tinitial idle <= 1'b1;\n\tinitial cs <= 1'b0;\n\t\n\t// Combinational Assignments\n\twire dataDc = internalData[8];\n\twire[0:7] dataShift = internalData[7:0]; // MSB first\n\t\n\tassign tft_sck = internalSck & cs; // only drive sck with an active CS\n\tassign tft_cs = !cs; // active low\n\t\n\t// Update SPI CLK + Output data\n\talways @ (posedge spiClk) begin\n\t\t// Store new data in internal register\n\t\tif (dataAvailable) begin\n\t\t\tinternalData <= data;\n\t\t\tidle <= 1'b0;\n\t\tend\n\t\t\n\t\t// Change data if we're actively sending\n\t\tif (!idle) begin\n\t\t\t// Toggle Clock on every active tick\n\t\t\tinternalSck <= !internalSck;\n\t\t\t\t\n\t\t\t// Check if SCK will be low next\n\t\t\tif (internalSck) begin\n\t\t\t\t// Update pins\n\t\t\t\ttft_dc <= dataDc;\n\t\t\t\ttft_sdi <= dataShift[counter];\n\t\t\t\tcs <= 1'b1;\n\t\t\t\t\n\t\t\t\t// Advance counter\n\t\t\t\tcounter <= counter + 1'b1;\n\t\t\t\tidle <= &counter; // we're just sending the last bit\n\t\t\tend\n\t\tend\n\t\telse begin\n\t\t\tinternalSck <= 1'b1; // idle mode (also: sent last bit)\n\t\t\tif (internalSck) cs <= 1'b0; // idle for two bits in a row -> deactivate CS\n\t\tend\n\tend\t\nendmodule" }, { "path": "verilog/pll_24_100/pll_24_100_0002.qip", "content": "set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to \"*pll_24_100_0002*|altera_pll:altera_pll_i*|*\"\n \nset_instance_assignment -name PLL_AUTO_RESET OFF -to \"*pll_24_100_0002*|altera_pll:altera_pll_i*|*\"\nset_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to \"*pll_24_100_0002*|altera_pll:altera_pll_i*|*\"\n" }, { "path": "verilog/pll_24_100/pll_24_100_0002.v", "content": "`timescale 1ns/10ps\nmodule pll_24_100_0002(\n\n\t// interface 'refclk'\n\tinput wire refclk,\n\n\t// interface 'reset'\n\tinput wire rst,\n\n\t// interface 'outclk0'\n\toutput wire outclk_0,\n\n\t// interface 'outclk1'\n\toutput wire outclk_1,\n\n\t// interface 'outclk2'\n\toutput wire outclk_2,\n\n\t// interface 'locked'\n\toutput wire locked\n);\n\n\taltera_pll #(\n\t\t.fractional_vco_multiplier(\"false\"),\n\t\t.reference_clock_frequency(\"50.0 MHz\"),\n\t\t.operation_mode(\"direct\"),\n\t\t.number_of_clocks(3),\n\t\t.output_clock_frequency0(\"24.000000 MHz\"),\n\t\t.phase_shift0(\"0 ps\"),\n\t\t.duty_cycle0(50),\n\t\t.output_clock_frequency1(\"100.000000 MHz\"),\n\t\t.phase_shift1(\"0 ps\"),\n\t\t.duty_cycle1(50),\n\t\t.output_clock_frequency2(\"60.000000 MHz\"),\n\t\t.phase_shift2(\"0 ps\"),\n\t\t.duty_cycle2(50),\n\t\t.output_clock_frequency3(\"0 MHz\"),\n\t\t.phase_shift3(\"0 ps\"),\n\t\t.duty_cycle3(50),\n\t\t.output_clock_frequency4(\"0 MHz\"),\n\t\t.phase_shift4(\"0 ps\"),\n\t\t.duty_cycle4(50),\n\t\t.output_clock_frequency5(\"0 MHz\"),\n\t\t.phase_shift5(\"0 ps\"),\n\t\t.duty_cycle5(50),\n\t\t.output_clock_frequency6(\"0 MHz\"),\n\t\t.phase_shift6(\"0 ps\"),\n\t\t.duty_cycle6(50),\n\t\t.output_clock_frequency7(\"0 MHz\"),\n\t\t.phase_shift7(\"0 ps\"),\n\t\t.duty_cycle7(50),\n\t\t.output_clock_frequency8(\"0 MHz\"),\n\t\t.phase_shift8(\"0 ps\"),\n\t\t.duty_cycle8(50),\n\t\t.output_clock_frequency9(\"0 MHz\"),\n\t\t.phase_shift9(\"0 ps\"),\n\t\t.duty_cycle9(50),\n\t\t.output_clock_frequency10(\"0 MHz\"),\n\t\t.phase_shift10(\"0 ps\"),\n\t\t.duty_cycle10(50),\n\t\t.output_clock_frequency11(\"0 MHz\"),\n\t\t.phase_shift11(\"0 ps\"),\n\t\t.duty_cycle11(50),\n\t\t.output_clock_frequency12(\"0 MHz\"),\n\t\t.phase_shift12(\"0 ps\"),\n\t\t.duty_cycle12(50),\n\t\t.output_clock_frequency13(\"0 MHz\"),\n\t\t.phase_shift13(\"0 ps\"),\n\t\t.duty_cycle13(50),\n\t\t.output_clock_frequency14(\"0 MHz\"),\n\t\t.phase_shift14(\"0 ps\"),\n\t\t.duty_cycle14(50),\n\t\t.output_clock_frequency15(\"0 MHz\"),\n\t\t.phase_shift15(\"0 ps\"),\n\t\t.duty_cycle15(50),\n\t\t.output_clock_frequency16(\"0 MHz\"),\n\t\t.phase_shift16(\"0 ps\"),\n\t\t.duty_cycle16(50),\n\t\t.output_clock_frequency17(\"0 MHz\"),\n\t\t.phase_shift17(\"0 ps\"),\n\t\t.duty_cycle17(50),\n\t\t.pll_type(\"General\"),\n\t\t.pll_subtype(\"General\")\n\t) altera_pll_i (\n\t\t.rst\t(rst),\n\t\t.outclk\t({outclk_2, outclk_1, outclk_0}),\n\t\t.locked\t(locked),\n\t\t.fboutclk\t( ),\n\t\t.fbclk\t(1'b0),\n\t\t.refclk\t(refclk)\n\t);\nendmodule\n\n" }, { "path": "verilog/pll_24_100.bsf", "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 2018 Intel Corporation. All rights reserved.\nYour use of Intel Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Intel Program License \nSubscription Agreement, the Intel Quartus Prime License Agreement,\nthe Intel FPGA IP License Agreement, or other applicable license\nagreement, including, without limitation, that your use is for\nthe sole purpose of programming logic devices manufactured by\nIntel and sold by Intel or its authorized distributors. Please\nrefer to the applicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.1\"))\n(symbol\n\t(rect 0 0 160 224)\n\t(text \"pll_24_100\" (rect 50 -1 92 11)(font \"Arial\" (font_size 10)))\n\t(text \"inst\" (rect 8 208 20 220)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 72)\n\t\t(input)\n\t\t(text \"refclk\" (rect 0 0 22 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"refclk\" (rect 4 61 40 72)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 72)(pt 48 72)(line_width 1))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"rst\" (rect 0 0 10 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"rst\" (rect 4 101 22 112)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 48 112)(line_width 1))\n\t)\n\t(port\n\t\t(pt 160 72)\n\t\t(output)\n\t\t(text \"outclk_0\" (rect 0 0 33 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"outclk_0\" (rect 117 61 165 72)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 72)(pt 112 72)(line_width 1))\n\t)\n\t(port\n\t\t(pt 160 112)\n\t\t(output)\n\t\t(text \"outclk_1\" (rect 0 0 31 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"outclk_1\" (rect 119 101 167 112)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 112)(pt 112 112)(line_width 1))\n\t)\n\t(port\n\t\t(pt 160 152)\n\t\t(output)\n\t\t(text \"outclk_2\" (rect 0 0 33 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"outclk_2\" (rect 117 141 165 152)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 152)(pt 112 152)(line_width 1))\n\t)\n\t(port\n\t\t(pt 160 192)\n\t\t(output)\n\t\t(text \"locked\" (rect 0 0 24 12)(font \"Arial\" (font_size 8)))\n\t\t(text \"locked\" (rect 127 181 163 192)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 192)(pt 112 192)(line_width 1))\n\t)\n\t(drawing\n\t\t(text \"refclk\" (rect 16 43 68 99)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"clk\" (rect 53 67 124 144)(font \"Arial\" (color 0 0 0)))\n\t\t(text \"reset\" (rect 19 83 68 179)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"reset\" (rect 53 107 136 224)(font \"Arial\" (color 0 0 0)))\n\t\t(text \"outclk0\" (rect 113 43 268 99)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"clk\" (rect 97 67 212 144)(font \"Arial\" (color 0 0 0)))\n\t\t(text \"outclk1\" (rect 113 83 268 179)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"clk\" (rect 97 107 212 224)(font \"Arial\" (color 0 0 0)))\n\t\t(text \"outclk2\" (rect 113 123 268 259)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"clk\" (rect 97 147 212 304)(font \"Arial\" (color 0 0 0)))\n\t\t(text \"locked\" (rect 113 163 262 339)(font \"Arial\" (color 128 0 0)(font_size 9)))\n\t\t(text \"export\" (rect 82 187 200 384)(font \"Arial\" (color 0 0 0)))\n\t\t(text \" altera_pll \" (rect 118 208 308 426)(font \"Arial\" ))\n\t\t(line (pt 48 32)(pt 112 32)(line_width 1))\n\t\t(line (pt 112 32)(pt 112 208)(line_width 1))\n\t\t(line (pt 48 208)(pt 112 208)(line_width 1))\n\t\t(line (pt 48 32)(pt 48 208)(line_width 1))\n\t\t(line (pt 49 52)(pt 49 76)(line_width 1))\n\t\t(line (pt 50 52)(pt 50 76)(line_width 1))\n\t\t(line (pt 49 92)(pt 49 116)(line_width 1))\n\t\t(line (pt 50 92)(pt 50 116)(line_width 1))\n\t\t(line (pt 111 52)(pt 111 76)(line_width 1))\n\t\t(line (pt 110 52)(pt 110 76)(line_width 1))\n\t\t(line (pt 111 92)(pt 111 116)(line_width 1))\n\t\t(line (pt 110 92)(pt 110 116)(line_width 1))\n\t\t(line (pt 111 132)(pt 111 156)(line_width 1))\n\t\t(line (pt 110 132)(pt 110 156)(line_width 1))\n\t\t(line (pt 111 172)(pt 111 196)(line_width 1))\n\t\t(line (pt 110 172)(pt 110 196)(line_width 1))\n\t\t(line (pt 0 0)(pt 160 0)(line_width 1))\n\t\t(line (pt 160 0)(pt 160 224)(line_width 1))\n\t\t(line (pt 0 224)(pt 160 224)(line_width 1))\n\t\t(line (pt 0 0)(pt 0 224)(line_width 1))\n\t)\n)\n" }, { "path": "verilog/pll_24_100.cmp", "content": "\tcomponent pll_24_100 is\n\t\tport (\n\t\t\trefclk : in std_logic := 'X'; -- clk\n\t\t\trst : in std_logic := 'X'; -- reset\n\t\t\toutclk_0 : out std_logic; -- clk\n\t\t\toutclk_1 : out std_logic; -- clk\n\t\t\toutclk_2 : out std_logic; -- clk\n\t\t\tlocked : out std_logic -- export\n\t\t);\n\tend component pll_24_100;\n\n" }, { "path": "verilog/pll_24_100.ppf", "content": "\n\n \n \n \n \n \n \n \n \n\n" }, { "path": "verilog/pll_24_100.qip", "content": "set_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_TOOL_NAME \"altera_pll\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_TOOL_VERSION \"18.0\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_TOOL_ENV \"mwpim\"\nset_global_assignment -library \"pll_24_100\" -name MISC_FILE [file join $::quartus(qip_path) \"pll_24_100.cmp\"]\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_TARGETED_DEVICE_FAMILY \"Cyclone V\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_GENERATED_DEVICE_FAMILY \"{Cyclone V}\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_QSYS_MODE \"UNKNOWN\"\nset_global_assignment -name SYNTHESIS_ONLY_QIP ON\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_NAME \"cGxsXzI0XzEwMA==\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_DISPLAY_NAME \"UExMIEludGVsIEZQR0EgSVA=\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_REPORT_HIERARCHY \"Off\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_INTERNAL \"Off\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_AUTHOR \"SW50ZWwgQ29ycG9yYXRpb24=\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_VERSION \"MTguMA==\"\nset_global_assignment -entity \"pll_24_100\" -library \"pll_24_100\" -name IP_COMPONENT_DESCRIPTION \"SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_NAME \"cGxsXzI0XzEwMF8wMDAy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_DISPLAY_NAME \"UExMIEludGVsIEZQR0EgSVA=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_REPORT_HIERARCHY \"Off\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_INTERNAL \"Off\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_AUTHOR \"SW50ZWwgQ29ycG9yYXRpb24=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_VERSION \"MTguMA==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_DESCRIPTION \"SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwxMywxMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMsMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1LDUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwzMCwyMDAwLDYwMC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssZmFsc2U=::UGFyYW1ldGVyIFZhbHVlcw==\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_COMPONENT_PARAMETER \"Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=\"\n\nset_global_assignment -library \"pll_24_100\" -name VERILOG_FILE [file join $::quartus(qip_path) \"pll_24_100.v\"]\nset_global_assignment -library \"pll_24_100\" -name VERILOG_FILE [file join $::quartus(qip_path) \"pll_24_100/pll_24_100_0002.v\"]\nset_global_assignment -library \"pll_24_100\" -name QIP_FILE [file join $::quartus(qip_path) \"pll_24_100/pll_24_100_0002.qip\"]\n\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_TOOL_NAME \"altera_pll\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_TOOL_VERSION \"18.0\"\nset_global_assignment -entity \"pll_24_100_0002\" -library \"pll_24_100\" -name IP_TOOL_ENV \"mwpim\"\n" }, { "path": "verilog/pll_24_100.sip", "content": "set_global_assignment -entity \"pll_24_100\" -library \"lib_pll_24_100\" -name IP_TOOL_NAME \"altera_pll\"\nset_global_assignment -entity \"pll_24_100\" -library \"lib_pll_24_100\" -name IP_TOOL_VERSION \"18.0\"\nset_global_assignment -entity \"pll_24_100\" -library \"lib_pll_24_100\" -name IP_TOOL_ENV \"mwpim\"\nset_global_assignment -library \"lib_pll_24_100\" -name SPD_FILE [file join $::quartus(sip_path) \"pll_24_100.spd\"]\n\nset_global_assignment -library \"lib_pll_24_100\" -name MISC_FILE [file join $::quartus(sip_path) \"pll_24_100_sim/pll_24_100.vo\"]\n" }, { "path": "verilog/pll_24_100.spd", "content": "\n\n \n \n \n\n" }, { "path": "verilog/pll_24_100.v", "content": "// megafunction wizard: %PLL Intel FPGA IP v18.0%\n// GENERATION: XML\n// pll_24_100.v\n\n// Generated using ACDS version 18.0 614\n\n`timescale 1 ps / 1 ps\nmodule pll_24_100 (\n\t\tinput wire refclk, // refclk.clk\n\t\tinput wire rst, // reset.reset\n\t\toutput wire outclk_0, // outclk0.clk\n\t\toutput wire outclk_1, // outclk1.clk\n\t\toutput wire outclk_2, // outclk2.clk\n\t\toutput wire locked // locked.export\n\t);\n\n\tpll_24_100_0002 pll_24_100_inst (\n\t\t.refclk (refclk), // refclk.clk\n\t\t.rst (rst), // reset.reset\n\t\t.outclk_0 (outclk_0), // outclk0.clk\n\t\t.outclk_1 (outclk_1), // outclk1.clk\n\t\t.outclk_2 (outclk_2), // outclk2.clk\n\t\t.locked (locked) // locked.export\n\t);\n\nendmodule\n// Retrieval info: \n//\n// Retrieval info: \n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval info: \t\n// Retrieval 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Corporation. All rights reserved.\n# Your use of Altera Corporation's design tools, logic functions and \n# other software and tools, and its AMPP partner logic functions, and \n# any output files any of the foregoing (including device programming \n# or simulation files), and any associated documentation or information \n# are expressly subject to the terms and conditions of the Altera \n# Program License Subscription Agreement, Altera MegaCore Function \n# License Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by Altera \n# or its authorized distributors. Please refer to the applicable \n# agreement for further details.\n\n# ACDS 18.0 614 win32 2019.08.23.14:15:47\n# ----------------------------------------\n# Auto-generated simulation script rivierapro_setup.tcl\n# ----------------------------------------\n# This script provides commands to simulate the following IP detected in\n# your Quartus project:\n# pll_24_100\n# \n# Altera recommends that you source this Quartus-generated IP simulation\n# script from your own customized top-level script, and avoid editing this\n# generated script.\n# \n# To write a top-level script that compiles Altera simulation libraries and\n# the Quartus-generated IP in your project, along with your design and\n# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below\n# into a new file, e.g. named \"aldec.do\", and modify the text as directed.\n# \n# ----------------------------------------\n# # TOP-LEVEL TEMPLATE - BEGIN\n# #\n# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to\n# # construct paths to the files required to simulate the IP in your Quartus\n# # project. By default, the IP script assumes that you are launching the\n# # simulator from the IP script location. If launching from another\n# # location, set QSYS_SIMDIR to the output directory you specified when you\n# # generated the IP script, relative to the directory from which you launch\n# # the simulator.\n# #\n# set QSYS_SIMDIR