Repository: ZFTurbo/MobileNet-in-FPGA Branch: master Commit: 24eb350e48c0 Files: 61 Total size: 1.7 MB Directory structure: gitextract_rr5i2nao/ ├── README.md ├── a00_common_functions.py ├── a01_oid_utils.py ├── docs/ │ └── Writing_weights_to_memory_using_UART.md ├── r01_prepare_open_images_dataset.py ├── r02_train_mobilenet.py ├── r03_mobilenet_v1_reduce_and_scale_model.py ├── r03_remove_batchnorm_layers.py ├── r04_find_optimal_bit_for_weights.py ├── r05_gen_weights_in_verilog_format.py ├── r06_generate_debug_data.py ├── r07_generate_verilog_for_mobilenet.py ├── r08_generate_weights_file_for_FPGA.py ├── utils/ │ └── data_uart_to_fpga.py └── verilog/ ├── CAMERA/ │ ├── camera_controller.v │ ├── cmos_i2c_ov5640/ │ │ ├── CMOS_Capture.v │ │ ├── i2c_com.v │ │ ├── ov5640_cfg.v │ │ ├── power_on_delay.v │ │ └── reg_config.v │ ├── sdram_ov5640_vga.v │ └── system_ctrl.v ├── GENERAL.qsf ├── GENERAL.qws ├── GENERAL.v ├── MobileNet_v3_conv_8_3x1/ │ ├── RAM.v │ ├── RAMtoMEM.v │ ├── TOP.v │ ├── addressRAM.v │ ├── border.v │ ├── conv.v │ ├── conv_TOP.v │ ├── dense.v │ └── result.v ├── OpenVino_MobileNet.qpf ├── RAM.v ├── Seg7.v ├── UART/ │ ├── async.v │ └── serialGPIO.v ├── ili9341/ │ ├── tft_ili9341.sv │ └── tft_ili9341_spi.sv ├── pll_24_100/ │ ├── pll_24_100_0002.qip │ └── pll_24_100_0002.v ├── pll_24_100.bsf ├── pll_24_100.cmp ├── pll_24_100.ppf ├── pll_24_100.qip ├── pll_24_100.sip ├── pll_24_100.spd ├── pll_24_100.v ├── pll_24_100_sim/ │ ├── aldec/ │ │ └── rivierapro_setup.tcl │ ├── cadence/ │ │ ├── cds.lib │ │ ├── hdl.var │ │ └── ncsim_setup.sh │ ├── mentor/ │ │ └── msim_setup.tcl │ ├── pll_24_100.vo │ └── synopsys/ │ ├── vcs/ │ │ └── vcs_setup.sh │ └── vcsmx/ │ ├── synopsys_sim.setup │ └── vcsmx_setup.sh ├── pll_24_100_sim.f └── scale_picture.v ================================================ FILE CONTENTS ================================================ ================================================ FILE: README.md ================================================ # MobileNet in FPGA Generator of verilog description for FPGA MobileNet implementation. There are several pre-trained models available for frequent tasks like detection of people, cars and animals. You can train your own model easily on your dataset using code from this repository and have the same very fast detector on FPGA working in real time for your own task. ## Software requirements Python 3.*, keras 2.2.4, tensorflow, kito ## Hardware requirements 1) TFT-screen ILI9341 Size: 2.8", Resolution: 240x320, Interface: SPI 2) Camera OV5640. Active array size: 2592 x 1944 3) OpenVINO Starter Kit. Cyclone V (301K LE, 13,917 Kbits embedded memory) ## Demo [![Youtube demo](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/Youtube-Screenshot.jpg)](https://www.youtube.com/watch?v=EQ9MJnWeHlo) ## How to run 1) `python3 r01_prepare_open_images_dataset.py` - it will create training files using [Open Images Dataset (OID)](https://storage.googleapis.com/openimages/web/index.html). 2) `python3 r02_train_mobilenet.py` - run training process. Will create weights for model and output accuracy of model. 3) `python3 r03_mobilenet_v1_reduce_and_scale_model.py` - batchnorm fusion and rescale model on range (0, 1) instead of (0, 6). Returns new rescaled model Note: You can skip part 1, 2 and 3 if you use our pretrained weight files below 4) `python3 r04_find_optimal_bit_for_weights.py` - code to find optimal bit for feature maps, weights and biases, also returns maximum overflow for weights and biases over 1.0 value. 5) `python3 r05_gen_weights_in_verilog_format.py` - generate weights in verliog format using optimal bits from previous step 6) `python3 r06_generate_debug_data.py` - generate intermediate feature maps for each layer and details about first pixel calculation (can be used for debug) 7) `python3 r07_generate_verilog_for_mobilenet.py` - generate verilog based on given model and parameters like number of convolution blocks ## Updates * **2019.10.04** We greatly improved speed of image reading and preprocessing. Now it takes only 5% of total time instead of 77% earlier. Speed for 8 convolution version of device increased from ~10 FPS up to ~ 40 FPS. ## Pre-trained models | | People detector (128px) | Cars detector (128px) | Animals detector (128px) | | --- | --- | --- | --- | | Accuracy (%) | 84.42 | 96.31 | 89.67 | | Init model (can be used for training and fine-tuning) | [people.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38.h5) | [cars.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67.h5) | [animals.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5) | | Reduced and rescaled model | [people.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5) | [cars.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5) | [animals.h5](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v1.0/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5) | | Optimal bits found | 12, 11, 10, 7, 3 | 10, 9, 8, 7, 3 | 12, 11, 10, 7, 3 | | Quartus project (verilog) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_people.zip) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_cars.zip) | [link](https://github.com/ZFTurbo/MobileNet-in-FPGA/releases/download/v2.0/OpenVino_MobileNet_verilog_project_animals.zip) | ## Connection of peripherals ![Connection of peripherals](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/Connection-of-Periferals.png) ## Writing weights in memory [See guide](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/docs/Writing_weights_to_memory_using_UART.md) ## Description of method [Innovate FPGA](http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=EM031) ================================================ FILE: a00_common_functions.py ================================================ # Util functions import pickle import gzip import cv2 import numpy as np import pandas as pd import os import glob import random ROOT_PATH = os.path.dirname(os.path.realpath(__file__)) + '/' MODEL_PATH = ROOT_PATH + 'models/' if not os.path.isdir(MODEL_PATH): os.mkdir(MODEL_PATH) CACHE_PATH = ROOT_PATH + 'cache/' if not os.path.isdir(CACHE_PATH): os.mkdir(CACHE_PATH) def save_in_file(arr, file_name): pickle.dump(arr, gzip.open(file_name, 'wb+', compresslevel=3)) def load_from_file(file_name): return pickle.load(gzip.open(file_name, 'rb')) def show_image(im, name='image'): cv2.imshow(name, im.astype(np.uint8)) cv2.waitKey(0) cv2.destroyAllWindows() def show_resized_image(P, w=1000, h=1000): res = cv2.resize(P.astype(np.uint8), (w, h), interpolation=cv2.INTER_CUBIC) show_image(res) def relu_1(x): from keras.activations import relu return relu(x, max_value=1.0) def save_history(history, path, columns=('loss', 'val_loss')): import matplotlib.pyplot as plt import pandas as pd s = pd.DataFrame(history.history) s.to_csv(path + '.csv') plt.plot(s[list(columns)]) plt.savefig(path + '.png') plt.close() def get_model(weights_path): from keras.models import load_model print('Load: {}'.format(weights_path)) model = load_model(weights_path, custom_objects={'relu_1': relu_1}) print('Number of layers: {}'.format(len(model.layers))) return model def get_model_memory_usage(batch_size, model): import numpy as np from keras import backend as K shapes_mem_count = 0 for l in model.layers: single_layer_mem = 1 for s in l.output_shape: if s is None: continue single_layer_mem *= s shapes_mem_count += single_layer_mem trainable_count = np.sum([K.count_params(p) for p in set(model.trainable_weights)]) non_trainable_count = np.sum([K.count_params(p) for p in set(model.non_trainable_weights)]) number_size = 4.0 if K.floatx() == 'float16': number_size = 2.0 if K.floatx() == 'float64': number_size = 8.0 total_memory = number_size*(batch_size*shapes_mem_count + trainable_count + non_trainable_count) gbytes = np.round(total_memory / (1024.0 ** 3), 3) return gbytes ================================================ FILE: a01_oid_utils.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' import platform from PIL import Image from a00_common_functions import * # Paths and constants if platform.processor() == 'Intel64 Family 6 Model 79 Stepping 1, GenuineIntel': DATASET_PATH = 'E:/Projects_M2/2019_06_Google_Open_Images/input/' else: DATASET_PATH = 'E:/Projects_2TB/2019_06_Google_Open_Images/input/' STORAGE_PATH_TRAIN = DATASET_PATH + 'train/' STORAGE_PATH_TEST = DATASET_PATH + 'test/' STORAGE_PATH_VALID = DATASET_PATH + 'validation/' OID_CLASS_DESCRIPTION = DATASET_PATH + 'data_detection/challenge-2019-classes-description-500.csv' OID_ANNOTATIONS_TRAIN = DATASET_PATH + 'data_detection/challenge-2019-train-detection-bbox.csv' OID_ANNOTATIONS_VALID = DATASET_PATH + 'data_detection/challenge-2019-validation-detection-bbox.csv' def get_model_memory_usage(batch_size, model): import numpy as np from keras import backend as K shapes_mem_count = 0 for l in model.layers: single_layer_mem = 1 for s in l.output_shape: if s is None: continue single_layer_mem *= s shapes_mem_count += single_layer_mem trainable_count = np.sum([K.count_params(p) for p in set(model.trainable_weights)]) non_trainable_count = np.sum([K.count_params(p) for p in set(model.non_trainable_weights)]) number_size = 4.0 if K.floatx() == 'float16': number_size = 2.0 if K.floatx() == 'float64': number_size = 8.0 total_memory = number_size*(batch_size*shapes_mem_count + trainable_count + non_trainable_count) gbytes = np.round(total_memory / (1024.0 ** 3), 3) return gbytes def get_description_for_labels(): out = open(OID_CLASS_DESCRIPTION) lines = out.readlines() ret_1, ret_2 = dict(), dict() for l in lines: arr = l.strip().split(',') ret_1[arr[0]] = arr[1] ret_2[arr[1]] = arr[0] return ret_1, ret_2 def random_intensity_change(img, max_change): img = img.astype(np.float32) for j in range(3): delta = random.randint(-max_change, max_change) img[:, :, j] += delta img[img < 0] = 0 img[img > 255] = 255 return img def random_rotate(image, max_angle): cols = image.shape[1] rows = image.shape[0] angle = random.uniform(-max_angle, max_angle) M = cv2.getRotationMatrix2D((cols // 2, rows // 2), angle, 1) dst = cv2.warpAffine(image, M, (cols, rows), borderMode=cv2.BORDER_REFLECT) return dst def read_single_image(path): try: img = np.array(Image.open(path)) except: try: img = cv2.cvtColor(cv2.imread(path), cv2.COLOR_BGR2RGB) except: print('Fail') return None if len(img.shape) == 2: img = cv2.cvtColor(img, cv2.COLOR_GRAY2RGB) if img.shape[2] == 2: img = img[:, :, :1] if img.shape[2] == 1: img = np.concatenate((img, img, img), axis=2) if img.shape[2] > 3: img = img[:, :, :3] return img def read_image_bgr_fast(path): img2 = cv2.imread(path) return img2 def prepare_training_csv(type, true_labels_enc, output_path, side_size=128, min_class_size=5): print('Go for: {} True labels: {}'.format(type, true_labels_enc)) if type == 'train': boxes = pd.read_csv(OID_ANNOTATIONS_TRAIN) else: boxes = pd.read_csv(OID_ANNOTATIONS_VALID) print('Initial boxes: {}'.format(len(boxes))) image_ids = boxes['ImageID'].unique() print('Unique images: {}'.format(len(image_ids))) boxes_part = boxes[boxes['LabelName'].isin(true_labels_enc)] print('Potential needed class boxes: {}'.format(len(boxes_part))) print('Potential images with class: {}'.format(len(boxes_part['ImageID'].unique()))) images_with_needed_class = set() for index, row in boxes_part.iterrows(): x1 = row['XMin'] x2 = row['XMax'] y1 = row['YMin'] y2 = row['YMax'] if (x2-x1)*side_size >= min_class_size and (y2-y1)*side_size >= min_class_size: images_with_needed_class |= {row['ImageID']} print('Images with class reduced: {}'.format(len(images_with_needed_class))) no_class = list(set(image_ids) - set(images_with_needed_class)) print('Images without class: {}'.format(len(no_class))) out = open(output_path, 'w') out.write('id,target\n') for id in sorted(list(images_with_needed_class)): out.write(id + ',1\n') for id in sorted(list(no_class)): out.write(id + ',0\n') out.close() def check_validation_set(input_csv): s = pd.read_csv(input_csv) print('Go for true') s_true = s[s['target'] == 1] ids_true = list(s_true['id'].values) for id in ids_true[:10]: img = cv2.imread(STORAGE_PATH_VALID + id + '.jpg') show_image(img) print('Go for false') s_true = s[s['target'] == 0] ids_true = list(s_true['id'].values) for id in ids_true[:10]: img = cv2.imread(STORAGE_PATH_VALID + id + '.jpg') show_image(img) def check_train_set(input_csv): s = pd.read_csv(input_csv) print('Go for true') s_true = s[s['target'] == 1] ids_true = list(s_true['id'].values) for id in ids_true[:10]: img = cv2.imread(STORAGE_PATH_TRAIN + id[:3] + '/' + id + '.jpg') show_image(img) print('Go for false') s_true = s[s['target'] == 0] ids_true = list(s_true['id'].values) for id in ids_true[:10]: img = cv2.imread(STORAGE_PATH_TRAIN + id[:3] + '/' + id + '.jpg') show_image(img) def get_class_labels(true_labels): d1, d2 = get_description_for_labels() arr = [] for t in true_labels: arr.append(d2[t]) print(arr) return arr ================================================ FILE: docs/Writing_weights_to_memory_using_UART.md ================================================ The [UART](https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter) port is used to write the neural net weights to the FPGA memory. And the weights are transferred directly from the PC using the Python language. First you need to connect all the necessary wires to OpenVino. See picture below. ![Wires](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/FPGA-Img-01.jpg) Next, turn on the device. Then launch Quartus Prime (we used version 18.0) and flash the entire project using Programmer. Next, run a special Python script: [data_uart_to_fpga.py](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/utils/data_uart_to_fpga.py). Make sure that your folder with weights is next to the executable file and has the correct name. Depending on what weights you need - for people, animals or cars - select the appropriate file. It must be written in the code [WEIGHT_FILE_TO_USE](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/utils/data_uart_to_fpga.py#L4). If everything is done correctly then progress will go. ![Wires](https://github.com/ZFTurbo/MobileNet-in-FPGA/blob/master/img/FPGA-Img-04.png) Upon completion of loading weights, an image from the camera will appear on the screen and the neural network will start to recognize it. The result will be displayed in the upper left corner in red (there is an required object) or in green (the required object is missing). ================================================ FILE: r01_prepare_open_images_dataset.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' ''' Prepare dataset for different classes from Open Images Dataset (OID) from google 1) Class must be at least 5px size (for 128x128 image) ''' if __name__ == '__main__': import os gpu_use = 0 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from a01_oid_utils import * # Definition for people TRUE_LABELS_PEOPLE = ['Person', 'Man', 'Woman', 'Boy', 'Girl', 'Human body', 'Human eye', 'Skull', 'Human head', 'Human face', 'Human mouth', 'Human ear', 'Human nose', 'Human hair', 'Human hand', 'Human foot', 'Human arm', 'Human leg', 'Human beard'] TRUE_LABELS_PEOPLE_ENC = ['/m/01g317', '/m/04yx4', '/m/03bt1vf', '/m/01bl7v', '/m/05r655', '/m/02p0tk3', '/m/014sv8', '/m/016m2d', '/m/04hgtk', '/m/0dzct', '/m/0283dt1', '/m/039xj_', '/m/0k0pj', '/m/03q69', '/m/0k65p', '/m/031n1', '/m/0dzf4', '/m/035r7c', '/m/015h_t'] # Definition for cars TRUE_LABELS_CAR = ['Car', 'Van', 'Taxi', 'Limousine', 'Truck', 'Bus', 'Ambulance'] TRUE_LABELS_CAR_ENC = ['/m/0k4j', '/m/0h2r6', '/m/0pg52', '/m/01lcw4', '/m/07r04', '/m/01bjv', '/m/012n7d'] # Definition for animals TRUE_LABELS_ANIMAL = ['Animal', 'Bird', 'Woodpecker', 'Blue jay', 'Ostrich', 'Penguin', 'Raven', 'Chicken', 'Eagle', 'Owl', 'Duck', 'Canary', 'Goose', 'Swan', 'Falcon', 'Parrot', 'Sparrow', 'Turkey', 'Invertebrate', 'Tick', 'Centipede', 'Marine invertebrates', 'Starfish', 'Lobster', 'Jellyfish', 'Shrimp', 'Crab', 'Insect', 'Bee', 'Beetle', 'Ladybug', 'Ant', 'Moths and butterflies', 'Caterpillar', 'Butterfly', 'Dragonfly', 'Spider', 'Oyster', 'Snail', 'Bat', 'Carnivore', 'Bear', 'Brown bear', 'Polar bear', 'Cat', 'Fox', 'Jaguar', 'Lynx', 'Tiger', 'Lion', 'Dog', 'Leopard', 'Cheetah', 'Otter', 'Raccoon', 'Camel', 'Cattle', 'Giraffe', 'Rhinoceros', 'Goat', 'Horse', 'Hamster', 'Kangaroo', 'Mouse', 'Pig', 'Rabbit', 'Squirrel', 'Sheep', 'Zebra', 'Monkey', 'Deer', 'Elephant', 'Porcupine', 'Bull', 'Antelope', 'Mule', 'Marine mammal', 'Dolphin', 'Whale', 'Sea lion', 'Harbor seal', 'Alpaca', 'Reptile', 'Dinosaur', 'Lizard', 'Snake', 'Turtle', 'Tortoise', 'Sea turtle', 'Crocodile', 'Frog', 'Fish', 'Goldfish', 'Shark', 'Seahorse', 'Shellfish'] TRUE_LABELS_ANIMAL_ENC = ['/m/0jbk', '/m/015p6', '/m/01dy8n', '/m/01f8m5', '/m/05n4y', '/m/05z6w', '/m/06j2d', '/m/09b5t', '/m/09csl', '/m/09d5_', '/m/09ddx', '/m/0ccs93', '/m/0dbvp', '/m/0dftk', '/m/0f6wt', '/m/0gv1x', '/m/0h23m', '/m/0jly1', '/m/03xxp', '/m/0175cv', '/m/019h78', '/m/03hl4l9', '/m/01h8tj', '/m/0cjq5', '/m/0d8zb', '/m/0ll1f78', '/m/0n28_', '/m/03vt0', '/m/01h3n', '/m/020jm', '/m/0gj37', '/m/0_k2', '/m/0d_2m', '/m/0cydv', '/m/0cyf8', '/m/0ft9s', '/m/09kmb', '/m/0_cp5', '/m/0f9_l', '/m/01h44', '/m/01lrl', '/m/01dws', '/m/01dxs', '/m/0633h', '/m/01yrx', '/m/0306r', '/m/0449p', '/m/04g2r', '/m/07dm6', '/m/096mb', '/m/0bt9lr', '/m/0c29q', '/m/0cd4d', '/m/0cn6p', '/m/0dq75', '/m/01x_v', '/m/01xq0k1', '/m/03bk1', '/m/03d443', '/m/03fwl', '/m/03k3r', '/m/03qrc', '/m/04c0y', '/m/04rmv', '/m/068zj', '/m/06mf6', '/m/071qp', '/m/07bgp', '/m/0898b', '/m/08pbxl', '/m/09kx5', '/m/0bwd_0j', '/m/0c568', '/m/0cnyhnx', '/m/0czz2', '/m/0dbzx', '/m/0gd2v', '/m/02hj4', '/m/084zz', '/m/0gd36', '/m/02l8p9', '/m/0pcr', '/m/06bt6', '/m/029tx', '/m/04m9y', '/m/078jl', '/m/09dzg', '/m/011k07', '/m/0120dh', '/m/09f_2', '/m/09ld4', '/m/0ch_cf', '/m/03fj2', '/m/0by6g', '/m/0nybt', '/m/0fbdv'] SIDE_SIZE = 128 MIN_CLASS_SIZE = 5 if __name__ == '__main__': # Prepare people CSV prepare_training_csv('validation', TRUE_LABELS_PEOPLE_ENC, CACHE_PATH + 'oid_validation_people.csv', SIDE_SIZE, MIN_CLASS_SIZE) prepare_training_csv('train', TRUE_LABELS_PEOPLE_ENC, CACHE_PATH + 'oid_train_people.csv', SIDE_SIZE, MIN_CLASS_SIZE) # Prepare cars CSV prepare_training_csv('validation', TRUE_LABELS_CAR_ENC, CACHE_PATH + 'oid_validation_cars.csv', SIDE_SIZE, MIN_CLASS_SIZE) prepare_training_csv('train', TRUE_LABELS_CAR_ENC, CACHE_PATH + 'oid_train_cars.csv', SIDE_SIZE, MIN_CLASS_SIZE) # Prepare animals CSV prepare_training_csv('validation', TRUE_LABELS_ANIMAL_ENC, CACHE_PATH + 'oid_validation_animals.csv', SIDE_SIZE, MIN_CLASS_SIZE) prepare_training_csv('train', TRUE_LABELS_ANIMAL_ENC, CACHE_PATH + 'oid_train_animals.csv', SIDE_SIZE, MIN_CLASS_SIZE) ================================================ FILE: r02_train_mobilenet.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' # Train MobileNet with batch generator and augmentations # Made for training with tensorflow only import os import glob if __name__ == '__main__': # Block to choose GPU gpu_use = 2 print('GPU use: {}'.format(gpu_use)) os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) import tensorflow as tf config = tf.ConfigProto() config.gpu_options.allow_growth = True session = tf.Session(config=config) MOBILENET_VERSION = 1 MOBILENET_ALFA = 0.25 MOBILENET_INPUT_SIZE = 128 CHANNEL_TYPE = 'RGB' from functools import partial from keras import backend as K from keras.optimizers import SGD, Adam if MOBILENET_VERSION == 1: from keras.applications.mobilenet import MobileNet, preprocess_input else: from keras.applications.mobilenet_v2 import MobileNetV2, preprocess_input from keras.layers.core import Dense from keras.models import Model from a01_oid_utils import * from a00_common_functions import * from albumentations import * import pandas as pd from r01_prepare_open_images_dataset import DATASET_PATH from multiprocessing.pool import ThreadPool from multiprocessing import cpu_count import random def strong_aug(p=.5): return Compose([ # RandomRotate90(), HorizontalFlip(p=0.5), # Transpose(), OneOf([ IAAAdditiveGaussianNoise(), GaussNoise(), ], p=0.1), OneOf([ MotionBlur(p=.2), MedianBlur(blur_limit=3, p=.1), Blur(blur_limit=3, p=.1), ], p=0.1), ShiftScaleRotate(shift_limit=0.0625, scale_limit=0.2, rotate_limit=10, p=0.1), OneOf([ OpticalDistortion(p=0.3), GridDistortion(p=0.1), IAAPiecewiseAffine(p=0.3), ], p=0.1), OneOf([ CLAHE(clip_limit=2), IAASharpen(), IAAEmboss(), ], p=0.3), RGBShift(p=0.1, r_shift_limit=(-30, 30), g_shift_limit=(-30, 30), b_shift_limit=(-30, 30)), RandomBrightnessContrast(p=0.05), HueSaturationValue(p=0.05), ToGray(p=0.05), JpegCompression(p=0.05, quality_lower=55, quality_upper=99), ElasticTransform(p=0.05), ], p=p) GLOBAL_AUG = strong_aug(p=1.0) def process_single_item(id, box_size, validation=True): global global_aug # Important: RGB order! if validation is not True: file_path = DATASET_PATH + 'train/' + id[:3] + '/' + id + '.jpg' else: file_path = DATASET_PATH + 'validation/' + id + '.jpg' if CHANNEL_TYPE == 'RGB': img = read_single_image(file_path) else: img = read_image_bgr_fast(file_path) if img is None: img = np.zeros((box_size, box_size, 3), dtype=np.uint8) if validation is not True: # img = GLOBAL_AUG(image=img)['image'] if 1: img = random_intensity_change(img, 10) img = random_rotate(img, 10) if random.randint(0, 1) == 0: # fliplr img = img[:, ::-1, :] if img.shape[0] != box_size: img = cv2.resize(img, (box_size, box_size), interpolation=cv2.INTER_LINEAR) return img def batch_generator(X_train, Y_train, batch_size, input_size, prep_input, validation): threads = cpu_count() - 1 p = ThreadPool(threads) process_item_func = partial(process_single_item, validation=validation, box_size=input_size) # Do around 50% of batch to have required class X_train_no_class = X_train[Y_train[:, 1] == 0] X_train_with_class = X_train[Y_train[:, 1] == 1] Y_train_no_class = Y_train[Y_train[:, 1] == 0] Y_train_with_class = Y_train[Y_train[:, 1] == 1] print('Use threads: {}'.format(threads)) print(X_train_no_class.shape, X_train_with_class.shape, Y_train_no_class.shape, Y_train_with_class.shape) b1 = batch_size // 2 b2 = batch_size - b1 while True: batch_indexes_no_cars = np.random.choice(X_train_no_class.shape[0], b1) batch_indexes_with_cars = np.random.choice(X_train_with_class.shape[0], b2) batch_image_files = np.concatenate( (X_train_no_class[batch_indexes_no_cars].copy(), X_train_with_class[batch_indexes_with_cars].copy()) ) batch_classes = np.concatenate( (Y_train_no_class[batch_indexes_no_cars].copy(), Y_train_with_class[batch_indexes_with_cars].copy()) ) batch_images = p.map(process_item_func, batch_image_files) batch_images = np.array(batch_images, np.float32) batch_images = prep_input(batch_images) yield batch_images, batch_classes def evaluate_generator(X_test, Y_test, batch_size, input_size, prep_input): number_of_batches = X_test.shape[0] // batch_size target_size = input_size i = 0 while 1: batch_images = np.zeros((batch_size, target_size, target_size, 3)) if i >= number_of_batches: print('Current {}'.format(i)) batch_image_files = X_test[-batch_size:] batch_classes = Y_test[-batch_size:] else: batch_image_files = X_test[i*batch_size:(i+1)*batch_size] batch_classes = Y_test[i*batch_size:(i+1)*batch_size] # Rescale to 128x128 for j in range(batch_size): path = DATASET_PATH + 'validation/' + batch_image_files[j] + '.jpg' if CHANNEL_TYPE == 'RGB': img = read_single_image(path) else: img = read_image_bgr_fast(path) if img.shape[0] != target_size: img = cv2.resize(img, (target_size, target_size), interpolation=cv2.INTER_LINEAR) batch_images[j, :, :, :] = img batch_images = prep_input(batch_images) i += 1 yield batch_images, batch_classes def load_train_valid_data(train_csv, valid_csv): from keras.utils import to_categorical valid = pd.read_csv(valid_csv) train = pd.read_csv(train_csv) X_train = train['id'].values Y_train = to_categorical(train['target'].values, num_classes=2) X_valid = valid['id'].values Y_valid = to_categorical(valid['target'].values, num_classes=2) return X_train, Y_train, X_valid, Y_valid def train_mobile_net_v1(input_size, train_csv, valid_csv, type): from keras.callbacks import EarlyStopping, ModelCheckpoint, CSVLogger, ReduceLROnPlateau batch_size = 1024 nb_classes = 2 nb_epoch = 1000 patience = 50 optimizer = 'Adam' learning_rate = 0.0001 restore = 1 print('Train MobileNet version: {} Input size: {}'.format(MOBILENET_VERSION, input_size)) print('Train for {} epochs with patience {}. Batch size: {}. Optimizer: {} Learing rate: {}'. format(nb_epoch, patience, batch_size, optimizer, learning_rate)) X_train, Y_train, X_valid, Y_valid = load_train_valid_data(train_csv, valid_csv) print('Train shape: {}'.format(X_train.shape)) print('Valid shape: {}'.format(X_valid.shape)) print('Dim ordering:', K.image_dim_ordering()) if MOBILENET_VERSION == 1: alpha = MOBILENET_ALFA base_model = MobileNet((input_size, input_size, 3), depth_multiplier=1, alpha=alpha, include_top=False, pooling='avg', weights='imagenet') else: alpha = 0.35 base_model = MobileNetV2((input_size, input_size, 3), depth_multiplier=1, alpha=alpha, include_top=False, pooling='avg', weights='imagenet') x = base_model.output x = Dense(nb_classes, activation='softmax', name='predictions', use_bias=False)(x) model = Model(inputs=base_model.input, outputs=x) print(model.summary()) if optimizer == 'SGD': optim = SGD(lr=learning_rate, decay=1e-6, momentum=0.9, nesterov=True) else: optim = Adam(lr=learning_rate) model.compile(optimizer=optim, loss='categorical_crossentropy', metrics=['accuracy']) print('Model memory usage: {:.3f} GB'.format(get_model_memory_usage(batch_size, model))) if not os.path.isdir('cache'): os.mkdir('cache') prefix = 'mobilenet_{}_{:.2f}_{}px_{}'.format(MOBILENET_VERSION, alpha, input_size, type) cache_model_path = os.path.join(MODEL_PATH, 'weights_{}.h5'.format(prefix)) cache_model_path_score = MODEL_PATH + 'weights_{}_'.format(prefix) + 'loss_{val_loss:.4f}_acc_{val_acc:.4f}_epoch_{epoch:02d}_' + '{}.h5'.format(CHANNEL_TYPE) if os.path.isfile(cache_model_path) and restore: print('Restore weights from cache: {}'.format(cache_model_path)) model.load_weights(cache_model_path) history_path = os.path.join(MODEL_PATH, 'weights_mobilenet_{}_{:.2f}_{}px_people_v2.csv'.format(MOBILENET_VERSION, alpha, input_size)) callbacks = [ EarlyStopping(monitor='val_loss', patience=patience, verbose=0), ModelCheckpoint(cache_model_path, monitor='val_loss', save_best_only=True, verbose=0), ModelCheckpoint(cache_model_path_score, monitor='val_loss', save_best_only=False, verbose=0), CSVLogger(MODEL_PATH + 'history_{}_lr_{}_optim_{}_v2.csv'.format(type, learning_rate, optimizer), append=True), ReduceLROnPlateau(monitor='val_loss', factor=0.9, patience=5, min_lr=1e-9, min_delta=0.00001, verbose=1, mode='min'), ] steps_per_epoch = 100 validation_steps = X_valid.shape[0] // batch_size history = model.fit_generator(generator=batch_generator(X_train, Y_train, batch_size, input_size, preprocess_input, validation=False), epochs=nb_epoch, steps_per_epoch=steps_per_epoch, validation_data=batch_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input, validation=True), validation_steps=validation_steps, verbose=1, max_queue_size=16, initial_epoch=0, callbacks=callbacks) pd.DataFrame(history.history).to_csv(history_path, index=False) score = model.evaluate_generator(generator=evaluate_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input), steps=X_valid.shape[0] // batch_size, max_queue_size=1) print('Full validation loss: {:.4f} Full validation accuracy: {:.4f} (For best model)'.format(score[0], score[1])) print('Best model stored in {}'.format(cache_model_path)) return cache_model_path def evaluate_model(model_path, input_size, train_csv, valid_csv): from keras.models import load_model print('Load model: {}'.format(model_path)) model = load_model(model_path) batch_size = 1024 X_train, Y_train, X_valid, Y_valid = load_train_valid_data(train_csv, valid_csv) print('Train shape: {}'.format(X_train.shape)) print('Valid shape: {}'.format(X_valid.shape)) score = model.evaluate_generator( generator=evaluate_generator(X_valid, Y_valid, batch_size, input_size, preprocess_input), steps=X_valid.shape[0] // batch_size, max_queue_size=10, verbose=1) print('Full validation loss: {:.4f} Full validation accuracy: {:.4f} (For best model)'.format(score[0], score[1])) if __name__ == '__main__': type = 'people' # type = 'cars' # type = 'animals' train_csv = CACHE_PATH + 'oid_train_{}.csv'.format(type) valid_csv = CACHE_PATH + 'oid_validation_{}.csv'.format(type) # best_model_path = train_mobile_net_v1(MOBILENET_INPUT_SIZE, train_csv, valid_csv, type) best_model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38.h5' evaluate_model(best_model_path, MOBILENET_INPUT_SIZE, train_csv, valid_csv) ''' Animals MobileNet v1 (0.25, 128px): Ep 1: 1563s 16s/step - loss: 0.3970 - acc: 0.8251 - val_loss: 0.4029 - val_acc: 0.8228 Ep 2: 1413s 14s/step - loss: 0.3499 - acc: 0.8453 - val_loss: 0.4436 - val_acc: 0.7914 Ep 3: 1435s 14s/step - loss: 0.3365 - acc: 0.8518 - val_loss: 0.3098 - val_acc: 0.8671 Ep 4: 1425s 14s/step - loss: 0.3279 - acc: 0.8563 - val_loss: 0.3208 - val_acc: 0.8587 Ep 5: 1441s 14s/step - loss: 0.3204 - acc: 0.8597 - val_loss: 0.3832 - val_acc: 0.8334 Ep 6: 1501s 15s/step - loss: 0.3198 - acc: 0.8610 - val_loss: 0.5252 - val_acc: 0.7404 Ep 7: 1506s 15s/step - loss: 0.3170 - acc: 0.8621 - val_loss: 0.3017 - val_acc: 0.8725 Ep 8: 1502s 15s/step - loss: 0.3124 - acc: 0.8643 - val_loss: 0.2960 - val_acc: 0.8740 Ep 14:1464s 15s/step - loss: 0.3020 - acc: 0.8687 - val_loss: 0.2765 - val_acc: 0.8811 Ep 17:1504s 15s/step - loss: 0.2951 - acc: 0.8712 - val_loss: 0.2786 - val_acc: 0.8853 Ep 18:1495s 15s/step - loss: 0.2944 - acc: 0.8733 - val_loss: 0.3067 - val_acc: 0.8671 Ep 19:1547s 15s/step - loss: 0.2923 - acc: 0.8738 - val_loss: 0.3065 - val_acc: 0.8663 Ep 33:1687s 17s/step - loss: 0.2748 - acc: 0.8826 - val_loss: 0.2486 - val_acc: 0.8967 - best Ep 35:1750s 18s/step - loss: 0.2751 - acc: 0.8817 - val_loss: 0.2686 - val_acc: 0.8831 Ep 38:1789s 18s/step - loss: 0.2729 - acc: 0.8822 - val_loss: 0.2726 - val_acc: 0.8883 Ep 39:1814s 18s/step - loss: 0.2722 - acc: 0.8837 - val_loss: 0.2951 - val_acc: 0.8752 Full validation loss: 0.2788 Full validation accuracy: 0.8866 (For best model) Cars MobileNet v1 (0.25, 128px): Ep 1: 1566s 16s/step - loss: 0.3212 - acc: 0.8624 - val_loss: 0.1829 - val_acc: 0.9324 Ep 2: 1429s 14s/step - loss: 0.2557 - acc: 0.8907 - val_loss: 0.1463 - val_acc: 0.9472 Ep 3: 1564s 16s/step - loss: 0.2438 - acc: 0.8968 - val_loss: 0.1586 - val_acc: 0.9424 Ep 4: 1566s 16s/step - loss: 0.2360 - acc: 0.9003 - val_loss: 0.1453 - val_acc: 0.9473 Ep 17:1664s 17s/step - loss: 0.1947 - acc: 0.9208 - val_loss: 0.1188 - val_acc: 0.9586 LR: 0.00090 Ep 21:1726s 17s/step - loss: 0.1908 - acc: 0.9214 - val_loss: 0.1240 - val_acc: 0.9552 Ep 24:1739s 17s/step - loss: 0.1819 - acc: 0.9261 - val_loss: 0.1183 - val_acc: 0.9567 LR: 0.00081 Ep 25:1747s 17s/step - loss: 0.1841 - acc: 0.9246 - val_loss: 0.1406 - val_acc: 0.9500 Ep 47:2232s 22s/step - loss: 0.1657 - acc: 0.9336 - val_loss: 0.1188 - val_acc: 0.9597 Ep 48:1713s 17s/step - loss: 0.1720 - acc: 0.9299 - val_loss: 0.1183 - val_acc: 0.9556 Ep 49:1544s 15s/step - loss: 0.1662 - acc: 0.9321 - val_loss: 0.1265 - val_acc: 0.9564 Ep 55:1558s 16s/step - loss: 0.1659 - acc: 0.9334 - val_loss: 0.1134 - val_acc: 0.9613 LR: 0.00045 Ep 67:1584s 16s/step - loss: 0.1576 - acc: 0.9355 - val_loss: 0.1088 - val_acc: 0.9631 LR: 0.0003645 - Best Ep 72:1625s 16s/step - loss: 0.1528 - acc: 0.9393 - val_loss: 0.1273 - val_acc: 0.9594 LR: 0.00032805 Full validation loss: 0.0993 Full validation accuracy: 0.9662 (For best model) People MobileNet v1 (0.25, 128px): Ep 1: 1716s 17s/step - loss: 0.4718 - acc: 0.7887 - val_loss: 0.7406 - val_acc: 0.7069 Ep 2: 1550s 15s/step - loss: 0.3771 - acc: 0.8368 - val_loss: 0.5902 - val_acc: 0.7573 Ep 20:1625s 16s/step - loss: 0.3022 - acc: 0.8749 - val_loss: 0.3756 - val_acc: 0.8370 Ep 25:1710s 17s/step - loss: 0.2953 - acc: 0.8794 - val_loss: 0.3769 - val_acc: 0.8374 Ep 30:1726s 17s/step - loss: 0.2953 - acc: 0.8775 - val_loss: 0.3741 - val_acc: 0.8411 Ep 32:1748s 17s/step - loss: 0.2911 - acc: 0.8813 - val_loss: 0.3645 - val_acc: 0.8442 Ep 38:1818s 18s/step - loss: 0.2844 - acc: 0.8844 - val_loss: 0.3600 - val_acc: 0.8442 - best Ep 41:1871s 19s/step - loss: 0.2891 - acc: 0.8810 - val_loss: 0.3963 - val_acc: 0.8322 LR: 8.100000122794882e-05 Ep 43:1895s 19s/step - loss: 0.2851 - acc: 0.8838 - val_loss: 0.3851 - val_acc: 0.8361 LR: 7.289999848580919e-05 Ep 52:1999s 20s/step - loss: 0.2805 - acc: 0.8852 - val_loss: 0.3790 - val_acc: 0.8433 Ep 68:2276s 23s/step - loss: 0.2795 - acc: 0.8862 - val_loss: 0.4114 - val_acc: 0.8298 LR: 4.304672074795235e-05 Full validation loss: 0.3053 Full validation accuracy: 0.8739 (For best model) ''' ================================================ FILE: r03_mobilenet_v1_reduce_and_scale_model.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' ''' Code to find reduction coefficients for fixed point representation of weights. It run some images from validation part of dataset to find maximum ranges of values. Then convert RELU6 -> RELU1 and rescale some weights and biases. At the end code checks that initial and rescaled models gives totally same result. ''' import os import glob from a01_oid_utils import read_single_image, DATASET_PATH if __name__ == '__main__': # Block to choose backend gpu_use = 4 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) print('GPU use: {}'.format(gpu_use)) from keras import backend as K from a00_common_functions import * # Coefficient to make safe gap for found range to prevent overflow. Lower - less safe, higher - more rounding error. GAP_COEFF = 1.0 def preproc_input_mathmodel(x): x /= 127.5 x -= 1. return x def rescale_weights(model, layer_num, coeff): w = model.layers[layer_num].get_weights() model.layers[layer_num].set_weights(w / coeff) return model def rescale_weights_with_bias(model, layer_num, coeff, current_scale): w, b = model.layers[layer_num].get_weights() w_new = w / coeff b_new = b / (coeff * current_scale) model.layers[layer_num].set_weights((w_new, b_new)) return model def rescale_only_bias(model, layer_num, coeff, current_scale): w, b = model.layers[layer_num].get_weights() w_new = w.copy() b_new = b / (coeff * current_scale) model.layers[layer_num].set_weights((w_new, b_new)) return model def rescale_batch_norm_weights_initital_v1(model, layer_num, coeff, current_scale): eps = 0.001 gamma, beta, run_mean, run_std = model.layers[layer_num].get_weights() gamma /= (coeff * current_scale) beta /= (coeff * current_scale) run_mean /= (coeff * current_scale) # Из за квадратного корня и EPS тут не всё так просто. Надо пересчитывать по формуле # после решения уравнения sqrt(Mx+e) = sqrt(x+e)/K # M = 1/(K*K) + e*(1-K*K)/(K*K*x) c2 = (coeff*coeff*current_scale*current_scale) # print('Run std: {}'.format(run_std)) run_std = run_std/c2 + eps*(1-c2)/c2 model.layers[layer_num].set_weights((gamma, beta, run_mean, run_std)) return model def rescale_batch_norm_weights_initital(model, layer_num, coeff, current_scale): gamma, beta, run_mean, run_std = model.layers[layer_num].get_weights() beta /= (coeff * current_scale) run_mean /= current_scale gamma /= coeff model.layers[layer_num].set_weights((gamma, beta, run_mean, run_std)) return model def rescale_dense_weights(model, layer_num, current_scale, coeff): weights = model.layers[layer_num].get_weights() if len(weights) == 2: w, b = weights w /= coeff b /= (current_scale*coeff) model.layers[layer_num].set_weights((w, b)) else: w = weights w /= coeff model.layers[layer_num].set_weights(w) return model def is_next_relu6(model, layer_id): if layer_id >= len(model.layers) - 1: return False layer = model.layers[layer_id + 1] layer_type = layer.__class__.__name__ if layer_type == 'Activation': config = layer.get_config() activation = config['activation'] if activation == 'relu6': return True return False def replace_intermediate_layer_in_keras(model, layer_id, new_layer): from keras.models import Model layers = [l for l in model.layers] x = layers[0].output for i in range(1, len(layers)): if i == layer_id: x = new_layer(x) else: x = layers[i](x) new_model = Model(inputs=layers[0].input, outputs=x) return new_model def get_min_max_for_model(model, img_list): from keras.models import Model from keras.layers import ReLU from keras.models import load_model from keras.optimizers import Adam reduction_koeffs = dict() current_six_value = 1.0 current_scale = 6.0 eps = 0.001 first_rescale = True for i in range(len(model.layers)): class_name = model.layers[i].__class__.__name__ layer = model.layers[i] print('Layer {}: {} Name {}'.format(i, class_name, layer.name)) print('In nodes: {}'.format(len(layer._inbound_nodes))) w1 = layer.get_weights() red_coeff = 1.0 if len(w1) > 0: submodel = Model(inputs=model.inputs, outputs=layer.output) print(submodel.summary()) # out = submodel.predict(img_list) if class_name == 'Conv2D': config = layer.get_config() use_bias = config['use_bias'] print('Min weights value: {} Max weights value: {}'.format(w1[0].min(), w1[0].max())) print('Min bias value: {} Max bias value: {}'.format(w1[1].min(), w1[1].max())) if first_rescale is True: model = rescale_weights_with_bias(model, i, 6.0, 1.0) first_rescale = False else: model = rescale_only_bias(model, i, red_coeff, current_scale) elif class_name == 'DepthwiseConv2D': config = layer.get_config() print(config) use_bias = config['use_bias'] print('Min weights value: {} Max weights value: {}'.format(w1[0].min(), w1[0].max())) print('Min bias value: {} Max bias value: {}'.format(w1[1].min(), w1[1].max())) model = rescale_only_bias(model, i, red_coeff, current_scale) elif class_name == 'Dense': config = layer.get_config() use_bias = config['use_bias'] print('Bias state: {}'.format(use_bias)) if use_bias == False: print('We dont need to rescale Dense') else: print('Bias not supported yet!') exit() else: continue reduction_koeffs[i] = red_coeff print('Layer: {} Scale: {} Reduction coeff: {} Six value: {}'.format(i, current_scale, red_coeff, current_six_value)) if class_name == 'Activation' or class_name == 'ReLU': print(layer.get_config()) # Replace model with new activation # model = replace_intermediate_layer_in_keras(model, i, Activation(lambda x: relu(x, max_value=current_six_value), name='custom_relu_{}'.format(i))) print('Activation six value: {}'.format(current_six_value)) if abs(current_six_value - 1.0) > 0.0000001: print('Not expected six value!') exit() # We always add relu_1 activation (due to scaling algorithm) model = replace_intermediate_layer_in_keras(model, i, ReLU(max_value=1.0, name='custom_relu_{}'.format(i))) model.compile(optimizer=Adam(), loss='categorical_crossentropy', metrics=['accuracy']) model.save(MODEL_PATH + 'debug.h5') model = load_model(MODEL_PATH + 'debug.h5') print(model.summary) if i == 0: continue # Check new min, max layer = model.layers[i] o = layer.output submodel = Model(inputs=model.inputs, outputs=o) print(submodel.summary()) out = submodel.predict(img_list) print('Rescaled submodel: {} Min out value: {} Max out value: {}'.format(out.shape, out.min(), out.max())) print('Reduction koeffs: ', reduction_koeffs) return model, reduction_koeffs def load_oid_data(type): from keras.utils import to_categorical valid = pd.read_csv(CACHE_PATH + 'oid_validation_{}.csv'.format(type)) train = pd.read_csv(CACHE_PATH + 'oid_train_{}.csv'.format(type)) X_train = train['id'].values Y_train = to_categorical(train['target'].values, num_classes=2) X_valid = valid['id'].values Y_valid = to_categorical(valid['target'].values, num_classes=2) return X_train, Y_train, X_valid, Y_valid def process_single_item(id, box_size): img = read_single_image(DATASET_PATH + 'validation/' + id + '.jpg') img = cv2.resize(img, (box_size, box_size), interpolation=cv2.INTER_LINEAR) return img def check_results_are_the_same(model_path1, model_path2, img_list): from keras.models import load_model modelA = load_model(model_path1) modelB = load_model(model_path2) resA = modelA.predict(img_list) resB = modelB.predict(img_list) print(resA) print(resB) print('Probabilities shape: {}'.format(resA.shape)) maxA = resA.argmax(axis=1) maxB = resB.argmax(axis=1) print(maxA) print(maxB) print('Answer shape: {}'.format(maxA.shape)) print(np.unique(maxA, return_counts=True)) print(np.unique(maxB, return_counts=True)) diff = len(maxA[maxA != maxB]) print('Answer difference: {}'.format(diff)) print((maxA - maxB).sum()) if __name__ == '__main__': from kito import reduce_keras_model from keras.models import load_model from keras.applications.mobilenet import preprocess_input # Params image_limit = 10000 input_size = 128 model_type = 'animals' model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5' model_path_reduced = model_path[:-3] + '_reduced.h5' model_path_rescaled = model_path[:-3] + '_reduced_rescaled.h5' if not os.path.isfile(model_path_reduced): model = load_model(model_path) model = reduce_keras_model(model, verbose=True) model.save(model_path_reduced) else: model = load_model(model_path_reduced) print(model.summary()) print('Number of layers: {}'.format(len(model.layers))) X_train, Y_train, X_test, Y_test = load_oid_data(model_type) print(X_train.shape, X_test.shape) X_test = X_test[:image_limit] Y_test = Y_test[:image_limit] uni = np.unique(Y_test, return_counts=True) print(uni[0].sum()) img_list = [] for i in range(len(X_test)): img = process_single_item(X_test[i], input_size) img_list.append(img) img_list = np.array(img_list, dtype=np.float32) img_list = preprocess_input(img_list) print("Image limit: {} Images shape: {}".format(image_limit, img_list.shape)) model, reduction_koeffs = get_min_max_for_model(model, img_list) overall_reduction_rate = 1.0 for i in sorted(reduction_koeffs.keys()): print('Layer {} reduction coeff: {}'.format(i, reduction_koeffs[i])) overall_reduction_rate *= reduction_koeffs[i] print('Overall scale change: {}'.format(overall_reduction_rate)) print('Save model in {}'.format(model_path_rescaled)) model.save(model_path_rescaled) check_results_are_the_same(model_path, model_path_rescaled, img_list) ================================================ FILE: r03_remove_batchnorm_layers.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' # Remove layers which is not needed for inference using KITO script import os import glob if __name__ == '__main__': # Block to choose GPU gpu_use = 4 print('GPU use: {}'.format(gpu_use)) os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from kito import reduce_keras_model from keras.models import load_model from a00_common_functions import * if __name__ == '__main__': model_path_in = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33.h5' model_path_out = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_bnfused.h5' model = load_model(model_path_in, custom_objects={'relu_1': relu_1}) model_reduced = reduce_keras_model(model, verbose=True) print(model_reduced.summary()) print('Initial layers: {}'.format(len(model.layers))) print('Reduced layers: {}'.format(len(model_reduced.layers))) model_reduced.save(model_path_out) ''' MobileNet V1 (Keras 2.2.4) Initial layers: 89 Reduced layers: 62 ''' ================================================ FILE: r04_find_optimal_bit_for_weights.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' ''' This code finds out which bit size for weight lead to zero classification error on fixed point test data comparing with floating point test data. Start search from 8 bits up to 32 bits. ''' if __name__ == '__main__': import os # Block to choose backend gpu_use = 2 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from a00_common_functions import * from scipy.signal import convolve2d import math import tensorflow as tf sess = tf.Session() sess.run(tf.global_variables_initializer()) tf.logging.set_verbosity(tf.logging.ERROR) # Note: We suppose that every Conv2D layer has type "same" # In Tensorflow weight matrices already transposed def my_convolve(input, kernel): output = np.zeros((input.shape[0], input.shape[1])) zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2)) zero_pad[1:-1, 1:-1] = input # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) for i in range(1, zero_pad.shape[0] - 1): for j in range(1, zero_pad.shape[1] - 1): sub = zero_pad[i-1:i+2, j-1:j+2] output[i-1, j-1] = np.sum(sub*kernel) return output def my_convolve_fixed_point(input, kernel, bit): output = np.zeros((input.shape[0], input.shape[1])) zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2)) zero_pad[1:-1, 1:-1] = input # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) for i in range(1, zero_pad.shape[0] - 1): for j in range(1, zero_pad.shape[1] - 1): sub = zero_pad[i-1:i+2, j-1:j+2] output[i-1, j-1] = np.sum((sub*kernel).astype(np.int64)) return output def preprocess_forward(arr, val): arr1 = arr.copy().astype(np.float32) arr1 /= val return arr1 def convert_to_fix_point(arr1, bit): arr2 = arr1.copy().astype(np.float32) arr2[arr2 < 0] = 0.0 arr2 = np.round(np.abs(arr2) * (2 ** bit)) arr3 = arr1.copy().astype(np.float32) arr3[arr3 > 0] = 0.0 arr3 = -np.round(np.abs(-arr3) * (2 ** bit)) arr4 = arr2 + arr3 return arr4.astype(np.int64) def from_fix_point_to_float(arr, bit): return arr / (2 ** bit) def compare_outputs(s1, s2, debug_info=True): if s1.shape != s2.shape: print('Shape of arrays is different! {} != {}'.format(s1.shape, s2.shape)) s = np.abs(s1 - s2) size = 1 for dim in np.shape(s): size *= dim if debug_info: print('Max difference: {}'.format(s.max())) print('Avg difference: {}'.format(s.mean())) print('Value range float: {} - {}'.format(s1.min(), s1.max())) print('Value range fixed: {} - {}'.format(s2.min(), s2.max())) def print_first_pixel_detailed_calculation_dense(previous_layer_output, wgt_bit, bit_precizion): i = 10 conv_my = 0 for j in range(0, previous_layer_output.shape[0]): print('Pixel {}: {}'.format(j, int(previous_layer_output[j]))) print('Weight {}: {}'.format(j, wgt_bit[j][i])) conv_my += np.right_shift((previous_layer_output[j]*wgt_bit[j][i]).astype(np.int64), bit_precizion) if j > 0 and j % 9 == 8: print('Current conv_my: {}'.format(conv_my)) print('Result first pixel: {}'.format(conv_my)) exit() def print_first_pixel_detailed_calculation(previous_layer_output, wgt_bit, bit_precizion): i = 0 x = 0 y = 0 conv_my = 0 print('Point: {} X: {} Y: {}'.format(i, x, y)) print('Weights shape: {}'.format(wgt_bit.shape)) for j in range(wgt_bit.shape[2]): full_image = previous_layer_output[:, :, j] zero_pad = np.zeros((full_image.shape[0] + 2, full_image.shape[1] + 2)) zero_pad[1:-1, 1:-1] = full_image pics = zero_pad[x+1-1:x+1+2, y+1-1:y+1+2].astype(np.int64) print('Pixel area 3x3 for [{}, {}]:'.format(x, y), pics) kernel = wgt_bit[:, :, j, i].copy() # Не надо переворачивать для TensorFlow # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) print('Weights {}: {}'.format(j, kernel)) res = np.sum(np.right_shift((pics*kernel).astype(np.int64), bit_precizion)) print('Convolution result {}: {}'.format(j, res)) conv_my += res print('Overall result: {}'.format(conv_my)) if conv_my[conv_my > 2 ** bit_precizion].any() or conv_my[conv_my < - 2 ** bit_precizion].any(): print('Overflow! {}'.format(conv_my[conv_my > 2 ** bit_precizion])) exit() if conv_my < 0: conv_my = 0 exit() def mmZeroPadding2D_floating_point(layer, img): config = layer.get_config() print(config) if len(config['padding']) == 1: padding1_start = config['padding'] padding1_end = config['padding'] padding2_start = config['padding'] padding2_end = config['padding'] elif len(config['padding']) == 2: padding1_start = config['padding'][0][0] padding1_end = config['padding'][0][1] padding2_start = config['padding'][1][0] padding2_end = config['padding'][1][1] out = np.zeros((img.shape[0], img.shape[1] + padding1_start + padding1_end, img.shape[2] + padding2_start + padding2_end, img.shape[3]), dtype=np.float64) out[:, padding1_start:out.shape[1] - padding1_end, padding2_start:out.shape[2] - padding2_end, :] = img.copy() return out def mmZeroPadding2D_fixed_point(layer, img): config = layer.get_config() print(config) if len(config['padding']) == 1: padding1_start = config['padding'] padding1_end = config['padding'] padding2_start = config['padding'] padding2_end = config['padding'] elif len(config['padding']) == 2: padding1_start = config['padding'][0][0] padding1_end = config['padding'][0][1] padding2_start = config['padding'][1][0] padding2_end = config['padding'][1][1] out = np.zeros((img.shape[0], img.shape[1] + padding1_start + padding1_end, img.shape[2] + padding2_start + padding2_end, img.shape[3]), dtype=np.int64) out[:, padding1_start:out.shape[1] - padding1_end, padding2_start:out.shape[2] - padding2_end, :] = img.copy() return out def run_TF_Conv2D(img, w, b, strides, padding, type='float'): global sess in1 = tf.Variable(img.astype(np.float64)) w1 = tf.Variable(w.astype(np.float64)) b1 = tf.Variable(b.astype(np.float64)) data = tf.nn.conv2d(in1, w1, (1,) + strides + (1,), str(padding).upper()) data = tf.nn.bias_add(data, b1) sess.run(tf.global_variables_initializer()) out = sess.run(data) if type == 'float': out = out.astype(np.float64) else: out = out.astype(np.int64) tf.reset_default_graph() sess = tf.Session() return out def run_TF_Depthwise_Conv2D(img, w, b, strides, padding, type='float'): global sess in1 = tf.Variable(img.astype(np.float64)) w1 = tf.Variable(w.astype(np.float64)) b1 = tf.Variable(b.astype(np.float64)) data = tf.nn.depthwise_conv2d(in1, w1, (1,) + strides + (1,), str(padding).upper()) data = tf.nn.bias_add(data, b1) sess.run(tf.global_variables_initializer()) out = sess.run(data) if type == 'float': out = out.astype(np.float64) else: out = out.astype(np.int64) tf.reset_default_graph() sess = tf.Session() return out def mmConv2D_floating_point(layer, img, debug_info): global sess calc_type = 'tf' config = layer.get_config() filters = config['filters'] use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] if debug_info and 0: print(config) sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 - (img.shape[1] % 2) sh2 -= 2 - (img.shape[2] % 2) if strides == (1, 1): out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64) elif strides == (2, 2): out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64) # calc_type = 'slow' else: print('Not supported conditions yet!') exit() if kernel_size != (3, 3) and kernel_size != (1, 1): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() if debug_info: print(w.shape, b.shape, out.shape) if calc_type == 'slow': # Cycle by different batch images for sh0 in range(img.shape[0]): # output filters cycle for wi in range(w.shape[-1]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # convolution for i in range(1, zero_pad.shape[0] - 1, strides[0]): for j in range(1, zero_pad.shape[1] - 1, strides[0]): if kernel_size == (3, 3): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += np.sum(sub * kernel) elif kernel_size == (1, 1): sub = zero_pad[i, j] out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += sub * kernel[0, 0] out[sh0, :, :, wi] += b[wi] elif calc_type == 'fast': # Cycle by different batch images for sh0 in range(img.shape[0]): # output filters cycle for wi in range(w.shape[-1]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj].copy() conv_my = convolve2d(slice, kernel, mode=padding) out[sh0, :, :, wi] += conv_my out[sh0, :, :, wi] += b[wi] elif calc_type == 'tf': out[...] = run_TF_Conv2D(img, w, b, strides, padding, 'float') return out def mmConv2D_fixed_point(layer, img, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info): global sess calc_type = 'tf' # Convolution with fixed point config = layer.get_config() filters = config['filters'] use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] if debug_info and 0: print(config) sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 - (img.shape[1] % 2) sh2 -= 2 - (img.shape[2] % 2) if strides == (1, 1): out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.int64) elif strides == (2, 2): out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.int64) else: print('Not supported conditions yet!') exit() if kernel_size != (3, 3) and kernel_size != (1, 1): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() if debug_info: print(w.shape, b.shape, out.shape) w = convert_to_fix_point(w.copy(), bit_precizion_weights) b = convert_to_fix_point(b.copy(), bit_precizion_bias) # We need to shift it to sum with result of multiplication b <<= bit_precizion_weights + (bit_precizion - bit_precizion_bias) if calc_type == 'slow': # Cycle by different batch images for sh0 in range(img.shape[0]): # output filters cycle for wi in range(w.shape[-1]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # convolution for i in range(1, zero_pad.shape[0] - 1, strides[0]): for j in range(1, zero_pad.shape[1] - 1, strides[0]): if kernel_size == (3, 3): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += np.sum((sub*kernel).astype(np.int64)) elif kernel_size == (1, 1): sub = zero_pad[i, j] out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wi] += (sub*kernel[0, 0]).astype(np.int64) out[sh0, :, :, wi] += b[wi] elif calc_type == 'fast': # Cycle by different batch images for sh0 in range(img.shape[0]): # output filters cycle for wi in range(w.shape[-1]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj].copy() conv_my = convolve2d(slice, kernel, mode=padding) out[sh0, :, :, wi] += conv_my out[sh0, :, :, wi] += b[wi] elif calc_type == 'tf': out[...] = run_TF_Conv2D(img, w, b, strides, padding, 'int') # Shift it back to initial scale out = np.right_shift(out.astype(np.int64), bit_precizion_weights) return out def mmGlobalAveragePooling2D_floating_point(img): # Standard glob pool result = np.zeros((img.shape[0], img.shape[-1])) for j in range(img.shape[0]): for i in range(img.shape[-1]): result[j, i] = img[j, :, :, i].mean() return result def mmGlobalAveragePooling2D_fixed_point(img): # Standard glob pool result = np.zeros((img.shape[0], img.shape[-1]), dtype=np.int64) block_size = img.shape[1] * img.shape[2] for j in range(img.shape[0]): for i in range(img.shape[-1]): value = img[j, :, :, i].sum() // block_size result[j, i] = value return result def mmActivation_floating_point(layer, img, one_value=1.0, debug_info=False): config = layer.get_config() activation = config['activation'] if activation != 'relu_1': print('Unsupported activation {}!'.format(activation)) exit() result = img.copy() result[result < 0] = 0. result[result > one_value] = one_value return result def mmActivation_fixed_point(layer, img, bit_precizion, debug_info=False): config = layer.get_config() activation = config['activation'] if activation != 'relu_1': print('Unsupported activation {}!'.format(activation)) exit() result = img.copy() result[result < 0] = 0. result[result >= 2 ** bit_precizion] = 2 ** bit_precizion - 1 return result def mmReLU_floating_point(layer, img, one_value=1.0, debug_info=False): config = layer.get_config() max_value = config['max_value'] if max_value != 1: print('Unsupported value for ReLU activation {}!'.format(max_value)) exit() result = img.copy() result[result < 0] = 0. result[result > one_value] = one_value return result def mmReLU_fixed_point(layer, img, bit_precizion, debug_info=False): config = layer.get_config() max_value = config['max_value'] if max_value != 1: print('Unsupported value for ReLU activation {}!'.format(max_value)) exit() result = img.copy() result[result < 0] = 0. result[result >= 2 ** bit_precizion] = 2 ** bit_precizion - 1 return result def mmDepthwiseConv2D_floating_point(layer, img, debug_info): config = layer.get_config() calc_type = 'tf' # print(config) use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] filters = img.shape[3] sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 - (img.shape[1] % 2) sh2 -= 2 - (img.shape[2] % 2) if strides == (1, 1): out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64) elif strides == (2, 2): out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64) else: print('Not supported strides yet: {}'.format(strides)) exit() if kernel_size != (3, 3): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() print(w.shape, b.shape, out.shape) if calc_type == 'slow': # Cycle by different batch images for sh0 in range(img.shape[0]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, 0].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) # convolution for i in range(1, zero_pad.shape[0] - 1, strides[0]): for j in range(1, zero_pad.shape[1] - 1, strides[0]): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] # print((i - 1) // strides[0], (j - 1) // strides[1], wi) out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wj] = np.sum(sub * kernel) out[sh0, :, :, wj] += b[wj] elif calc_type == 'tf': out[...] = run_TF_Depthwise_Conv2D(img, w, b, strides, padding, 'float') return out def mmDepthwiseConv2D_fixed_point(layer, img, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info): config = layer.get_config() calc_type = 'tf' # print(config) use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] filters = img.shape[3] sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 - (img.shape[1] % 2) sh2 -= 2 - (img.shape[2] % 2) if strides == (1, 1): out = np.zeros((img.shape[0], sh1, sh2, filters), dtype=np.float64) elif strides == (2, 2): out = np.zeros((img.shape[0], sh1 // 2, sh2 // 2, filters), dtype=np.float64) else: print('Not supported strides yet: {}'.format(strides)) exit() if kernel_size != (3, 3): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() print(w.shape, b.shape, out.shape) w = convert_to_fix_point(w.copy(), bit_precizion_weights) b = convert_to_fix_point(b.copy(), bit_precizion_bias) # We need to shift it to sum with result of multiplication b <<= bit_precizion_weights + (bit_precizion - bit_precizion_bias) if calc_type == 'slow': # Cycle by different batch images for sh0 in range(img.shape[0]): # input filters cycle for wj in range(w.shape[-2]): kernel = w[:, :, wj, 0].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) # convolution for i in range(1, zero_pad.shape[0] - 1, strides[0]): for j in range(1, zero_pad.shape[1] - 1, strides[0]): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] # print((i - 1) // strides[0], (j - 1) // strides[1], wi) out[sh0, (i - 1) // strides[0], (j - 1) // strides[1], wj] = np.sum((sub*kernel).astype(np.int64)) out[sh0, :, :, wj] += b[wj] elif calc_type == 'tf': out[...] = run_TF_Depthwise_Conv2D(img, w, b, strides, padding, 'int') # Shift it back to initial scale out = np.right_shift(out.astype(np.int64), bit_precizion_weights) return out def mmDense_floating_point(layer, img, debug_info): config = layer.get_config() print(config) use_bias = config['use_bias'] activation = config['activation'] units = config['units'] batch_size = img.shape[0] if use_bias: (w, b) = layer.get_weights() else: (w,) = layer.get_weights() print('Dense weights shape: {}'.format(w.shape)) if activation != 'softmax': print('Activation {} is not supported'.format(activation)) exit() if use_bias is True: print('Bias currently not supported!') exit() out = np.zeros((batch_size, units)) for sh0 in range(batch_size): for i in range(w.shape[1]): for j in range(w.shape[0]): out[sh0, i] += img[sh0, j] * w[j, i] # Softmax activation part # We skip it here because we will use max at the end if 0: for sh0 in range(batch_size): maxy = out[sh0].max() out[sh0] = np.exp(out[sh0] - maxy) sum = out[sh0].sum() out[sh0] /= sum return out def mmDense_fixed_point(layer, img, bit_precizion, bit_precizion_weights, debug_info): config = layer.get_config() if debug_info is True: print(config) use_bias = config['use_bias'] activation = config['activation'] units = config['units'] batch_size = img.shape[0] if use_bias: (w, b) = layer.get_weights() else: (w,) = layer.get_weights() if use_bias is True: print('Bias currently not supported!') exit() if debug_info is True: print('Dense weights shape: {}'.format(w.shape)) if activation != 'softmax': print('Activation {} is not supported'.format(activation)) exit() w = convert_to_fix_point(w.copy(), bit_precizion_weights) out = np.zeros((batch_size, units)) for sh0 in range(batch_size): for i in range(w.shape[1]): for j in range(w.shape[0]): out[sh0, i] += img[sh0, j] * w[j, i] # Divide by 2^bp out = np.right_shift(out.astype(np.int64), bit_precizion_weights) if out[out > 2 ** bit_precizion].any() or out[out < - 2 ** bit_precizion].any(): if out[out > 2 ** bit_precizion].any(): print('Warning overflow on current level! {}'.format(out[out > 2 ** bit_precizion])) else: print('Warning overflow on current level! {}'.format(out[out < - 2 ** bit_precizion])) print('Max is {}'.format(2 ** bit_precizion)) # We don't need to find softmax here, since we only need the # position of max value, which will be the same return out # bit_precizion - fixed point accuracy in bits def go_mat_model(model, images, bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info=True): level_out = dict() level_out_reduced = dict() print_pixel_calc = False # Hack before we solve problem with exact 1.0 value one_value = (2 ** bit_precizion - 1) / (2 ** bit_precizion) for level_id in range(len(model.layers)): layer = model.layers[level_id] layer_type = layer.__class__.__name__ if debug_info: print('Layer name: {} Layer type: {}'.format(layer.name, layer_type)) if level_id > 0: print('Input shape: {}'.format(level_out[level_id-1].shape)) if layer_type == 'InputLayer': level_out[level_id] = images.copy() level_out_reduced[level_id] = convert_to_fix_point(images.copy(), bit_precizion) elif layer_type == 'ZeroPadding2D': level_out[level_id] = mmZeroPadding2D_floating_point(layer, level_out[level_id - 1].copy()) level_out_reduced[level_id] = mmZeroPadding2D_fixed_point(layer, level_out_reduced[level_id - 1].copy()) elif layer_type == 'Conv2D': level_out[level_id] = mmConv2D_floating_point(layer, level_out[level_id - 1].copy(), debug_info) level_out_reduced[level_id] = mmConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info) elif layer_type == 'DepthwiseConv2D': level_out[level_id] = mmDepthwiseConv2D_floating_point(layer, level_out[level_id - 1].copy(), debug_info) level_out_reduced[level_id] = mmDepthwiseConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, bit_precizion_weights, bit_precizion_bias, debug_info) elif layer_type == 'Activation': level_out[level_id] = mmActivation_floating_point(layer, level_out[level_id - 1].copy(), one_value=one_value, debug_info=debug_info) level_out_reduced[level_id] = mmActivation_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, debug_info) elif layer_type == 'ReLU': level_out[level_id] = mmReLU_floating_point(layer, level_out[level_id - 1].copy(), one_value=one_value, debug_info=debug_info) level_out_reduced[level_id] = mmReLU_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, debug_info) elif layer_type == 'GlobalAveragePooling2D': level_out[level_id] = mmGlobalAveragePooling2D_floating_point(level_out[level_id - 1].copy()) level_out_reduced[level_id] = mmGlobalAveragePooling2D_fixed_point(level_out_reduced[level_id - 1].copy()) elif layer_type == 'Dense': level_out[level_id] = mmDense_floating_point(layer, level_out[level_id - 1].copy(), debug_info) level_out_reduced[level_id] = mmDense_fixed_point(layer, level_out_reduced[level_id - 1].copy(), bit_precizion, bit_precizion_weights, debug_info) # Convert back to float for comparison checker_tmp = from_fix_point_to_float(level_out_reduced[level_id], bit_precizion) compare_outputs(level_out[level_id], checker_tmp, debug_info) if debug_info: print('') if level_id > 1000: exit() if layer.name == 'conv_dw_2_bn_': exit() print(level_out[len(model.layers) - 1].shape) print(level_out[len(model.layers) - 1]) print(level_out_reduced[len(model.layers) - 1].shape) print(level_out_reduced[len(model.layers) - 1]) pred_float = np.argmax(level_out[len(model.layers) - 1], axis=1) pred_fixed = np.argmax(level_out_reduced[len(model.layers) - 1], axis=1) error_rate = (pred_float != pred_fixed).sum() / level_out[len(model.layers) - 1].shape[0] return error_rate, pred_float, pred_fixed def get_error_rate(a1, a2): miss = 0 for i in range(len(a1)): if a1[i] != a2[i]: miss += 1 print('Error rate: {}%'.format(round(100*miss/len(a1), 2))) return miss def preproc_input_mathmodel(x): x -= 127.5 x /= 128. return x def load_oid_data_optimal(type): valid = pd.read_csv(CACHE_PATH + 'oid_validation_{}.csv'.format(type)) X_valid = valid['id'].values Y_valid = valid['target'].values return X_valid, Y_valid def get_image_set(type, image_limit, preproc_type='keras'): from keras.applications.mobilenet import preprocess_input from r03_mobilenet_v1_reduce_and_scale_model import process_single_item from a01_oid_utils import read_single_image, DATASET_PATH input_size = 128 X_test, Y_test = load_oid_data_optimal(type) condition1 = (Y_test == 0) print(X_test.shape, Y_test.shape) X_test = np.concatenate(( X_test[condition1][:image_limit // 2], X_test[~condition1][:image_limit // 2], )) Y_test = np.concatenate(( Y_test[condition1][:image_limit // 2], Y_test[~condition1][:image_limit // 2], )) print(X_test.shape) uni = np.unique(Y_test, return_counts=True) print('Targets: {}'.format(uni)) img_list = [] for i in range(len(X_test)): img = process_single_item(X_test[i], input_size) img_list.append(img) img_list = np.array(img_list, dtype=np.float32) if preproc_type == 'keras': img_list = preprocess_input(img_list) else: img_list = preproc_input_mathmodel(img_list) print("Image limit: {} Images shape: {}".format(image_limit, img_list.shape)) return img_list, Y_test def find_conv_overflow_bit_values(model): max_w = -1000000000 max_b = -1000000000 for level_id in range(len(model.layers)): layer = model.layers[level_id] layer_type = layer.__class__.__name__ if layer_type == 'Conv2D' or layer_type == 'DepthwiseConv2D': print('Go for layer: {}'.format(layer.name)) config = layer.get_config() w, b = layer.get_weights() print('Weights range: {} - {}'.format(w.min(), w.max())) print('Bias range: {} - {}'.format(w.min(), w.max())) if w.max() > max_w: max_w = w.max() if np.abs(w.min()) > max_w: max_w = np.abs(w.min()) if b.max() > max_b: max_b = b.max() if np.abs(b.min()) > max_b: max_b = np.abs(b.min()) print('Maximum weight in covolution overall: {}'.format(max_w)) print('Maximum bias in covolution overall: {}'.format(max_b)) max_w_bit = math.ceil(math.log(max_w, 2)) max_b_bit = math.ceil(math.log(max_b, 2)) print('Overflow for conv weights w: {} bits b: {} bits'.format(max_w_bit, max_b_bit)) return max_w_bit, max_b_bit # This function works slow, so it should be run once to find optimal bit def get_optimal_bit_for_weights(type, model_path, image_limit, acceptable_error_rate, use_cache): cache_path = CACHE_PATH + 'optimal_bit_{}_{}.pklz'.format(type, image_limit) if not os.path.isfile(cache_path) or use_cache is not True: print('Read model...') # We read already reduced weights. We don't need to fix them any way model = get_model(model_path) print(model.summary()) convW, convB = find_conv_overflow_bit_values(model) # We doing preprocessing a little bit different because values shouldn't goes to -1 and 1 values (it will lead to overflow). # It can reduce accuracy a little bit. Probably we should initially train with this preproc images, answers = get_image_set(type, image_limit, 'math') print('Classify images...') keras_out = model.predict(images) res_keras_array = [] acc = 0. for i in range(keras_out.shape[0]): res_keras_array.append(np.argmax(keras_out[i])) if res_keras_array[-1] == answers[i]: acc += 1. print('Keras result raw: ', keras_out) print('Keras result pos: ', res_keras_array) print('Accuracy: {}'.format(acc / keras_out.shape[0])) image_bit_precision = 8 weight_bit_precision = 16 bias_bit_precision = 16 if 1: print('First run') while 1: print('\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision)) error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True) print('Error rate: {:.6f}'.format(error_rate)) print(res_keras_array) print(pred_float) print(pred_fixed) image_bit_precision += 1 if error_rate < acceptable_error_rate or image_bit_precision > 36: break if image_bit_precision > 32: return -1, -1, -1, -1, -1 print('Second run. Decrease weights bitsize') while 1: weight_bit_precision -= 1 # bias_bit_precision = image_bit_precision print('\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision)) error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True) print('Error rate: {:.6f}'.format(error_rate)) print(res_keras_array) print(pred_float) print(pred_fixed) if error_rate > acceptable_error_rate: weight_bit_precision += 1 break print('Third run. Decrease bias bitsize') while 1: bias_bit_precision -= 1 print('\nStart image bit precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision)) error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True) print('Error rate: {:.6f}'.format(error_rate)) print(res_keras_array) print(pred_float) print(pred_fixed) if error_rate > acceptable_error_rate: bias_bit_precision += 1 break if 0: print('Single debug run') print('\nStart error precision: {} Weights precision: {} Bias precision: {}'.format(image_bit_precision, weight_bit_precision, bias_bit_precision)) error_rate, pred_float, pred_fixed = go_mat_model(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, debug_info=True) print('Error rate: {:.6f}'.format(error_rate)) print(res_keras_array) print(pred_float) print(pred_fixed) save_in_file((image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB), cache_path) return image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB else: return load_from_file(cache_path) if __name__ == '__main__': if 0: use_cache = False acceptable_error_rate = 0.005 # 0.5% image_limit = 3000 type = 'people' model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5' if 0: use_cache = False acceptable_error_rate = 0.005 # 0.5% image_limit = 3000 type = 'cars' model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5' if 1: use_cache = False acceptable_error_rate = 0.005 # 0.5% image_limit = 3000 type = 'animals' model_path_rescaled = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5' image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights(type, model_path_rescaled, image_limit, acceptable_error_rate, use_cache) if image_bit_precision > 0: print('Optimal bit size for image and feature maps (sign bit is not included) is: {}'.format(image_bit_precision)) print('Optimal bit size for weights: {}'.format(weight_bit_precision)) print('Optimal bit size for bias: {}'.format(bias_bit_precision)) print('Bit overflows. Weights {} Bias: {}'.format(convW, convB)) else: print('Impossible to find optimal bit!') sess.close() ''' Max error rate: 0.5% weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5 Optimal 12, 11, 10, 7, 3 weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5 Optimal 10, 9, 8, 7, 3 weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5 Optimal 12, 11, 10, 7, 3 ''' ================================================ FILE: r05_gen_weights_in_verilog_format.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' ''' Generate weights with optimal bit size in verilog format ''' if __name__ == '__main__': import os # Block to choose backend gpu_use = 4 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from r04_find_optimal_bit_for_weights import * STORAGE_COUNT_WEIGHTS = 0 STORAGE_COUNT_BIAS = 0 # Note: We suppose that every Conv2D layer has type "same" # In Tensorflow weight matrices already transposed def my_convolve(input, kernel): output = np.zeros((input.shape[0], input.shape[1])) zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2)) zero_pad[1:-1, 1:-1] = input # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) for i in range(1, zero_pad.shape[0] - 1): for j in range(1, zero_pad.shape[1] - 1): sub = zero_pad[i-1:i+2, j-1:j+2] output[i-1, j-1] = np.sum(sub*kernel) return output def my_convolve_fixed_point(input, kernel, bit): output = np.zeros((input.shape[0], input.shape[1])) zero_pad = np.zeros((input.shape[0] + 2, input.shape[1] + 2)) zero_pad[1:-1, 1:-1] = input # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) for i in range(1, zero_pad.shape[0] - 1): for j in range(1, zero_pad.shape[1] - 1): sub = zero_pad[i-1:i+2, j-1:j+2] output[i-1, j-1] = np.sum((sub*kernel).astype(np.int64)) return output def preprocess_forward(arr, val): arr1 = arr.copy().astype(np.float32) arr1 /= val return arr1 def convert_to_fix_point(arr1, bit): arr2 = arr1.copy().astype(np.float32) arr2[arr2 < 0] = 0.0 arr2 = np.round(np.abs(arr2) * (2 ** bit)) arr3 = arr1.copy().astype(np.float32) arr3[arr3 > 0] = 0.0 arr3 = -np.round(np.abs(-arr3) * (2 ** bit)) arr4 = arr2 + arr3 return arr4.astype(np.int64) def from_fix_point_to_float(arr, bit): return arr / (2 ** bit) def compare_outputs(s1, s2, debug_info=True): if s1.shape != s2.shape: print('Shape of arrays is different! {} != {}'.format(s1.shape, s2.shape)) s = np.abs(s1 - s2) size = 1 for dim in np.shape(s): size *= dim if debug_info: print('Max difference: {}'.format(s.max())) print('Avg difference: {}'.format(s.mean()/size)) print('Value range float: {} - {}'.format(s1.min(), s1.max())) print('Value range fixed: {} - {}'.format(s2.min(), s2.max())) def dump_memory_structure_conv(arr, out_file): print('Dump memory structure in file: {}'.format(out_file)) out = open(out_file, "w") total = 0 for a in range(arr.shape[2]): for i in range(arr.shape[0]): for j in range(arr.shape[1]): out.write(str(total) + " LVL: {} X: {} Y: {} ".format(a, i, j) + str(arr[i, j, a]) + '\n') total += 1 out.close() def dump_memory_structure_dense(arr, out_file): print('Dump memory structure for dense layer in file: {}'.format(out_file)) out = open(out_file, "w") total = 0 print('Shape:', arr.shape) for j in range(arr.shape[0]): out.write(str(total) + " POS: {} ".format(j) + str(arr[j]) + '\n') total += 1 out.close() def print_first_pixel_detailed_calculation_dense(previous_layer_output, wgt_bit, bit_precizion): i = 10 conv_my = 0 for j in range(0, previous_layer_output.shape[0]): print('Pixel {}: {}'.format(j, int(previous_layer_output[j]))) print('Weight {}: {}'.format(j, wgt_bit[j][i])) conv_my += np.right_shift((previous_layer_output[j]*wgt_bit[j][i]).astype(np.int64), bit_precizion) if j > 0 and j % 9 == 8: print('Current conv_my: {}'.format(conv_my)) print('Result first pixel: {}'.format(conv_my)) exit() def print_first_pixel_detailed_calculation(previous_layer_output, wgt_bit, bit_precizion): i = 0 x = 0 y = 0 conv_my = 0 print('Point: {} X: {} Y: {}'.format(i, x, y)) print('Weights shape: {}'.format(wgt_bit.shape)) for j in range(wgt_bit.shape[2]): full_image = previous_layer_output[:, :, j] zero_pad = np.zeros((full_image.shape[0] + 2, full_image.shape[1] + 2)) zero_pad[1:-1, 1:-1] = full_image pics = zero_pad[x+1-1:x+1+2, y+1-1:y+1+2].astype(np.int64) print('Pixel area 3x3 for [{}, {}]:'.format(x, y), pics) kernel = wgt_bit[:, :, j, i].copy() # Не надо переворачивать для TensorFlow # kernel = np.flipud(kernel) # kernel = np.fliplr(kernel) print('Weights {}: {}'.format(j, kernel)) res = np.sum(np.right_shift((pics*kernel).astype(np.int64), bit_precizion)) print('Convolution result {}: {}'.format(j, res)) conv_my += res print('Overall result: {}'.format(conv_my)) if conv_my[conv_my > 2 ** bit_precizion].any() or conv_my[conv_my < - 2 ** bit_precizion].any(): print('Overflow! {}'.format(conv_my[conv_my > 2 ** bit_precizion])) exit() if conv_my < 0: conv_my = 0 exit() def convert_to_normalized_form(value, precision, required_precision=None): sign = 0 ret = value if ret < 0: sign = 1 ret = abs(ret) # down = ret - math.floor(ret) # print(ret, down) normed = int(round(ret * 2**(precision-1))) #if sign == 1 and normed != 0: # Complement code for negative numbers #normed = 2**(precision) - normed down_binary_str = "{:0b}".format(normed) if required_precision is None: required_precision = precision for j in range(len(down_binary_str), required_precision): down_binary_str = '0' + down_binary_str return sign, down_binary_str def convert_to_normalized_form_array(value, precision): ret = np.abs(value) normed = np.round(ret * 2**(precision - 1)).astype(np.int64) return normed def convert_to_normalized_form_v2(value, precision): sign = 0 ret = value if ret < 0: sign = 1 ret = abs(ret) normed = ret #if sign == 1 and normed != 0: # Complement code for negative numbers #normed = 2**(precision) - normed down_binary_str = "{:b}".format(normed) for j in range(len(down_binary_str), precision): down_binary_str = '0' + down_binary_str return sign, down_binary_str def get_shape_string(w): r = str(w.shape)[1:-1] r = r.replace(',', '') r = r.replace(' ', '_') return r def gen_convolution_weights(level_id, layer, bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias): global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS # Convolution with fixed point config = layer.get_config() use_bias = config['use_bias'] kernel_size = config['kernel_size'] requred_mem_in_bits = 0 if kernel_size != (3, 3) and kernel_size != (1, 1): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() # w = convert_to_fix_point(w.copy(), bit_precizion) # Check that everything is fine with weights if w[w > 2 ** convW].any() or w[w < -2 ** convW].any(): print('Overflow for conv weights!') exit() # Check that everything is fine with bias if b[b > 2 ** convB].any() or b[b < -2 ** convB].any(): print('Overflow for conv bias!') exit() precisionW = weight_bit_precision + 1 + convW precisionB = bias_bit_precision + 1 + convB print('Initial bits weights: {} bias: {}'.format(precisionW, precisionB)) w_check = convert_to_normalized_form_array(w, weight_bit_precision + 1) w_check_max = w_check.max() precisionW = np.log2(w_check_max).astype(np.int64) + 1 + 1 b_check = convert_to_normalized_form_array(b, bias_bit_precision + 1) b_check_max = b_check.max() precisionB = np.log2(b_check_max).astype(np.int64) + 1 + 1 print('Max value to store weights: {} bias: {}'.format(w_check_max, b_check_max)) print('Reduced bits weights: {} bias: {}'.format(precisionW, precisionB)) print('Go for: {} Shape: {}'.format(layer.name, w.shape)) tp1 = 'bin' s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} {} {} Shape: {}\n\n'.format(level_id, layer.name, layer.__class__.__name__, bit_precizion + 1, weight_bit_precision + 1 + convW, bias_bit_precision + 1 + convB, get_shape_string(w)) out_weights.write(s1) out_bias.write(s1) # Cycle by outputs for i in range(w.shape[3]): # Cycle by inputs for j in range(w.shape[2]): # Cycle by conv 3x3 for k in range(w.shape[1]): for l in range(w.shape[0]): sign, bin1 = convert_to_normalized_form(w[k, l, j, i].copy(), weight_bit_precision + 1, precisionW) sgn = ' ' if sign == 1: sgn = '-' dec_verilog = int(bin1, 2) if sign == 1: dec_verilog = -dec_verilog if tp1 == 'hex': hx = hex(int(bin1, 2))[2:].upper() out_weights.write( "storage[{}] = {}{}'h{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, hx, dec_verilog, w[k, l, j, i])) else: out_weights.write( "storage[{}] = {}{}'b{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, bin1, dec_verilog, w[k, l, j, i])) requred_mem_in_bits += precisionW STORAGE_COUNT_WEIGHTS += 1 if w.shape[1] > 1: out_weights.write('\n') out_weights.write('\n') # Cycle by outputs for i in range(w.shape[3]): sign, bin1 = convert_to_normalized_form(b[i].copy(), bias_bit_precision + 1, precisionB) sgn = ' ' if sign == 1: sgn = '-' dec_verilog = int(bin1, 2) if sign == 1: dec_verilog = -dec_verilog if tp1 == 'hex': hx = hex(int(bin1, 2))[2:].upper() out_bias.write( "storage_bias[{}] = {}{}'h{}; // {} {}\n".format(STORAGE_COUNT_BIAS, sgn, precisionB, hx, dec_verilog, b[i])) else: out_bias.write( "storage_bias[{}] = {}{}'b{}; // {} {}\n".format(STORAGE_COUNT_BIAS, sgn, precisionB, bin1, dec_verilog, b[i])) requred_mem_in_bits += precisionB STORAGE_COUNT_BIAS += 1 out_bias.write('\n') return requred_mem_in_bits def gen_depthwise_convolution_weights(level_id, layer, bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias): global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS config = layer.get_config() use_bias = config['use_bias'] kernel_size = config['kernel_size'] requred_mem_in_bits = 0 if kernel_size != (3, 3) and kernel_size != (1, 1): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() # Check that everything is fine with weights if w[w > 2 ** convW].any() or w[w < -2 ** convW].any(): print('Overflow for conv weights!') exit() # Check that everything is fine with bias if b[b > 2 ** convB].any() or b[b < -2 ** convB].any(): print('Overflow for conv bias!') exit() precisionW = weight_bit_precision + 1 + convW precisionB = bias_bit_precision + 1 + convB print('Initial bits weights: {} bias: {}'.format(precisionW, precisionB)) w_check = convert_to_normalized_form_array(w, weight_bit_precision + 1) w_check_max = w_check.max() precisionW = np.log2(w_check_max).astype(np.int64) + 1 + 1 b_check = convert_to_normalized_form_array(b, bias_bit_precision + 1) b_check_max = b_check.max() precisionB = np.log2(b_check_max).astype(np.int64) + 1 + 1 print('Max value to store weights: {} bias: {}'.format(w_check_max, b_check_max)) print('Reduced bits weights: {} bias: {}'.format(precisionW, precisionB)) print('Go for: {} Shape: {}'.format(layer.name, w.shape)) s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} {} {} Shape: {}\n\n'.format(level_id, layer.name, layer.__class__.__name__, bit_precizion + 1, weight_bit_precision + 1 + convW, bias_bit_precision + 1 + convB, get_shape_string(w)) out_weights.write(s1) out_bias.write(s1) tp1 = 'bin' # Cycle by inputs. Output is always 1 for i in range(w.shape[2]): # Cycle by conv 3x3 for k in range(w.shape[1]): for l in range(w.shape[0]): sign, bin1 = convert_to_normalized_form(w[k, l, i, 0].copy(), weight_bit_precision + 1, precisionW) sgn = ' ' if sign == 1: sgn = '-' dec_verilog = int(bin1, 2) if sign == 1: dec_verilog = -dec_verilog if tp1 == 'hex': hx = hex(int(bin1, 2))[2:].upper() out_weights.write( "storage[{}] = {}{}'h{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, hx, dec_verilog, w[k, l, i, 0])) else: out_weights.write( "storage[{}] = {}{}'b{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precisionW, bin1, dec_verilog, w[k, l, i, 0])) requred_mem_in_bits += precisionW STORAGE_COUNT_WEIGHTS += 1 out_weights.write('\n') # Cycle by inputs. Output is always 1 for i in range(w.shape[2]): sign, bin1 = convert_to_normalized_form(b[i].copy(), bias_bit_precision + 1, precisionB) sgn = ' ' if sign == 1: sgn = '-' dec_verilog = int(bin1, 2) if sign == 1: dec_verilog = -dec_verilog if tp1 == 'hex': hx = hex(int(bin1, 2))[2:].upper() out_bias.write( "storage_bias[{}] = {}{}'h{}; // {} {}\n".format(STORAGE_COUNT_BIAS, sgn, precisionB, hx, dec_verilog, w[k, l, i, 0])) else: out_bias.write( "storage_bias[{}] = {}{}'b{}; // {} {}\n".format(STORAGE_COUNT_BIAS, sgn, precisionB, bin1, dec_verilog, w[k, l, i, 0])) requred_mem_in_bits += precisionB STORAGE_COUNT_BIAS += 1 out_bias.write('\n') return requred_mem_in_bits def gen_dense_weights(level_id, layer, bit_precizion, out_weights): global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS config = layer.get_config() use_bias = config['use_bias'] requred_mem_in_bits = 0 if use_bias: print('Bias currently unsupported!') exit() (w,) = layer.get_weights() # Check that everything is fine with weights if w[w > 1].any() or w[w < -1].any(): print('Overflow for depthwise conv weights!') exit() print('Go for: {} Shape: {}'.format(layer.name, w.shape)) s1 = '// Level: {:02d} Name: {} Type: {} BP Set: {} Shape: {}\n\n'.format(level_id, layer.name, layer.__class__.__name__, bit_precizion + 1, get_shape_string(w)) out_weights.write(s1) tp1 = 'bin' precision = bit_precizion + 1 # Cycle by outputs for i in range(w.shape[1]): # Cycle by inputs for j in range(w.shape[0]): sign, bin1 = convert_to_normalized_form(w[j, i].copy(), precision) sgn = ' ' if sign == 1: sgn = '-' dec_verilog = int(bin1, 2) if sign == 1: dec_verilog = -dec_verilog if tp1 == 'hex': hx = hex(int(bin1, 2))[2:].upper() out_weights.write( "storage[{}] = {}{}'h{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precision, hx, dec_verilog, w[j, i])) else: out_weights.write( "storage[{}] = {}{}'b{}; // {} {}\n".format(STORAGE_COUNT_WEIGHTS, sgn, precision, bin1, dec_verilog, w[j, i])) STORAGE_COUNT_WEIGHTS += 1 requred_mem_in_bits += precision out_weights.write('\n') return requred_mem_in_bits def generate_weights_for_layers(model, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_dir): global STORAGE_COUNT_WEIGHTS, STORAGE_COUNT_BIAS STORAGE_COUNT_WEIGHTS = 0 STORAGE_COUNT_BIAS = 0 weights_required_memory = 0 out_weights = open(out_dir + 'storage.v', 'w') out_bias = open(out_dir + 'storage_bias.v', 'w') for level_id in range(len(model.layers)): layer = model.layers[level_id] layer_type = layer.__class__.__name__ req_mem = 0 if layer_type == 'Conv2D': req_mem = gen_convolution_weights(level_id, layer, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias) elif layer_type == 'DepthwiseConv2D': req_mem = gen_depthwise_convolution_weights(level_id, layer, bp, weight_bit_precision, bias_bit_precision, convW, convB, out_weights, out_bias) elif layer_type == 'Dense': req_mem = gen_dense_weights(level_id, layer, weight_bit_precision, out_weights) else: continue print('Required weights memory: {} bit'.format(req_mem)) weights_required_memory += req_mem out_weights.close() out_bias.close() print('Overall weights memory requirements: {} bit ({:.2f} MB)'.format(weights_required_memory, weights_required_memory / (1024*1024))) if __name__ == '__main__': type = 'animals' model_path = MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5' acceptable_error_rate = 0.005 # 0.5% image_limit = 3000 if 0: image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights(type, model_path, image_limit, acceptable_error_rate, use_cache=True) else: image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3 out_dir = CACHE_PATH + type + '/' if not os.path.isdir(out_dir): os.mkdir(out_dir) model = get_model(model_path) generate_weights_for_layers(model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB, out_dir) ================================================ FILE: r06_generate_debug_data.py ================================================ # coding: utf-8 __author__ = 'Roman Solovyev (ZFTurbo), IPPM RAS' ''' This code takes one image run it through the network and store all intermediate feature maps in fixed point representation in separate files. Also detailed first pixel calculation is generated. It used later to check generated verilog on correctness. ''' if __name__ == '__main__': import os # Block to choose backend and GPU to run gpu_use = 4 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from r04_find_optimal_bit_for_weights import * import math def convert_to_normalized_form_v2(value, precision): sign = 0 ret = value if ret < 0: sign = 1 ret = abs(ret) normed = ret #if sign == 1 and normed != 0: # Complement code for negative numbers #normed = 2**(precision) - normed down_binary_str = "{:b}".format(normed) for j in range(len(down_binary_str), precision): down_binary_str = '0' + down_binary_str return sign, down_binary_str def store_layer_result(level_id, layer, layer_type, bp, res): r = str(res.shape[1:])[1:-1] r = r.replace(',', '') r = r.replace(' ', '_') out_file = INTERMEDIATE_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}_shape_{}.txt'.format(level_id, layer.name, bp+1, r) print('Write to {}'.format(out_file)) out = open(out_file, 'w') if layer_type != 'Conv2D' and layer_type != 'DepthwiseConv2D': if np.abs(res).max() >= 2 ** bp: print('Some layer result problem here! ({} > {})'.format(np.abs(res).max(), 2 ** bp)) exit() else: if np.abs(res).max() >= 2 ** bp: print('Overflow on {} layer! ({} > {}). It is expected, increase bit space!'.format(layer_type, np.abs(res).max(), 2 ** bp)) precision = bp + 1 # Possible overflow. It's fine bit_max = math.ceil(math.log(np.abs(res).max() + 1, 2)) + 1 if bit_max > precision: precision = bit_max total = 0 if len(res.shape) == 4: if 1: # Start from channels for i in range(res.shape[3]): for j in range(res.shape[1]): for k in range(res.shape[2]): sign, bin1 = convert_to_normalized_form_v2(res[0, j, k, i].copy(), precision) sgn = ' ' if sign == 1: sgn = '-' out.write("pixel[{}] = {}{}'b{}; // {}\n".format(total, sgn, precision, bin1, res[0, j, k, i])) total += 1 out.write('\n') elif len(res.shape) == 2: for i in range(res.shape[1]): sign, bin1 = convert_to_normalized_form_v2(res[0, i].copy(), precision) sgn = ' ' if sign == 1: sgn = '-' out.write("pixel[{}] = {}{}'b{}; // {}\n".format(total, sgn, precision, bin1, res[0, i])) total += 1 else: print('Shape problem!') exit() out.close() def print_convolution_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision, bias_bit_precision): config = layer.get_config() filters = config['filters'] use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 sh2 -= 2 if kernel_size != (3, 3) and kernel_size != (1, 1): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name, image_bit_precizion + 1) print('Write to {}'.format(out_file)) out = open(out_file, 'w') w = convert_to_fix_point(w.copy(), weight_bit_precision) b = convert_to_fix_point(b.copy(), bias_bit_precision) i = 0 x = 0 y = 0 # Output filter number wi = i # Batch image number sh0 = 0 out.write('Point: {} X: {} Y: {}\n'.format(i, x, y)) # input filters cycle value = 0 for wj in range(w.shape[-2]): kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # Convolution for single output pixel i = x*strides[0] + 1 j = y*strides[1] + 1 if kernel_size == (3, 3): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] vv = np.sum((sub * kernel).astype(np.int64)) elif kernel_size == (1, 1): sub = zero_pad[i, j] vv = (sub * kernel[0, 0]).astype(np.int64) out.write('Input kernel number: {}\n'.format(wj)) out.write('Kernel:\n{}\n'.format(kernel)) out.write('Part:\n{}\n'.format(sub)) out.write('Current result: {}\n\n'.format(vv)) value += vv b[wi] <<= weight_bit_precision + (image_bit_precizion - bias_bit_precision) out.write('Add bias: {}\n'.format(b[wi])) value += b[wi] out.write('Overall result before shift: {}\n'.format(value)) # Divide by 2^bp value = np.right_shift(value, weight_bit_precision) out.write('Overall result after shift: {}\n'.format(value)) out.close() def print_depthwise_conv_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision, bias_bit_precision): config = layer.get_config() use_bias = config['use_bias'] strides = config['strides'] padding = config['padding'] kernel_size = config['kernel_size'] sh1 = img.shape[1] sh2 = img.shape[2] if padding == 'valid': sh1 -= 2 sh2 -= 2 if kernel_size != (3, 3): print('Unsupported kernel size: {}'.format(kernel_size)) exit() (w, b) = layer.get_weights() out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name, image_bit_precizion+1) print('Write to {}'.format(out_file)) out = open(out_file, 'w') w = convert_to_fix_point(w.copy(), weight_bit_precision) b = convert_to_fix_point(b.copy(), bias_bit_precision) i = 0 x = 0 y = 0 # Output filter number wj = i wi = 0 # Batch image number sh0 = 0 out.write('Point: {} X: {} Y: {}\n'.format(i, x, y)) # input filters cycle value = 0 kernel = w[:, :, wj, wi].copy() slice = img[sh0, :, :, wj] if padding == 'same': zero_pad = np.zeros((slice.shape[0] + 2, slice.shape[1] + 2)) zero_pad[1:-1, 1:-1] = slice elif padding == 'valid': zero_pad = slice.copy() else: print('Unknown padding: {}'.format(padding)) exit() # Convolution for single output pixel i = x*strides[0] + 1 j = y*strides[1] + 1 if kernel_size == (3, 3): sub = zero_pad[i - 1:i + 2, j - 1:j + 2] vv = np.sum((sub * kernel).astype(np.int64)) elif kernel_size == (1, 1): sub = zero_pad[i, j] vv = (sub * kernel[0, 0]).astype(np.int64) value = vv out.write('Input kernel number: {}\n'.format(wj)) out.write('Kernel:\n{}\n'.format(kernel)) out.write('Part:\n{}\n'.format(sub)) b[wj] <<= weight_bit_precision + (image_bit_precizion - bias_bit_precision) out.write('Add bias: {}\n'.format(b[wj])) value += b[wj] out.write('Overall result before shift: {}\n'.format(value)) # Divide by 2^bp value = np.right_shift(value, weight_bit_precision) out.write('Overall result after shift: {}\n'.format(value)) out.close() def print_dense_detailed_first_pixel_calculation(level_id, layer, img, image_bit_precizion, weight_bit_precision): config = layer.get_config() use_bias = config['use_bias'] activation = config['activation'] if use_bias: (w, b) = layer.get_weights() else: (w,) = layer.get_weights() if use_bias is True: print('Bias currently not supported!') exit() if activation != 'softmax': print('Activation {} is not supported'.format(activation)) exit() w = convert_to_fix_point(w.copy(), weight_bit_precision) out_file = FIRST_PIXEL_OUTPUT_PATH + 'level_{:02d}_name_{}_bp_{}.txt'.format(level_id, layer.name, weight_bit_precision + 1) print('Write to {}'.format(out_file)) out = open(out_file, 'w') i = 0 x = 0 # Batch image number sh0 = 0 out.write('Point: {} X: {}\n'.format(i, x)) value = 0 for j in range(w.shape[0]): out.write('Weight {}: {}\n'.format(j, w[j, i])) vv = img[sh0, j] * w[j, i] value += vv out.write('Current intermediate result: {} [Accumulate: {}]\n'.format(vv, value)) out.write('Overall result before shift: {}\n'.format(value)) # Divide by 2^bp value = np.right_shift(value.astype(np.int64), weight_bit_precision) out.write('Overall result after shift: {}\n'.format(value)) out.close() def get_filters_size(arr): a = np.prod(np.array(arr.shape).astype(np.int64)) return a def generate_layer_results(model, images, image_bit_precizion, weight_bit_precision, bias_bit_precision, convW, convB): if images.shape[0] > 1: print('Only one image must be in batch for debug!') exit() level_out_reduced = dict() debug_info = False prev_filters_space = -1 next_filters_space = -1 max_filter_space = -1 critical_layer = -1 for level_id in range(len(model.layers)): layer = model.layers[level_id] layer_type = layer.__class__.__name__ print('Layer num: {} Layer name: {} Layer type: {}'.format(level_id, layer.name, layer_type)) if level_id == 0: next_filters_space = get_filters_size(images[0]) * (image_bit_precizion + 1) if level_id > 0: print('Input shape: {}'.format(level_out_reduced[level_id-1].shape)) prev_filters_space = next_filters_space.copy() next_filters_space = get_filters_size(level_out_reduced[level_id-1][0]) * (image_bit_precizion + 1) if prev_filters_space + next_filters_space > max_filter_space: max_filter_space = prev_filters_space + next_filters_space critical_layer = level_id if layer_type == 'InputLayer': level_out_reduced[level_id] = convert_to_fix_point(images.copy(), image_bit_precizion) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'ZeroPadding2D': level_out_reduced[level_id] = mmZeroPadding2D_fixed_point(layer, level_out_reduced[level_id - 1].copy()) elif layer_type == 'Conv2D': level_out_reduced[level_id] = mmConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision, debug_info) print_convolution_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'DepthwiseConv2D': level_out_reduced[level_id] = mmDepthwiseConv2D_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision, debug_info) print_depthwise_conv_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, bias_bit_precision) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'Activation': level_out_reduced[level_id] = mmActivation_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, debug_info) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'ReLU': level_out_reduced[level_id] = mmReLU_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, debug_info) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'GlobalAveragePooling2D': level_out_reduced[level_id] = mmGlobalAveragePooling2D_fixed_point(level_out_reduced[level_id - 1].copy()) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) elif layer_type == 'Dense': level_out_reduced[level_id] = mmDense_fixed_point(layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision, debug_info) print_dense_detailed_first_pixel_calculation(level_id, layer, level_out_reduced[level_id - 1].copy(), image_bit_precizion, weight_bit_precision) store_layer_result(level_id, layer, layer_type, image_bit_precizion, level_out_reduced[level_id]) print('Required space to store intermediate results of calculations: {} bits ({:.2f} MB)'.format(max_filter_space, max_filter_space / (1024 * 1024))) print('Critical layer number: {}'.format(critical_layer)) def get_debug_image(): img = cv2.imread(CACHE_PATH + 'image.png') img_list = [] img_list.append(img.copy()) img_list = np.array(img_list, dtype=np.float32) img_list = preproc_input_mathmodel(img_list) print(img_list.shape, img_list.max(), img_list.min()) return img_list def generate_layer_results_for_image(type, model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB): print(model.summary()) # Get only one image try: a = 10/0 # If OID dataset exists images, answers = get_image_set(type, 2, 'math') images = images[0:1] print('Use OID images') except: images = np.zeros((1, 128, 128, 3), dtype=np.float32) images[...] = 255 images = preproc_input_mathmodel(images) print('No OID images found. Use generated image') generate_layer_results(model, images, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB) if __name__ == '__main__': problem_type = 'people' INTERMEDIATE_OUTPUT_PATH = CACHE_PATH + 'intermediate_{}/'.format(problem_type) if not os.path.isdir(INTERMEDIATE_OUTPUT_PATH): os.mkdir(INTERMEDIATE_OUTPUT_PATH) FIRST_PIXEL_OUTPUT_PATH = CACHE_PATH + 'first_pixel_{}/'.format(problem_type) if not os.path.isdir(FIRST_PIXEL_OUTPUT_PATH): os.mkdir(FIRST_PIXEL_OUTPUT_PATH) if problem_type == 'people': model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_people_loss_0.3600_acc_0.8442_epoch_38_reduced_rescaled.h5') # bit_precision - without sign, so we need to add 1 to it to store sign as well # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights() image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3 elif problem_type == 'cars': model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_cars_loss_0.1088_acc_0.9631_epoch_67_reduced_rescaled.h5') # bit_precision - without sign, so we need to add 1 to it to store sign as well # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights() image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 10, 9, 8, 7, 3 elif problem_type == 'animals': model = get_model(MODEL_PATH + 'best/weights_mobilenet_1_0.25_128px_animals_loss_0.2486_acc_0.8967_epoch_33_reduced_rescaled.h5') # bit_precision - without sign, so we need to add 1 to it to store sign as well # image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = get_optimal_bit_for_weights() image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB = 12, 11, 10, 7, 3 generate_layer_results_for_image(problem_type, model, image_bit_precision, weight_bit_precision, bias_bit_precision, convW, convB) ================================================ FILE: r07_generate_verilog_for_mobilenet.py ================================================ # coding: utf-8 __author__ = 'Alex Kustov, IPPM RAS' import os gpu_use = 0 os.environ["KERAS_BACKEND"] = "tensorflow" os.environ["CUDA_VISIBLE_DEVICES"] = "{}".format(gpu_use) from r04_find_optimal_bit_for_weights import * def addressRAM(directory, steps_count, max_address_value): f = open(directory + "addressRAM.v", 'w') bit_steps_count = len(bin(steps_count)) - 2 bit_max_address_value = len(bin(max_address_value)) - 2 f.write("module addressRAM(\n") f.write(" input ["+str(bit_steps_count-1)+":0] step,\n") f.write(" output reg re_weights,\n") f.write(" output reg re_bias,\n") f.write(" output reg ["+str(bit_max_address_value-1)+":0] firstaddr, lastaddr\n") f.write(");\n") f.write("parameter convolution_size = 9;\n") f.write("parameter conv1 = 1*8*3 * convolution_size;\n") f.write("parameter conv2_1 = 8 * convolution_size + conv1;\n") f.write("parameter conv2_2 = (8*8*2) + conv2_1;\n") f.write("parameter conv3_1 = 16 * convolution_size + conv2_2;\n") f.write("parameter conv3_2 = (16*16*2) + conv3_1;\n") f.write("parameter conv4_1 = 32 * convolution_size + conv3_2;\n") f.write("parameter conv4_2 = (32*32) + conv4_1;\n") f.write("parameter conv5_1 = 32 * convolution_size + conv4_2;\n") f.write("parameter conv5_2 = (32*32*2) + conv5_1;\n") f.write("parameter conv6_1 = 64 * convolution_size + conv5_2;\n") f.write("parameter conv6_2 = (64*64) + conv6_1;\n") f.write("parameter conv7_1 = 64 * convolution_size + conv6_2;\n") f.write("parameter conv7_2 = (64*64*2) + conv7_1;\n") f.write("parameter conv8_1 = 128 * convolution_size + conv7_2;\n") f.write("parameter conv8_2 = (128*128) + conv8_1;\n") f.write("parameter conv9_1 = 128 * convolution_size + conv8_2;\n") f.write("parameter conv9_2 = (128*128) + conv9_1;\n") f.write("parameter conv10_1 = 128 * convolution_size + conv9_2;\n") f.write("parameter conv10_2 = (128*128) + conv10_1;\n") f.write("parameter conv11_1 = 128 * convolution_size + conv10_2;\n") f.write("parameter conv11_2 = (128*128) + conv11_1;\n") f.write("parameter conv12_1 = 128 * convolution_size + conv11_2;\n") f.write("parameter conv12_2 = (128*128) + conv12_1;\n") f.write("parameter conv13_1 = 128 * convolution_size + conv12_2;\n") f.write("parameter conv13_2 = (128*128*2) + conv13_1;\n") f.write("parameter conv14_1 = 256 * convolution_size + conv13_2;\n") f.write("parameter conv14_2_1 = ((256*256)>>1) + conv14_1;\n") f.write("parameter conv14_2_2 = ((256*256)>>1) + conv14_2_1;\n") f.write("parameter predict = 512 + conv14_2_2;\n") f.write("\n") f.write("\n") f.write("parameter bias1 = 8;\n") f.write("parameter bias2_1 = (8)+8;\n") f.write("parameter bias2_2 = (16)+16;\n") f.write("parameter bias3_1 = (32)+16;\n") f.write("parameter bias3_2 = (48)+32;\n") f.write("parameter bias4_1 = (80)+32;\n") f.write("parameter bias4_2 = (112)+32;\n") f.write("parameter bias5_1 = (144)+32;\n") f.write("parameter bias5_2 = (176)+64;\n") f.write("parameter bias6_1 = (240)+64;\n") f.write("parameter bias6_2 = (304)+64;\n") f.write("parameter bias7_1 = (368)+64;\n") f.write("parameter bias7_2 = (432)+128;\n") f.write("parameter bias8_1 = (560)+128;\n") f.write("parameter bias8_2 = (688)+128;\n") f.write("parameter bias9_1 = (816)+128;\n") f.write("parameter bias9_2 = (944)+128;\n") f.write("parameter bias10_1 = (1072)+128;\n") f.write("parameter bias10_2 = (1200)+128;\n") f.write("parameter bias11_1 = (1328)+128;\n") f.write("parameter bias11_2 = (1456)+128;\n") f.write("parameter bias12_1 = (1584)+128;\n") f.write("parameter bias12_2 = (1712)+128;\n") f.write("parameter bias13_1 = (1840)+128;\n") f.write("parameter bias13_2 = (1968)+256;\n") f.write("parameter bias14_1 = (2224)+256;\n") f.write("parameter bias14_2_1 = (2480)+(256>>1);\n") f.write("parameter bias14_2_2 = (2608)+(256>>1);\n") f.write("\n") f.write("\n") f.write("always @(step)\n") f.write("case (step) \n") f.write("8'd1: begin //weights conv1 \n") f.write(" firstaddr = 0;\n") f.write(" lastaddr = conv1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd2: begin //bias conv1\n") f.write(" firstaddr = 0;\n") f.write(" lastaddr = bias1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd4: begin //weights conv2 dw 1\n") f.write(" firstaddr = conv1;\n") f.write(" lastaddr = conv2_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd5: begin //bias conv2 dw\n") f.write(" firstaddr = bias1;\n") f.write(" lastaddr = bias2_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd7: begin //weights conv2 1x1\n") f.write(" firstaddr = conv2_1;\n") f.write(" lastaddr = conv2_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd8: begin //bias conv2 1x1\n") f.write(" firstaddr = bias2_1;\n") f.write(" lastaddr = bias2_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd10: begin //weights conv3 dw 2\n") f.write(" firstaddr = conv2_2;\n") f.write(" lastaddr = conv3_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd11: begin //bias conv3 DW\n") f.write(" firstaddr = bias2_2;\n") f.write(" lastaddr = bias3_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd13: begin //weights conv3 1x1\n") f.write(" firstaddr = conv3_1;\n") f.write(" lastaddr = conv3_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd14: begin //bias conv\n") f.write(" firstaddr = bias3_1;\n") f.write(" lastaddr = bias3_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd16: begin\n") f.write(" firstaddr = conv3_2; // dw 3\n") f.write(" lastaddr = conv4_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd17: begin\n") f.write(" firstaddr = bias3_2;\n") f.write(" lastaddr = bias4_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd19: begin\n") f.write(" firstaddr = conv4_1;\n") f.write(" lastaddr = conv4_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd20: begin\n") f.write(" firstaddr = bias4_1;\n") f.write(" lastaddr = bias4_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd22: begin\n") f.write(" firstaddr = conv4_2; // dw 4\n") f.write(" lastaddr = conv5_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd23: begin\n") f.write(" firstaddr = bias4_2;\n") f.write(" lastaddr = bias5_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd25: begin\n") f.write(" firstaddr = conv5_1;\n") f.write(" lastaddr = conv5_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd26: begin\n") f.write(" firstaddr = bias5_1;\n") f.write(" lastaddr = bias5_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd28: begin\n") f.write(" firstaddr = conv5_2; // dw 5\n") f.write(" lastaddr = conv6_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd29: begin\n") f.write(" firstaddr = bias5_2;\n") f.write(" lastaddr = bias6_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd31: begin\n") f.write(" firstaddr = conv6_1;\n") f.write(" lastaddr = conv6_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd32: begin\n") f.write(" firstaddr = bias6_1;\n") f.write(" lastaddr = bias6_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd34: begin\n") f.write(" firstaddr = conv6_2; // dw 6\n") f.write(" lastaddr = conv7_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd35: begin\n") f.write(" firstaddr = bias6_2;\n") f.write(" lastaddr = bias7_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd37: begin\n") f.write(" firstaddr = conv7_1;\n") f.write(" lastaddr = conv7_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd38: begin\n") f.write(" firstaddr = bias7_1;\n") f.write(" lastaddr = bias7_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd40: begin\n") f.write(" firstaddr = conv7_2; // dw 7\n") f.write(" lastaddr = conv8_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd41: begin\n") f.write(" firstaddr = bias7_2;\n") f.write(" lastaddr = bias8_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd43: begin\n") f.write(" firstaddr = conv8_1;\n") f.write(" lastaddr = conv8_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd44: begin\n") f.write(" firstaddr = bias8_1;\n") f.write(" lastaddr = bias8_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd46: begin\n") f.write(" firstaddr = conv8_2; // dw 8\n") f.write(" lastaddr = conv9_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd47: begin\n") f.write(" firstaddr = bias8_2;\n") f.write(" lastaddr = bias9_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd49: begin\n") f.write(" firstaddr = conv9_1;\n") f.write(" lastaddr = conv9_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd50: begin\n") f.write(" firstaddr = bias9_1;\n") f.write(" lastaddr = bias9_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd52: begin\n") f.write(" firstaddr = conv9_2; // dw 9\n") f.write(" lastaddr = conv10_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd53: begin\n") f.write(" firstaddr = bias9_2;\n") f.write(" lastaddr = bias10_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd55: begin\n") f.write(" firstaddr = conv10_1;\n") f.write(" lastaddr = conv10_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd56: begin\n") f.write(" firstaddr = bias10_1;\n") f.write(" lastaddr = bias10_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd58: begin\n") f.write(" firstaddr = conv10_2; // dw 10\n") f.write(" lastaddr = conv11_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd59: begin\n") f.write(" firstaddr = bias10_2;\n") f.write(" lastaddr = bias11_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd61: begin\n") f.write(" firstaddr = conv11_1;\n") f.write(" lastaddr = conv11_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd62: begin\n") f.write(" firstaddr = bias11_1;\n") f.write(" lastaddr = bias11_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd64: begin\n") f.write(" firstaddr = conv11_2; // dw 11\n") f.write(" lastaddr = conv12_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd65: begin\n") f.write(" firstaddr = bias11_2;\n") f.write(" lastaddr = bias12_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd67: begin\n") f.write(" firstaddr = conv12_1;\n") f.write(" lastaddr = conv12_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd68: begin\n") f.write(" firstaddr = bias12_1;\n") f.write(" lastaddr = bias12_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd70: begin\n") f.write(" firstaddr = conv12_2; // dw 12\n") f.write(" lastaddr = conv13_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd71: begin\n") f.write(" firstaddr = bias12_2;\n") f.write(" lastaddr = bias13_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd73: begin\n") f.write(" firstaddr = conv13_1;\n") f.write(" lastaddr = conv13_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd74: begin\n") f.write(" firstaddr = bias13_1;\n") f.write(" lastaddr = bias13_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd76: begin\n") f.write(" firstaddr = conv13_2; // dw 13\n") f.write(" lastaddr = conv14_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd77: begin\n") f.write(" firstaddr = bias13_2;\n") f.write(" lastaddr = bias14_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd79: begin\n") f.write(" firstaddr = conv14_1;\n") f.write(" lastaddr = conv14_2_1;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd80: begin\n") f.write(" firstaddr = bias14_1;\n") f.write(" lastaddr = bias14_2_1;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd82: begin\n") f.write(" firstaddr = conv14_2_1;\n") f.write(" lastaddr = conv14_2_2;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("8'd83: begin\n") f.write(" firstaddr = bias14_2_1;\n") f.write(" lastaddr = bias14_2_2;\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 1;\n") f.write(" end\n") f.write("8'd85: begin\n") f.write(" firstaddr = conv14_2_2;\n") f.write(" lastaddr = predict;\n") f.write(" re_weights = 1;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("default:\n") f.write(" begin\n") f.write(" re_weights = 0;\n") f.write(" re_bias = 0;\n") f.write(" end\n") f.write("endcase\n") f.write("endmodule\n") f.close() def border(directory, razmer): f = open(directory + "border.v",'w') bit_matrix = len(bin(razmer))-2 bit_matrix_2=len(bin(razmer*razmer))-2 f.write("module border(\n") f.write(" input clk, go,\n") f.write(" input ["+str(bit_matrix_2-1)+":0] i,\n") f.write(" input ["+str(bit_matrix-1)+":0] matrix,\n") f.write(" output reg [1:0] prov\n") f.write(");\n") f.write(" always @(posedge clk)\n") f.write(" begin \n") f.write(" if (go == 1)\n") f.write(" begin\n") f.write(" prov = 0;\n") for i in range(128): f.write(" if ((i == "+str(i+1)+"*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10;\n") f.write("\n") for i in range(128+1): f.write(" if ((i == "+str(i)+"*matrix) && (prov != 2'b11)) prov = 2'b11;\n") f.write(" end\n") f.write(" else\n") f.write(" prov = 0;\n") f.write(" end\n") f.write("endmodule\n") f.close() def conv_block(directory,razmer): f = open(directory + "conv.v",'w') bit_matrix = len(bin(razmer)) - 2 bit_matrix_2 = len(bin(razmer*razmer)) - 2 f.write("module conv(clk,Y1,prov,matrix,matrix2,i,up_perm,down_perm,p1,p2,p3,w1,w2,w3,conv_en,dense_en,stride_plus_prov);\n") f.write("\n") f.write("parameter SIZE=0;\n") f.write("parameter SIZE_address_pix=18;\n") f.write("parameter SIZE_weights=0;\n") f.write("\n") f.write("input clk;\n") f.write("output reg signed [32-1:0] Y1;\n") f.write("input [1:0] prov;\n") f.write("input ["+str(bit_matrix-1)+":0] matrix;\n") f.write("input ["+str(bit_matrix_2-1)+":0] matrix2;\n") f.write("input ["+str(bit_matrix_2-1)+":0] i;\n") f.write("input up_perm,down_perm;\n") f.write("input signed [SIZE-1:0] p1,p2,p3;\n") f.write("input signed [SIZE_weights-1:0] w1,w2,w3;\n") f.write("input conv_en;\n") f.write("input dense_en;\n") f.write("input [SIZE_address_pix-1:0] stride_plus_prov;\n") f.write("\n") f.write("wire up,down;\n") f.write("\n") f.write("assign up = (((i+stride_plus_prov)<=matrix-1'b1)&&(up_perm))?1'b1:1'b0;\n") f.write("assign down = (((i+stride_plus_prov)>=matrix2-matrix)&&(down_perm))?1'b1:1'b0;\n") f.write("\n") f.write("always @(posedge clk)\n") f.write(" begin\n") f.write(" if (conv_en==1)\n") f.write(" begin\n") f.write(" Y1=0;\n") f.write(" if ((prov!=2'b11)&&(!up)&&(!down)) Y1 = Y1+(p1*w1);\n") f.write(" if ((!up)&&(!down)) Y1 = Y1+(p2*w2);\n") f.write(" if ((prov!=2'b10)&&(!up)&&(!down)) Y1 = Y1+(p3*w3);\n") f.write(" end\n") f.write(" end\n") f.write("\n") f.write("endmodule\n") f.close() def conv_TOP(directory, razmer, max_conv_input_size, max_conv_output_size, num_conv, steps_count, sizeI, sizeW): f = open(directory + "conv_TOP.v", 'w') bit_matrix=len(bin(razmer))-2 bit_matrix_2=len(bin(razmer*razmer))-2 bit_max_conv_input_size = len(bin(max_conv_input_size)) - 2 bit_max_conv_output_size = len(bin(max_conv_output_size)) - 2 bit_razmer_2 = len(bin(razmer * razmer)) - 2 bit_steps_count = len(bin(steps_count)) - 2 Y='' w='' p='' res_out='' res='' res_old='' glob_average_perem='' glob_average_perem_1='' res_bias_check='' data_bias='' for i in range(num_conv): Y = Y + "Y" + str(i + 1) + "," w = w + "w"+str(i+1)+"1,w"+str(i+1)+"2,w"+str(i+1)+"3," p = p + "p" + str(i) + "_1,p" + str(i) + "_2,p" + str(i) + "_3," res_out = res_out + "res_out_" +str(i+1) + "," res = res + "res"+ str(i+1) + "," res_old = res_old + "res_old_" + str(i+1) + "," glob_average_perem = glob_average_perem + "glob_average_perem_" + str(i+1) + "," glob_average_perem_1 = glob_average_perem_1 + "glob_average_perem_" + str(i + 1) + "_1," res_bias_check = res_bias_check + "res_bias_check_" + str(i+1) + "," data_bias = data_bias + "data_bias_" + str(i+1) + "," f.write("module conv_TOP(clk,conv_en,STOP,memstartp,memstartw,memstartzap,read_addressp,write_addressp,read_addresstp,write_addresstp,read_addressw,we,re_wb,re,we_t,re_t,qp,qtp,qw,dp,dtp,prov,matrix,matrix2,i_to_prov,lvl,slvl,mem,") f.write(Y) f.write(w) f.write(p) f.write("go,up_perm,down_perm,num,filt,bias,glob_average_en,step,stride,depthwise,onexone,q_bias,read_addressb,memstartb,stride_plus_prov);\n") f.write("\n") for i in range(num_conv): f.write("parameter SIZE_"+str(i+1)+"=0;\n") f.write("parameter SIZE_address_pix=13;\n") f.write("parameter SIZE_address_pix_t=12;\n") f.write("parameter SIZE_address_wei=13;\n") f.write("parameter SIZE_weights=0;\n") f.write("parameter SIZE_bias=0;\n") f.write("\n") f.write("input clk,conv_en,glob_average_en;\n") f.write("input [1:0] prov;\n") f.write("input ["+str(bit_matrix-1)+":0] matrix;\n") f.write("input ["+str(bit_matrix_2-1)+":0] matrix2;\n") f.write("input [SIZE_address_pix-1:0] memstartp;\n") f.write("input [SIZE_address_wei-1:0] memstartw;\n") f.write("input [SIZE_address_pix-1:0] memstartzap;\n") f.write("input [10:0] memstartb;\n") f.write("input ["+str(bit_max_conv_input_size-1)+":0] lvl;\n") f.write("input [8:0] slvl;\n") f.write("output reg [SIZE_address_pix-1:0] read_addressp;\n") f.write("output reg [SIZE_address_pix_t-1:0] read_addresstp;\n") f.write("output reg [SIZE_address_wei-1:0] read_addressw;\n") f.write("output reg [10:0] read_addressb;\n") f.write("output reg [SIZE_address_pix-1:0] write_addressp;\n") f.write("output reg [SIZE_address_pix_t-1:0] write_addresstp;\n") f.write("output reg we,re,re_wb;\n") f.write("output reg we_t,re_t;\n") f.write("input signed [SIZE_"+str(num_conv)+"-1:0] qp;\n") f.write("input signed [32*"+str(num_conv)+"-1:0] qtp;\n") f.write("input signed [SIZE_weights*9-1:0] qw;\n") f.write("input signed [SIZE_bias-1:0] q_bias;\n") f.write("output signed [SIZE_"+str(num_conv)+"-1:0] dp;\n") f.write("output signed [32*"+str(num_conv)+"-1:0] dtp;\n") f.write("output reg STOP;\n") f.write("output reg ["+str(bit_razmer_2-1)+":0] i_to_prov;\n") f.write("input signed [32-1:0] "+Y[:-1]+";\n") f.write("output reg signed [SIZE_weights-1:0] "+w[:-1]+";\n") f.write("output reg signed [SIZE_1-1:0] "+p[:-1]+";\n") f.write("output reg go;\n") f.write("output reg up_perm,down_perm;\n") f.write("input [2:0] num;\n") f.write("input ["+str(bit_max_conv_output_size-1)+":0] mem;\n") f.write("input ["+str(bit_max_conv_input_size-1)+":0] filt;\n") f.write("input bias;\n") f.write("input ["+str(bit_steps_count-1)+":0] step;\n") f.write("input [1:0] stride;\n") f.write("output reg [SIZE_address_pix-1:0] stride_plus_prov;\n") f.write("\n") f.write("input depthwise,onexone;\n") f.write("\n") for i in range(num_conv): f.write("reg signed [SIZE_weights-1:0] w" + str(i + 1) + "1_pre,w" + str(i + 1) + "2_pre,w" + str(i + 1) + "3_pre,w" + str(i + 1) + "4_pre,w" + str(i + 1) + "5_pre,w" + str(i + 1) + "6_pre,w" + str(i + 1) + "7_pre,w" + str(i + 1) + "8_pre,w" + str(i + 1) + "9_pre;\n") f.write("reg signed [SIZE_1-1:0]") for i in range(int(num_conv/4)): f.write("p" + str(0+8*i) + "_pre,p" + str(1+8*i) + "_pre,p" + str(2+8*i) + "_pre,p" + str(3+8*i) + "_pre,p" + str(4+8*i) + "_pre,p" + str(5+8*i) + "_pre,p" + str(6+8*i) + "_pre,p" + str(7+8*i) + "_pre") if ((i+1)==(int(num_conv/4))): f.write(";") else: f.write(",") f.write("\n") f.write("reg signed [SIZE_1-1:0] "+res_out[:-1]+";\n") f.write("reg signed [32-1:0] "+res[:-1]+";\n") f.write("reg signed [32-1:0] "+res_old[:-1]+";\n") f.write("reg signed [21:0] "+glob_average_perem[:-1]+";\n") f.write("wire signed [SIZE_1-1:0] "+glob_average_perem_1[:-1]+";\n") f.write("\n") f.write("reg signed [SIZE_1-1:0]") for i in range(num_conv): f.write("buff" + str(i) + "_0 [2:0]") if (i != (num_conv-1)): f.write(", ") else: f.write(";\n") f.write("reg signed [SIZE_1-1:0]") for i in range(num_conv): f.write("buff" + str(i) + "_1 [2:0]") if (i != (num_conv-1)): f.write(", ") else: f.write(";\n") f.write("reg signed [SIZE_1-1:0]") for i in range(num_conv): f.write("buff" + str(i) + "_2 [2:0]") if (i != (num_conv-1)): f.write(", ") else: f.write(";\n") f.write("\n") f.write("reg [4:0] marker;\n") f.write("reg zagryzka_weight;\n") f.write("reg [15:0] i;\n") f.write("reg [15:0] i_onexone,i_onexone_1;\n") f.write("wire [15:0] i_onexone_plus1;\n") f.write("assign i_onexone_plus1 = i_onexone + 1'b1;\n") f.write("reg [SIZE_address_pix-1:0] stride_plus,next_number,next_number_prov;\n") f.write("\n") f.write("reg signed [19-1:0] "+res_bias_check[:-1]+";\n") f.write("\n") f.write("reg signed [SIZE_bias-1:0] " + data_bias[:-1]+";\n") f.write("\n") f.write("initial zagryzka_weight=0;\n") f.write("initial marker=0;\n") f.write("\n") f.write("wire [15:0] line_stride;\n") f.write("\n") f.write("assign line_stride=matrix>>(stride-1);\n") f.write("\n") f.write("always @(posedge clk)\n") f.write("begin\n") f.write("if (conv_en==1)\n") f.write(" begin\n") f.write(" if (zagryzka_weight==0)\n") f.write(" begin\n") f.write(" next_number = matrix;\n") f.write(" next_number_prov = matrix;\n") f.write(" if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus=0;\n") f.write(" else stride_plus=matrix;\n") f.write(" if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus_prov=0;\n") f.write(" else stride_plus_prov=matrix;\n") f.write(" case (marker)\n") for i in range(num_conv+2): f.write(" "+str(i)+": begin\n") if (i==0): f.write(" re_wb=1;\n") if (i < num_conv): f.write(" read_addressw=memstartw+" + str(i) + "*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1)));\n") f.write(" read_addressb=memstartb+" + str(i) + ";\n") if ((i=2)): for j in range(9): f.write(" w"+str(i-1)+str(j+1)+"_pre=qw[SIZE_weights*"+str(j+1)+"-1:") if (j==0): f.write("0") else: f.write("SIZE_weights*"+str(j)) f.write("]; \n") f.write("\n") f.write(" data_bias_" + str(i-1) + " = q_bias;\n") if (i == num_conv + 1): f.write(" zagryzka_weight=1; re_wb=0; marker=-1;\n") f.write(" end\n") f.write(" default: \n") f.write(" begin\n") f.write(" read_addressw=0;\n") f.write(" read_addressb=0;\n") f.write(" re_wb=0;\n") f.write(" $display(\"Check zagryzka_weight\");\n") f.write(" end\n") f.write(" endcase\n") f.write(" marker=marker+1;\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" re=1;\n") f.write(" case (marker)\n") f.write(" 0: begin \n") f.write(" re_t=0;\n") f.write(" if ((stride==2)&&(i==next_number))\n") f.write(" begin\n") f.write(" stride_plus=stride_plus+matrix;\n") f.write(" next_number = matrix+next_number;\n") f.write(" end\n") f.write(" if (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\n") f.write(" else read_addressp=i+memstartp+stride_plus;\n") f.write("\n") f.write(" if (onexone)\n") f.write(" begin\n") for i in range(num_conv): f.write(" p" + str(i) + "_1=p6_pre;\n") f.write(" p" + str(i) + "_2=p7_pre;\n") f.write(" p" + str(i) + "_3=0;\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" if (depthwise)\n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_2[2]=qp[SIZE_" + str(num_conv-i) + "-1:") if (num_conv==(i+1)): f.write("0") else: f.write("SIZE_"+ str(num_conv-i-1)) f.write("];\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" if (((i+stride_plus-1)1): if (i==0): f.write(" if") else: f.write(" else if") f.write(" ({"+lvl[1:]+"}=="+str(len(bin(num_conv))-3)+"'d"+str(i)+") \n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_2[2]=qp["+one_size+"-1:"+two_size+"];\n") f.write(" end\n") else: f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "2[2]=qp[SIZE_1-1:0];\n") f.write(" end\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_2[2]=0;\n") f.write(" end\n") f.write(" end\n") for i in range(num_conv): f.write(" p" + str(i) + "_1=buff" + str(i) + "_2[0];\n") f.write(" p" + str(i) + "_2=buff" + str(i) + "_2[1];\n") f.write(" p" + str(i) + "_3=buff" + str(i) + "_2[2];\n") f.write("\n") f.write(" end\n") f.write("\n") for i in range(num_conv): f.write(" w" + str(i+1) + "1=(onexone)?w" + str(i+1) + "3_pre:w" + str(i+1) + "3_pre;\n") f.write(" w" + str(i+1) + "2=(onexone)?w" + str(i+1) + "2_pre:w" + str(i+1) + "2_pre;\n") f.write(" w" + str(i+1) + "3=(onexone)?w" + str(i+1) + "1_pre:w" + str(i+1) + "1_pre;\n") f.write(" up_perm=0;\n") f.write(" if (onexone) down_perm=0; else down_perm=1;\n") for i in range(num_conv): f.write(" res" + str(i+1) + "=Y" + str(i+1) + ";\n") f.write(" end\n") f.write(" 1: begin\n") f.write(" if (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\n") f.write(" else if ((i+stride_plus)>=matrix-1) read_addressp=i-matrix+memstartp+stride_plus;\n") f.write("\n") for i in range(num_conv): f.write(" res" + str(i+1) + "=res" + str(i+1) + "+Y" + str(i+1) + ";\n") f.write(" if ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1))) \n") f.write(" begin\n") for i in range(num_conv): f.write(" res_old_" + str(i+1) + "=qtp[32*" + str(num_conv-i) + "-1:32*") if (num_conv==(i+1)): f.write("0") else: f.write(str(num_conv-i-1)) f.write("];\n") f.write(" end\n") f.write(" go=0;\n") f.write(" i_to_prov=i_to_prov+1'b1;\n") f.write(" if ((stride==2)&&(i_to_prov==next_number_prov)) \n") f.write(" begin\n") f.write(" stride_plus_prov=stride_plus_prov+matrix;\n") f.write(" next_number_prov = matrix+next_number_prov;\n") f.write(" end\n") f.write("\n") for i in range(num_conv): f.write(" buff" + str(i) + "_2[0]=buff" + str(i) + "_2[1];\n") f.write(" buff" + str(i) + "_1[0]=buff" + str(i) + "_1[1];\n") f.write(" buff" + str(i) + "_0[0]=buff" + str(i) + "_0[1];\n") f.write(" buff" + str(i) + "_2[1]=buff" + str(i) + "_2[2];\n") f.write(" buff" + str(i) + "_1[1]=buff" + str(i) + "_1[2];\n") f.write(" buff" + str(i) + "_0[1]=buff" + str(i) + "_0[2];\n") f.write("\n") f.write(" end\n") f.write(" 2: begin\n") f.write(" if (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1;\n") f.write(" else if ((i+stride_plus)1): if (i==0): f.write(" if") else: f.write(" else if") f.write(" ({"+lvl[1:]+"}=="+str(len(bin(num_conv))-3)+"'d"+str(i)+") \n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_1[2]=qp["+one_size+"-1:"+two_size+"];\n") f.write(" end\n") else: f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "1[2]=qp[SIZE_1-1:0];\n") f.write(" end\n") f.write(" end\n") for i in range(num_conv): f.write(" p" + str(i) + "_1=buff" + str(i) + "_1[0];\n") f.write(" p" + str(i) + "_2=buff" + str(i) + "_1[1];\n") f.write(" p" + str(i) + "_3=buff" + str(i) + "_1[2];\n") f.write("\n") f.write(" end\n") for i in range(num_conv): f.write(" w" + str(i+1) + "1=(onexone)?w" + str(i+1) + "9_pre:w" + str(i+1) + "6_pre;\n") f.write(" w" + str(i+1) + "2=(onexone)?w" + str(i+1) + "8_pre:w" + str(i+1) + "5_pre;\n") f.write(" w" + str(i+1) + "3=(onexone)?w" + str(i+1) + "7_pre:w" + str(i+1) + "4_pre;\n") f.write("\n") f.write(" go=1;\n") f.write(" up_perm=0;\n") f.write(" down_perm=0;\n") f.write(" if ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1)))\n") f.write(" begin\n") f.write(" if (onexone) write_addresstp=i_onexone-2;\n") f.write(" else write_addresstp=(i>>(stride-1))-1;\n") f.write(" if (glob_average_en) write_addressp=memstartzap;\n") f.write(" else\n") f.write(" begin\n") f.write(" if (onexone) write_addressp=memstartzap+i_onexone-2;\n") f.write(" else write_addressp=memstartzap+((i-2)>>(stride-1));\n") f.write(" end\n") f.write("\n") f.write(" if (((onexone && (i_onexone_1 == 0)) || !onexone)&&(!bias)) we_t=1;\n") f.write("\n") for i in range(num_conv): f.write(" res" + str(i+1) + "=res" + str(i+1) + "+Y" + str(i+1) + ";\n") f.write("\n") f.write(" if ((lvl!=0)&&(!depthwise))\n") f.write(" begin\n") for i in range(num_conv): f.write(" res" + str(i+1) + "=res" + str(i+1) + "+res_old_" + str(i+1) + ";\n") f.write(" end\n") f.write(" if (bias)\n") f.write(" begin\n") for i in range(num_conv): f.write(" res" + str(i+1) + "=res" + str(i+1) + "+(data_bias_" + str(i+1) + "<<"+str(sizeI+1)+");\n") f.write("\n") for i in range(num_conv): f.write(" if (res" + str(i+1) + "<0) res" + str(i+1) + "=0; //RELU\n") f.write("\n") for i in range(num_conv): f.write(" res_bias_check_" + str(i+1) + "=res" + str(i+1) + "["+ str(sizeI+sizeW+2) +"-1-2:SIZE_1-2];\n") f.write("\n") for i in range(num_conv): f.write(" if (res_bias_check_" + str(i+1) + ">(2**(SIZE_1-1))-1) res_out_" + str(i+1) + "=(2**(SIZE_1-1))-1;\n") f.write(" else res_out_" + str(i+1) + "=res" + str(i+1) + "[SIZE_1+SIZE_1-2-2:SIZE_1-2];\n") f.write("\n") f.write(" if ((glob_average_en)&&(i_onexone_1 == 0))\n") f.write(" begin\n") for i in range(num_conv): f.write(" glob_average_perem_" + str(i+1) + " = glob_average_perem_" + str(i+1) + " + res_out_" + str(i+1) + ";\n") f.write(" end\n") f.write(" if ((onexone && (i_onexone_1 == 0)) || !onexone) we=1;\n") f.write(" end\n") f.write(" end\n") f.write(" end\n") f.write(" 3: begin\n") f.write(" re_t=1;\n") f.write(" if (onexone) read_addresstp=i_onexone-1;\n") f.write(" else read_addresstp=(i>>(stride-1))-1;\n") f.write("\n") f.write(" if (onexone)\n") f.write(" begin\n") if (num_conv<8): for i in range(num_conv): f.write(" p" + str(num_conv+i) + "_pre = qp[SIZE_" + str(num_conv-i) + "-1:") if (num_conv==(i+1)): f.write("0") else: f.write("SIZE_" + str(num_conv-i-1)) f.write("];\n") f.write("\n") for i in range(num_conv): f.write(" p" + str(i) + "_1=p3_pre;\n") f.write(" p" + str(i) + "_2=p4_pre;\n") f.write(" p" + str(i) + "_3=p5_pre;\n") f.write("\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" if (depthwise)\n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_0[2]=qp[SIZE_" + str(num_conv-i) + "-1:") if (num_conv==(i+1)): f.write("0") else: f.write("SIZE_" + str(num_conv-i-1)) f.write("];\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" if ((i+stride_plus)>=matrix-1)\n") f.write(" begin\n") lvl='' for i in range(len(bin(num_conv))-3): lvl = ",lvl["+str(i)+"]" + lvl for i in range(num_conv): one_size="SIZE_"+str(num_conv-i) if ((num_conv-i-1)==0): two_size="0" else: two_size="SIZE_"+str(num_conv-i-1) if (num_conv>1): if (i==0): f.write(" if") else: f.write(" else if") f.write(" ({"+lvl[1:]+"}=="+str(len(bin(num_conv))-3)+"'d"+str(i)+") \n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_0[2]=qp["+one_size+"-1:"+two_size+"];\n") f.write(" end\n") else: f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "0[2]=qp[SIZE_1-1:0];\n") f.write(" end\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") for i in range(num_conv): f.write(" buff" + str(i) + "_0[2]=0;\n") f.write(" end\n") f.write(" end\n") for i in range(num_conv): f.write(" p" + str(i) + "_1=buff" + str(i) + "_0[0];\n") f.write(" p" + str(i) + "_2=buff" + str(i) + "_0[1];\n") f.write(" p" + str(i) + "_3=buff" + str(i) + "_0[2];\n") f.write("\n") f.write(" end\n") for i in range(num_conv): f.write(" w" + str(i+1) + "1=(onexone)?w" + str(i+1) + "6_pre:w" + str(i+1) + "9_pre;\n") f.write(" w" + str(i+1) + "2=(onexone)?w" + str(i+1) + "5_pre:w" + str(i+1) + "8_pre;\n") f.write(" w" + str(i+1) + "3=(onexone)?w" + str(i+1) + "4_pre:w" + str(i+1) + "7_pre;\n") f.write("\n") f.write(" if (onexone) up_perm=0; else up_perm=1;\n") f.write(" down_perm=0;\n") f.write(" we_t=0;\n") f.write(" we=0;\n") f.write(" end \n") f.write(" default: $display(\"Check case conv_TOP\");\n") f.write(" endcase\n") f.write("\n") f.write(" if (marker!=3) marker=marker+1;\n") f.write(" else begin \n") f.write(" marker=0; \n") f.write(" if (((i>2)\n") f.write(" begin\n") f.write(" i_onexone = i_onexone + 1;\n") f.write(" i_onexone_1 = 0;\n") f.write(" end\n") f.write(" else i_onexone_1 = i_onexone_1 + 1;\n") f.write(" end\n") f.write(" end\n") f.write(" else STOP=1; \n") f.write(" end\n") f.write(" end\n") f.write(" end\n") f.write("else \n") f.write(" begin\n") f.write(" i=0;\n") f.write(" i_to_prov=-2;\n") f.write(" stride_plus=0;\n") f.write(" next_number=matrix;\n") f.write(" zagryzka_weight=0;\n") f.write(" STOP=0;\n") f.write(" re=0;\n") f.write(" re_t=0;\n") f.write(" go=0;\n") f.write(" marker=0;\n") for i in range(num_conv): f.write(" glob_average_perem_"+str(i+1)+"=0;\n") f.write(" i_onexone = 0;\n") f.write(" i_onexone_1 = 0;\n") f.write(" read_addressw=0;\n") f.write(" read_addressb=0;\n") f.write(" re_wb=0;\n") f.write(" end\n") f.write("end\n") for i in range(num_conv): f.write("assign glob_average_perem_" + str(i+1) + "_1=glob_average_perem_" + str(i+1) + ">>4;\n") f.write("assign dp={") for i in range(num_conv): f.write("(glob_average_en?glob_average_perem_" + str(i+1) + "_1:res_out_" + str(i+1) + ")") if ((i+1)!=num_conv): f.write(",") f.write("\n") f.write("};\n") f.write("assign dtp={" + str(res[:-1]) + "};\n") f.write("endmodule\n") f.close() def dense(directory, in_dense_razmer, out_dense_razmer, num_conv, sizeI, sizeW): file = open(directory + "dense.v", 'w') bit_in = len(bin(in_dense_razmer)) - 2 bit_out = len(bin(out_dense_razmer)) - 2 Y='' w='' p='' Ypl='' Y_use='' Y_use_pl='' for i in range(num_conv): Y=Y+" Y"+str(i+1)+"," Y_use=Y_use+" Y"+str(i+1)+"_use," Y_use_pl = Y_use_pl + " Y" + str(i + 1) + "_use+" Ypl = Ypl + " (Y" + str(i + 1) + "_use?Y" + str(i + 1) + ":0)+" w=w+" w"+str(i+1)+"1, w"+str(i+1)+"2, w"+str(i+1)+"3," p=p+" p"+str(i+1)+"1, p"+str(i+1)+"2, p"+str(i+1)+"3," file.write("module dense(clk, dense_en, STOP, in, out, we, re_p, re_w, read_addressp, read_addressw, write_addressp, memstartp, memstartzap, qp, qw, res,"+Y+w+p+" go, nozero);\n\n") file.write("parameter num_conv=0;\n") file.write("\n") for i in range(num_conv): file.write("parameter SIZE_"+str(i+1)+"=0;\n") file.write("parameter SIZE_address_pix=0;\n") file.write("parameter SIZE_address_wei=0;\n") file.write("parameter SIZE_weights=0;\n") file.write("\n") file.write("input clk,dense_en;\n") file.write("output reg STOP;\n") file.write("input ["+str(bit_in-1)+":0] in;\n") file.write("input ["+str(bit_out-1)+":0] out;\n") file.write("output reg we,re_p,re_w;\n") file.write("output reg [SIZE_address_pix-1:0] read_addressp;\n") file.write("output reg [SIZE_address_wei-1:0] read_addressw;\n") file.write("output reg [SIZE_address_pix-1:0] write_addressp;\n") file.write("input [SIZE_address_pix-1:0] memstartp,memstartzap;\n") file.write("input signed [SIZE_"+str(num_conv)+"-1:0] qp;\n") file.write("input signed [SIZE_weights*9-1:0] qw;\n") file.write("output reg signed [SIZE_"+str(num_conv)+"-1:0] res;\n") file.write("input signed [32-1:0]"+Y[:-1]+";\n") file.write("output reg signed [SIZE_weights - 1:0]"+w[:-1]+";\n") file.write("output reg signed [SIZE_1-1:0]"+p[:-1]+";\n") file.write("output reg go;\n") file.write("input nozero;\n") file.write("\n") for i in range(num_conv): file.write("reg signed[SIZE_weights - 1:0] w"+str(i+1)+"1_pre, w"+str(i+1)+"2_pre, w"+str(i+1)+"3_pre, w"+str(i+1)+"4_pre, w"+str(i+1)+"5_pre, w"+str(i+1)+"6_pre, w"+str(i+1)+"7_pre, w"+str(i+1)+"8_pre, w"+str(i+1)+"9_pre;\n") file.write("\n") for i in range(num_conv): file.write("reg signed[SIZE_1 - 1:0] p"+str(i+1)+"1_pre, p"+str(i+1)+"2_pre, p"+str(i+1)+"3_pre, p"+str(i+1)+"4_pre, p"+str(i+1)+"5_pre, p"+str(i+1)+"6_pre, p"+str(i+1)+"7_pre, p"+str(i+1)+"8_pre, p"+str(i+1)+"9_pre;\n") file.write("reg [3:0] marker;\n") file.write("reg [6:0] lvl;\n") file.write("reg [8:0] i;\n") file.write("reg [8:0] j;\n") bit_sh=len(bin(num_conv)) - 4 if (bit_sh>0): sh="["+str(bit_sh)+":0]" else: sh='' file.write("reg "+sh+" sh;\n") file.write("reg signed [32-1:0] dp;\n") ###[(SIZE_2)*"+str(num_conv)+"-1:0] file.write("reg signed [SIZE_1-1:0] dp_shift;\n") file.write("reg signed [19-1:0]dp_check;\n\n") file.write("always @(posedge clk)\n") file.write("begin\n") file.write(" if (dense_en==1)\n") file.write(" begin\n") file.write(" re_p=1;\n") file.write(" case (marker)\n") k1=1 k2=1 k3=1 k4=1 k7=1 k8=1 k9=1 k10=1 i=2 STOP=0 while (STOP==0): file.write(str(i)+":begin\n") file.write(" if (i>(in>>"+str(len(bin(num_conv))-3)+")+1) begin\n") file.write(" ") for j in range(num_conv): file.write(" p"+str(k1)+str(k2)+"_pre = 0;") if (k2==9): k2=1 k1+=1 else: k2+=1 file.write("\n end\n") file.write(" else begin\n") file.write(" ") for j in range(num_conv): one="SIZE_"+str(num_conv-j) if (num_conv-j-1==0): two="0" else: two = "SIZE_"+str(num_conv - j - 1) file.write(" p"+str(k3)+str(k4)+"_pre = qp["+one+" - 1:"+two+"];") if (k4==9): k4=1 k3+=1 else: k4+=1 file.write("\n end\n") file.write(" ") if (((i>=2)|((i<2)&((i+num_conv)<=num_conv)))&(i<(num_conv+2))): k6=9 for k5 in range(9): if (i<2): m=(num_conv*1+1) else: m=0 file.write("w"+str(i-1+m)+str(k5+1)+"_pre=qw[SIZE_weights*"+str(k6)+"-1:SIZE_weights*") if ((k6-1)==0): file.write("0]; ") else: file.write(str(k6-1)+"]; ") k6-=1 file.write("\n") if (i(in>>"+str(len(bin(num_conv))-3)+")+4)&&(marker==4))\n") file.write(" begin\n") file.write(" write_addressp=memstartzap+(lvl>>(num_conv>>1));\n") file.write(" dp_check=dp["+str(sizeI+sizeW+2)+"-1-2:SIZE_1-2];\n") file.write(" if ((dp_shift<0)&&(nozero==0)) dp_shift=0;\n") file.write(" if (dp_check>2**(SIZE_1-1)-1) dp_shift=2**(SIZE_1-1)-1;\n") file.write(" else dp_shift=dp_check;\n") for i in range(num_conv): file.write(" if (sh == "+str(i)+") begin") if (i==0): file.write(" res=0;") file.write(" res[SIZE_"+str(num_conv-i)+"-1:") if (num_conv-i-1==0): file.write("0") else: file.write("SIZE_"+str(num_conv-i-1)) file.write("]=dp_shift; end\n") file.write(" lvl=lvl+1;\n") file.write(" i=0; \n") file.write(" j=0; \n") file.write(" dp=0; \n") file.write(" marker=0;\n") file.write(" sh=sh+1; if (sh==num_conv) sh=0; \n") file.write(" if ((sh==0)||(lvl==out)) we=1;\n") file.write(" if (lvl==out) STOP=1;\n") file.write(" end\n") file.write("end\n") file.write("else\n") file.write("begin\n") file.write(" marker=0;\n") file.write(" i=0;\n") file.write(" j=0;\n") file.write(" sh=0;\n") file.write(" we=0;\n") file.write(" dp=0;\n") file.write(" res=0;\n") file.write(" re_p=0;\n") file.write(" re_w=0;\n") file.write(" STOP=0;\n") file.write(" lvl=0;\n") file.write("end\n") file.write("end\n") file.write("endmodule\n") file.close() def RAM(directory, max_weights_per_layer, num_conv): f = open(directory + "RAM.v", 'w') f.write("module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk,clk_RAM_w,q_bias,d_bias,we_bias,re_bias,write_address_bias,read_address_bias);\n") f.write("parameter picture_size=0; \n") for i in range(num_conv): f.write("parameter SIZE_"+str(i+1)+"=0;\n") f.write("parameter SIZE_address_pix=13;\n") f.write("parameter SIZE_address_pix_t=12;\n") f.write("parameter SIZE_address_wei=13;\n") f.write("parameter SIZE_address_image=16;\n") f.write("parameter SIZE_weights=0;\n") f.write("parameter SIZE_bias=0;\n") f.write("\n") f.write("output reg signed [SIZE_"+str(num_conv)+"-1:0] qp; //read data\n") f.write("output reg signed [32*"+str(num_conv)+"-1:0] qtp; //read data\n") f.write("output reg signed [SIZE_weights*9-1:0] qw; //read weight\n") f.write("output reg signed [SIZE_bias-1:0] q_bias;\n") f.write("input signed [SIZE_1*"+str(num_conv)+"-1:0] dp; //write data\n") f.write("input signed [32*"+str(num_conv)+"-1:0] dtp; //write data\n") f.write("input signed [SIZE_weights*9-1:0] dw; //write weight\n") f.write("input signed [SIZE_bias-1:0] d_bias;\n") f.write("input [SIZE_address_pix-1:0] write_addressp, read_addressp;\n") f.write("input [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;\n") f.write("input [SIZE_address_wei-1:0] write_addressw, read_addressw;\n") f.write("input [10:0] write_address_bias,read_address_bias;\n") f.write("input we_p;\n") f.write("input we_tp;\n") f.write("input we_w;\n") f.write("input we_bias;\n") f.write("input re_p;\n") f.write("input re_tp;\n") f.write("input re_w;\n") f.write("input re_bias;\n") f.write("input clk,clk_RAM_w;\n") f.write("\n") f.write("reg signed [SIZE_1*"+str(num_conv)+"-1:0] mem [0:128*128*"+str(int(4/num_conv))+"+4096*"+str(num_conv)+"-1];\n") f.write("reg signed [32*"+str(num_conv)+"-1:0] mem_t [0:4096-1];\n") f.write("reg signed [SIZE_weights*9-1:0] weight [0:4095]; \n") f.write("reg signed [SIZE_bias-1:0] mem_bias [0:256];\n") f.write("always @ (posedge clk) \n") f.write(" begin\n") f.write(" if (we_p) mem[write_addressp] <= dp;\n") f.write(" if (we_tp) mem_t[write_addresstp] <= dtp;\n") f.write(" end\n") f.write("always @ (posedge clk_RAM_w)\n") f.write(" begin\n") f.write(" if (we_w) weight[write_addressw] <= dw;\n") f.write(" if (we_bias) mem_bias[write_address_bias] <= d_bias;\n") f.write(" end\n") f.write("always @ (posedge clk)\n") f.write(" begin\n") f.write(" if (re_p) qp <= mem[read_addressp];\n") f.write(" if (re_tp)qtp <= mem_t[read_addresstp];\n") f.write(" if (re_w) qw <= weight[read_addressw];\n") f.write(" if (re_bias) q_bias <= mem_bias[read_address_bias];\n") f.write(" end\n") f.write("\n") f.write("endmodule\n") f.close() def RAMtoMEM(directory, max_address_value, steps_count, in_dense_razmer, conv_block_size, num_conv): f = open(directory + "RAMtoMEM.v", 'w') bit_max_address_value = len(bin(max_address_value)) - 2 bit_weight_case = len(bin(conv_block_size*conv_block_size)) - 2 bit_steps_count = len(bin(steps_count)) - 2 bit_in_dense_razmer = len(bin(in_dense_razmer)) - 2 f.write("module memorywork(clk_RAM_w,data,data_bias,address,we_w,re_weights,re_bias,nextstep,dw,addrw,step_out,GO,in_dense,load_weights,onexone,address_bias,d_bias,load_bias,we_bias,write_address_bias);\n") f.write("\n") f.write("parameter num_conv=0;\n") f.write("\n") for i in range(num_conv): f.write("parameter SIZE_"+str(i+1)+"=0;\n") f.write("parameter SIZE_address_pix=0;\n") f.write("parameter SIZE_address_wei=0;\n") f.write("parameter SIZE_weights=0;\n") f.write("parameter SIZE_bias=0;\n") f.write("\n") f.write("input clk_RAM_w;\n") f.write("input signed [SIZE_weights-1:0] data;\n") f.write("input signed [SIZE_bias-1:0] data_bias;\n") f.write("output [23:0] address;\n") f.write("output reg we_w;\n") f.write("output re_weights,re_bias;\n") f.write("input nextstep;\n") f.write("output reg signed [SIZE_weights*9-1:0] dw;\n") f.write("output reg [SIZE_address_wei-1:0] addrw;\n") f.write("output ["+str(bit_steps_count-1)+":0] step_out;\n") f.write("input GO;\n") f.write("input ["+str(bit_in_dense_razmer-1)+":0] in_dense;\n") f.write("input load_weights,load_bias;\n") f.write("\n") f.write("output reg signed [SIZE_bias-1:0] d_bias;\n") f.write("output reg we_bias;\n") f.write("output reg [10:0] write_address_bias;\n") f.write("output [11:0] address_bias;\n") f.write("\n") f.write("input onexone; \n") f.write("\n") f.write("reg [SIZE_address_pix-1:0] addr;\n") f.write("wire ["+str(bit_max_address_value-1)+":0] firstaddr,lastaddr;\n") f.write("\n") f.write("wire [18:0] razn_addr;\n") f.write("assign razn_addr = lastaddr-firstaddr;\n") f.write("\n") f.write("reg ["+str(bit_steps_count-1)+":0] step;\n") f.write("reg ["+str(bit_steps_count-1)+":0] step_n;\n") f.write("reg ["+str(bit_weight_case-1)+":0] weight_case;\n") f.write("reg [SIZE_weights*9-1:0] buff;\n") f.write("reg ["+str(bit_max_address_value-1)+":0] i;\n") f.write("reg ["+str(bit_max_address_value-1)+":0] i_d;\n") f.write("reg ["+str(bit_max_address_value-1)+":0] i1;\n") f.write("addressRAM inst_1(.step(step_out),.re_weights(re_weights),.re_bias(re_bias),.firstaddr(firstaddr),.lastaddr(lastaddr)); \n") f.write("initial weight_case=0;\n") f.write("initial i=0;\n") f.write("initial i_d=0;\n") f.write("initial i1=0;\n") f.write("\n") f.write("always @(negedge clk_RAM_w)\n") f.write(" if ( (step_out==1)||(step_out==2)\n") f.write(" ||(step_out==4)||(step_out==5)\n") f.write(" ||(step_out==7)||(step_out==8)\n") f.write(" ||(step_out==10)||(step_out==11)\n") f.write(" ||(step_out==13)||(step_out==14)\n") f.write(" ||(step_out==16)||(step_out==17)\n") f.write(" ||(step_out==19)||(step_out==20)\n") f.write(" ||(step_out==22)||(step_out==23)\n") f.write(" ||(step_out==25)||(step_out==26)\n") f.write(" ||(step_out==28)||(step_out==29)\n") f.write(" ||(step_out==31)||(step_out==32)\n") f.write(" ||(step_out==34)||(step_out==35)\n") f.write(" ||(step_out==37)||(step_out==38)\n") f.write(" ||(step_out==40)||(step_out==41)\n") f.write(" ||(step_out==43)||(step_out==44)\n") f.write(" ||(step_out==46)||(step_out==47)\n") f.write(" ||(step_out==49)||(step_out==50)\n") f.write(" ||(step_out==52)||(step_out==53)\n") f.write(" ||(step_out==55)||(step_out==56)\n") f.write(" ||(step_out==58)||(step_out==59)\n") f.write(" ||(step_out==61)||(step_out==62)\n") f.write(" ||(step_out==64)||(step_out==65)\n") f.write(" ||(step_out==67)||(step_out==68)\n") f.write(" ||(step_out==70)||(step_out==71)\n") f.write(" ||(step_out==73)||(step_out==74)\n") f.write(" ||(step_out==76)||(step_out==77)\n") f.write(" ||(step_out==79)||(step_out==80)\n") f.write(" ||(step_out==82)||(step_out==83)\n") f.write(" ||(step_out==85)\n") f.write(" )\n") f.write(" begin\n") f.write(" if ((i<=razn_addr+1)&&(re_weights)) addr=i1;\n") f.write(" if ((i<=razn_addr+1)&&(re_bias)) addr=i;\n") f.write(" end\n") f.write("\n") f.write("always @(posedge clk_RAM_w or posedge GO)\n") f.write(" if (GO) step=1;\n") f.write(" else\n") f.write(" begin\n") f.write(" case (step_out)\n") f.write(" 8'd1,8'd4,8'd7,8'd10,8'd13,8'd16,8'd19,8'd22,8'd25,8'd28,8'd31,8'd34,8'd37,8'd40,8'd43,8'd46,8'd49,8'd52,8'd55,8'd58,8'd61,8'd64,8'd67,8'd70,8'd73,8'd76,8'd79,8'd82,8'd85:\n") f.write(" begin\n") f.write(" if (i<=razn_addr+3)\n") f.write(" begin\n") f.write(" we_w=0;\n") f.write(" addrw=addr;\n") f.write(" if (load_weights==1'b1) i=i+1; \n") f.write(" if (step_out==85) if (i_d==((in_dense)+1)) begin dw=buff; we_w=1; weight_case=1; i_d=1; i1=i1+1; end\n") f.write(" case (weight_case)\n") f.write(" 0: ;\n") f.write(" 1: begin buff=0; buff[SIZE_weights*9-1:SIZE_weights*8]=data[SIZE_weights-1:0]; end \n") f.write(" 2: buff[SIZE_weights*8-1:SIZE_weights*7]=data[SIZE_weights-1:0]; \n") f.write(" 3: buff[SIZE_weights*7-1:SIZE_weights*6]=data[SIZE_weights-1:0]; \n") f.write(" 4: buff[SIZE_weights*6-1:SIZE_weights*5]=data[SIZE_weights-1:0]; \n") f.write(" 5: buff[SIZE_weights*5-1:SIZE_weights*4]=data[SIZE_weights-1:0]; \n") f.write(" 6: buff[SIZE_weights*4-1:SIZE_weights*3]=data[SIZE_weights-1:0]; \n") f.write(" 7: buff[SIZE_weights*3-1:SIZE_weights*2]=data[SIZE_weights-1:0]; \n") f.write(" 8: buff[SIZE_weights*2-1:SIZE_weights]=data[SIZE_weights-1:0]; \n") f.write(" 9: begin buff[SIZE_weights-1:0]=data[SIZE_weights-1:0]; end\n") f.write(" default: $display(\"Check weight_case\");\n") f.write(" endcase\n") f.write(" if (load_weights==1'b1) i_d=i_d+1;\n") f.write(" if (load_weights==1'b1)\n") f.write(" begin\n") f.write(" if ((weight_case==9)||((onexone)&&(weight_case==8))) \n") f.write(" begin \n") f.write(" weight_case=1; \n") f.write(" dw=buff; \n") f.write(" we_w=1; \n") f.write(" i1=i1+1;\n") f.write(" end \n") f.write(" else \n") f.write(" begin\n") f.write(" weight_case=weight_case+1;\n") f.write(" end\n") f.write(" end\n") f.write(" end\n") f.write(" if (i>razn_addr+3)\n") f.write(" begin\n") f.write(" step=step+1; //next step\n") f.write(" i=0;\n") f.write(" i_d=0;\n") f.write(" i1=0;\n") f.write(" weight_case=0;\n") f.write(" end\n") f.write(" end\n") f.write(" 8'd2,8'd5,8'd8,8'd11,8'd14,8'd17,8'd20,8'd23,8'd26,8'd29,8'd32,8'd35,8'd38,8'd41,8'd44,8'd47,8'd50,8'd53,8'd56,8'd59,8'd62,8'd65,8'd68,8'd71,8'd74,8'd77,8'd80,8'd83:\n") f.write(" begin\n") f.write(" if (i<=razn_addr)\n") f.write(" begin\n") f.write(" we_bias=1;\n") f.write(" write_address_bias=addr;\n") f.write(" if (load_bias==1'b1) i=i+1;\n") f.write(" d_bias=data_bias;\n") f.write(" end\n") f.write(" else \n") f.write(" begin\n") f.write(" step=step+1;\n") f.write(" i=0;\n") f.write(" we_bias=0;\n") f.write(" end\n") f.write(" end\n") f.write(" default:\n") f.write(" begin\n") f.write(" we_w=0;\n") f.write(" we_bias=0;\n") f.write(" i=0;\n") f.write(" i_d=0;\n") f.write(" i1=0;\n") f.write(" end\n") f.write(" endcase\n") f.write(" end\n") f.write("always @(posedge nextstep) if (GO==1) step_n=0; else step_n=step_n+1;\n") f.write("assign step_out=step+step_n;\n") f.write("assign address=(re_weights)?(firstaddr+i):0;\n") f.write("assign address_bias=(re_bias)?(firstaddr+i):0;\n") f.write("endmodule\n") f.close() def result(directory,output_neurons_count,num_conv): f = open(directory + "result.v", 'w') bit_output_neurons_count = len(bin(output_neurons_count))-2 bit_marker_chislo = len(bin(output_neurons_count+2)) - 2 f.write("module result(clk,enable,STOP,memstartp,read_addressp,qp,re,RESULT);\n") f.write("\n") for i in range(num_conv): f.write("parameter SIZE_"+str(i+1)+"=0;\n") f.write("parameter SIZE_address_pix=0;\n") f.write("\n") f.write("input clk,enable;\n") f.write("output reg STOP;\n") f.write("input [SIZE_address_pix-1:0] memstartp;\n") f.write("input [SIZE_"+str(num_conv)+"-1:0] qp;\n") f.write("output reg re;\n") f.write("output reg [SIZE_address_pix-1:0] read_addressp;\n") f.write("output reg ["+str(bit_output_neurons_count-1)+":0] RESULT;\n") f.write("\n") f.write("reg ["+str(bit_marker_chislo-1)+":0] marker;\n") f.write("wire signed [SIZE_1-1:0] p1,p2;\n") f.write("always @(posedge clk)\n") f.write("begin\n") f.write("if (enable==1)\n") f.write("begin\n") f.write("re=1;\n") f.write("case (marker)\n") f.write(" 0: read_addressp=memstartp;\n") f.write(" 1: ;\n") f.write(" 2: begin\n") f.write(" RESULT=0; \n") f.write(" if (p2>=p1) RESULT=1; \n") f.write(" else RESULT=0; \n") f.write(" STOP=1; \n") f.write(" end\n") f.write(" default: $display(\"Check case result\");\n") f.write("endcase\n") f.write("marker=marker+1;\n") f.write("end\n") f.write("else \n") f.write("begin\n") f.write("re=0;\n") f.write("marker=0;\n") f.write("STOP=0;\n") f.write("end\n") f.write("end\n") f.write("\n") f.write("assign p1=qp[SIZE_" + str(num_conv) + "-1:SIZE_" + str(num_conv-1) + "];\n") f.write("assign p2=qp[SIZE_" + str(num_conv-1) + "-1:") if (num_conv-2!=0): f.write("SIZE_" + str(num_conv-2)) else: f.write("0") f.write("];\n") f.write("endmodule\n") def TOP(directory, sizeI, sizeW, sizeB, razmer, max_address_value, output_neurons_count, max_weights_per_layer, total_conv_layers_number, max_conv_input_size, in_dense_razmer, out_dense_razmer, max_conv_output_size, layers, num_conv, steps_count): f = open(directory + "TOP.v", 'w') bit_max_address_value = len(bin(max_address_value)) - 2 bit_output_neurons_count = len(bin(output_neurons_count)) - 2 bit_address_pix = len(bin(razmer*razmer*8+razmer*razmer)) - 2 bit_address_pix_t = len(bin(razmer*razmer*4)) - 2 bit_max_weights_per_layer = len(bin(max_weights_per_layer)) - 2 bit_total_conv_layers_number = len(bin(total_conv_layers_number)) - 2 bit_max_conv_input_size = len(bin(max_conv_input_size)) - 2 bit_razmer = len(bin(razmer)) - 2 bit_razmer_2 = len(bin(razmer*razmer)) - 2 bit_in_dense_razmer = len(bin(in_dense_razmer)) - 2 bit_out_dense_razmer = len(bin(out_dense_razmer)) - 2 bit_max_conv_output_size = len(bin(max_conv_output_size)) - 2 bit_steps_count = len(bin(steps_count)) - 2 Y='' p='' w='' p_d='' w_c='' w_d='' for i in range(num_conv): Y=Y+"Y"+str(i+1)+"," w_c=w_c+"w"+str(i+1)+"1_c,w"+str(i+1)+"2_c,w"+str(i+1)+"3_c,w"+str(i+1)+"4_c,w"+str(i+1)+"5_c,w"+str(i+1)+"6_c,w"+str(i+1)+"7_c,w"+str(i+1)+"8_c,w"+str(i+1)+"9_c," w_d=w_d+"w"+str(i+1)+"1_d,w"+str(i+1)+"2_d,w"+str(i+1)+"3_d,w"+str(i+1)+"4_d,w"+str(i+1)+"5_d,w"+str(i+1)+"6_d,w"+str(i+1)+"7_d,w"+str(i+1)+"8_d,w"+str(i+1)+"9_d," p_d=p_d+"p"+str(i+1)+"1_d,p"+str(i+1)+"2_d,p"+str(i+1)+"3_d,p"+str(i+1)+"4_d,p"+str(i+1)+"5_d,p"+str(i+1)+"6_d,p"+str(i+1)+"7_d,p"+str(i+1)+"8_d,p"+str(i+1)+"9_d," p = p + "p" + str(i + 1) + "1,p" + str(i + 1) + "2,p" + str(i + 1) + "3,p" + str(i + 1) + "4,p" + str(i + 1) + "5,p" + str(i + 1) + "6,p" + str(i + 1) + "7,p" + str(i + 1) + "8,p" + str(i + 1) + "9," w = w + "w" + str(i + 1) + "1,w" + str(i + 1) + "2,w" + str(i + 1) + "3,w" + str(i + 1) + "4,w" + str(i + 1) + "5,w" + str(i + 1) + "6,w" + str(i + 1) + "7,w" + str(i + 1) + "8,w" + str(i + 1) + "9," f.write("module TOP(\n") f.write("clk,\n") f.write("clk_RAM_w,\n") f.write("clk_RAM_p,\n") f.write("GO,\n") f.write("RESULT,\n") f.write("STOP,\n") f.write("\n") f.write("re_weights,\n") f.write("load_weights,\n") f.write("dp_weights,\n") f.write("address_weights,\n") f.write("\n") f.write("re_bias,\n") f.write("load_bias,\n") f.write("dp_bias,\n") f.write("address_bias,\n") f.write("\n") f.write("we_image,\n") f.write("dp_image,\n") f.write("address_image,\n") f.write("step\n") f.write(");\n") f.write("\n") f.write("parameter num_conv="+str(num_conv)+";\n") f.write("parameter SIZE_weights = "+str(sizeW+1)+";\n") f.write("parameter SIZE_bias = "+str(sizeB+1)+";\n") for i in range(num_conv): f.write("parameter SIZE_"+ str(i+1) +"=" + str((sizeI + 1)*(i+1)) + ";\n") f.write("parameter SIZE_address_pix="+str(bit_address_pix)+";\n") f.write("parameter SIZE_address_pix_t="+str(bit_address_pix_t)+";\n") f.write("parameter SIZE_address_wei="+str(bit_max_weights_per_layer)+";\n") f.write("parameter SIZE_address_image=16;\n") f.write("parameter picture_size = "+str(razmer)+";\n") f.write("parameter picture_storage_limit = 0;\n") f.write("parameter razmpar = picture_size >> 1;\n") f.write("parameter razmpar2 = picture_size >> 2;\n") f.write("parameter picture_storage_limit_2 = picture_size*picture_size;\n") f.write("input clk,clk_RAM_w,clk_RAM_p;\n") f.write("input GO;\n") f.write("output ["+str(bit_output_neurons_count-1)+":0] RESULT;\n") f.write("input signed [SIZE_weights-1:0] dp_weights;\n") f.write("input signed [SIZE_bias-1:0] dp_bias;\n") f.write("output [23:0] address_weights;\n") f.write("output [11:0] address_bias;\n") f.write("input load_weights,load_bias;\n") f.write("input signed [SIZE_1-1:0] dp_image;\n") f.write("input [SIZE_address_image-1:0] address_image;\n") f.write("input we_image;\n") f.write("output reg STOP;\n") f.write("output re_weights,re_bias;\n") f.write("output ["+str(bit_steps_count-1)+":0] step;\n") f.write("\n") f.write("wire [SIZE_address_image-1:0] address_image_1;\n") f.write("\n") f.write("reg conv_en;\n") f.write("wire STOP_conv;\n") f.write("\n") f.write("reg dense_en;\n") f.write("wire STOP_dense;\n") f.write("\n") f.write("reg result_en;\n") f.write("wire STOP_res; \n") f.write("wire ["+str(bit_output_neurons_count-1)+":0] res_out;\n") f.write("\n") f.write("reg bias,glob_average_en;\n") f.write("\n") f.write("reg ["+str(bit_total_conv_layers_number-1)+":0] TOPlvl_conv;\n") f.write("wire ["+str(bit_total_conv_layers_number-1)+":0] TOPlvl;\n") f.write("reg [8:0] lvl;\n") f.write("reg [8:0] slvl;\n") f.write("reg [2:0] num;\n") f.write("reg [SIZE_address_pix-1:0] memstartp;\n") f.write("wire [SIZE_address_pix-1:0] memstartp_lvl;\n") f.write("reg [SIZE_address_wei-1:0] memstartw;\n") f.write("wire [SIZE_address_wei-1:0] memstartw_lvl;\n") f.write("reg [SIZE_address_pix-1:0] memstartzap;\n") f.write("wire [SIZE_address_pix-1:0] memstartzap_num;\n") f.write("wire [10:0] memstartb;\n") f.write("wire [SIZE_address_pix-1:0] read_addressp;\n") f.write("wire [SIZE_address_image-1:0] read_addressp_init;\n") f.write("wire [SIZE_address_pix_t-1:0] read_addresstp;\n") f.write("wire [SIZE_address_wei-1:0] read_addressw;\n") f.write("wire [10:0] read_address_bias; \n") f.write("wire [SIZE_address_pix-1:0] read_addressp_conv;\n") f.write("wire [SIZE_address_pix-1:0] read_addressp_dense;\n") f.write("wire [SIZE_address_pix-1:0] read_addressp_res;\n") f.write("wire [SIZE_address_wei-1:0] read_addressw_conv;\n") f.write("wire [SIZE_address_wei-1:0] read_addressw_dense;\n") f.write("wire [SIZE_address_pix-1:0] write_addressp;\n") f.write("wire [SIZE_address_pix_t-1:0] write_addresstp;\n") f.write("wire [SIZE_address_wei-1:0] write_addressw;\n") f.write("wire [10:0] write_address_bias; \n") f.write("wire [SIZE_address_pix-1:0] write_addressp_zagr;\n") f.write("wire [SIZE_address_pix-1:0] write_addressp_conv;\n") f.write("wire [SIZE_address_pix-1:0] write_addressp_dense;\n") f.write("wire we_p,we_tp,we_w;\n") f.write("wire re_p,re_tp,re_w,re_p_init;\n") f.write("wire re_bias_RAM;\n") f.write("wire we_p_zagr;\n") f.write("wire we_conv,re_wb_conv,re_conv;\n") f.write("wire we_dense,re_p_dense,re_w_dense;\n") f.write("wire we_bias;\n") f.write("wire re_p_res;\n") f.write("wire signed [SIZE_"+str(num_conv)+"-1:0] qp;\n") f.write("wire signed [32*"+str(num_conv)+"-1:0] qtp;\n") f.write("wire signed [SIZE_weights*9-1:0] qw;\n") f.write("wire signed [SIZE_bias-1:0] q_bias;\n") f.write("wire signed [SIZE_"+str(num_conv)+"-1:0] dp;\n") f.write("wire signed [32*"+str(num_conv)+"-1:0] dtp;\n") f.write("wire signed [SIZE_weights*9-1:0] dw;\n") f.write("wire signed [SIZE_"+str(num_conv)+"-1:0] dp_conv;\n") f.write("wire signed [SIZE_"+str(num_conv)+"-1:0] dp_dense;\n") f.write("wire signed [SIZE_"+str(num_conv)+"-1:0] dp_zagr;\n") f.write("wire signed [SIZE_bias-1:0] d_bias;\n") f.write("\n") f.write("wire [1:0] prov;\n") f.write("wire ["+str(bit_razmer_2-1)+":0] i_conv;\n") f.write("wire signed [32-1:0] ") for i in range(num_conv): f.write("Y"+str(i+1)) if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("\n") f.write("wire signed [SIZE_weights-1:0] ") for i in range(num_conv): f.write("w"+str(i+1)+"1,w"+str(i+1)+"2,w"+str(i+1)+"3") if (i!=num_conv-1): f.write(",") f.write(";\n") f.write("wire signed [SIZE_weights-1:0] ") for i in range(num_conv): f.write("w"+str(i+1)+"1_c,w"+str(i+1)+"2_c,w"+str(i+1)+"3_c") if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("wire signed [SIZE_weights-1:0] ") for i in range(num_conv): f.write("w"+str(i+1)+"1_d,w"+str(i+1)+"2_d,w"+str(i+1)+"3_d") if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("wire signed [SIZE_1-1:0] ") for i in range(num_conv): f.write("p"+str(i+1)+"1,p"+str(i+1)+"2,p"+str(i+1)+"3") if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("wire signed [SIZE_1-1:0] ") for i in range(num_conv): f.write("p"+str(i+1)+"1_c,p"+str(i+1)+"2_c,p"+str(i+1)+"3_c") if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("wire signed [SIZE_1-1:0] ") for i in range(num_conv): f.write("p"+str(i+1)+"1_d,p"+str(i+1)+"2_d,p"+str(i+1)+"3_d") if (i != num_conv - 1): f.write(",") f.write(";\n") f.write("wire go_conv;\n") f.write("wire go_conv_TOP;\n") f.write("wire go_dense;\n") f.write("\n") f.write("reg nextstep;\n") f.write("\n") f.write("reg ["+str(bit_razmer-1)+":0] matrix;\n") f.write("wire ["+str(bit_razmer_2-1)+":0] matrix2; //razmer*razmer\n") f.write("\n") f.write("reg ["+str(bit_max_conv_output_size-1)+":0] mem;\n") f.write("reg ["+str(bit_max_conv_input_size-1)+":0] filt;\n") f.write("reg [1:0] stride;\n") f.write("reg depthwise;\n") f.write("reg onexone;\n") f.write("\n") f.write("reg ["+str(bit_in_dense_razmer-1)+":0] in_dense;\n") f.write("reg ["+str(bit_out_dense_razmer-1)+":0] out_dense;\n") f.write("reg nozero_dense;\n") f.write("\n") f.write("wire clk_RAM;\n") f.write("\n") f.write("wire up_perm,down_perm;\n") f.write("wire [SIZE_address_pix-1:0] stride_plus_prov;\n") f.write("\n") f.write("conv_TOP #(\n") for i in range(num_conv): f.write(" SIZE_"+ str(i+1) +",\n") f.write(" SIZE_address_pix,\n") f.write(" SIZE_address_pix_t,\n") f.write(" SIZE_address_wei,\n") f.write(" SIZE_weights,\n") f.write(" SIZE_bias\n") f.write(") conv_TOP (\n") f.write(" .clk (clk),\n") f.write(" .conv_en (conv_en),\n") f.write(" .STOP (STOP_conv),\n") f.write(" .memstartp (memstartp_lvl),\n") f.write(" .memstartw (memstartw_lvl),\n") f.write(" .memstartb (memstartb),\n") f.write(" .memstartzap (memstartzap_num),\n") f.write(" .read_addressp (read_addressp_conv),\n") f.write(" .write_addressp (write_addressp_conv),\n") f.write(" .read_addresstp (read_addresstp),\n") f.write(" .write_addresstp (write_addresstp),\n") f.write(" .read_addressb (read_address_bias),\n") f.write(" .read_addressw (read_addressw_conv),\n") f.write(" .we (we_conv),\n") f.write(" .re_wb (re_wb_conv),\n") f.write(" .re (re_conv),\n") f.write(" .we_t (we_tp),\n") f.write(" .re_t (re_tp),\n") f.write(" .qp (qp),\n") f.write(" .qtp (qtp),\n") f.write(" .qw (qw),\n") f.write(" .q_bias (q_bias),\n") f.write(" .dp (dp_conv),\n") f.write(" .dtp (dtp),\n") f.write(" .prov (prov),\n") f.write(" .matrix (matrix),\n") f.write(" .matrix2 (matrix2),\n") f.write(" .i_to_prov (i_conv),\n") f.write(" .lvl (lvl),\n") f.write(" .slvl (slvl),\n") for i in range(num_conv): f.write(" .Y"+str(i+1)+" (Y"+str(i+1)+"),\n") for i in range(num_conv): for j in range(3): f.write(" .w"+str(i+1)+str(j+1)+" (w"+str(i+1)+str(j+1)+"_c),\n") for i in range(num_conv): for j in range(3): f.write(" .p"+str(i)+"_"+str(j+1)+" (p"+str(i+1)+str(j+1)+"_c),\n") f.write(" .go (go_conv_TOP),\n") f.write(" .up_perm (up_perm),\n") f.write(" .down_perm (down_perm),\n") f.write(" .stride_plus_prov (stride_plus_prov),\n") f.write(" .num (num),\n") f.write(" .filt (filt),\n") f.write(" .mem (mem),\n") f.write(" .bias (bias),\n") f.write(" .glob_average_en (glob_average_en),\n") f.write(" .step (step),\n") f.write(" .stride (stride),\n") f.write(" .depthwise (depthwise),\n") f.write(" .onexone (onexone)\n") f.write(");\n") f.write("memorywork #(\n") f.write(" num_conv,\n") for i in range(num_conv): f.write(" SIZE_"+ str(i+1) +",\n") f.write(" SIZE_address_pix,\n") f.write(" SIZE_address_wei,\n") f.write(" SIZE_weights,\n") f.write(" SIZE_bias\n") f.write(") block (\n") f.write(" .clk_RAM_w (clk_RAM_w),\n") f.write(" .we_w (we_w),\n") f.write(" .re_weights (re_weights),\n") f.write(" .re_bias (re_bias),\n") f.write(" .load_weights (load_weights),\n") f.write(" .addrw (write_addressw),\n") f.write(" .dw (dw),\n") f.write(" .step_out (step),\n") f.write(" .nextstep (nextstep),\n") f.write(" .data (dp_weights),\n") f.write(" .address (address_weights),\n") f.write(" .GO (GO),\n") f.write(" .in_dense (in_dense),\n") f.write(" .onexone (onexone),\n") f.write(" .data_bias (dp_bias),\n") f.write(" .load_bias (load_bias),\n") f.write(" .address_bias (address_bias),\n") f.write(" .write_address_bias (write_address_bias),\n") f.write(" .we_bias (we_bias),\n") f.write(" .d_bias (d_bias)\n") f.write(");\n") f.write("RAM #(\n") f.write(" picture_size,\n") for i in range(num_conv): f.write(" SIZE_"+ str(i+1) +",\n") f.write(" SIZE_address_pix,\n") f.write(" SIZE_address_pix_t,\n") f.write(" SIZE_address_wei,\n") f.write(" SIZE_address_image,\n") f.write(" SIZE_weights,\n") f.write(" SIZE_bias\n") f.write(") memory (\n") f.write(" .qp (qp),\n") f.write(" .qtp (qtp),\n") f.write(" .qw (qw),\n") f.write(" .dp (dp),\n") f.write(" .dtp (dtp),\n") f.write(" .dw (dw),\n") f.write(" .write_addressp (write_addressp),\n") f.write(" .read_addressp (read_addressp),\n") f.write(" .write_addresstp (write_addresstp),\n") f.write(" .read_addresstp (read_addresstp),\n") f.write(" .write_addressw (write_addressw),\n") f.write(" .read_addressw (read_addressw),\n") f.write(" .we_p (we_p),\n") f.write(" .we_tp (we_tp),\n") f.write(" .we_w (we_w),\n") f.write(" .re_p (re_p),\n") f.write(" .re_tp (re_tp),\n") f.write(" .re_w (re_w),\n") f.write(" .clk (clk_RAM),\n") f.write(" .clk_RAM_w (clk_RAM_w),\n") f.write(" .q_bias (q_bias),\n") f.write(" .d_bias (d_bias),\n") f.write(" .we_bias (we_bias),\n") f.write(" .re_bias (re_bias_RAM),\n") f.write(" .write_address_bias (write_address_bias),\n") f.write(" .read_address_bias (read_address_bias)\n") f.write(");\n") f.write("border border(\n") f.write(" .clk (clk),\n") f.write(" .go (conv_en && (!onexone)),\n") f.write(" .i (i_conv),\n") f.write(" .matrix (matrix),\n") f.write(" .prov (prov)\n") f.write(");\n") f.write("dense #(\n") f.write(" num_conv,\n") for i in range(num_conv): f.write(" SIZE_"+ str(i+1) +",\n") f.write(" SIZE_address_pix,\n") f.write(" SIZE_address_wei,\n") f.write(" SIZE_weights\n") f.write(") dense (\n") f.write(" .clk (clk),\n") f.write(" .dense_en (dense_en),\n") f.write(" .STOP (STOP_dense),\n") f.write(" .in (in_dense),\n") f.write(" .out (out_dense),\n") f.write(" .we (we_dense),\n") f.write(" .re_p (re_p_dense),\n") f.write(" .re_w (re_w_dense),\n") f.write(" .read_addressp (read_addressp_dense),\n") f.write(" .read_addressw (read_addressw_dense),\n") f.write(" .write_addressp (write_addressp_dense),\n") f.write(" .memstartp (memstartp_lvl),\n") f.write(" .memstartzap (memstartzap_num),\n") f.write(" .qp (qp),\n") f.write(" .qw (qw),\n") f.write(" .res (dp_dense),\n") for i in range(num_conv): f.write(" .Y"+str(i+1)+" (Y"+str(i+1)+"),\n") for i in range(num_conv): f.write(" .w"+str(i+1)+"1 (w"+str(i+1)+"1_d),\n") f.write(" .w"+str(i+1)+"2 (w"+str(i+1)+"2_d),\n") f.write(" .w"+str(i+1)+"3 (w"+str(i+1)+"3_d),\n") for i in range(num_conv): f.write(" .p" + str(i + 1) + "1 (p" + str(i + 1) + "1_d),\n") f.write(" .p" + str(i + 1) + "2 (p" + str(i + 1) + "2_d),\n") f.write(" .p" + str(i + 1) + "3 (p" + str(i + 1) + "3_d),\n") f.write(" .go (go_dense),\n") f.write(" .nozero (nozero_dense)\n") f.write(");\n") f.write("result #(\n") for i in range(num_conv): f.write(" SIZE_"+ str(i+1) +",\n") f.write(" SIZE_address_pix\n") f.write(") result (\n") f.write(" .clk (clk),\n") f.write(" .enable (result_en),\n") f.write(" .STOP (STOP_res),\n") f.write(" .memstartp (memstartp_lvl),\n") f.write(" .read_addressp (read_addressp_res),\n") f.write(" .qp (qp),\n") f.write(" .re (re_p_res),\n") f.write(" .RESULT (res_out)\n") f.write(");\n") for i in range(num_conv): f.write("conv #(\n") f.write(" SIZE_1,\n") f.write(" SIZE_address_pix,\n") f.write(" SIZE_weights\n") f.write(") conv"+str(i+1)+" (\n") f.write(" .clk (clk),\n") f.write(" .Y1 (Y"+str(i+1)+"),\n") f.write(" .prov (prov),\n") f.write(" .matrix (matrix),\n") f.write(" .matrix2 (matrix2),\n") f.write(" .i (i_conv),\n") f.write(" .up_perm ((up_perm && (!dense_en))),\n") f.write(" .down_perm ((down_perm && (!dense_en))),\n") f.write(" .p1 (p"+str(i+1)+"1),\n") f.write(" .p2 (p"+str(i+1)+"2),\n") f.write(" .p3 (p"+str(i+1)+"3),\n") f.write(" .w1 (w"+str(i+1)+"1),\n") f.write(" .w2 (w"+str(i+1)+"2),\n") f.write(" .w3 (w"+str(i+1)+"3),\n") f.write(" .conv_en (go_conv),\n") f.write(" .dense_en ((onexone||dense_en)),\n") f.write(" .stride_plus_prov (stride_plus_prov)\n") f.write(");\n") f.write("always @(posedge clk )\n") f.write("begin\n") f.write("if (GO==1)\n") f.write("begin\n") f.write("STOP=0;\n") f.write("nextstep=1;\n") f.write("glob_average_en=0;\n") f.write("result_en=0;\n") f.write("end\n") f.write("else nextstep=0;\n") f.write("if (STOP==0)\n") f.write("begin\n") TOPlvl = 1 step = 0 start = 1 start_me = 0 onexone = 0 ZeroPadding2D = 0 GlobalAveragePooling2D = 0 one = "picture_storage_limit" two = "picture_storage_limit_2" for i in range(len(layers)): layer = str(layers[i].__class__.__name__) #print(layer,layers[i].input_shape,layers[i].output_shape) if 'Conv2D' in layer: if (str(layers[i+2].__class__.__name__) == 'GlobalAveragePooling2D'): GlobalAveragePooling2D=1 else: GlobalAveragePooling2D=0 for j in range(1+GlobalAveragePooling2D): mem = int(layers[i].output_shape[3]/(1+GlobalAveragePooling2D)-1) filt = layers[i].input_shape[3]-1 if (start == 0): f.write(" if ((TOPlvl=="+str(TOPlvl)+")&&(step=="+str(step)+")) \n") f.write(" begin\n") f.write(" nextstep = 1;\n") f.write(" onexone = " + str(onexone) + ";\n") f.write(" end\n") else: start = 0 step += 3 f.write(" if ((TOPlvl=="+str(TOPlvl)+")&&(step=="+str(step)+"))\n") f.write(" begin\n") if (ZeroPadding2D): f.write(" matrix = "+str(layers[i].input_shape[1] - 1)+";\n") else: f.write(" matrix = "+str(layers[i].input_shape[1])+";\n") f.write(" memstartp = "+str(one)+";\n") f.write(" memstartw = 0;\n") if (GlobalAveragePooling2D): f.write(" memstartzap = "+str(two)+ "+" + str(j*int(128/num_conv)) + ";\n") else: f.write(" memstartzap = "+str(two)+";\n") f.write(" conv_en = 1;\n") f.write(" dense_en=0;\n") if (start_me == 0): f.write(" mem = "+str(mem)+";\n") f.write(" filt = "+str(filt)+";\n") else: f.write(" mem = "+str(filt)+";\n") f.write(" filt = "+str(mem)+";\n") f.write(" stride=" + str(layers[i].strides[0]) + ";\n") f.write(" onexone=" + str(onexone) + ";\n") if (layer == 'DepthwiseConv2D'): f.write(" depthwise=1;\n") if (GlobalAveragePooling2D == 0): onexone = 1 else: f.write(" depthwise=0;\n") if (GlobalAveragePooling2D == 0): onexone = 0 if (GlobalAveragePooling2D): f.write(" glob_average_en=1;\n") else: f.write(" glob_average_en=0;\n") f.write(" end\n") if (j == GlobalAveragePooling2D): one_t=one two_t=two two=one_t one=two_t TOPlvl += 1 start_me = 1 ZeroPadding2D=0 if 'ZeroPadding2D' in layer: ZeroPadding2D = 1 if 'Dense' in layer: f.write(" if ((TOPlvl==" + str(TOPlvl) + ")&&(step==" + str(step) + ")) \n") f.write(" begin\n") f.write(" nextstep=1;\n") f.write(" onexone=0;\n") f.write(" in_dense="+str(layers[i].input_shape[1])+";\n") f.write(" out_dense="+str(layers[i].output_shape[1])+";\n") f.write(" end\n") step += 2 f.write(" if ((TOPlvl=="+str(TOPlvl)+")&&(step=="+str(step)+"))\n") f.write(" begin\n") f.write(" memstartp= " + str(one) + ";\n") f.write(" memstartzap = " + str(two) + ";\n") f.write(" conv_en=0;\n") f.write(" dense_en=1;\n") f.write(" nozero_dense=1;\n") f.write(" depthwise=0;\n") f.write(" end\n") one_t=one two_t=two two=one_t one=two_t TOPlvl += 1 if (i == len(layers)-1): step += 1 f.write(" if ((TOPlvl=="+str(TOPlvl-1)+")&&(STOP_dense==0)&&(step=="+str(step)+"))\n") f.write(" begin\n") f.write(" memstartp = "+str(one)+";\n") f.write(" result_en = 1;\n") f.write(" end\n") f.write(" if ((depthwise)||(lvl==filt)||((onexone)&&(mem==((lvl+1)*8)-1))) bias=1; else bias=0;\n") f.write(" if ((STOP_conv)&&(conv_en==1)) conv_en=0;\n") f.write(" if (STOP_dense==1) begin dense_en=0; nextstep=1; end\n") f.write(" if ((STOP_res==1)&&(result_en==1))\n") f.write(" begin\n") f.write(" result_en=0;\n") f.write(" STOP=1;\n") f.write(" end\n") f.write("end\n") f.write("end\n") f.write("\n") f.write("always @(negedge STOP_conv or posedge GO)\n") f.write(" begin\n") f.write(" if (GO)\n") f.write(" begin\n") f.write(" lvl=0;\n") f.write(" slvl=0;\n") f.write(" TOPlvl_conv=1;\n") f.write(" num=0;\n") f.write(" end\n") f.write(" else\n") f.write(" begin\n") f.write(" if (lvl==(filt)||((lvl==filt>>"+ str(len(bin(num_conv))-3) +")&&(depthwise))||((lvl==((mem+1)>>3)-1)&&(onexone)))\n") f.write(" begin\n") f.write(" lvl=0;\n") f.write(" if ((num!=") if (num_conv<=4): f.write("4-num_conv") else: f.write("0") f.write(")&&(!depthwise)) num=num+1; else num=0;\n") f.write(" if ((num==0)||(depthwise))\n") f.write(" begin \n") f.write(" if ((depthwise)||((!onexone)&&(mem==("+str(num_conv)+"+(slvl*"+str(num_conv)+"))-1))||((onexone)&&(filt==("+str(num_conv)+"+(slvl*"+str(num_conv)+"))-1))) \n") f.write(" begin\n") f.write(" slvl=0; \n") f.write(" TOPlvl_conv=TOPlvl_conv+1'b1;\n") f.write(" end\n") f.write(" else slvl = slvl + 1'b1;\n") f.write(" end\n") f.write(" end\n") f.write(" else\n") f.write(" lvl=lvl+1;\n") f.write(" end\n") f.write(" end\n") f.write("\n") f.write("assign address_image_1 = address_image[") if (num_conv<3): f.write(str(bit_razmer_2-len(bin(num_conv))+3)) else: f.write(str(13)) f.write(":0]+1; \n") f.write("\n") f.write("assign memstartw_lvl=memstartw+((onexone?num*(((mem+1)>>3)-1)+lvl:(depthwise?lvl*num_conv:lvl))+(((!depthwise)&&(!onexone))?(slvl*(4*(filt+1))):(1'b0))+((!onexone)?(num*(filt+1)):num+slvl*((mem+1)") if (num_conv<=4): f.write(">>"+str(len(bin(8-num_conv))-3)) else: f.write("<<"+str(len(bin(num_conv-8))-3)) f.write(")));\n") f.write("assign memstartzap_num = memstartzap+((glob_average_en)?(num+slvl*1):0)+(((conv_en==1)&&(!glob_average_en))?(num*((matrix>>(stride-1))*(matrix>>(stride-1)))+slvl*((matrix>>(stride-1))*(matrix>>(stride-1)))") if (num_conv<=4): f.write("*(5-num_conv)") f.write("+((depthwise)?lvl*((matrix>>(stride-1))*(matrix>>(stride-1))):0)):0);\n") f.write("assign memstartp_lvl=memstartp+(onexone?((lvl") if (num_conv>4): f.write("[8:"+str(len(bin(num_conv))-6)+"]") f.write(")*matrix2") if (num_conv<=4): f.write("*(8>>2)") f.write("):(depthwise?(lvl*matrix2):((lvl>>num_conv-1)*matrix2))); \n") f.write("assign memstartb=slvl*"+str(num_conv)+"+num+(depthwise?lvl*num_conv:0)+1;\n") f.write("\n") f.write("assign re_p=GO?1'b1:((conv_en==1)?re_conv:((dense_en==1)?re_p_dense:((result_en==1)?re_p_res:0)));\n") f.write("assign re_w=(conv_en==1)?re_wb_conv:((dense_en==1)?re_w_dense:0);\n") f.write("assign re_bias_RAM=(conv_en==1)?re_wb_conv:0;\n") f.write("assign read_addressp=GO?address_image_1[") if (num_conv < 3): f.write(str(bit_razmer_2 - len(bin(num_conv)) + 3)) else: f.write(str(13)) f.write(":0]:((conv_en==1)?read_addressp_conv:((dense_en==1)?read_addressp_dense:((result_en==1)?read_addressp_res:0)));\n") f.write("assign we_p=GO?we_image:((conv_en==1)?we_conv:((dense_en==1)?we_dense:0));\n") f.write("assign dp=GO?") n = 0 for i in range(3): #ИСПРАВИТЬ НА ЗАВИСИМОСТЬ (картинка 3-х цветная) f.write("((address_image<128*128*" + str(i+1) + ")?") f.write("{") for j in range(num_conv): if (j==n): f.write("dp_image") elif ((j>i)|(j==num_conv-1)): f.write(str(sizeI+1)+"'d0") else: f.write("qp[SIZE_"+str(num_conv-j)+"-1:SIZE_"+str(num_conv-j-1)+"]") if (j+1!=num_conv): f.write(",") if (n max_weights_per_layer: max_weights_per_layer = max_weights_per_layer_1 elif 'Dense' in str(layer.__class__.__name__): w = layer.get_weights() total_dense_layers_number += 1 dense_inputs.append(layer.input_shape[1]) dense_outputs.append(layer.output_shape[1]) max_address_value += len(layer.get_weights()[0][0]) * len(w[0]) max_weights_per_layer_1 = int(len(w[0][0]) * len(w[0])/(conv_block_size_1*conv_block_size_2)) + 1 if max_weights_per_layer_1 > max_weights_per_layer: max_weights_per_layer = max_weights_per_layer_1 if i == len(model.layers) - 1: # Number of neurons on final classification layer. output_neurons_count = layer.output_shape[1] if 'ZeroPadding2D' in str(layer.__class__.__name__): ZeroPadding2D = 1 # Maximum size of image for neural net. Equal to 128. max_input_image_size = max(conv_inputs) # Number of steps in neural net. Step means any action like loading data, processing convolution layer. steps_count = 2 + (total_conv_layers_number*3) + (total_dense_layers_number*2) + 1 # Bit size of input data for dense layer in_dense_size = max(dense_inputs) # Bit size of output data for dense layer out_dense_size = max(dense_outputs) # Size of convolution block. conv_block_size = max(conv_blocks) # Maximum number of input feature maps for all convolution layers max_conv_input_size = max(conv_filt) # Maximum number of output feature maps for all convolution layers max_conv_output_size = max(conv_mem) max_address_value += input print("Make addressRAM file") addressRAM(output_directory, steps_count, max_address_value) print("Make border file") border(output_directory, max_input_image_size) print("Make conv_block file") conv_block(output_directory,max_input_image_size) print("Make conv_TOP file") conv_TOP(output_directory, max_input_image_size, max_conv_input_size, max_conv_output_size, num_conv, steps_count,image_bit_precision,weight_bit_precision+convW) print("Make dense file") dense(output_directory, in_dense_size, out_dense_size, num_conv, image_bit_precision, weight_bit_precision+convW) print("Make RAM file") RAM(output_directory, max_weights_per_layer, num_conv) print("Make RAMtoMEM file") RAMtoMEM(output_directory, max_address_value, steps_count, in_dense_size, conv_block_size, num_conv) print("Make result file") result(output_directory, output_neurons_count, num_conv) TOP(output_directory, image_bit_precision, weight_bit_precision+convW, bias_bit_precision+convB, max_input_image_size, max_address_value, output_neurons_count, max_weights_per_layer, total_conv_layers_number, max_conv_input_size, in_dense_size, out_dense_size, max_conv_output_size, model.layers, num_conv, steps_count) ================================================ FILE: r08_generate_weights_file_for_FPGA.py ================================================ # coding: utf-8 __author__ = 'Alex Kustov, IPPM RAS' def load_cache_file(f): file = open(f,'r') result_list = [] for i in file: if ((i[:2] != '//') & (i != '\n')): result_list.append(i) file.close() return result_list if __name__ == '__main__': nn_type = 'people' f_w = 'cache/{}/storage.v'.format(nn_type) f_b = 'cache/{}/storage_bias.v'.format(nn_type) f_r = 'cache/{}/weights.txt'.format(nn_type) weights = load_cache_file(f_w) bias = load_cache_file(f_b) file = open(f_r,'w') for i in range(len(weights)): for j in range(len(weights[i])): file.write(weights[i][j]) for i in range(3): file.write('storage[0] = 12\'b000000000000; // 0 0\n') for i in range(len(bias)): for j in range(len(bias[i])): file.write(bias[i][j]) file.close() ================================================ FILE: utils/data_uart_to_fpga.py ================================================ import serial from tqdm import tqdm WEIGHT_FILE_TO_USE = 'weights/weights_cars.txt' if __name__ == '__main__': ser = serial.Serial(port='COM4', baudrate=115200, bytesize=8, timeout=0) ser.write(bytes([255])) file = open(WEIGHT_FILE_TO_USE, 'r') k = 0 j = 0 l = 0 for i in file: k += 1 file.close() file = open(WEIGHT_FILE_TO_USE, 'r') for i in tqdm(range(k)): string_current = file.readline() if ((string_current.split(" ")[0] != "\n") & (string_current.split(" ")[0] != "//")): if string_current.split(" ")[2] == '': data_current = string_current.split(" ")[3][4:-1] minus = '0' else: data_current = string_current.split(" ")[2][5:-1] minus = '1' while len(data_current) != 21: data_current = "0" + data_current ser.write(bytes([int('00' + data_current[15] + data_current[16] + data_current[17] + data_current[18] + data_current[19] + data_current[20], 2)])) ser.write(bytes([int('00' + data_current[9] + data_current[10] + data_current[11] + data_current[12] + data_current[13] + data_current[14], 2)])) ser.write(bytes([int('00' + data_current[3] + data_current[4] + data_current[5] + data_current[6] + data_current[7] + data_current[8], 2)])) ser.write(bytes([int('0000' + minus + data_current[0] + data_current[1] + data_current[2], 2)])) l += 1 for i in range(3): ser.write(bytes([191])) for i in range(3): ser.write(bytes([0])) file.close() print("Counter numbers: " + str(l)) ================================================ FILE: verilog/CAMERA/camera_controller.v ================================================ module camera_contoller( output CMOS_SCLK, //cmos i2c clock inout CMOS_SDAT, //cmos i2c data input CMOS_VSYNC, //cmos vsync input CMOS_HREF, //cmos hsync refrence input CMOS_PCLK, //cmos pxiel clock output CMOS_XCLK, //cmos externl clock input [7:0] CMOS_DB, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos pwer down ); wire clk_camera; wire clk_vga; //vga clock wire clk_ref; //sdram ctrl clock wire clk_refout; //sdram clock output wire clk_25M; wire sys_rst_n; //global reset wire sys_we; //system data write enable wire [15:0] sys_data_in; //system data input wire sdram_init_done; //sdram init done wire initial_en; wire locked; //pll pll_inst(clk, tft_clk, clk_10khz, clk_camera, locked); pll_test pll_test ( .refclk (clk), // refclk.clk .rst (1'b0), // reset.reset .outclk_0 (tft_clk), // outclk0.clk .outclk_1 (), // outclk1.clk .outclk_2 (clk_camera), // outclk2.clk .locked (locked) // locked.export ); reg [9:0] delay_cnt; reg delay_done; always @(posedge tft_clk or negedge rst_n) begin if(!rst_n) begin delay_cnt <= 0; delay_done <= 1'b0; end else begin if (delay_cnt== 1000) delay_done <= 1'b1; else delay_cnt <= delay_cnt +1'b1; end end assign sys_rst_n=delay_done; //上电延迟部分 power_on_delay power_on_delay_inst( .clk_50M (clk_camera), .reset_n (sys_rst_n), .camera_rstn (cmos_rst_n), .camera_pwnd (cmos_pwdn), .initial_en (initial_en) ); //Camera初始化部分,Camera LED FLASH control reg_config reg_config_inst( .clk_25M (clk_camera), .camera_rstn (cmos_rst_n), .initial_en (initial_en), .i2c_sclk (CMOS_SCLK), .i2c_sdat (CMOS_SDAT), .reg_conf_done (Config_Done), .strobe_flash (), .reg_index (), .clock_20k (), .key1 (KEY1) ); //----------------------------------------------- wire frame_valid; //data valid, or address restart wire [7:0] cmos_fps_data; //cmos frame rate CMOS_Capture u_CMOS_Capture ( //Global Clock .iCLK (clk_camera), //24MHz .iRST_N (sys_rst_n), //global reset //I2C Initilize Done .Init_Done (Config_Done /*& sdram_init_done*/), //Init Done //Sensor Interface .CMOS_XCLK (CMOS_XCLK), //cmos .CMOS_PCLK (CMOS_PCLK), //24MHz .CMOS_iDATA (CMOS_DB), //CMOS Data .CMOS_VSYNC (CMOS_VSYNC), //L: Vaild .CMOS_HREF (CMOS_HREF), //H: Vaild //Ouput Sensor Data .CMOS_oCLK (sys_we), //Data PCLK .CMOS_oDATA (sys_data_in), //16Bits RGB .CMOS_VALID (frame_valid), //Data Enable .CMOS_FPS_DATA ({LED[7],LED[6],LED[5],LED[4],LED[3],LED[2],LED[1],LED[0]})//(cmos_fps_data) //cmos frame rate ); endmodule ================================================ FILE: verilog/CAMERA/cmos_i2c_ov5640/CMOS_Capture.v ================================================ /*------------------------------------------------------------------------- Description : sdram test with uart interface. Modification History : Data By Version Change Description =========================================================================== --------------------------------------------------------------------------*/ `timescale 1ns/1ns module CMOS_Capture ( //Global Clock input iCLK, //24MHz input iRST_N, //I2C Initilize Done input Init_Done, //Init Done //Sensor Interface output CMOS_XCLK, //24MHz input CMOS_PCLK, //24MHz input [7:0] CMOS_iDATA, //CMOS Data input CMOS_VSYNC, //L: Vaild input CMOS_HREF, //H: Vaild //Ouput Sensor Data output reg CMOS_oCLK, //1/2 PCLK output reg [15:0] CMOS_oDATA, //16Bits RGB output reg CMOS_VALID, //Data Enable output reg [7:0] CMOS_FPS_DATA //cmos fps ); assign CMOS_XCLK = iCLK; //24MHz XCLK //----------------------------------------------------- //ͬ//Sensor HS & VS Vaild Capture /************************************************** ________ ________ VS |_________________________________| HS _______ _______ _____________| |__...___| |____________ **************************************************/ /* //---------------------------------------------- reg mCMOS_HREF; //ͬߵƽЧ always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) mCMOS_HREF <= 0; else mCMOS_HREF <= CMOS_HREF; end wire CMOS_HREF_over = ({mCMOS_HREF,CMOS_HREF} == 2'b10) ? 1'b1 : 1'b0; //HREF ½ؽ */ //---------------------------------------------- reg mCMOS_VSYNC; always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) mCMOS_VSYNC <= 1; else mCMOS_VSYNC <= CMOS_VSYNC; //ͬ͵ƽЧ end wire CMOS_VSYNC_over = ({mCMOS_VSYNC,CMOS_VSYNC} == 2'b01) ? 1'b1 : 1'b0; //VSYNCؽ /* //-------------------------------------------- //Counter the HS & VS Pixel localparam H_DISP = 12'd640; localparam V_DISP = 12'd480; reg [11:0] X_Cont; //640 reg [11:0] Y_Cont; //480 always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) X_Cont <= 0; else if(~CMOS_VSYNC & CMOS_HREF) //źЧ X_Cont <= (byte_state == 1'b1) ? X_Cont + 1'b1 : X_Cont; else X_Cont <= 0; end always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) Y_Cont <= 0; else if(CMOS_VSYNC == 1'b0) begin if(CMOS_HREF_over == 1'b1) //HREF½ һн Y_Cont <= Y_Cont + 1'b1; end else Y_Cont <= 0; end */ //----------------------------------------------------- //Change the sensor data from 8 bits to 16 bits. reg byte_state; //byte state count reg [7:0] Pre_CMOS_iDATA; always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) begin byte_state <= 0; Pre_CMOS_iDATA <= 8'd0; CMOS_oDATA <= 16'd0; end else begin if(~CMOS_VSYNC & CMOS_HREF) //гЧ{first_byte, second_byte} begin byte_state <= byte_state + 1'b1; //RGB565 = {first_byte, second_byte} case(byte_state) 1'b0 : Pre_CMOS_iDATA[7:0] <= CMOS_iDATA; 1'b1 : CMOS_oDATA[15:0] <= {Pre_CMOS_iDATA[7:0], CMOS_iDATA[7:0]}; endcase end else begin byte_state <= 0; Pre_CMOS_iDATA <= 8'd0; CMOS_oDATA <= CMOS_oDATA; end end end //-------------------------------------------- //Wait for Sensor output Data valid 10 Franme reg [3:0] Frame_Cont; reg Frame_valid; always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) begin Frame_Cont <= 0; Frame_valid <= 0; end else if(Init_Done) //CMOS I2Cʼ begin if(CMOS_VSYNC_over == 1'b1) //VSأ1֡д begin if(Frame_Cont < 12) begin Frame_Cont <= Frame_Cont + 1'b1; Frame_valid <= 1'b0; end else begin Frame_Cont <= Frame_Cont; Frame_valid <= 1'b1; //Ч end end end end //----------------------------------------------------- //CMOS_DATAͬʹʱ always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) CMOS_oCLK <= 0; else if(Frame_valid == 1'b1 && byte_state)//(X_Cont >= 12'd1 && X_Cont <= H_DISP)) CMOS_oCLK <= ~CMOS_oCLK; else CMOS_oCLK <= 0; end //---------------------------------------------------- //ЧCMOS_VALID always@(posedge CMOS_PCLK or negedge iRST_N) begin if(!iRST_N) CMOS_VALID <= 0; else if(Frame_valid == 1'b1) CMOS_VALID <= ~CMOS_VSYNC; else CMOS_VALID <= 0; end /************************************************************ Caculate Frame Rate per second *************************************************************/ //----------------------------------------------------- // 2s ʱ reg [25:0] delay_cnt; //25_000000 * 2 always@(posedge iCLK or negedge iRST_N) begin if(!iRST_N) delay_cnt <= 0; else if(Frame_valid) begin if(delay_cnt < 26'd50_000000) delay_cnt <= delay_cnt + 1'b1; else delay_cnt <= 0; end else delay_cnt <= 0; end wire delay_2s = (delay_cnt == 26'd50_000000) ? 1'b1 : 1'b0; //------------------------------------------- //֡ʲ reg fps_state; reg [7:0] fps_data; always@(posedge iCLK or negedge iRST_N) begin if(!iRST_N) begin fps_data <= 0; fps_state <= 0; CMOS_FPS_DATA <= 0; end else if(Frame_valid) begin case(fps_state) 0: begin CMOS_FPS_DATA <= CMOS_FPS_DATA; if(delay_2s == 0) begin fps_state <= 0; if(CMOS_VSYNC_over == 1'b1) //VSأ1֡д fps_data <= fps_data + 1'b1; end else fps_state <= 1; end 1: begin fps_state <= 0; fps_data <= 0; CMOS_FPS_DATA <= fps_data >>1; end endcase end else begin fps_data <= 0; fps_state <= 0; CMOS_FPS_DATA <= 0; end end endmodule ================================================ FILE: verilog/CAMERA/cmos_i2c_ov5640/i2c_com.v ================================================ //sclksdinݴʱ루i2cдƴ룩 module i2c_com(clock_i2c, //i2cƽӿڴʱӣ0-400khz˴Ϊ20khz camera_rstn, ack, //Ӧź i2c_data, //sdinӿڴ32λ start, //ʼ־ tr_end, //־ i2c_sclk, //FPGAcamera iicʱӽӿ i2c_sdat); //FPGAcamera iicݽӿ input [31:0]i2c_data; input camera_rstn; input clock_i2c; output ack; input start; output tr_end; output i2c_sclk; inout i2c_sdat; reg [5:0] cyc_count; reg reg_sdat; reg sclk; reg ack1,ack2,ack3; reg tr_end; wire i2c_sclk; wire i2c_sdat; wire ack; assign ack=ack1|ack2|ack3; assign i2c_sclk=sclk|(((cyc_count>=4)&(cyc_count<=39))?~clock_i2c:0); assign i2c_sdat=reg_sdat?1'bz:0; always@(posedge clock_i2c or negedge camera_rstn) begin if(!camera_rstn) cyc_count<=6'b111111; else begin if(start==0) cyc_count<=0; else if(cyc_count<6'b111111) cyc_count<=cyc_count+1; end end always@(posedge clock_i2c or negedge camera_rstn) begin if(!camera_rstn) begin tr_end<=0; ack1<=1; ack2<=1; ack3<=1; sclk<=1; reg_sdat<=1; end else case(cyc_count) 0:begin ack1<=1;ack2<=1;ack3<=1;tr_end<=0;sclk<=1;reg_sdat<=1;end 1:reg_sdat<=0; //ʼ 2:sclk<=0; 3:reg_sdat<=i2c_data[31]; 4:reg_sdat<=i2c_data[30]; 5:reg_sdat<=i2c_data[29]; 6:reg_sdat<=i2c_data[28]; 7:reg_sdat<=i2c_data[27]; 8:reg_sdat<=i2c_data[26]; 9:reg_sdat<=i2c_data[25]; 10:reg_sdat<=i2c_data[24]; 11:reg_sdat<=1; //Ӧź 12:begin reg_sdat<=i2c_data[23];ack1<=i2c_sdat;end 13:reg_sdat<=i2c_data[22]; 14:reg_sdat<=i2c_data[21]; 15:reg_sdat<=i2c_data[20]; 16:reg_sdat<=i2c_data[19]; 17:reg_sdat<=i2c_data[18]; 18:reg_sdat<=i2c_data[17]; 19:reg_sdat<=i2c_data[16]; 20:reg_sdat<=1; //Ӧź 21:begin reg_sdat<=i2c_data[15];ack1<=i2c_sdat;end 22:reg_sdat<=i2c_data[14]; 23:reg_sdat<=i2c_data[13]; 24:reg_sdat<=i2c_data[12]; 25:reg_sdat<=i2c_data[11]; 26:reg_sdat<=i2c_data[10]; 27:reg_sdat<=i2c_data[9]; 28:reg_sdat<=i2c_data[8]; 29:reg_sdat<=1; //Ӧź 30:begin reg_sdat<=i2c_data[7];ack2<=i2c_sdat;end 31:reg_sdat<=i2c_data[6]; 32:reg_sdat<=i2c_data[5]; 33:reg_sdat<=i2c_data[4]; 34:reg_sdat<=i2c_data[3]; 35:reg_sdat<=i2c_data[2]; 36:reg_sdat<=i2c_data[1]; 37:reg_sdat<=i2c_data[0]; 38:reg_sdat<=1; //Ӧź 39:begin ack3<=i2c_sdat;sclk<=0;reg_sdat<=0;end 40:sclk<=1; 41:begin reg_sdat<=1;tr_end<=1;end endcase end endmodule ================================================ FILE: verilog/CAMERA/cmos_i2c_ov5640/ov5640_cfg.v ================================================ module ov5640_cfg( ); endmodule ================================================ FILE: verilog/CAMERA/cmos_i2c_ov5640/power_on_delay.v ================================================ //camera power on timing requirement module power_on_delay(clk_50M,reset_n,camera_rstn,camera_pwnd,initial_en); input clk_50M; input reset_n; output camera_rstn; output camera_pwnd; output initial_en; reg [18:0]cnt1; reg [15:0]cnt2; reg [19:0]cnt3; reg initial_en; reg camera_rstn_reg; reg camera_pwnd_reg; assign camera_rstn=camera_rstn_reg; assign camera_pwnd=camera_pwnd_reg; //5ms, delay from sensor power up stable to Pwdn pull down always@(posedge clk_50M) begin if(reset_n==1'b0) begin cnt1<=0; camera_pwnd_reg<=1'b1; end else if(cnt1<18'h40000) begin cnt1<=cnt1+1'b1; camera_pwnd_reg<=1'b1; end else camera_pwnd_reg<=1'b0; end //1.3ms, delay from pwdn low to resetb pull up always@(posedge clk_50M) begin if(camera_pwnd_reg==1) begin cnt2<=0; camera_rstn_reg<=1'b0; end else if(cnt2<16'hffff) begin cnt2<=cnt2+1'b1; camera_rstn_reg<=1'b0; end else camera_rstn_reg<=1'b1; end //21ms, delay from resetb pul high to SCCB initialization always@(posedge clk_50M) begin if(camera_rstn_reg==0) begin cnt3<=0; initial_en<=1'b0; end else if(cnt3<20'hfffff) begin cnt3<=cnt3+1'b1; initial_en<=1'b0; end else initial_en<=1'b1; end endmodule ================================================ FILE: verilog/CAMERA/cmos_i2c_ov5640/reg_config.v ================================================ //camera�мĴ��������ó��� module reg_config( input clk_25M, input camera_rstn, input initial_en, output reg strobe_flash, output reg_conf_done, output i2c_sclk, inout i2c_sdat, output reg clock_20k, output reg [8:0]reg_index, input key1 ); reg [15:0]clock_20k_cnt; reg [1:0]config_step; reg [31:0]i2c_data; reg [23:0]reg_data; reg start; reg reg_conf_done_reg; reg [15:0] on_counter; reg [15:0] off_counter; reg key_on, key_off; i2c_com u1(.clock_i2c(clock_20k), .camera_rstn(camera_rstn), .ack(ack), .i2c_data(i2c_data), .start(start), .tr_end(tr_end), .i2c_sclk(i2c_sclk), .i2c_sdat(i2c_sdat)); assign reg_conf_done=reg_conf_done_reg; //����i2c����ʱ��-20khz always@(posedge clk_25M or negedge camera_rstn) begin if(!camera_rstn) begin clock_20k<=0; clock_20k_cnt<=0; end else if(clock_20k_cnt<1249) clock_20k_cnt<=clock_20k_cnt+1'b1; else begin clock_20k<=!clock_20k; clock_20k_cnt<=0; end end //��ť�������� always @(posedge clock_20k or negedge camera_rstn) if (!camera_rstn) begin on_counter<=0; off_counter<=0; key_on<=1'b0; key_off<=1'b0; end else begin if (key1==1'b1) //������ťû�а��£��Ĵ���Ϊ0 on_counter<=0; else if ((key1==1'b0)& (on_counter<=16'h00c8)) //������ť���²�����ʱ������10ms,���� on_counter<=on_counter+1'b1; if (on_counter==16'h00c7) //һ�ΰ�ť������Ч key_on<=1'b1; else key_on<=1'b0; if (key1==1'b0) //������ťû���ͷţ��Ĵ���Ϊ0 off_counter<=0; else if ((key1==1'b1)& (off_counter<=16'h00c8)) //������ť�ͷŲ�ʱ������10ms,���� off_counter<=off_counter+1'b1; if (off_counter==16'h00c7) //һ�ΰ�ť�ɿ���Ч key_off<=1'b1; else key_off<=1'b0; end ////iic�Ĵ������ù��̿��� always@(posedge clock_20k or negedge camera_rstn) begin if(!camera_rstn) begin config_step<=0; start<=0; reg_index<=0; reg_conf_done_reg<=0; strobe_flash<=1'b0; end else begin if(reg_conf_done_reg==1'b0) begin //����camera��ʼ��δ���� // if(reg_index<251) begin if(reg_index<302) begin case(config_step) 0:begin i2c_data<={8'h78,reg_data}; //IIC Device address is 0x78 start<=1; config_step<=1; end 1:begin if(tr_end) begin //IIC���ͽ��� start<=0; config_step<=2; end end 2:begin reg_index<=reg_index+1'b1; config_step<=0; end endcase end else reg_conf_done_reg<=1'b1; end else begin //����camera��ʼ�������� case(config_step) 0:begin if(key_on==1'b1) begin //��������,���üĴ���ʹ��������� config_step<=1; reg_index<=302; //�ӵ�302��ʼд�Ĵ��� strobe_flash<=1'b1; end else if (key_off==1'b1) begin //�����ɿ�,���üĴ���ʹ��������� config_step<=1; reg_index<=303; //�ӵ�303��ʼд�Ĵ��� strobe_flash<=1'b0; end end 1:begin i2c_data<={8'h78,reg_data}; //IIC Device address is 0x78 start<=1; config_step<=2; end 2:begin if(tr_end) begin //IIC���ͽ��� start<=0; config_step<=3; end end 3:begin config_step<=0; reg_index<=300; end endcase end end end ////iic��Ҫ���õļĴ���ֵ always@(reg_index) begin case(reg_index) 0:reg_data<=24'h310311;// system clock from pad, bit[1] 1:reg_data<=24'h300882;// software reset, bit[7]// delay 5ms 2:reg_data<=24'h300842;// software power down, bit[6] 3:reg_data<=24'h310303;// system clock from PLL, bit[1] 4:reg_data<=24'h3017ff;// FREX, Vsync, HREF, PCLK, D[9:6] output enable 5:reg_data<=24'h3018ff;// D[5:0], GPIO[1:0] output enable 6:reg_data<=24'h30341A;// MIPI 10-bit 7:reg_data<=24'h303713;// PLL root divider, bit[4], PLL pre-divider, bit[3:0] 8:reg_data<=24'h310801;// PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] // SCLK root divider, bit[1:0] 9:reg_data<=24'h363036; 10:reg_data<=24'h36310e; 11:reg_data<=24'h3632e2; 12:reg_data<=24'h363312; 13:reg_data<=24'h3621e0; 14:reg_data<=24'h3704a0; 15:reg_data<=24'h37035a; 16:reg_data<=24'h371578; 17:reg_data<=24'h371701; 18:reg_data<=24'h370b60; 19:reg_data<=24'h37051a; 20:reg_data<=24'h390502; 21:reg_data<=24'h390610; 22:reg_data<=24'h39010a; 23:reg_data<=24'h373112; 24:reg_data<=24'h360008;// VCM control 25:reg_data<=24'h360133;// VCM control 26:reg_data<=24'h302d60;// system control 27:reg_data<=24'h362052; 28:reg_data<=24'h371b20; 29:reg_data<=24'h471c50; 30:reg_data<=24'h3a1343;// pre-gain = 1.047x 31:reg_data<=24'h3a1800;// gain ceiling 32:reg_data<=24'h3a19f8;// gain ceiling = 15.5x 33:reg_data<=24'h363513; 34:reg_data<=24'h363603; 35:reg_data<=24'h363440; 36:reg_data<=24'h362201; // 50/60Hz detection 50/60Hz 灯光条纹过滤 37:reg_data<=24'h3c0134;// Band auto, bit[7] 38:reg_data<=24'h3c0428;// threshold low sum 39:reg_data<=24'h3c0598;// threshold high sum 40:reg_data<=24'h3c0600;// light meter 1 threshold[15:8] 41:reg_data<=24'h3c0708;// light meter 1 threshold[7:0] 42:reg_data<=24'h3c0800;// light meter 2 threshold[15:8] 43:reg_data<=24'h3c091c;// light meter 2 threshold[7:0] 44:reg_data<=24'h3c0a9c;// sample number[15:8] 45:reg_data<=24'h3c0b40;// sample number[7:0] 46:reg_data<=24'h381000;// Timing Hoffset[11:8] 47:reg_data<=24'h381100;//10;// Timing Hoffset[7:0] 48:reg_data<=24'h381200;// Timing Voffset[10:8] 49:reg_data<=24'h370864; 50:reg_data<=24'h400102;// BLC start from line 2 51:reg_data<=24'h40051a;// BLC always update 52:reg_data<=24'h300000;// enable blocks 53:reg_data<=24'h3004ff;// enable clocks 54:reg_data<=24'h300e58;// MIPI power down, DVP enable 55:reg_data<=24'h302e00; 56:reg_data<=24'h430060;// RGB565 57:reg_data<=24'h501f01;// ISP RGB 58:reg_data<=24'h440e00; 59:reg_data<=24'h5000a7; // Lenc on, raw gamma on, BPC on, WPC on, CIP on // AEC target 自动曝光控制 60:reg_data<=24'h3a0f30;// stable range in high 61:reg_data<=24'h3a1028;// stable range in low 62:reg_data<=24'h3a1b30;// stable range out high 63:reg_data<=24'h3a1e26;// stable range out low 64:reg_data<=24'h3a1160;// fast zone high 65:reg_data<=24'h3a1f14;// fast zone low// Lens correction for ? 镜头补偿 66:reg_data<=24'h580023; 67:reg_data<=24'h580114; 68:reg_data<=24'h58020f; 69:reg_data<=24'h58030f; 70:reg_data<=24'h580412; 71:reg_data<=24'h580526; 72:reg_data<=24'h58060c; 73:reg_data<=24'h580708; 74:reg_data<=24'h580805; 75:reg_data<=24'h580905; 76:reg_data<=24'h580a08; 77:reg_data<=24'h580b0d; 78:reg_data<=24'h580c08; 79:reg_data<=24'h580d03; 80:reg_data<=24'h580e00; 81:reg_data<=24'h580f00; 82:reg_data<=24'h581003; 83:reg_data<=24'h581109; 84:reg_data<=24'h581207; 85:reg_data<=24'h581303; 86:reg_data<=24'h581400; 87:reg_data<=24'h581501; 88:reg_data<=24'h581603; 89:reg_data<=24'h581708; 90:reg_data<=24'h58180d; 91:reg_data<=24'h581908; 92:reg_data<=24'h581a05; 93:reg_data<=24'h581b06; 94:reg_data<=24'h581c08; 95:reg_data<=24'h581d0e; 96:reg_data<=24'h581e29; 97:reg_data<=24'h581f17; 98:reg_data<=24'h582011; 99:reg_data<=24'h582111; 100:reg_data<=24'h582215; 101:reg_data<=24'h582328; 102:reg_data<=24'h582446; 103:reg_data<=24'h582526; 104:reg_data<=24'h582608; 105:reg_data<=24'h582726; 106:reg_data<=24'h582864; 107:reg_data<=24'h582926; 108:reg_data<=24'h582a24; 109:reg_data<=24'h582b22; 110:reg_data<=24'h582c24; 111:reg_data<=24'h582d24; 112:reg_data<=24'h582e06; 113:reg_data<=24'h582f22; 114:reg_data<=24'h583040; 115:reg_data<=24'h583142; 116:reg_data<=24'h583224; 117:reg_data<=24'h583326; 118:reg_data<=24'h583424; 119:reg_data<=24'h583522; 120:reg_data<=24'h583622; 121:reg_data<=24'h583726; 122:reg_data<=24'h583844; 123:reg_data<=24'h583924; 124:reg_data<=24'h583a26; 125:reg_data<=24'h583b28; 126:reg_data<=24'h583c42; 127:reg_data<=24'h583dce;// lenc BR offset // AWB 自动白平衡 128:reg_data<=24'h5180ff;// AWB B block 129:reg_data<=24'h5181f2;// AWB control 130:reg_data<=24'h518200;// [7:4] max local counter, [3:0] max fast counter 131:reg_data<=24'h518314;// AWB advanced 132:reg_data<=24'h518425; 133:reg_data<=24'h518524; 134:reg_data<=24'h518609; 135:reg_data<=24'h518709; 136:reg_data<=24'h518809; 137:reg_data<=24'h518975; 138:reg_data<=24'h518a54; 139:reg_data<=24'h518be0; 140:reg_data<=24'h518cb2; 141:reg_data<=24'h518d42; 142:reg_data<=24'h518e3d; 143:reg_data<=24'h518f56; 144:reg_data<=24'h519046; 145:reg_data<=24'h5191f8;// AWB top limit 146:reg_data<=24'h519204;// AWB bottom limit 147:reg_data<=24'h519370;// red limit 148:reg_data<=24'h5194f0;// green limit 149:reg_data<=24'h5195f0;// blue limit 150:reg_data<=24'h519603;// AWB control 151:reg_data<=24'h519701;// local limit 152:reg_data<=24'h519804; 153:reg_data<=24'h519912; 154:reg_data<=24'h519a04; 155:reg_data<=24'h519b00; 156:reg_data<=24'h519c06; 157:reg_data<=24'h519d82; 158:reg_data<=24'h519e38;// AWB control // Gamma 伽玛曲线 159:reg_data<=24'h548001;// Gamma bias plus on, bit[0] 160:reg_data<=24'h548108; 161:reg_data<=24'h548214; 162:reg_data<=24'h548328; 163:reg_data<=24'h548451; 164:reg_data<=24'h548565; 165:reg_data<=24'h548671; 166:reg_data<=24'h54877d; 167:reg_data<=24'h548887; 168:reg_data<=24'h548991; 169:reg_data<=24'h548a9a; 170:reg_data<=24'h548baa; 171:reg_data<=24'h548cb8; 172:reg_data<=24'h548dcd; 173:reg_data<=24'h548edd; 174:reg_data<=24'h548fea; 175:reg_data<=24'h54901d;// color matrix 色彩矩阵 176:reg_data<=24'h53811e;// CMX1 for Y 177:reg_data<=24'h53825b;// CMX2 for Y 178:reg_data<=24'h538308;// CMX3 for Y 179:reg_data<=24'h53840a;// CMX4 for U 180:reg_data<=24'h53857e;// CMX5 for U 181:reg_data<=24'h538688;// CMX6 for U 182:reg_data<=24'h53877c;// CMX7 for V 183:reg_data<=24'h53886c;// CMX8 for V 184:reg_data<=24'h538910;// CMX9 for V 185:reg_data<=24'h538a01;// sign[9] 186:reg_data<=24'h538b98; // sign[8:1] // UV adjust UV色彩饱和度调整 187:reg_data<=24'h558006;// saturation on, bit[1] 188:reg_data<=24'h558340; 189:reg_data<=24'h558410; 190:reg_data<=24'h558910; 191:reg_data<=24'h558a00; 192:reg_data<=24'h558bf8; 193:reg_data<=24'h501d40;// enable manual offset of contrast// CIP 锐化和降噪 194:reg_data<=24'h530008;// CIP sharpen MT threshold 1 195:reg_data<=24'h530130;// CIP sharpen MT threshold 2 196:reg_data<=24'h530210;// CIP sharpen MT offset 1 197:reg_data<=24'h530300;// CIP sharpen MT offset 2 198:reg_data<=24'h530408;// CIP DNS threshold 1 199:reg_data<=24'h530530;// CIP DNS threshold 2 200:reg_data<=24'h530608;// CIP DNS offset 1 201:reg_data<=24'h530716;// CIP DNS offset 2 202:reg_data<=24'h530908;// CIP sharpen TH threshold 1 203:reg_data<=24'h530a30;// CIP sharpen TH threshold 2 204:reg_data<=24'h530b04;// CIP sharpen TH offset 1 205:reg_data<=24'h530c06;// CIP sharpen TH offset 2 206:reg_data<=24'h502500; 207:reg_data<=24'h300802; // wake up from standby, bit[6] 208:reg_data<=24'h303511;// PLL //640x480 30帧/秒, night mode 5fps, input clock =24Mhz, PCLK =56Mhz 209:reg_data<=24'h303646;// PLL 210:reg_data<=24'h3c0708;// light meter 1 threshold [7:0] 211:reg_data<=24'h382041;// Sensor flip off, ISP flip on 212:reg_data<=24'h382107;// Sensor mirror on, ISP mirror on, H binning on 213:reg_data<=24'h381431;// X INC 214:reg_data<=24'h381531;// Y INC 215:reg_data<=24'h380000;// HS: X address start high byte 216:reg_data<=24'h380100;// HS: X address start low byte 217:reg_data<=24'h380200;// VS: Y address start high byte 218:reg_data<=24'h380304;// VS: Y address start low byte 219:reg_data<=24'h38040a;// HW (HE) 220:reg_data<=24'h38053f;// HW (HE) 221:reg_data<=24'h380607;// VH (VE) 222:reg_data<=24'h38079b;// VH (VE) 223:reg_data<=24'h380803;// DVPHO 224:reg_data<=24'h380920;// DVPHO 225:reg_data<=24'h380a02;// DVPVO 226:reg_data<=24'h380b58;// DVPVO 227:reg_data<=24'h380c07;// HTS //Total horizontal size 800 228:reg_data<=24'h380d68;// HTS 229:reg_data<=24'h380e03;// VTS //total vertical size 500 230:reg_data<=24'h380fd8;// VTS 231:reg_data<=24'h381306;// Timing Voffset 232:reg_data<=24'h361800; 233:reg_data<=24'h361229; 234:reg_data<=24'h370952; 235:reg_data<=24'h370c03; 236:reg_data<=24'h3a0217;// 60Hz max exposure, night mode 5fps 237:reg_data<=24'h3a0310;// 60Hz max exposure // banding filters are calculated automatically in camera driver 238:reg_data<=24'h3a1417;// 50Hz max exposure, night mode 5fps 239:reg_data<=24'h3a1510;// 50Hz max exposure //reg_data<=24'h3a0801;// B50 step //reg_data<=24'h3a0927;// B50 step //reg_data<=24'h3a0a00;// B60 step //reg_data<=24'h3a0bf6;// B60 step //reg_data<=24'h3a0e03;// 50Hz max band //reg_data<=24'h3a0d04;// 60Hz max band 240:reg_data<=24'h400402;// BLC 2 lines 241:reg_data<=24'h30021c;// reset JFIFO, SFIFO, JPEG 242:reg_data<=24'h3006c3;// disable clock of JPEG2x, JPEG 243:reg_data<=24'h471303;// JPEG mode 3 244:reg_data<=24'h440704;// Quantization scale 245:reg_data<=24'h460b35; 246:reg_data<=24'h460c22; 247:reg_data<=24'h483722; // DVP CLK divider 248:reg_data<=24'h382402; // DVP CLK divider 249:reg_data<=24'h5001a3; // SDE on, scale on, UV average off, color matrix on, AWB on //set OV5640 to video mode 720p 250:reg_data<=24'h350300; // AEC/AGC on 251:reg_data<=24'h303521;// PLL input clock =24Mhz, PCLK =84Mhz 252:reg_data<=24'h303669;// PLL 253:reg_data<=24'h3c0707; // lightmeter 1 threshold[7:0] 254:reg_data<=24'h382047; // flip 255:reg_data<=24'h382100;//07; // mirror 256:reg_data<=24'h381431; // timing X inc 257:reg_data<=24'h381531; // timing Y inc 258:reg_data<=24'h380000; // HS 259:reg_data<=24'h380100; // HS 260:reg_data<=24'h380200; // VS 261:reg_data<=24'h380300;//fa; // VS 262:reg_data<=24'h38040a; // HW (HE) 263:reg_data<=24'h38053f; // HW (HE) 264:reg_data<=24'h380607;//06; // VH (VE) 265:reg_data<=24'h38079f;//a9; // VH (VE) 266:reg_data<=24'h380801; //320 267:reg_data<=24'h380940; 268:reg_data<=24'h380a00; //240 269:reg_data<=24'h380bf0; 270:reg_data<=24'h380c0c;//07; // HTS 271:reg_data<=24'h380d80;//64; // HTS 272:reg_data<=24'h380e07;//02; // VTS 273:reg_data<=24'h380fd0;//e4; // VTS 274:reg_data<=24'h381300;//04; // timing V offset 275:reg_data<=24'h361800; 276:reg_data<=24'h361229; 277:reg_data<=24'h370952; 278:reg_data<=24'h370c03; 279:reg_data<=24'h3a0202; // 60Hz max exposure 280:reg_data<=24'h3a03e0; // 60Hz max exposure 281:reg_data<=24'h3a0800; // B50 step 282:reg_data<=24'h3a096f; // B50 step 283:reg_data<=24'h3a0a00; // B60 step 284:reg_data<=24'h3a0b5c; // B60 step 285:reg_data<=24'h3a0e06; // 50Hz max band 286:reg_data<=24'h3a0d08; // 60Hz max band 287:reg_data<=24'h3a1402; // 50Hz max exposure 288:reg_data<=24'h3a15e0; // 50Hz max exposure 289:reg_data<=24'h400402; // BLC line number 290:reg_data<=24'h30021c; // reset JFIFO, SFIFO, JPG 291:reg_data<=24'h3006c3; // disable clock of JPEG2x, JPEG 292:reg_data<=24'h471303; // JPEG mode 3 293:reg_data<=24'h440704; // Quantization sacle 294:reg_data<=24'h460b37; 295:reg_data<=24'h460c20; 296:reg_data<=24'h483716; // MIPI global timing 297:reg_data<=24'h382404; // PCLK manual divider 298:reg_data<=24'h5001a3;//83; // SDE on, CMX on, AWB on 299:reg_data<=24'h350300; // AEC/AGC on 300:reg_data<=24'h301602; //Strobe output enable 301:reg_data<=24'h3b070a; //FREX strobe mode1 //strobe flash and frame exposure // 302:reg_data<=24'h3b0083; //STROBE CTRL: strobe request ON, Strobe mode: LED3 // 303:reg_data<=24'h3b0000; //STROBE CTRL: strobe request OFF 302:reg_data<=24'h503d80; //reg_data<=24'h503d80; test pattern selection control, 80:color bar,00: test disable 303:reg_data<=24'h474101; //reg_data<=24'h47401; test pattern enable, Test pattern 8-bit default:reg_data<=24'h000000; endcase end endmodule ================================================ FILE: verilog/CAMERA/sdram_ov5640_vga.v ================================================ /*------------------------------------------------------------------------- Filename : sdram_ov5640_vga.v Description : sdram vga controller with ov5640 display 1024 * 768. Modification History : Data By Version Change Description =========================================================================== 15/02/1 --------------------------------------------------------------------------*/ `timescale 1ns / 1ps module ov5640 ( //global clock 50MHz input CLOCK, input rst_n, //global reset /*//sdram control output S_CLK, //sdram clock output S_CKE, //sdram clock enable output S_NCS, //sdram chip select output S_NWE, //sdram write enable output S_NCAS, //sdram column address strobe output S_NRAS, //sdram row address strobe output [1 :0] S_DQM, //sdram data enable output [1 :0] S_BA, //sdram bank address output [12:0] S_A, //sdram address inout [15:0] S_DB, //sdram data //VGA port output VGA_HSYNC, //horizontal sync output VGA_VSYNC, //vertical sync output [15:0] lcd_rgb, //VGA data*/ //cmos interface output CMOS_SCLK, //cmos i2c clock inout CMOS_SDAT, //cmos i2c data input CMOS_VSYNC, //cmos vsync input CMOS_HREF, //cmos hsync refrence input CMOS_PCLK, //cmos pxiel clock output CMOS_XCLK, //cmos externl clock input [7:0] CMOS_DB, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos pwer down output sys_we, //system data write enable output [15:0] sys_data_in, //system data input output frame_valid, //data valid, or address restart input KEY1, //KEY1 input output [3:0] LED, //led data input input clk24 ); //--------------------------------------------- wire clk_vga; //vga clock wire clk_ref; //sdram ctrl clock wire clk_refout; //sdram clock output wire clk_25M; wire sys_rst_n; //global reset wire sdram_init_done; //sdram init done system_ctrl u_system_ctrl ( .clk (CLOCK), //global clock 50MHZ .rst_n (rst_n), //external reset .sys_rst_n (sys_rst_n), //global reset .clk_c1 (CLOCK) ); wire initial_en; wire Config_Done; //�ϵ��ӳٲ��� power_on_delay power_on_delay_inst( .clk_50M (clk24), .reset_n (sys_rst_n), .camera_rstn (cmos_rst_n), .camera_pwnd (cmos_pwdn), .initial_en (initial_en) ); //Camera��ʼ������,Camera LED FLASH control reg_config reg_config_inst( .clk_25M (clk24), .camera_rstn (cmos_rst_n), .initial_en (initial_en), .i2c_sclk (CMOS_SCLK), .i2c_sdat (CMOS_SDAT), .reg_conf_done (Config_Done), .strobe_flash (), .reg_index (), .clock_20k (), .key1 (KEY1) ); //----------------------------------------------- wire [7:0] cmos_fps_data; //cmos frame rate CMOS_Capture u_CMOS_Capture ( //Global Clock .iCLK (clk24), //24MHz .iRST_N (sys_rst_n), //global reset //I2C Initilize Done .Init_Done (Config_Done /*& sdram_init_done*/), //Init Done //Sensor Interface .CMOS_XCLK (CMOS_XCLK), //cmos .CMOS_PCLK (CMOS_PCLK), //24MHz .CMOS_iDATA (CMOS_DB), //CMOS Data .CMOS_VSYNC (CMOS_VSYNC), //L: Vaild .CMOS_HREF (CMOS_HREF), //H: Vaild //Ouput Sensor Data .CMOS_oCLK (sys_we), //Data PCLK .CMOS_oDATA (sys_data_in), //16Bits RGB .CMOS_VALID (frame_valid), //Data Enable .CMOS_FPS_DATA ()//(cmos_fps_data) //cmos frame rate ); endmodule ================================================ FILE: verilog/CAMERA/system_ctrl.v ================================================ /*------------------------------------------------------------------------- Description : sdram vga controller with ov7670 display. =========================================================================== 15/02/1 --------------------------------------------------------------------------*/ `timescale 1 ns / 1 ns module system_ctrl ( input clk, //50MHz input rst_n, //global reset output sys_rst_n, //system reset input clk_c1, output clk_c2, //-75deg output clk_c3 //-75deg ); //---------------------------------------------- reg [9:0] delay_cnt; reg delay_done; always @(posedge clk_c1 or negedge rst_n) begin if(!rst_n) begin delay_cnt <= 0; delay_done <= 1'b0; end else begin if (delay_cnt== 1000) delay_done <= 1'b1; else delay_cnt <= delay_cnt +1'b1; end end assign sys_rst_n=delay_done; //---------------------------------------------- //Component instantiation wire clk_50; wire clk_c2_oddr,clk_c0_oddr; /* ODDR2 #( .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset ) U_ODDR2_c2 ( .Q(clk_c2), // 1-bit DDR output data .C0(clk_c2_oddr), // 1-bit clock input .C1(~clk_c2_oddr), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(1'b1), // 1-bit data input (associated with C0) .D1(1'b0), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0) // 1-bit set input );*/ /* ODDR2 #( .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset ) U_ODDR2_c0 ( .Q(clk_c0), // 1-bit DDR output data .C0(clk_c0_oddr), // 1-bit clock input .C1(~clk_c0_oddr), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(1'b1), // 1-bit data input (associated with C0) .D1(1'b0), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0) // 1-bit set input ); */ endmodule ================================================ FILE: verilog/GENERAL.qsf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition # Date created = 15:25:52 July 27, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # GENERAL_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC9D6F27C7 set_global_assignment -name TOP_LEVEL_ENTITY GENERAL set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:25:52 JULY 27, 2019" set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX set_location_assignment PIN_W25 -to UART_CTS set_location_assignment PIN_W26 -to UART_RTS set_location_assignment PIN_P22 -to UART_RX set_location_assignment PIN_P21 -to UART_TX set_location_assignment PIN_U20 -to LED[0] set_location_assignment PIN_T19 -to LED[1] set_location_assignment PIN_Y24 -to LED[2] set_location_assignment PIN_Y23 -to LED[3] set_location_assignment PIN_M21 -to KEY[0] set_location_assignment PIN_K25 -to KEY[1] set_location_assignment PIN_K26 -to KEY[2] set_location_assignment PIN_G26 -to KEY[3] set_location_assignment PIN_R20 -to CLOCK_50 set_location_assignment PIN_T8 -to HEX0[0] set_location_assignment PIN_P26 -to HEX0[1] set_location_assignment PIN_V8 -to HEX0[2] set_location_assignment PIN_U7 -to HEX0[3] set_location_assignment PIN_U25 -to HEX0[4] set_location_assignment PIN_W8 -to HEX0[5] set_location_assignment PIN_U26 -to HEX0[6] set_location_assignment PIN_N25 -to HEX1[6] set_location_assignment PIN_W21 -to HEX1[5] set_location_assignment PIN_Y9 -to HEX1[4] set_location_assignment PIN_AC22 -to HEX1[3] set_location_assignment PIN_AB6 -to HEX1[2] set_location_assignment PIN_W20 -to HEX1[1] set_location_assignment PIN_T7 -to HEX1[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1 set_location_assignment PIN_H14 -to tft_sdo set_location_assignment PIN_G17 -to tft_sck set_location_assignment PIN_J12 -to tft_dc set_location_assignment PIN_C20 -to tft_reset set_location_assignment PIN_J11 -to tft_sdi set_location_assignment PIN_B19 -to tft_cs set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_sdo set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_sdi set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_sck set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_dc set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cmos_rst_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_reset set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tft_cs set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cmos_pwdn set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_XCLK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_VSYNC set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_SDAT set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_SCLK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_PCLK set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_HREF set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CMOS_DB set_location_assignment PIN_C14 -to CMOS_SCLK set_location_assignment PIN_B15 -to CMOS_SDAT set_location_assignment PIN_D15 -to CMOS_PCLK set_location_assignment PIN_C15 -to CMOS_VSYNC set_location_assignment PIN_D21 -to CMOS_DB[3] set_location_assignment PIN_A19 -to CMOS_DB[2] set_location_assignment PIN_D20 -to CMOS_DB[7] set_location_assignment PIN_A18 -to CMOS_DB[6] set_location_assignment PIN_E20 -to CMOS_XCLK set_location_assignment PIN_B22 -to CMOS_HREF set_location_assignment PIN_E19 -to CMOS_DB[0] set_location_assignment PIN_A21 -to CMOS_DB[4] set_location_assignment PIN_E18 -to CMOS_DB[5] set_location_assignment PIN_C23 -to CMOS_DB[1] set_location_assignment PIN_F18 -to cmos_rst_n set_location_assignment PIN_C22 -to cmos_pwdn set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/TOP.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/result.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/RAMtoMEM.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/RAM.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/dense.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/conv_TOP.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/conv.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/border.v set_global_assignment -name VERILOG_FILE MobileNet_v3_conv_8_3x1/addressRAM.v set_global_assignment -name VERILOG_FILE scale_picture.v set_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/reg_config.v set_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/power_on_delay.v set_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/ov5640_cfg.v set_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/i2c_com.v set_global_assignment -name VERILOG_FILE CAMERA/cmos_i2c_ov5640/CMOS_Capture.v set_global_assignment -name VERILOG_FILE UART/serialGPIO.v set_global_assignment -name VERILOG_FILE UART/async.v set_global_assignment -name VERILOG_FILE GENERAL.v set_global_assignment -name VERILOG_FILE RAM.v set_global_assignment -name VERILOG_FILE Seg7.v set_global_assignment -name VERILOG_FILE CAMERA/system_ctrl.v set_global_assignment -name VERILOG_FILE CAMERA/sdram_ov5640_vga.v set_global_assignment -name SYSTEMVERILOG_FILE ili9341/tft_ili9341_spi.sv set_global_assignment -name SYSTEMVERILOG_FILE ili9341/tft_ili9341.sv set_global_assignment -name QIP_FILE pll_24_100.qip set_global_assignment -name SIP_FILE pll_24_100.sip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ================================================ FILE: verilog/GENERAL.v ================================================ module GENERAL( input CLOCK_50, //////////// ILI9341 ////////////// input tft_sdo, output tft_sck, output tft_sdi, output tft_dc, output tft_reset, output tft_cs, //////////// CAMERA /////////// output CMOS_SCLK, //cmos i2c clock inout CMOS_SDAT, //cmos i2c data input CMOS_VSYNC, //cmos vsync input CMOS_HREF, //cmos hsync refrence input CMOS_PCLK, //cmos pxiel clock output CMOS_XCLK, //cmos externl clock input [7:0] CMOS_DB, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos pwer down input UART_RX, output UART_TX, input UART_CTS, output UART_RTS, output [6:0] HEX0, output [6:0] HEX1, input [3:0] KEY, output [3:0] LED ); wire [7:0] step; reg [15:0] x; wire [15:0] data_camera,currentPixel; reg [9:0] x_tft,y_tft,x_in,y_in,x_neuro_image,y_neuro_image; reg enable_image; //neuroset reg GO_neuroset,start_neuroset; reg [1:0] RESULT; reg [2:0] step_image; //scale_image wire [7:0] r_out_scale,g_out_scale,b_out_scale; wire [16:0] addr_out_scale; wire signed [12:0] r_out_scale_13,g_out_scale_13,b_out_scale_13; wire [15:0] ram_data; wire valid_data_out_scale; wire [18:0] addr_tft; //scale_image reg new_go,new_image,sh,sh_1,da; wire [18:0] addr_new_image; wire [23:0] data_scale_ram; wire [3:0] RESULT_neuroset; reg [3:0] res; wire [20:0] test1; wire [20:0] test2; wire test2_en; wire signed [20:0] data_in_weights; wire signed [20:0] data_out_weights; reg signed [20:0] delete; reg delete2,delete3; wire [23:0] address_in_weights; wire [23:0] address_out_weights; wire [11:0] address_out_bias; reg clk25; wire clk100; reg [1:0] pre_button; reg trigger; reg start_wr; reg [1:0] sh_result; reg RESULT_0,RESULT_1,RESULT_2; // / ////////////////////////////////////////////// // reset_n and start_n control reg [31:0] cont; always@(posedge CLOCK_50) cont<=(cont==32'd4_000_001)?32'd0:cont+1'b1; reg[4:0] sample; always@(posedge CLOCK_50) begin if(cont==32'd4_000_000) sample[4:0]={sample[3:0],KEY[0] || KEY[3]}; else sample[4:0]=sample[4:0]; end assign test_software_reset_n=(sample[1:0]==2'b10)?1'b0:1'b1; assign test_global_reset_n =(sample[3:2]==2'b10)?1'b0:1'b1; assign test_start_n =(sample[4:3]==2'b01)?1'b0:1'b1; ////////////////////////////////////////////////// pll_24_100 pll_24_100 ( .refclk (CLOCK_50), .rst (1'b0/*~rst_n*/), .locked (), .outclk_0 (clk24), //24Mhz .outclk_1 (clk100), //100Mhz .outclk_2 (clk60) ); always @(posedge CLOCK_50 or negedge KEY[0]) if (!KEY[0]) begin clk25=0; pre_button <= 2'b11; trigger <= 1'b0; end else begin clk25=!clk25; pre_button <= {pre_button[0], test_start_n}; trigger <= !pre_button[0] && pre_button[1]; if (trigger) start_wr=1; end ov5640 ov5640 ( .CLOCK (CLOCK_50), .rst_n (KEY[0]), .clk24 (clk24), .CMOS_SCLK (CMOS_SCLK), //cmos i2c clock .CMOS_SDAT (CMOS_SDAT), //cmos i2c data .CMOS_VSYNC (CMOS_VSYNC), //cmos vsync .CMOS_HREF (CMOS_HREF), //cmos hsync refrence .CMOS_PCLK (CMOS_PCLK), //cmos pxiel clock .CMOS_XCLK (CMOS_XCLK), //cmos externl clock .CMOS_DB (CMOS_DB), //cmos data .cmos_rst_n (cmos_rst_n), //cmos reset .cmos_pwdn (cmos_pwdn), //cmos pwer down .sys_we (clk_camera), //system data write enable .sys_data_in (data_camera), //system data input .frame_valid (valid_data_camera) //data valid, or address restart ); always @(posedge CMOS_PCLK or negedge KEY[0]) begin if (!KEY[0]) begin new_go=0; new_image=0; x_in=0; y_in=0; sh=0; sh_1=0; da=0; end else begin if ((!GO_neuroset) && da) sh=sh+1; da=GO_neuroset; if (((new_image==0)&&(new_go==0)&&(!GO_neuroset)&&(sh_1!=sh))) begin new_go = 1'b1; sh_1=sh; end if ((new_image==0)&&(new_go==1)&&(x_in==0)&&(y_in==0)) begin new_go = 0; new_image = 1; end if ((clk_camera)&&(valid_data_camera)) begin if (x_in < (320-1)) x_in = x_in+1'b1; else begin x_in = 0; if (y_in < 240-1) y_in = y_in+1'b1; else begin y_in=0; new_image=0; end end end if (!valid_data_camera) begin x_in=0; end end end assign addr_new_image=x_in+y_in*320; tft_ili9341 #(.INPUT_CLK_MHZ(100)) tft( .clk (clk100), .tft_sdo (tft_sdo), .tft_sck (tft_sck), .tft_sdi (tft_sdi), .tft_dc (tft_dc), .tft_reset (tft_reset), .tft_cs (tft_cs), .framebufferData (((x_tft<20)&&(y_tft<20))?(RESULT[0]?16'b1110000000000:16'b100):{currentPixel[7],currentPixel[6],currentPixel[5],currentPixel[4],currentPixel[3],currentPixel[2],currentPixel[1],currentPixel[0],currentPixel[15],currentPixel[14],currentPixel[13],currentPixel[12],currentPixel[11],currentPixel[10],currentPixel[9],currentPixel[8]}), .framebufferClk (fbClk) ); always @(posedge fbClk or negedge KEY[0]) if (!KEY[0]) begin x_tft=0; y_tft=0; end else begin if (x_tft<319) x_tft=x_tft+1; else begin x_tft=0; if (y_tft<239) y_tft=y_tft+1; else y_tft=0; end end always @(posedge CLOCK_50 or negedge KEY[0]) if (!KEY[0]) begin x_neuro_image=0; y_neuro_image=0; end else begin if (GO_neuroset) begin if (x_neuro_image<128-1) x_neuro_image=x_neuro_image+1; else begin x_neuro_image=0; if (y_neuro_image<128-1) y_neuro_image=y_neuro_image+1; else y_neuro_image=0; end end end always @(posedge CLOCK_50 or negedge KEY[0]) begin if (!KEY[0]) begin start_neuroset = 0; GO_neuroset = 0; step_image = 0; RESULT = 0; end else begin if (STOP_neuroset) begin step_image = 1; if (sh_result<2) sh_result = sh_result+1'b1; else sh_result=0; if (sh==0) RESULT_0 = RESULT_neuroset[1:0]; if (sh==1) RESULT_1 = RESULT_neuroset[1:0]; if (sh==2) RESULT_2 = RESULT_neuroset[1:0]; if (sh_result==0) begin if (RESULT_0==RESULT_1) RESULT = RESULT_0; else if (RESULT_0==RESULT_2) RESULT = RESULT_0; else if (RESULT_1==RESULT_2) RESULT = RESULT_1; end end if (UART_stop) start_neuroset = 1; if ((start_neuroset)&&(step_image<4)) begin if ((y_neuro_image*128+x_neuro_image) == 0) step_image = step_image + 1; GO_neuroset = 1; end else GO_neuroset = 0; end end assign addr_tft = x_tft + y_tft*320; serialGPIO( .clk25 (clk25), .RxD (UART_RX), .TxD (UART_TX), .reset (KEY[0]), .address (address_in_weights), .data (data_in_weights), .write_enable (we_weights), .start (UART_start), .stop (UART_stop), .data_tx (test2[15:8]), .enable_tx (test2_en && delete2) ); scale_picture scale_picture( .clk (fbClk), .rst (KEY[0]), .valid_data (1), .r ({currentPixel[4],currentPixel[3],currentPixel[2],currentPixel[1],currentPixel[0],1'b0,1'b0,1'b0}), .g ({currentPixel[10],currentPixel[9],currentPixel[8],currentPixel[7],currentPixel[6],currentPixel[5],1'b0,1'b0}), .b ({currentPixel[15],currentPixel[14],currentPixel[13],currentPixel[12],currentPixel[11],1'b0,1'b0,1'b0}), .x (x_tft), .y (y_tft), .r_out (r_out_scale), .g_out (g_out_scale), .b_out (b_out_scale), .addr_out (addr_out_scale), .valid_data_out (valid_data_out_scale) ); assign r_out_scale_13 = (data_scale_ram[23:16]*2 - 255)*16; assign g_out_scale_13 = (data_scale_ram[15:8]*2 - 255)*16; assign b_out_scale_13 = (data_scale_ram[7:0]*2 - 255)*16; TOP neuroset( .clk (CLOCK_50), .clk_RAM_w (CLOCK_50), .clk_RAM_p (CLOCK_50), .GO (GO_neuroset), .RESULT (RESULT_neuroset), .STOP (STOP_neuroset), .re_weights (re_weights), .load_weights (re_weights && (!GO_neuroset)), .dp_weights (data_out_weights), .address_weights (address_out_weights), .re_bias (re_bias), .load_bias (re_bias), .dp_bias (data_out_weights), .address_bias (address_out_bias), .we_image (GO_neuroset), .dp_image ((step_image==1)?(b_out_scale_13):((step_image==2)?(g_out_scale_13):((step_image==3)?(r_out_scale_13):0))), .address_image ((x_neuro_image+y_neuro_image*128)+((step_image-1)*128*128)), .step (step)/*, .test1 (test1), .test2 (test2), .test2_en (test2_en)*/ ); RAM_general RAM_general( .clk_in (clk25), .clk_out (CLOCK_50), .clk_in_im (CMOS_PCLK), .clk_out_im (fbClk), .clk_in_im_scale (fbClk), .clk_out_im_scale (CLOCK_50), .data_in_im (data_camera), .data_out_im (currentPixel), .address_in_im (addr_new_image), .address_out_im (addr_tft), .we_image ((new_image)&&(clk_camera)&&(valid_data_camera)), .re_image (1), .data_in_im_scale ({r_out_scale,g_out_scale,b_out_scale}), .data_out_im_scale (data_scale_ram), .address_in_im_scale (addr_out_scale), .address_out_im_scale (x_neuro_image+y_neuro_image*128), .we_image_scale (valid_data_out_scale), .re_image_scale (GO_neuroset), .data_in_weights (data_in_weights), .data_out_weights (data_out_weights), .address_in_weights (address_in_weights), .address_out_weights ((re_weights)?address_out_weights:(208115 + address_out_bias)), .we_weights (we_weights), .re_weights ((re_weights && (!GO_neuroset)) || re_bias), ); reg [31:0] sh_cadr,res_sh_cadr; reg wait_cadr; reg [2:0] sh_show; assign LED[3] = new_image; assign LED[2] = sh; assign LED[1] = sh_1; assign LED[0] = sh_show[0]; always @(posedge CLOCK_50 or negedge KEY[0]) if (!KEY[0]) begin wait_cadr=0; sh_cadr=0; res_sh_cadr=0; end else begin if (GO_neuroset && (!STOP_neuroset) && (!wait_cadr)) begin sh_cadr=0; wait_cadr=1; end else sh_cadr=sh_cadr+1; if (/*!GO_neuroset*/STOP_neuroset && wait_cadr) begin res_sh_cadr=sh_cadr; wait_cadr=0; end end always @(negedge KEY[3] or negedge KEY[0]) if (!KEY[0]) sh_show=0; else if (sh_show<3) sh_show=sh_show+1; else sh_show=0; Seg7 seg7_0( .data (((sh_show==0)?res_sh_cadr[3:0]:((sh_show==1)?res_sh_cadr[11:8]:((sh_show==2)?res_sh_cadr[19:16]:((sh_show==3)?res_sh_cadr[27:24]:0))))), .hex (HEX0) ); Seg7 seg7_1( .data (((sh_show==0)?res_sh_cadr[7:4]:((sh_show==1)?res_sh_cadr[15:12]:((sh_show==2)?res_sh_cadr[23:20]:((sh_show==3)?res_sh_cadr[31:28]:0))))), .hex (HEX1) ); endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/RAM.v ================================================ module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk,clk_RAM_w,q_bias,d_bias,we_bias,re_bias,write_address_bias,read_address_bias); parameter picture_size=0; parameter SIZE_1=0; parameter SIZE_2=0; parameter SIZE_3=0; parameter SIZE_4=0; parameter SIZE_5=0; parameter SIZE_6=0; parameter SIZE_7=0; parameter SIZE_8=0; parameter SIZE_address_pix=13; parameter SIZE_address_pix_t=12; parameter SIZE_address_wei=13; parameter SIZE_address_image=16; parameter SIZE_weights=0; parameter SIZE_bias=0; output reg signed [SIZE_8-1:0] qp; //read data output reg signed [32*8-1:0] qtp; //read data output reg signed [SIZE_weights*9-1:0] qw; //read weight output reg signed [SIZE_bias-1:0] q_bias; input signed [SIZE_1*8-1:0] dp; //write data input signed [32*8-1:0] dtp; //write data input signed [SIZE_weights*9-1:0] dw; //write weight input signed [SIZE_bias-1:0] d_bias; input [SIZE_address_pix-1:0] write_addressp, read_addressp; input [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp; input [SIZE_address_wei-1:0] write_addressw, read_addressw; input [10:0] write_address_bias,read_address_bias; input we_p; input we_tp; input we_w; input we_bias; input re_p; input re_tp; input re_w; input re_bias; input clk,clk_RAM_w; reg signed [SIZE_1*8-1:0] mem [0:128*128*1+4096*2-1]; reg signed [32*8-1:0] mem_t [0:4096-1]; reg signed [SIZE_weights*9-1:0] weight [0:4095]; reg signed [SIZE_bias-1:0] mem_bias [0:256]; always @ (posedge clk) begin if (we_p) mem[write_addressp] <= dp; if (we_tp) mem_t[write_addresstp] <= dtp; end always @ (posedge clk_RAM_w) begin if (we_w) weight[write_addressw] <= dw; if (we_bias) mem_bias[write_address_bias] <= d_bias; end always @ (posedge clk) begin if (re_p) qp <= mem[read_addressp]; if (re_tp)qtp <= mem_t[read_addresstp]; if (re_w) qw <= weight[read_addressw]; if (re_bias) q_bias <= mem_bias[read_address_bias]; end endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/RAMtoMEM.v ================================================ module memorywork(clk_RAM_w,data,data_bias,address,we_w,re_weights,re_bias,nextstep,dw,addrw,step_out,GO,in_dense,load_weights,onexone,address_bias,d_bias,load_bias,we_bias,write_address_bias); parameter num_conv=0; parameter SIZE_1=0; parameter SIZE_2=0; parameter SIZE_3=0; parameter SIZE_4=0; parameter SIZE_5=0; parameter SIZE_6=0; parameter SIZE_7=0; parameter SIZE_8=0; parameter SIZE_address_pix=0; parameter SIZE_address_wei=0; parameter SIZE_weights=0; parameter SIZE_bias=0; input clk_RAM_w; input signed [SIZE_weights-1:0] data; input signed [SIZE_bias-1:0] data_bias; output [23:0] address; output reg we_w; output re_weights,re_bias; input nextstep; output reg signed [SIZE_weights*9-1:0] dw; output reg [SIZE_address_wei-1:0] addrw; output [6:0] step_out; input GO; input [8:0] in_dense; input load_weights,load_bias; output reg signed [SIZE_bias-1:0] d_bias; output reg we_bias; output reg [10:0] write_address_bias; output [11:0] address_bias; input onexone; reg [SIZE_address_pix-1:0] addr; wire [17:0] firstaddr,lastaddr; wire [18:0] razn_addr; assign razn_addr = lastaddr-firstaddr; reg [6:0] step; reg [6:0] step_n; reg [3:0] weight_case; reg [SIZE_weights*9-1:0] buff; reg [17:0] i; reg [17:0] i_d; reg [17:0] i1; addressRAM inst_1(.step(step_out),.re_weights(re_weights),.re_bias(re_bias),.firstaddr(firstaddr),.lastaddr(lastaddr)); initial weight_case=0; initial i=0; initial i_d=0; initial i1=0; always @(negedge clk_RAM_w) if ( (step_out==1)||(step_out==2) ||(step_out==4)||(step_out==5) ||(step_out==7)||(step_out==8) ||(step_out==10)||(step_out==11) ||(step_out==13)||(step_out==14) ||(step_out==16)||(step_out==17) ||(step_out==19)||(step_out==20) ||(step_out==22)||(step_out==23) ||(step_out==25)||(step_out==26) ||(step_out==28)||(step_out==29) ||(step_out==31)||(step_out==32) ||(step_out==34)||(step_out==35) ||(step_out==37)||(step_out==38) ||(step_out==40)||(step_out==41) ||(step_out==43)||(step_out==44) ||(step_out==46)||(step_out==47) ||(step_out==49)||(step_out==50) ||(step_out==52)||(step_out==53) ||(step_out==55)||(step_out==56) ||(step_out==58)||(step_out==59) ||(step_out==61)||(step_out==62) ||(step_out==64)||(step_out==65) ||(step_out==67)||(step_out==68) ||(step_out==70)||(step_out==71) ||(step_out==73)||(step_out==74) ||(step_out==76)||(step_out==77) ||(step_out==79)||(step_out==80) ||(step_out==82)||(step_out==83) ||(step_out==85) ) begin if ((i<=razn_addr+1)&&(re_weights)) addr=i1; if ((i<=razn_addr+1)&&(re_bias)) addr=i; end always @(posedge clk_RAM_w or posedge GO) if (GO) step=1; else begin case (step_out) 8'd1,8'd4,8'd7,8'd10,8'd13,8'd16,8'd19,8'd22,8'd25,8'd28,8'd31,8'd34,8'd37,8'd40,8'd43,8'd46,8'd49,8'd52,8'd55,8'd58,8'd61,8'd64,8'd67,8'd70,8'd73,8'd76,8'd79,8'd82,8'd85: begin if (i<=razn_addr+3) begin we_w=0; addrw=addr; if (load_weights==1'b1) i=i+1; if (step_out==85) if (i_d==((in_dense)+1)) begin dw=buff; we_w=1; weight_case=1; i_d=1; i1=i1+1; end case (weight_case) 0: ; 1: begin buff=0; buff[SIZE_weights*9-1:SIZE_weights*8]=data[SIZE_weights-1:0]; end 2: buff[SIZE_weights*8-1:SIZE_weights*7]=data[SIZE_weights-1:0]; 3: buff[SIZE_weights*7-1:SIZE_weights*6]=data[SIZE_weights-1:0]; 4: buff[SIZE_weights*6-1:SIZE_weights*5]=data[SIZE_weights-1:0]; 5: buff[SIZE_weights*5-1:SIZE_weights*4]=data[SIZE_weights-1:0]; 6: buff[SIZE_weights*4-1:SIZE_weights*3]=data[SIZE_weights-1:0]; 7: buff[SIZE_weights*3-1:SIZE_weights*2]=data[SIZE_weights-1:0]; 8: buff[SIZE_weights*2-1:SIZE_weights]=data[SIZE_weights-1:0]; 9: begin buff[SIZE_weights-1:0]=data[SIZE_weights-1:0]; end default: $display("Check weight_case"); endcase if (load_weights==1'b1) i_d=i_d+1; if (load_weights==1'b1) begin if ((weight_case==9)||((onexone)&&(weight_case==8))) begin weight_case=1; dw=buff; we_w=1; i1=i1+1; end else begin weight_case=weight_case+1; end end end if (i>razn_addr+3) begin step=step+1; //next step i=0; i_d=0; i1=0; weight_case=0; end end 8'd2,8'd5,8'd8,8'd11,8'd14,8'd17,8'd20,8'd23,8'd26,8'd29,8'd32,8'd35,8'd38,8'd41,8'd44,8'd47,8'd50,8'd53,8'd56,8'd59,8'd62,8'd65,8'd68,8'd71,8'd74,8'd77,8'd80,8'd83: begin if (i<=razn_addr) begin we_bias=1; write_address_bias=addr; if (load_bias==1'b1) i=i+1; d_bias=data_bias; end else begin step=step+1; i=0; we_bias=0; end end default: begin we_w=0; we_bias=0; i=0; i_d=0; i1=0; end endcase end always @(posedge nextstep) if (GO==1) step_n=0; else step_n=step_n+1; assign step_out=step+step_n; assign address=(re_weights)?(firstaddr+i):0; assign address_bias=(re_bias)?(firstaddr+i):0; endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/TOP.v ================================================ module TOP( clk, clk_RAM_w, clk_RAM_p, GO, RESULT, STOP, re_weights, load_weights, dp_weights, address_weights, re_bias, load_bias, dp_bias, address_bias, we_image, dp_image, address_image, step ); parameter num_conv=8; parameter SIZE_weights = 19; parameter SIZE_bias = 14; parameter SIZE_1=13; parameter SIZE_2=26; parameter SIZE_3=39; parameter SIZE_4=52; parameter SIZE_5=65; parameter SIZE_6=78; parameter SIZE_7=91; parameter SIZE_8=104; parameter SIZE_address_pix=18; parameter SIZE_address_pix_t=17; parameter SIZE_address_wei=17; parameter SIZE_address_image=16; parameter picture_size = 128; parameter picture_storage_limit = 0; parameter razmpar = picture_size >> 1; parameter razmpar2 = picture_size >> 2; parameter picture_storage_limit_2 = picture_size*picture_size*1; input clk,clk_RAM_w,clk_RAM_p; input GO; output [1:0] RESULT; input signed [SIZE_weights-1:0] dp_weights; input signed [SIZE_bias-1:0] dp_bias; output [23:0] address_weights; output [11:0] address_bias; input load_weights,load_bias; input signed [SIZE_1-1:0] dp_image; input [SIZE_address_image-1:0] address_image; input we_image; output reg STOP; output re_weights,re_bias; output [6:0] step; wire [SIZE_address_image-1:0] address_image_1; reg conv_en; wire STOP_conv; reg dense_en; wire STOP_dense; reg result_en; wire STOP_res; wire [1:0] res_out; reg bias,glob_average_en; reg [4:0] TOPlvl_conv; wire [4:0] TOPlvl; reg [8:0] lvl; reg [8:0] slvl; reg [2:0] num; reg [SIZE_address_pix-1:0] memstartp; wire [SIZE_address_pix-1:0] memstartp_lvl; reg [SIZE_address_wei-1:0] memstartw; wire [SIZE_address_wei-1:0] memstartw_lvl; reg [SIZE_address_pix-1:0] memstartzap; wire [SIZE_address_pix-1:0] memstartzap_num; wire [10:0] memstartb; wire [SIZE_address_pix-1:0] read_addressp; wire [SIZE_address_image-1:0] read_addressp_init; wire [SIZE_address_pix_t-1:0] read_addresstp; wire [SIZE_address_wei-1:0] read_addressw; wire [10:0] read_address_bias; wire [SIZE_address_pix-1:0] read_addressp_conv; wire [SIZE_address_pix-1:0] read_addressp_dense; wire [SIZE_address_pix-1:0] read_addressp_res; wire [SIZE_address_wei-1:0] read_addressw_conv; wire [SIZE_address_wei-1:0] read_addressw_dense; wire [SIZE_address_pix-1:0] write_addressp; wire [SIZE_address_pix_t-1:0] write_addresstp; wire [SIZE_address_wei-1:0] write_addressw; wire [10:0] write_address_bias; wire [SIZE_address_pix-1:0] write_addressp_zagr; wire [SIZE_address_pix-1:0] write_addressp_conv; wire [SIZE_address_pix-1:0] write_addressp_dense; wire we_p,we_tp,we_w; wire re_p,re_tp,re_w,re_p_init; wire re_bias_RAM; wire we_p_zagr; wire we_conv,re_wb_conv,re_conv; wire we_dense,re_p_dense,re_w_dense; wire we_bias; wire re_p_res; wire signed [SIZE_8-1:0] qp; wire signed [32*8-1:0] qtp; wire signed [SIZE_weights*9-1:0] qw; wire signed [SIZE_bias-1:0] q_bias; wire signed [SIZE_8-1:0] dp; wire signed [32*8-1:0] dtp; wire signed [SIZE_weights*9-1:0] dw; wire signed [SIZE_8-1:0] dp_conv; wire signed [SIZE_8-1:0] dp_dense; wire signed [SIZE_8-1:0] dp_zagr; wire signed [SIZE_bias-1:0] d_bias; wire [1:0] prov; wire [14:0] i_conv; wire signed [32-1:0] Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8; wire signed [SIZE_weights-1:0] w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83; wire signed [SIZE_weights-1:0] w11_c,w12_c,w13_c,w21_c,w22_c,w23_c,w31_c,w32_c,w33_c,w41_c,w42_c,w43_c,w51_c,w52_c,w53_c,w61_c,w62_c,w63_c,w71_c,w72_c,w73_c,w81_c,w82_c,w83_c; wire signed [SIZE_weights-1:0] w11_d,w12_d,w13_d,w21_d,w22_d,w23_d,w31_d,w32_d,w33_d,w41_d,w42_d,w43_d,w51_d,w52_d,w53_d,w61_d,w62_d,w63_d,w71_d,w72_d,w73_d,w81_d,w82_d,w83_d; wire signed [SIZE_1-1:0] p11,p12,p13,p21,p22,p23,p31,p32,p33,p41,p42,p43,p51,p52,p53,p61,p62,p63,p71,p72,p73,p81,p82,p83; wire signed [SIZE_1-1:0] p11_c,p12_c,p13_c,p21_c,p22_c,p23_c,p31_c,p32_c,p33_c,p41_c,p42_c,p43_c,p51_c,p52_c,p53_c,p61_c,p62_c,p63_c,p71_c,p72_c,p73_c,p81_c,p82_c,p83_c; wire signed [SIZE_1-1:0] p11_d,p12_d,p13_d,p21_d,p22_d,p23_d,p31_d,p32_d,p33_d,p41_d,p42_d,p43_d,p51_d,p52_d,p53_d,p61_d,p62_d,p63_d,p71_d,p72_d,p73_d,p81_d,p82_d,p83_d; wire go_conv; wire go_conv_TOP; wire go_dense; reg nextstep; reg [7:0] matrix; wire [14:0] matrix2; //razmer*razmer reg [8:0] mem; reg [8:0] filt; reg [1:0] stride; reg depthwise; reg onexone; reg [8:0] in_dense; reg [1:0] out_dense; reg nozero_dense; wire clk_RAM; wire up_perm,down_perm; wire [SIZE_address_pix-1:0] stride_plus_prov; conv_TOP #( SIZE_1, SIZE_2, SIZE_3, SIZE_4, SIZE_5, SIZE_6, SIZE_7, SIZE_8, SIZE_address_pix, SIZE_address_pix_t, SIZE_address_wei, SIZE_weights, SIZE_bias ) conv_TOP ( .clk (clk), .conv_en (conv_en), .STOP (STOP_conv), .memstartp (memstartp_lvl), .memstartw (memstartw_lvl), .memstartb (memstartb), .memstartzap (memstartzap_num), .read_addressp (read_addressp_conv), .write_addressp (write_addressp_conv), .read_addresstp (read_addresstp), .write_addresstp (write_addresstp), .read_addressb (read_address_bias), .read_addressw (read_addressw_conv), .we (we_conv), .re_wb (re_wb_conv), .re (re_conv), .we_t (we_tp), .re_t (re_tp), .qp (qp), .qtp (qtp), .qw (qw), .q_bias (q_bias), .dp (dp_conv), .dtp (dtp), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i_to_prov (i_conv), .lvl (lvl), .slvl (slvl), .Y1 (Y1), .Y2 (Y2), .Y3 (Y3), .Y4 (Y4), .Y5 (Y5), .Y6 (Y6), .Y7 (Y7), .Y8 (Y8), .w11 (w11_c), .w12 (w12_c), .w13 (w13_c), .w21 (w21_c), .w22 (w22_c), .w23 (w23_c), .w31 (w31_c), .w32 (w32_c), .w33 (w33_c), .w41 (w41_c), .w42 (w42_c), .w43 (w43_c), .w51 (w51_c), .w52 (w52_c), .w53 (w53_c), .w61 (w61_c), .w62 (w62_c), .w63 (w63_c), .w71 (w71_c), .w72 (w72_c), .w73 (w73_c), .w81 (w81_c), .w82 (w82_c), .w83 (w83_c), .p0_1 (p11_c), .p0_2 (p12_c), .p0_3 (p13_c), .p1_1 (p21_c), .p1_2 (p22_c), .p1_3 (p23_c), .p2_1 (p31_c), .p2_2 (p32_c), .p2_3 (p33_c), .p3_1 (p41_c), .p3_2 (p42_c), .p3_3 (p43_c), .p4_1 (p51_c), .p4_2 (p52_c), .p4_3 (p53_c), .p5_1 (p61_c), .p5_2 (p62_c), .p5_3 (p63_c), .p6_1 (p71_c), .p6_2 (p72_c), .p6_3 (p73_c), .p7_1 (p81_c), .p7_2 (p82_c), .p7_3 (p83_c), .go (go_conv_TOP), .up_perm (up_perm), .down_perm (down_perm), .stride_plus_prov (stride_plus_prov), .num (num), .filt (filt), .mem (mem), .bias (bias), .glob_average_en (glob_average_en), .step (step), .stride (stride), .depthwise (depthwise), .onexone (onexone) ); memorywork #( num_conv, SIZE_1, SIZE_2, SIZE_3, SIZE_4, SIZE_5, SIZE_6, SIZE_7, SIZE_8, SIZE_address_pix, SIZE_address_wei, SIZE_weights, SIZE_bias ) block ( .clk_RAM_w (clk_RAM_w), .we_w (we_w), .re_weights (re_weights), .re_bias (re_bias), .load_weights (load_weights), .addrw (write_addressw), .dw (dw), .step_out (step), .nextstep (nextstep), .data (dp_weights), .address (address_weights), .GO (GO), .in_dense (in_dense), .onexone (onexone), .data_bias (dp_bias), .load_bias (load_bias), .address_bias (address_bias), .write_address_bias (write_address_bias), .we_bias (we_bias), .d_bias (d_bias) ); RAM #( picture_size, SIZE_1, SIZE_2, SIZE_3, SIZE_4, SIZE_5, SIZE_6, SIZE_7, SIZE_8, SIZE_address_pix, SIZE_address_pix_t, SIZE_address_wei, SIZE_address_image, SIZE_weights, SIZE_bias ) memory ( .qp (qp), .qtp (qtp), .qw (qw), .dp (dp), .dtp (dtp), .dw (dw), .write_addressp (write_addressp), .read_addressp (read_addressp), .write_addresstp (write_addresstp), .read_addresstp (read_addresstp), .write_addressw (write_addressw), .read_addressw (read_addressw), .we_p (we_p), .we_tp (we_tp), .we_w (we_w), .re_p (re_p), .re_tp (re_tp), .re_w (re_w), .clk (clk_RAM), .clk_RAM_w (clk_RAM_w), .q_bias (q_bias), .d_bias (d_bias), .we_bias (we_bias), .re_bias (re_bias_RAM), .write_address_bias (write_address_bias), .read_address_bias (read_address_bias) ); border border( .clk (clk), .go (conv_en && (!onexone)), .i (i_conv), .matrix (matrix), .prov (prov) ); dense #( num_conv, SIZE_1, SIZE_2, SIZE_3, SIZE_4, SIZE_5, SIZE_6, SIZE_7, SIZE_8, SIZE_address_pix, SIZE_address_wei, SIZE_weights ) dense ( .clk (clk), .dense_en (dense_en), .STOP (STOP_dense), .in (in_dense), .out (out_dense), .we (we_dense), .re_p (re_p_dense), .re_w (re_w_dense), .read_addressp (read_addressp_dense), .read_addressw (read_addressw_dense), .write_addressp (write_addressp_dense), .memstartp (memstartp_lvl), .memstartzap (memstartzap_num), .qp (qp), .qw (qw), .res (dp_dense), .Y1 (Y1), .Y2 (Y2), .Y3 (Y3), .Y4 (Y4), .Y5 (Y5), .Y6 (Y6), .Y7 (Y7), .Y8 (Y8), .w11 (w11_d), .w12 (w12_d), .w13 (w13_d), .w21 (w21_d), .w22 (w22_d), .w23 (w23_d), .w31 (w31_d), .w32 (w32_d), .w33 (w33_d), .w41 (w41_d), .w42 (w42_d), .w43 (w43_d), .w51 (w51_d), .w52 (w52_d), .w53 (w53_d), .w61 (w61_d), .w62 (w62_d), .w63 (w63_d), .w71 (w71_d), .w72 (w72_d), .w73 (w73_d), .w81 (w81_d), .w82 (w82_d), .w83 (w83_d), .p11 (p11_d), .p12 (p12_d), .p13 (p13_d), .p21 (p21_d), .p22 (p22_d), .p23 (p23_d), .p31 (p31_d), .p32 (p32_d), .p33 (p33_d), .p41 (p41_d), .p42 (p42_d), .p43 (p43_d), .p51 (p51_d), .p52 (p52_d), .p53 (p53_d), .p61 (p61_d), .p62 (p62_d), .p63 (p63_d), .p71 (p71_d), .p72 (p72_d), .p73 (p73_d), .p81 (p81_d), .p82 (p82_d), .p83 (p83_d), .go (go_dense), .nozero (nozero_dense) ); result #( SIZE_1, SIZE_2, SIZE_3, SIZE_4, SIZE_5, SIZE_6, SIZE_7, SIZE_8, SIZE_address_pix ) result ( .clk (clk), .enable (result_en), .STOP (STOP_res), .memstartp (memstartp_lvl), .read_addressp (read_addressp_res), .qp (qp), .re (re_p_res), .RESULT (res_out) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv1 ( .clk (clk), .Y1 (Y1), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p11), .p2 (p12), .p3 (p13), .w1 (w11), .w2 (w12), .w3 (w13), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv2 ( .clk (clk), .Y1 (Y2), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p21), .p2 (p22), .p3 (p23), .w1 (w21), .w2 (w22), .w3 (w23), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv3 ( .clk (clk), .Y1 (Y3), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p31), .p2 (p32), .p3 (p33), .w1 (w31), .w2 (w32), .w3 (w33), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv4 ( .clk (clk), .Y1 (Y4), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p41), .p2 (p42), .p3 (p43), .w1 (w41), .w2 (w42), .w3 (w43), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv5 ( .clk (clk), .Y1 (Y5), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p51), .p2 (p52), .p3 (p53), .w1 (w51), .w2 (w52), .w3 (w53), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv6 ( .clk (clk), .Y1 (Y6), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p61), .p2 (p62), .p3 (p63), .w1 (w61), .w2 (w62), .w3 (w63), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv7 ( .clk (clk), .Y1 (Y7), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p71), .p2 (p72), .p3 (p73), .w1 (w71), .w2 (w72), .w3 (w73), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); conv #( SIZE_1, SIZE_address_pix, SIZE_weights ) conv8 ( .clk (clk), .Y1 (Y8), .prov (prov), .matrix (matrix), .matrix2 (matrix2), .i (i_conv), .up_perm ((up_perm && (!dense_en))), .down_perm ((down_perm && (!dense_en))), .p1 (p81), .p2 (p82), .p3 (p83), .w1 (w81), .w2 (w82), .w3 (w83), .conv_en (go_conv), .dense_en ((onexone||dense_en)), .stride_plus_prov (stride_plus_prov) ); always @(posedge clk ) begin if (GO==1) begin STOP=0; nextstep=1; glob_average_en=0; result_en=0; end else nextstep=0; if (STOP==0) begin if ((TOPlvl==1)&&(step==3)) begin matrix = 128; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 7; filt = 2; stride=2; onexone=0; depthwise=0; glob_average_en=0; end if ((TOPlvl==2)&&(step==3)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==2)&&(step==6)) begin matrix = 64; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 7; filt = 7; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==3)&&(step==6)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==3)&&(step==9)) begin matrix = 64; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 7; filt = 15; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==4)&&(step==9)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==4)&&(step==12)) begin matrix = 64; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 15; filt = 15; stride=2; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==5)&&(step==12)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==5)&&(step==15)) begin matrix = 32; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 15; filt = 31; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==6)&&(step==15)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==6)&&(step==18)) begin matrix = 32; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 31; filt = 31; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==7)&&(step==18)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==7)&&(step==21)) begin matrix = 32; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 31; filt = 31; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==8)&&(step==21)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==8)&&(step==24)) begin matrix = 32; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 31; filt = 31; stride=2; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==9)&&(step==24)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==9)&&(step==27)) begin matrix = 16; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 31; filt = 63; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==10)&&(step==27)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==10)&&(step==30)) begin matrix = 16; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 63; filt = 63; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==11)&&(step==30)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==11)&&(step==33)) begin matrix = 16; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 63; filt = 63; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==12)&&(step==33)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==12)&&(step==36)) begin matrix = 16; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 63; filt = 63; stride=2; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==13)&&(step==36)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==13)&&(step==39)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 63; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==14)&&(step==39)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==14)&&(step==42)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==15)&&(step==42)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==15)&&(step==45)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==16)&&(step==45)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==16)&&(step==48)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==17)&&(step==48)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==17)&&(step==51)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==18)&&(step==51)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==18)&&(step==54)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==19)&&(step==54)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==19)&&(step==57)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==20)&&(step==57)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==20)&&(step==60)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==21)&&(step==60)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==21)&&(step==63)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==22)&&(step==63)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==22)&&(step==66)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==23)&&(step==66)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==23)&&(step==69)) begin matrix = 8; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==24)&&(step==69)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==24)&&(step==72)) begin matrix = 8; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 127; filt = 127; stride=2; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==25)&&(step==72)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==25)&&(step==75)) begin matrix = 4; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2; conv_en = 1; dense_en=0; mem = 127; filt = 255; stride=1; onexone=1; depthwise=0; glob_average_en=0; end if ((TOPlvl==26)&&(step==75)) begin nextstep = 1; onexone = 0; end if ((TOPlvl==26)&&(step==78)) begin matrix = 4; memstartp = picture_storage_limit_2; memstartw = 0; memstartzap = picture_storage_limit; conv_en = 1; dense_en=0; mem = 255; filt = 255; stride=1; onexone=0; depthwise=1; glob_average_en=0; end if ((TOPlvl==27)&&(step==78)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==27)&&(step==81)) begin matrix = 4; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2+0; conv_en = 1; dense_en=0; mem = 255; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=1; end if ((TOPlvl==28)&&(step==81)) begin nextstep = 1; onexone = 1; end if ((TOPlvl==28)&&(step==84)) begin matrix = 4; memstartp = picture_storage_limit; memstartw = 0; memstartzap = picture_storage_limit_2+16; conv_en = 1; dense_en=0; mem = 255; filt = 127; stride=1; onexone=1; depthwise=0; glob_average_en=1; end if ((TOPlvl==29)&&(step==84)) begin nextstep=1; onexone=0; in_dense=256; out_dense=2; end if ((TOPlvl==29)&&(step==86)) begin memstartp= picture_storage_limit_2; memstartzap = picture_storage_limit; conv_en=0; dense_en=1; nozero_dense=1; depthwise=0; end if ((TOPlvl==29)&&(STOP_dense==0)&&(step==87)) begin memstartp = picture_storage_limit; result_en = 1; end if ((depthwise)||(lvl==filt)||((onexone)&&(mem==((lvl+1)*8)-1))) bias=1; else bias=0; if ((STOP_conv)&&(conv_en==1)) conv_en=0; if (STOP_dense==1) begin dense_en=0; nextstep=1; end if ((STOP_res==1)&&(result_en==1)) begin result_en=0; STOP=1; end end end always @(negedge STOP_conv or posedge GO) begin if (GO) begin lvl=0; slvl=0; TOPlvl_conv=1; num=0; end else begin if (lvl==(filt)||((lvl==filt>>3)&&(depthwise))||((lvl==((mem+1)>>3)-1)&&(onexone))) begin lvl=0; if ((num!=0)&&(!depthwise)) num=num+1; else num=0; if ((num==0)||(depthwise)) begin if ((depthwise)||((!onexone)&&(mem==(8+(slvl*8))-1))||((onexone)&&(filt==(8+(slvl*8))-1))) begin slvl=0; TOPlvl_conv=TOPlvl_conv+1'b1; end else slvl = slvl + 1'b1; end end else lvl=lvl+1; end end assign address_image_1 = address_image[13:0]+1; assign memstartw_lvl=memstartw+((onexone?num*(((mem+1)>>3)-1)+lvl:(depthwise?lvl*num_conv:lvl))+(((!depthwise)&&(!onexone))?(slvl*(4*(filt+1))):(1'b0))+((!onexone)?(num*(filt+1)):num+slvl*((mem+1)<<0))); assign memstartzap_num = memstartzap+((glob_average_en)?(num+slvl*1):0)+(((conv_en==1)&&(!glob_average_en))?(num*((matrix>>(stride-1))*(matrix>>(stride-1)))+slvl*((matrix>>(stride-1))*(matrix>>(stride-1)))+((depthwise)?lvl*((matrix>>(stride-1))*(matrix>>(stride-1))):0)):0); assign memstartp_lvl=memstartp+(onexone?((lvl[8:0])*matrix2):(depthwise?(lvl*matrix2):((lvl>>num_conv-1)*matrix2))); assign memstartb=slvl*8+num+(depthwise?lvl*num_conv:0)+1; assign re_p=GO?1'b1:((conv_en==1)?re_conv:((dense_en==1)?re_p_dense:((result_en==1)?re_p_res:0))); assign re_w=(conv_en==1)?re_wb_conv:((dense_en==1)?re_w_dense:0); assign re_bias_RAM=(conv_en==1)?re_wb_conv:0; assign read_addressp=GO?address_image_1[13:0]:((conv_en==1)?read_addressp_conv:((dense_en==1)?read_addressp_dense:((result_en==1)?read_addressp_res:0))); assign we_p=GO?we_image:((conv_en==1)?we_conv:((dense_en==1)?we_dense:0)); assign dp=GO?((address_image<128*128*1)?{dp_image,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0}:((address_image<128*128*2)?{qp[SIZE_8-1:SIZE_7],dp_image,13'd0,13'd0,13'd0,13'd0,13'd0,13'd0}:((address_image<128*128*3)?{qp[SIZE_8-1:SIZE_7],qp[SIZE_7-1:SIZE_6],dp_image,13'd0,13'd0,13'd0,13'd0,13'd0}:0))):((conv_en==1)?dp_conv:((dense_en==1)?dp_dense:0)); assign write_addressp=GO?(address_image[13:0]):((conv_en==1)?write_addressp_conv:((dense_en==1)?write_addressp_dense:0)); assign read_addressw=(conv_en==1)?read_addressw_conv:((dense_en==1)?read_addressw_dense:0); assign matrix2=matrix*matrix; assign clk_RAM=GO?clk_RAM_p:clk; assign p11=(conv_en==1)?p11_c:((dense_en==1)?p11_d:0); assign p12=(conv_en==1)?p12_c:((dense_en==1)?p12_d:0); assign p13=(conv_en==1)?p13_c:((dense_en==1)?p13_d:0); assign p21=(conv_en==1)?p21_c:((dense_en==1)?p21_d:0); assign p22=(conv_en==1)?p22_c:((dense_en==1)?p22_d:0); assign p23=(conv_en==1)?p23_c:((dense_en==1)?p23_d:0); assign p31=(conv_en==1)?p31_c:((dense_en==1)?p31_d:0); assign p32=(conv_en==1)?p32_c:((dense_en==1)?p32_d:0); assign p33=(conv_en==1)?p33_c:((dense_en==1)?p33_d:0); assign p41=(conv_en==1)?p41_c:((dense_en==1)?p41_d:0); assign p42=(conv_en==1)?p42_c:((dense_en==1)?p42_d:0); assign p43=(conv_en==1)?p43_c:((dense_en==1)?p43_d:0); assign p51=(conv_en==1)?p51_c:((dense_en==1)?p51_d:0); assign p52=(conv_en==1)?p52_c:((dense_en==1)?p52_d:0); assign p53=(conv_en==1)?p53_c:((dense_en==1)?p53_d:0); assign p61=(conv_en==1)?p61_c:((dense_en==1)?p61_d:0); assign p62=(conv_en==1)?p62_c:((dense_en==1)?p62_d:0); assign p63=(conv_en==1)?p63_c:((dense_en==1)?p63_d:0); assign p71=(conv_en==1)?p71_c:((dense_en==1)?p71_d:0); assign p72=(conv_en==1)?p72_c:((dense_en==1)?p72_d:0); assign p73=(conv_en==1)?p73_c:((dense_en==1)?p73_d:0); assign p81=(conv_en==1)?p81_c:((dense_en==1)?p81_d:0); assign p82=(conv_en==1)?p82_c:((dense_en==1)?p82_d:0); assign p83=(conv_en==1)?p83_c:((dense_en==1)?p83_d:0); assign w11=(conv_en==1)?w11_c:((dense_en==1)?w11_d:0); assign w12=(conv_en==1)?w12_c:((dense_en==1)?w12_d:0); assign w13=(conv_en==1)?w13_c:((dense_en==1)?w13_d:0); assign w21=(conv_en==1)?w21_c:((dense_en==1)?w21_d:0); assign w22=(conv_en==1)?w22_c:((dense_en==1)?w22_d:0); assign w23=(conv_en==1)?w23_c:((dense_en==1)?w23_d:0); assign w31=(conv_en==1)?w31_c:((dense_en==1)?w31_d:0); assign w32=(conv_en==1)?w32_c:((dense_en==1)?w32_d:0); assign w33=(conv_en==1)?w33_c:((dense_en==1)?w33_d:0); assign w41=(conv_en==1)?w41_c:((dense_en==1)?w41_d:0); assign w42=(conv_en==1)?w42_c:((dense_en==1)?w42_d:0); assign w43=(conv_en==1)?w43_c:((dense_en==1)?w43_d:0); assign w51=(conv_en==1)?w51_c:((dense_en==1)?w51_d:0); assign w52=(conv_en==1)?w52_c:((dense_en==1)?w52_d:0); assign w53=(conv_en==1)?w53_c:((dense_en==1)?w53_d:0); assign w61=(conv_en==1)?w61_c:((dense_en==1)?w61_d:0); assign w62=(conv_en==1)?w62_c:((dense_en==1)?w62_d:0); assign w63=(conv_en==1)?w63_c:((dense_en==1)?w63_d:0); assign w71=(conv_en==1)?w71_c:((dense_en==1)?w71_d:0); assign w72=(conv_en==1)?w72_c:((dense_en==1)?w72_d:0); assign w73=(conv_en==1)?w73_c:((dense_en==1)?w73_d:0); assign w81=(conv_en==1)?w81_c:((dense_en==1)?w81_d:0); assign w82=(conv_en==1)?w82_c:((dense_en==1)?w82_d:0); assign w83=(conv_en==1)?w83_c:((dense_en==1)?w83_d:0); assign TOPlvl=TOPlvl_conv; assign go_conv=(conv_en==1)?go_conv_TOP:((dense_en==1)?go_dense:0); assign RESULT=(STOP)?res_out:4'b1111; endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/addressRAM.v ================================================ module addressRAM( input [6:0] step, output reg re_weights, output reg re_bias, output reg [17:0] firstaddr, lastaddr ); parameter convolution_size = 9; parameter conv1 = 1*8*3 * convolution_size; parameter conv2_1 = 8 * convolution_size + conv1; parameter conv2_2 = (8*8*2) + conv2_1; parameter conv3_1 = 16 * convolution_size + conv2_2; parameter conv3_2 = (16*16*2) + conv3_1; parameter conv4_1 = 32 * convolution_size + conv3_2; parameter conv4_2 = (32*32) + conv4_1; parameter conv5_1 = 32 * convolution_size + conv4_2; parameter conv5_2 = (32*32*2) + conv5_1; parameter conv6_1 = 64 * convolution_size + conv5_2; parameter conv6_2 = (64*64) + conv6_1; parameter conv7_1 = 64 * convolution_size + conv6_2; parameter conv7_2 = (64*64*2) + conv7_1; parameter conv8_1 = 128 * convolution_size + conv7_2; parameter conv8_2 = (128*128) + conv8_1; parameter conv9_1 = 128 * convolution_size + conv8_2; parameter conv9_2 = (128*128) + conv9_1; parameter conv10_1 = 128 * convolution_size + conv9_2; parameter conv10_2 = (128*128) + conv10_1; parameter conv11_1 = 128 * convolution_size + conv10_2; parameter conv11_2 = (128*128) + conv11_1; parameter conv12_1 = 128 * convolution_size + conv11_2; parameter conv12_2 = (128*128) + conv12_1; parameter conv13_1 = 128 * convolution_size + conv12_2; parameter conv13_2 = (128*128*2) + conv13_1; parameter conv14_1 = 256 * convolution_size + conv13_2; parameter conv14_2_1 = ((256*256)>>1) + conv14_1; parameter conv14_2_2 = ((256*256)>>1) + conv14_2_1; parameter predict = 512 + conv14_2_2; parameter bias1 = 8; parameter bias2_1 = (8)+8; parameter bias2_2 = (16)+16; parameter bias3_1 = (32)+16; parameter bias3_2 = (48)+32; parameter bias4_1 = (80)+32; parameter bias4_2 = (112)+32; parameter bias5_1 = (144)+32; parameter bias5_2 = (176)+64; parameter bias6_1 = (240)+64; parameter bias6_2 = (304)+64; parameter bias7_1 = (368)+64; parameter bias7_2 = (432)+128; parameter bias8_1 = (560)+128; parameter bias8_2 = (688)+128; parameter bias9_1 = (816)+128; parameter bias9_2 = (944)+128; parameter bias10_1 = (1072)+128; parameter bias10_2 = (1200)+128; parameter bias11_1 = (1328)+128; parameter bias11_2 = (1456)+128; parameter bias12_1 = (1584)+128; parameter bias12_2 = (1712)+128; parameter bias13_1 = (1840)+128; parameter bias13_2 = (1968)+256; parameter bias14_1 = (2224)+256; parameter bias14_2_1 = (2480)+(256>>1); parameter bias14_2_2 = (2608)+(256>>1); always @(step) case (step) 8'd1: begin //weights conv1 firstaddr = 0; lastaddr = conv1; re_weights = 1; re_bias = 0; end 8'd2: begin //bias conv1 firstaddr = 0; lastaddr = bias1; re_weights = 0; re_bias = 1; end 8'd4: begin //weights conv2 dw 1 firstaddr = conv1; lastaddr = conv2_1; re_weights = 1; re_bias = 0; end 8'd5: begin //bias conv2 dw firstaddr = bias1; lastaddr = bias2_1; re_weights = 0; re_bias = 1; end 8'd7: begin //weights conv2 1x1 firstaddr = conv2_1; lastaddr = conv2_2; re_weights = 1; re_bias = 0; end 8'd8: begin //bias conv2 1x1 firstaddr = bias2_1; lastaddr = bias2_2; re_weights = 0; re_bias = 1; end 8'd10: begin //weights conv3 dw 2 firstaddr = conv2_2; lastaddr = conv3_1; re_weights = 1; re_bias = 0; end 8'd11: begin //bias conv3 DW firstaddr = bias2_2; lastaddr = bias3_1; re_weights = 0; re_bias = 1; end 8'd13: begin //weights conv3 1x1 firstaddr = conv3_1; lastaddr = conv3_2; re_weights = 1; re_bias = 0; end 8'd14: begin //bias conv firstaddr = bias3_1; lastaddr = bias3_2; re_weights = 0; re_bias = 1; end 8'd16: begin firstaddr = conv3_2; // dw 3 lastaddr = conv4_1; re_weights = 1; re_bias = 0; end 8'd17: begin firstaddr = bias3_2; lastaddr = bias4_1; re_weights = 0; re_bias = 1; end 8'd19: begin firstaddr = conv4_1; lastaddr = conv4_2; re_weights = 1; re_bias = 0; end 8'd20: begin firstaddr = bias4_1; lastaddr = bias4_2; re_weights = 0; re_bias = 1; end 8'd22: begin firstaddr = conv4_2; // dw 4 lastaddr = conv5_1; re_weights = 1; re_bias = 0; end 8'd23: begin firstaddr = bias4_2; lastaddr = bias5_1; re_weights = 0; re_bias = 1; end 8'd25: begin firstaddr = conv5_1; lastaddr = conv5_2; re_weights = 1; re_bias = 0; end 8'd26: begin firstaddr = bias5_1; lastaddr = bias5_2; re_weights = 0; re_bias = 1; end 8'd28: begin firstaddr = conv5_2; // dw 5 lastaddr = conv6_1; re_weights = 1; re_bias = 0; end 8'd29: begin firstaddr = bias5_2; lastaddr = bias6_1; re_weights = 0; re_bias = 1; end 8'd31: begin firstaddr = conv6_1; lastaddr = conv6_2; re_weights = 1; re_bias = 0; end 8'd32: begin firstaddr = bias6_1; lastaddr = bias6_2; re_weights = 0; re_bias = 1; end 8'd34: begin firstaddr = conv6_2; // dw 6 lastaddr = conv7_1; re_weights = 1; re_bias = 0; end 8'd35: begin firstaddr = bias6_2; lastaddr = bias7_1; re_weights = 0; re_bias = 1; end 8'd37: begin firstaddr = conv7_1; lastaddr = conv7_2; re_weights = 1; re_bias = 0; end 8'd38: begin firstaddr = bias7_1; lastaddr = bias7_2; re_weights = 0; re_bias = 1; end 8'd40: begin firstaddr = conv7_2; // dw 7 lastaddr = conv8_1; re_weights = 1; re_bias = 0; end 8'd41: begin firstaddr = bias7_2; lastaddr = bias8_1; re_weights = 0; re_bias = 1; end 8'd43: begin firstaddr = conv8_1; lastaddr = conv8_2; re_weights = 1; re_bias = 0; end 8'd44: begin firstaddr = bias8_1; lastaddr = bias8_2; re_weights = 0; re_bias = 1; end 8'd46: begin firstaddr = conv8_2; // dw 8 lastaddr = conv9_1; re_weights = 1; re_bias = 0; end 8'd47: begin firstaddr = bias8_2; lastaddr = bias9_1; re_weights = 0; re_bias = 1; end 8'd49: begin firstaddr = conv9_1; lastaddr = conv9_2; re_weights = 1; re_bias = 0; end 8'd50: begin firstaddr = bias9_1; lastaddr = bias9_2; re_weights = 0; re_bias = 1; end 8'd52: begin firstaddr = conv9_2; // dw 9 lastaddr = conv10_1; re_weights = 1; re_bias = 0; end 8'd53: begin firstaddr = bias9_2; lastaddr = bias10_1; re_weights = 0; re_bias = 1; end 8'd55: begin firstaddr = conv10_1; lastaddr = conv10_2; re_weights = 1; re_bias = 0; end 8'd56: begin firstaddr = bias10_1; lastaddr = bias10_2; re_weights = 0; re_bias = 1; end 8'd58: begin firstaddr = conv10_2; // dw 10 lastaddr = conv11_1; re_weights = 1; re_bias = 0; end 8'd59: begin firstaddr = bias10_2; lastaddr = bias11_1; re_weights = 0; re_bias = 1; end 8'd61: begin firstaddr = conv11_1; lastaddr = conv11_2; re_weights = 1; re_bias = 0; end 8'd62: begin firstaddr = bias11_1; lastaddr = bias11_2; re_weights = 0; re_bias = 1; end 8'd64: begin firstaddr = conv11_2; // dw 11 lastaddr = conv12_1; re_weights = 1; re_bias = 0; end 8'd65: begin firstaddr = bias11_2; lastaddr = bias12_1; re_weights = 0; re_bias = 1; end 8'd67: begin firstaddr = conv12_1; lastaddr = conv12_2; re_weights = 1; re_bias = 0; end 8'd68: begin firstaddr = bias12_1; lastaddr = bias12_2; re_weights = 0; re_bias = 1; end 8'd70: begin firstaddr = conv12_2; // dw 12 lastaddr = conv13_1; re_weights = 1; re_bias = 0; end 8'd71: begin firstaddr = bias12_2; lastaddr = bias13_1; re_weights = 0; re_bias = 1; end 8'd73: begin firstaddr = conv13_1; lastaddr = conv13_2; re_weights = 1; re_bias = 0; end 8'd74: begin firstaddr = bias13_1; lastaddr = bias13_2; re_weights = 0; re_bias = 1; end 8'd76: begin firstaddr = conv13_2; // dw 13 lastaddr = conv14_1; re_weights = 1; re_bias = 0; end 8'd77: begin firstaddr = bias13_2; lastaddr = bias14_1; re_weights = 0; re_bias = 1; end 8'd79: begin firstaddr = conv14_1; lastaddr = conv14_2_1; re_weights = 1; re_bias = 0; end 8'd80: begin firstaddr = bias14_1; lastaddr = bias14_2_1; re_weights = 0; re_bias = 1; end 8'd82: begin firstaddr = conv14_2_1; lastaddr = conv14_2_2; re_weights = 1; re_bias = 0; end 8'd83: begin firstaddr = bias14_2_1; lastaddr = bias14_2_2; re_weights = 0; re_bias = 1; end 8'd85: begin firstaddr = conv14_2_2; lastaddr = predict; re_weights = 1; re_bias = 0; end default: begin re_weights = 0; re_bias = 0; end endcase endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/border.v ================================================ module border( input clk, go, input [14:0] i, input [7:0] matrix, output reg [1:0] prov ); always @(posedge clk) begin if (go == 1) begin prov = 0; if ((i == 1*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 2*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 3*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 4*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 5*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 6*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 7*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 8*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 9*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 10*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 11*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 12*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 13*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 14*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 15*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 16*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 17*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 18*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 19*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 20*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 21*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 22*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 23*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 24*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 25*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 26*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 27*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 28*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 29*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 30*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 31*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 32*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 33*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 34*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 35*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 36*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 37*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 38*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 39*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 40*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 41*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 42*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 43*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 44*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 45*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 46*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 47*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 48*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 49*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 50*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 51*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 52*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 53*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 54*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 55*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 56*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 57*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 58*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 59*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 60*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 61*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 62*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 63*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 64*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 65*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 66*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 67*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 68*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 69*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 70*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 71*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 72*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 73*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 74*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 75*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 76*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 77*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 78*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 79*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 80*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 81*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 82*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 83*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 84*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 85*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 86*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 87*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 88*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 89*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 90*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 91*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 92*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 93*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 94*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 95*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 96*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 97*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 98*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 99*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 100*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 101*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 102*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 103*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 104*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 105*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 106*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 107*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 108*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 109*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 110*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 111*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 112*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 113*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 114*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 115*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 116*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 117*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 118*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 119*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 120*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 121*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 122*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 123*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 124*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 125*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 126*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 127*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 128*matrix-1'b1) && (prov != 2'b10)) prov = 2'b10; if ((i == 0*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 1*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 2*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 3*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 4*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 5*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 6*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 7*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 8*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 9*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 10*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 11*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 12*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 13*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 14*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 15*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 16*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 17*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 18*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 19*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 20*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 21*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 22*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 23*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 24*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 25*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 26*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 27*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 28*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 29*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 30*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 31*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 32*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 33*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 34*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 35*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 36*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 37*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 38*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 39*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 40*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 41*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 42*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 43*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 44*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 45*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 46*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 47*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 48*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 49*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 50*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 51*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 52*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 53*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 54*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 55*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 56*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 57*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 58*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 59*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 60*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 61*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 62*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 63*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 64*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 65*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 66*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 67*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 68*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 69*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 70*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 71*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 72*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 73*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 74*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 75*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 76*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 77*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 78*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 79*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 80*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 81*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 82*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 83*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 84*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 85*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 86*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 87*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 88*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 89*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 90*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 91*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 92*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 93*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 94*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 95*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 96*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 97*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 98*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 99*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 100*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 101*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 102*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 103*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 104*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 105*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 106*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 107*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 108*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 109*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 110*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 111*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 112*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 113*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 114*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 115*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 116*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 117*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 118*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 119*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 120*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 121*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 122*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 123*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 124*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 125*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 126*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 127*matrix) && (prov != 2'b11)) prov = 2'b11; if ((i == 128*matrix) && (prov != 2'b11)) prov = 2'b11; end else prov = 0; end endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/conv.v ================================================ module conv(clk,Y1,prov,matrix,matrix2,i,up_perm,down_perm,p1,p2,p3,w1,w2,w3,conv_en,dense_en,stride_plus_prov); parameter SIZE=0; parameter SIZE_address_pix=18; parameter SIZE_weights=0; input clk; output reg signed [32-1:0] Y1; input [1:0] prov; input [7:0] matrix; input [14:0] matrix2; input [14:0] i; input up_perm,down_perm; input signed [SIZE-1:0] p1,p2,p3; input signed [SIZE_weights-1:0] w1,w2,w3; input conv_en; input dense_en; input [SIZE_address_pix-1:0] stride_plus_prov; wire up,down; assign up = (((i+stride_plus_prov)<=matrix-1'b1)&&(up_perm))?1'b1:1'b0; assign down = (((i+stride_plus_prov)>=matrix2-matrix)&&(down_perm))?1'b1:1'b0; always @(posedge clk) begin if (conv_en==1) begin Y1=0; if ((prov!=2'b11)&&(!up)&&(!down)) Y1 = Y1+(p1*w1); if ((!up)&&(!down)) Y1 = Y1+(p2*w2); if ((prov!=2'b10)&&(!up)&&(!down)) Y1 = Y1+(p3*w3); end end endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/conv_TOP.v ================================================ module conv_TOP(clk,conv_en,STOP,memstartp,memstartw,memstartzap,read_addressp,write_addressp,read_addresstp,write_addresstp,read_addressw,we,re_wb,re,we_t,re_t,qp,qtp,qw,dp,dtp,prov,matrix,matrix2,i_to_prov,lvl,slvl,mem,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83,p0_1,p0_2,p0_3,p1_1,p1_2,p1_3,p2_1,p2_2,p2_3,p3_1,p3_2,p3_3,p4_1,p4_2,p4_3,p5_1,p5_2,p5_3,p6_1,p6_2,p6_3,p7_1,p7_2,p7_3,go,up_perm,down_perm,num,filt,bias,glob_average_en,step,stride,depthwise,onexone,q_bias,read_addressb,memstartb,stride_plus_prov); parameter SIZE_1=0; parameter SIZE_2=0; parameter SIZE_3=0; parameter SIZE_4=0; parameter SIZE_5=0; parameter SIZE_6=0; parameter SIZE_7=0; parameter SIZE_8=0; parameter SIZE_address_pix=13; parameter SIZE_address_pix_t=12; parameter SIZE_address_wei=13; parameter SIZE_weights=0; parameter SIZE_bias=0; input clk,conv_en,glob_average_en; input [1:0] prov; input [7:0] matrix; input [14:0] matrix2; input [SIZE_address_pix-1:0] memstartp; input [SIZE_address_wei-1:0] memstartw; input [SIZE_address_pix-1:0] memstartzap; input [10:0] memstartb; input [8:0] lvl; input [8:0] slvl; output reg [SIZE_address_pix-1:0] read_addressp; output reg [SIZE_address_pix_t-1:0] read_addresstp; output reg [SIZE_address_wei-1:0] read_addressw; output reg [10:0] read_addressb; output reg [SIZE_address_pix-1:0] write_addressp; output reg [SIZE_address_pix_t-1:0] write_addresstp; output reg we,re,re_wb; output reg we_t,re_t; input signed [SIZE_8-1:0] qp; input signed [32*8-1:0] qtp; input signed [SIZE_weights*9-1:0] qw; input signed [SIZE_bias-1:0] q_bias; output signed [SIZE_8-1:0] dp; output signed [32*8-1:0] dtp; output reg STOP; output reg [14:0] i_to_prov; input signed [32-1:0] Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8; output reg signed [SIZE_weights-1:0] w11,w12,w13,w21,w22,w23,w31,w32,w33,w41,w42,w43,w51,w52,w53,w61,w62,w63,w71,w72,w73,w81,w82,w83; output reg signed [SIZE_1-1:0] p0_1,p0_2,p0_3,p1_1,p1_2,p1_3,p2_1,p2_2,p2_3,p3_1,p3_2,p3_3,p4_1,p4_2,p4_3,p5_1,p5_2,p5_3,p6_1,p6_2,p6_3,p7_1,p7_2,p7_3; output reg go; output reg up_perm,down_perm; input [2:0] num; input [8:0] mem; input [8:0] filt; input bias; input [6:0] step; input [1:0] stride; output reg [SIZE_address_pix-1:0] stride_plus_prov; input depthwise,onexone; reg signed [SIZE_weights-1:0] w11_pre,w12_pre,w13_pre,w14_pre,w15_pre,w16_pre,w17_pre,w18_pre,w19_pre; reg signed [SIZE_weights-1:0] w21_pre,w22_pre,w23_pre,w24_pre,w25_pre,w26_pre,w27_pre,w28_pre,w29_pre; reg signed [SIZE_weights-1:0] w31_pre,w32_pre,w33_pre,w34_pre,w35_pre,w36_pre,w37_pre,w38_pre,w39_pre; reg signed [SIZE_weights-1:0] w41_pre,w42_pre,w43_pre,w44_pre,w45_pre,w46_pre,w47_pre,w48_pre,w49_pre; reg signed [SIZE_weights-1:0] w51_pre,w52_pre,w53_pre,w54_pre,w55_pre,w56_pre,w57_pre,w58_pre,w59_pre; reg signed [SIZE_weights-1:0] w61_pre,w62_pre,w63_pre,w64_pre,w65_pre,w66_pre,w67_pre,w68_pre,w69_pre; reg signed [SIZE_weights-1:0] w71_pre,w72_pre,w73_pre,w74_pre,w75_pre,w76_pre,w77_pre,w78_pre,w79_pre; reg signed [SIZE_weights-1:0] w81_pre,w82_pre,w83_pre,w84_pre,w85_pre,w86_pre,w87_pre,w88_pre,w89_pre; reg signed [SIZE_1-1:0]p0_pre,p1_pre,p2_pre,p3_pre,p4_pre,p5_pre,p6_pre,p7_pre,p8_pre,p9_pre,p10_pre,p11_pre,p12_pre,p13_pre,p14_pre,p15_pre; reg signed [SIZE_1-1:0] res_out_1,res_out_2,res_out_3,res_out_4,res_out_5,res_out_6,res_out_7,res_out_8; reg signed [32-1:0] res1,res2,res3,res4,res5,res6,res7,res8; reg signed [32-1:0] res_old_1,res_old_2,res_old_3,res_old_4,res_old_5,res_old_6,res_old_7,res_old_8; reg signed [21:0] glob_average_perem_1,glob_average_perem_2,glob_average_perem_3,glob_average_perem_4,glob_average_perem_5,glob_average_perem_6,glob_average_perem_7,glob_average_perem_8; wire signed [SIZE_1-1:0] glob_average_perem_1_1,glob_average_perem_2_1,glob_average_perem_3_1,glob_average_perem_4_1,glob_average_perem_5_1,glob_average_perem_6_1,glob_average_perem_7_1,glob_average_perem_8_1; reg signed [SIZE_1-1:0]buff0_0 [2:0], buff1_0 [2:0], buff2_0 [2:0], buff3_0 [2:0], buff4_0 [2:0], buff5_0 [2:0], buff6_0 [2:0], buff7_0 [2:0]; reg signed [SIZE_1-1:0]buff0_1 [2:0], buff1_1 [2:0], buff2_1 [2:0], buff3_1 [2:0], buff4_1 [2:0], buff5_1 [2:0], buff6_1 [2:0], buff7_1 [2:0]; reg signed [SIZE_1-1:0]buff0_2 [2:0], buff1_2 [2:0], buff2_2 [2:0], buff3_2 [2:0], buff4_2 [2:0], buff5_2 [2:0], buff6_2 [2:0], buff7_2 [2:0]; reg [4:0] marker; reg zagryzka_weight; reg [15:0] i; reg [15:0] i_onexone,i_onexone_1; wire [15:0] i_onexone_plus1; assign i_onexone_plus1 = i_onexone + 1'b1; reg [SIZE_address_pix-1:0] stride_plus,next_number,next_number_prov; reg signed [19-1:0] res_bias_check_1,res_bias_check_2,res_bias_check_3,res_bias_check_4,res_bias_check_5,res_bias_check_6,res_bias_check_7,res_bias_check_8; reg signed [SIZE_bias-1:0] data_bias_1,data_bias_2,data_bias_3,data_bias_4,data_bias_5,data_bias_6,data_bias_7,data_bias_8; initial zagryzka_weight=0; initial marker=0; wire [15:0] line_stride; assign line_stride=matrix>>(stride-1); always @(posedge clk) begin if (conv_en==1) begin if (zagryzka_weight==0) begin next_number = matrix; next_number_prov = matrix; if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus=0; else stride_plus=matrix; if ((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72)) stride_plus_prov=0; else stride_plus_prov=matrix; case (marker) 0: begin re_wb=1; read_addressw=memstartw+0*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+0; end 1: begin read_addressw=memstartw+1*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+1; end 2: begin read_addressw=memstartw+2*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+2; w11_pre=qw[SIZE_weights-1:0]; w12_pre=qw[SIZE_weights*2-1:SIZE_weights]; w13_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w14_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w15_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w16_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w17_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w18_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w19_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_1 = q_bias; end 3: begin read_addressw=memstartw+3*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+3; w21_pre=qw[SIZE_weights-1:0]; w22_pre=qw[SIZE_weights*2-1:SIZE_weights]; w23_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w24_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w25_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w26_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w27_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w28_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w29_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_2 = q_bias; end 4: begin read_addressw=memstartw+4*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+4; w31_pre=qw[SIZE_weights-1:0]; w32_pre=qw[SIZE_weights*2-1:SIZE_weights]; w33_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w34_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w35_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w36_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w37_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w38_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w39_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_3 = q_bias; end 5: begin read_addressw=memstartw+5*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+5; w41_pre=qw[SIZE_weights-1:0]; w42_pre=qw[SIZE_weights*2-1:SIZE_weights]; w43_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w44_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w45_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w46_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w47_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w48_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w49_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_4 = q_bias; end 6: begin read_addressw=memstartw+6*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+6; w51_pre=qw[SIZE_weights-1:0]; w52_pre=qw[SIZE_weights*2-1:SIZE_weights]; w53_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w54_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w55_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w56_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w57_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w58_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w59_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_5 = q_bias; end 7: begin read_addressw=memstartw+7*((depthwise)?1:((onexone)?((mem+1)>>3):(filt+1))); read_addressb=memstartb+7; w61_pre=qw[SIZE_weights-1:0]; w62_pre=qw[SIZE_weights*2-1:SIZE_weights]; w63_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w64_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w65_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w66_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w67_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w68_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w69_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_6 = q_bias; end 8: begin w71_pre=qw[SIZE_weights-1:0]; w72_pre=qw[SIZE_weights*2-1:SIZE_weights]; w73_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w74_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w75_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w76_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w77_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w78_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w79_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_7 = q_bias; end 9: begin w81_pre=qw[SIZE_weights-1:0]; w82_pre=qw[SIZE_weights*2-1:SIZE_weights]; w83_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w84_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w85_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w86_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w87_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w88_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w89_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; data_bias_8 = q_bias; zagryzka_weight=1; re_wb=0; marker=-1; end default: begin read_addressw=0; read_addressb=0; re_wb=0; $display("Check zagryzka_weight"); end endcase marker=marker+1; end else begin re=1; case (marker) 0: begin re_t=0; if ((stride==2)&&(i==next_number)) begin stride_plus=stride_plus+matrix; next_number = matrix+next_number; end if (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1; else read_addressp=i+memstartp+stride_plus; if (onexone) begin p0_1=p6_pre; p0_2=p7_pre; p0_3=0; p1_1=p6_pre; p1_2=p7_pre; p1_3=0; p2_1=p6_pre; p2_2=p7_pre; p2_3=0; p3_1=p6_pre; p3_2=p7_pre; p3_3=0; p4_1=p6_pre; p4_2=p7_pre; p4_3=0; p5_1=p6_pre; p5_2=p7_pre; p5_3=0; p6_1=p6_pre; p6_2=p7_pre; p6_3=0; p7_1=p6_pre; p7_2=p7_pre; p7_3=0; end else begin if (depthwise) begin buff0_2[2]=qp[SIZE_8-1:SIZE_7]; buff1_2[2]=qp[SIZE_7-1:SIZE_6]; buff2_2[2]=qp[SIZE_6-1:SIZE_5]; buff3_2[2]=qp[SIZE_5-1:SIZE_4]; buff4_2[2]=qp[SIZE_4-1:SIZE_3]; buff5_2[2]=qp[SIZE_3-1:SIZE_2]; buff6_2[2]=qp[SIZE_2-1:SIZE_1]; buff7_2[2]=qp[SIZE_1-1:0]; end else begin if (((i+stride_plus-1)=matrix-1) read_addressp=i-matrix+memstartp+stride_plus; res1=res1+Y1; res2=res2+Y2; res3=res3+Y3; res4=res4+Y4; res5=res5+Y5; res6=res6+Y6; res7=res7+Y7; res8=res8+Y8; if ((i>=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1))) begin res_old_1=qtp[32*8-1:32*7]; res_old_2=qtp[32*7-1:32*6]; res_old_3=qtp[32*6-1:32*5]; res_old_4=qtp[32*5-1:32*4]; res_old_5=qtp[32*4-1:32*3]; res_old_6=qtp[32*3-1:32*2]; res_old_7=qtp[32*2-1:32*1]; res_old_8=qtp[32*1-1:32*0]; end go=0; i_to_prov=i_to_prov+1'b1; if ((stride==2)&&(i_to_prov==next_number_prov)) begin stride_plus_prov=stride_plus_prov+matrix; next_number_prov = matrix+next_number_prov; end buff0_2[0]=buff0_2[1]; buff0_1[0]=buff0_1[1]; buff0_0[0]=buff0_0[1]; buff0_2[1]=buff0_2[2]; buff0_1[1]=buff0_1[2]; buff0_0[1]=buff0_0[2]; buff1_2[0]=buff1_2[1]; buff1_1[0]=buff1_1[1]; buff1_0[0]=buff1_0[1]; buff1_2[1]=buff1_2[2]; buff1_1[1]=buff1_1[2]; buff1_0[1]=buff1_0[2]; buff2_2[0]=buff2_2[1]; buff2_1[0]=buff2_1[1]; buff2_0[0]=buff2_0[1]; buff2_2[1]=buff2_2[2]; buff2_1[1]=buff2_1[2]; buff2_0[1]=buff2_0[2]; buff3_2[0]=buff3_2[1]; buff3_1[0]=buff3_1[1]; buff3_0[0]=buff3_0[1]; buff3_2[1]=buff3_2[2]; buff3_1[1]=buff3_1[2]; buff3_0[1]=buff3_0[2]; buff4_2[0]=buff4_2[1]; buff4_1[0]=buff4_1[1]; buff4_0[0]=buff4_0[1]; buff4_2[1]=buff4_2[2]; buff4_1[1]=buff4_1[2]; buff4_0[1]=buff4_0[2]; buff5_2[0]=buff5_2[1]; buff5_1[0]=buff5_1[1]; buff5_0[0]=buff5_0[1]; buff5_2[1]=buff5_2[2]; buff5_1[1]=buff5_1[2]; buff5_0[1]=buff5_0[2]; buff6_2[0]=buff6_2[1]; buff6_1[0]=buff6_1[1]; buff6_0[0]=buff6_0[1]; buff6_2[1]=buff6_2[2]; buff6_1[1]=buff6_1[2]; buff6_0[1]=buff6_0[2]; buff7_2[0]=buff7_2[1]; buff7_1[0]=buff7_1[1]; buff7_0[0]=buff7_0[1]; buff7_2[1]=buff7_2[2]; buff7_1[1]=buff7_1[2]; buff7_0[1]=buff7_0[2]; end 2: begin if (onexone) read_addressp = memstartp+(matrix*matrix)*(3*i_onexone_1+marker)+i_onexone-1; else if ((i+stride_plus)=2)&&(((stride==2)&&((((step==3)||(step==12)||(step==24)||(step==36)||(step==72))&&(i[0]==1))||(((step!=3)&&(step!=12)&&(step!=24)&&(step!=36)&&(step!=72))&&(i[0]==0))))||(stride==1))) begin if (onexone) write_addresstp=i_onexone-2; else write_addresstp=(i>>(stride-1))-1; if (glob_average_en) write_addressp=memstartzap; else begin if (onexone) write_addressp=memstartzap+i_onexone-2; else write_addressp=memstartzap+((i-2)>>(stride-1)); end if (((onexone && (i_onexone_1 == 0)) || !onexone)&&(!bias)) we_t=1; res1=res1+Y1; res2=res2+Y2; res3=res3+Y3; res4=res4+Y4; res5=res5+Y5; res6=res6+Y6; res7=res7+Y7; res8=res8+Y8; if ((lvl!=0)&&(!depthwise)) begin res1=res1+res_old_1; res2=res2+res_old_2; res3=res3+res_old_3; res4=res4+res_old_4; res5=res5+res_old_5; res6=res6+res_old_6; res7=res7+res_old_7; res8=res8+res_old_8; end if (bias) begin res1=res1+(data_bias_1<<13); res2=res2+(data_bias_2<<13); res3=res3+(data_bias_3<<13); res4=res4+(data_bias_4<<13); res5=res5+(data_bias_5<<13); res6=res6+(data_bias_6<<13); res7=res7+(data_bias_7<<13); res8=res8+(data_bias_8<<13); if (res1<0) res1=0; //RELU if (res2<0) res2=0; //RELU if (res3<0) res3=0; //RELU if (res4<0) res4=0; //RELU if (res5<0) res5=0; //RELU if (res6<0) res6=0; //RELU if (res7<0) res7=0; //RELU if (res8<0) res8=0; //RELU res_bias_check_1=res1[32-1-2:SIZE_1-2]; res_bias_check_2=res2[32-1-2:SIZE_1-2]; res_bias_check_3=res3[32-1-2:SIZE_1-2]; res_bias_check_4=res4[32-1-2:SIZE_1-2]; res_bias_check_5=res5[32-1-2:SIZE_1-2]; res_bias_check_6=res6[32-1-2:SIZE_1-2]; res_bias_check_7=res7[32-1-2:SIZE_1-2]; res_bias_check_8=res8[32-1-2:SIZE_1-2]; if (res_bias_check_1>(2**(SIZE_1-1))-1) res_out_1=(2**(SIZE_1-1))-1; else res_out_1=res1[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_2>(2**(SIZE_1-1))-1) res_out_2=(2**(SIZE_1-1))-1; else res_out_2=res2[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_3>(2**(SIZE_1-1))-1) res_out_3=(2**(SIZE_1-1))-1; else res_out_3=res3[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_4>(2**(SIZE_1-1))-1) res_out_4=(2**(SIZE_1-1))-1; else res_out_4=res4[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_5>(2**(SIZE_1-1))-1) res_out_5=(2**(SIZE_1-1))-1; else res_out_5=res5[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_6>(2**(SIZE_1-1))-1) res_out_6=(2**(SIZE_1-1))-1; else res_out_6=res6[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_7>(2**(SIZE_1-1))-1) res_out_7=(2**(SIZE_1-1))-1; else res_out_7=res7[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if (res_bias_check_8>(2**(SIZE_1-1))-1) res_out_8=(2**(SIZE_1-1))-1; else res_out_8=res8[SIZE_1+SIZE_1-2-2:SIZE_1-2]; if ((glob_average_en)&&(i_onexone_1 == 0)) begin glob_average_perem_1 = glob_average_perem_1 + res_out_1; glob_average_perem_2 = glob_average_perem_2 + res_out_2; glob_average_perem_3 = glob_average_perem_3 + res_out_3; glob_average_perem_4 = glob_average_perem_4 + res_out_4; glob_average_perem_5 = glob_average_perem_5 + res_out_5; glob_average_perem_6 = glob_average_perem_6 + res_out_6; glob_average_perem_7 = glob_average_perem_7 + res_out_7; glob_average_perem_8 = glob_average_perem_8 + res_out_8; end if ((onexone && (i_onexone_1 == 0)) || !onexone) we=1; end end end 3: begin re_t=1; if (onexone) read_addresstp=i_onexone-1; else read_addresstp=(i>>(stride-1))-1; if (onexone) begin p8_pre = qp[SIZE_8-1:SIZE_7]; p9_pre = qp[SIZE_7-1:SIZE_6]; p10_pre = qp[SIZE_6-1:SIZE_5]; p11_pre = qp[SIZE_5-1:SIZE_4]; p12_pre = qp[SIZE_4-1:SIZE_3]; p13_pre = qp[SIZE_3-1:SIZE_2]; p14_pre = qp[SIZE_2-1:SIZE_1]; p15_pre = qp[SIZE_1-1:0]; p0_1=p3_pre; p0_2=p4_pre; p0_3=p5_pre; p1_1=p3_pre; p1_2=p4_pre; p1_3=p5_pre; p2_1=p3_pre; p2_2=p4_pre; p2_3=p5_pre; p3_1=p3_pre; p3_2=p4_pre; p3_3=p5_pre; p4_1=p3_pre; p4_2=p4_pre; p4_3=p5_pre; p5_1=p3_pre; p5_2=p4_pre; p5_3=p5_pre; p6_1=p3_pre; p6_2=p4_pre; p6_3=p5_pre; p7_1=p3_pre; p7_2=p4_pre; p7_3=p5_pre; end else begin if (depthwise) begin buff0_0[2]=qp[SIZE_8-1:SIZE_7]; buff1_0[2]=qp[SIZE_7-1:SIZE_6]; buff2_0[2]=qp[SIZE_6-1:SIZE_5]; buff3_0[2]=qp[SIZE_5-1:SIZE_4]; buff4_0[2]=qp[SIZE_4-1:SIZE_3]; buff5_0[2]=qp[SIZE_3-1:SIZE_2]; buff6_0[2]=qp[SIZE_2-1:SIZE_1]; buff7_0[2]=qp[SIZE_1-1:0]; end else begin if ((i+stride_plus)>=matrix-1) begin if ({lvl[2],lvl[1],lvl[0]}==3'd0) begin buff0_0[2]=qp[SIZE_8-1:SIZE_7]; buff1_0[2]=qp[SIZE_8-1:SIZE_7]; buff2_0[2]=qp[SIZE_8-1:SIZE_7]; buff3_0[2]=qp[SIZE_8-1:SIZE_7]; buff4_0[2]=qp[SIZE_8-1:SIZE_7]; buff5_0[2]=qp[SIZE_8-1:SIZE_7]; buff6_0[2]=qp[SIZE_8-1:SIZE_7]; buff7_0[2]=qp[SIZE_8-1:SIZE_7]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd1) begin buff0_0[2]=qp[SIZE_7-1:SIZE_6]; buff1_0[2]=qp[SIZE_7-1:SIZE_6]; buff2_0[2]=qp[SIZE_7-1:SIZE_6]; buff3_0[2]=qp[SIZE_7-1:SIZE_6]; buff4_0[2]=qp[SIZE_7-1:SIZE_6]; buff5_0[2]=qp[SIZE_7-1:SIZE_6]; buff6_0[2]=qp[SIZE_7-1:SIZE_6]; buff7_0[2]=qp[SIZE_7-1:SIZE_6]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd2) begin buff0_0[2]=qp[SIZE_6-1:SIZE_5]; buff1_0[2]=qp[SIZE_6-1:SIZE_5]; buff2_0[2]=qp[SIZE_6-1:SIZE_5]; buff3_0[2]=qp[SIZE_6-1:SIZE_5]; buff4_0[2]=qp[SIZE_6-1:SIZE_5]; buff5_0[2]=qp[SIZE_6-1:SIZE_5]; buff6_0[2]=qp[SIZE_6-1:SIZE_5]; buff7_0[2]=qp[SIZE_6-1:SIZE_5]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd3) begin buff0_0[2]=qp[SIZE_5-1:SIZE_4]; buff1_0[2]=qp[SIZE_5-1:SIZE_4]; buff2_0[2]=qp[SIZE_5-1:SIZE_4]; buff3_0[2]=qp[SIZE_5-1:SIZE_4]; buff4_0[2]=qp[SIZE_5-1:SIZE_4]; buff5_0[2]=qp[SIZE_5-1:SIZE_4]; buff6_0[2]=qp[SIZE_5-1:SIZE_4]; buff7_0[2]=qp[SIZE_5-1:SIZE_4]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd4) begin buff0_0[2]=qp[SIZE_4-1:SIZE_3]; buff1_0[2]=qp[SIZE_4-1:SIZE_3]; buff2_0[2]=qp[SIZE_4-1:SIZE_3]; buff3_0[2]=qp[SIZE_4-1:SIZE_3]; buff4_0[2]=qp[SIZE_4-1:SIZE_3]; buff5_0[2]=qp[SIZE_4-1:SIZE_3]; buff6_0[2]=qp[SIZE_4-1:SIZE_3]; buff7_0[2]=qp[SIZE_4-1:SIZE_3]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd5) begin buff0_0[2]=qp[SIZE_3-1:SIZE_2]; buff1_0[2]=qp[SIZE_3-1:SIZE_2]; buff2_0[2]=qp[SIZE_3-1:SIZE_2]; buff3_0[2]=qp[SIZE_3-1:SIZE_2]; buff4_0[2]=qp[SIZE_3-1:SIZE_2]; buff5_0[2]=qp[SIZE_3-1:SIZE_2]; buff6_0[2]=qp[SIZE_3-1:SIZE_2]; buff7_0[2]=qp[SIZE_3-1:SIZE_2]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd6) begin buff0_0[2]=qp[SIZE_2-1:SIZE_1]; buff1_0[2]=qp[SIZE_2-1:SIZE_1]; buff2_0[2]=qp[SIZE_2-1:SIZE_1]; buff3_0[2]=qp[SIZE_2-1:SIZE_1]; buff4_0[2]=qp[SIZE_2-1:SIZE_1]; buff5_0[2]=qp[SIZE_2-1:SIZE_1]; buff6_0[2]=qp[SIZE_2-1:SIZE_1]; buff7_0[2]=qp[SIZE_2-1:SIZE_1]; end else if ({lvl[2],lvl[1],lvl[0]}==3'd7) begin buff0_0[2]=qp[SIZE_1-1:0]; buff1_0[2]=qp[SIZE_1-1:0]; buff2_0[2]=qp[SIZE_1-1:0]; buff3_0[2]=qp[SIZE_1-1:0]; buff4_0[2]=qp[SIZE_1-1:0]; buff5_0[2]=qp[SIZE_1-1:0]; buff6_0[2]=qp[SIZE_1-1:0]; buff7_0[2]=qp[SIZE_1-1:0]; end end else begin buff0_0[2]=0; buff1_0[2]=0; buff2_0[2]=0; buff3_0[2]=0; buff4_0[2]=0; buff5_0[2]=0; buff6_0[2]=0; buff7_0[2]=0; end end p0_1=buff0_0[0]; p0_2=buff0_0[1]; p0_3=buff0_0[2]; p1_1=buff1_0[0]; p1_2=buff1_0[1]; p1_3=buff1_0[2]; p2_1=buff2_0[0]; p2_2=buff2_0[1]; p2_3=buff2_0[2]; p3_1=buff3_0[0]; p3_2=buff3_0[1]; p3_3=buff3_0[2]; p4_1=buff4_0[0]; p4_2=buff4_0[1]; p4_3=buff4_0[2]; p5_1=buff5_0[0]; p5_2=buff5_0[1]; p5_3=buff5_0[2]; p6_1=buff6_0[0]; p6_2=buff6_0[1]; p6_3=buff6_0[2]; p7_1=buff7_0[0]; p7_2=buff7_0[1]; p7_3=buff7_0[2]; end w11=(onexone)?w16_pre:w19_pre; w12=(onexone)?w15_pre:w18_pre; w13=(onexone)?w14_pre:w17_pre; w21=(onexone)?w26_pre:w29_pre; w22=(onexone)?w25_pre:w28_pre; w23=(onexone)?w24_pre:w27_pre; w31=(onexone)?w36_pre:w39_pre; w32=(onexone)?w35_pre:w38_pre; w33=(onexone)?w34_pre:w37_pre; w41=(onexone)?w46_pre:w49_pre; w42=(onexone)?w45_pre:w48_pre; w43=(onexone)?w44_pre:w47_pre; w51=(onexone)?w56_pre:w59_pre; w52=(onexone)?w55_pre:w58_pre; w53=(onexone)?w54_pre:w57_pre; w61=(onexone)?w66_pre:w69_pre; w62=(onexone)?w65_pre:w68_pre; w63=(onexone)?w64_pre:w67_pre; w71=(onexone)?w76_pre:w79_pre; w72=(onexone)?w75_pre:w78_pre; w73=(onexone)?w74_pre:w77_pre; w81=(onexone)?w86_pre:w89_pre; w82=(onexone)?w85_pre:w88_pre; w83=(onexone)?w84_pre:w87_pre; if (onexone) up_perm=0; else up_perm=1; down_perm=0; we_t=0; we=0; end default: $display("Check case conv_TOP"); endcase if (marker!=3) marker=marker+1; else begin marker=0; if (((i>2) begin i_onexone = i_onexone + 1; i_onexone_1 = 0; end else i_onexone_1 = i_onexone_1 + 1; end end else STOP=1; end end end else begin i=0; i_to_prov=-2; stride_plus=0; next_number=matrix; zagryzka_weight=0; STOP=0; re=0; re_t=0; go=0; marker=0; glob_average_perem_1=0; glob_average_perem_2=0; glob_average_perem_3=0; glob_average_perem_4=0; glob_average_perem_5=0; glob_average_perem_6=0; glob_average_perem_7=0; glob_average_perem_8=0; i_onexone = 0; i_onexone_1 = 0; read_addressw=0; read_addressb=0; re_wb=0; end end assign glob_average_perem_1_1=glob_average_perem_1>>4; assign glob_average_perem_2_1=glob_average_perem_2>>4; assign glob_average_perem_3_1=glob_average_perem_3>>4; assign glob_average_perem_4_1=glob_average_perem_4>>4; assign glob_average_perem_5_1=glob_average_perem_5>>4; assign glob_average_perem_6_1=glob_average_perem_6>>4; assign glob_average_perem_7_1=glob_average_perem_7>>4; assign glob_average_perem_8_1=glob_average_perem_8>>4; assign dp={(glob_average_en?glob_average_perem_1_1:res_out_1), (glob_average_en?glob_average_perem_2_1:res_out_2), (glob_average_en?glob_average_perem_3_1:res_out_3), (glob_average_en?glob_average_perem_4_1:res_out_4), (glob_average_en?glob_average_perem_5_1:res_out_5), (glob_average_en?glob_average_perem_6_1:res_out_6), (glob_average_en?glob_average_perem_7_1:res_out_7), (glob_average_en?glob_average_perem_8_1:res_out_8) }; assign dtp={res1,res2,res3,res4,res5,res6,res7,res8}; endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/dense.v ================================================ module dense(clk, dense_en, STOP, in, out, we, re_p, re_w, read_addressp, read_addressw, write_addressp, memstartp, memstartzap, qp, qw, res, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, w11, w12, w13, w21, w22, w23, w31, w32, w33, w41, w42, w43, w51, w52, w53, w61, w62, w63, w71, w72, w73, w81, w82, w83, p11, p12, p13, p21, p22, p23, p31, p32, p33, p41, p42, p43, p51, p52, p53, p61, p62, p63, p71, p72, p73, p81, p82, p83, go, nozero); parameter num_conv=0; parameter SIZE_1=0; parameter SIZE_2=0; parameter SIZE_3=0; parameter SIZE_4=0; parameter SIZE_5=0; parameter SIZE_6=0; parameter SIZE_7=0; parameter SIZE_8=0; parameter SIZE_address_pix=0; parameter SIZE_address_wei=0; parameter SIZE_weights=0; input clk,dense_en; output reg STOP; input [8:0] in; input [1:0] out; output reg we,re_p,re_w; output reg [SIZE_address_pix-1:0] read_addressp; output reg [SIZE_address_wei-1:0] read_addressw; output reg [SIZE_address_pix-1:0] write_addressp; input [SIZE_address_pix-1:0] memstartp,memstartzap; input signed [SIZE_8-1:0] qp; input signed [SIZE_weights*9-1:0] qw; output reg signed [SIZE_8-1:0] res; input signed [32-1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8; output reg signed [SIZE_weights - 1:0] w11, w12, w13, w21, w22, w23, w31, w32, w33, w41, w42, w43, w51, w52, w53, w61, w62, w63, w71, w72, w73, w81, w82, w83; output reg signed [SIZE_1-1:0] p11, p12, p13, p21, p22, p23, p31, p32, p33, p41, p42, p43, p51, p52, p53, p61, p62, p63, p71, p72, p73, p81, p82, p83; output reg go; input nozero; reg signed[SIZE_weights - 1:0] w11_pre, w12_pre, w13_pre, w14_pre, w15_pre, w16_pre, w17_pre, w18_pre, w19_pre; reg signed[SIZE_weights - 1:0] w21_pre, w22_pre, w23_pre, w24_pre, w25_pre, w26_pre, w27_pre, w28_pre, w29_pre; reg signed[SIZE_weights - 1:0] w31_pre, w32_pre, w33_pre, w34_pre, w35_pre, w36_pre, w37_pre, w38_pre, w39_pre; reg signed[SIZE_weights - 1:0] w41_pre, w42_pre, w43_pre, w44_pre, w45_pre, w46_pre, w47_pre, w48_pre, w49_pre; reg signed[SIZE_weights - 1:0] w51_pre, w52_pre, w53_pre, w54_pre, w55_pre, w56_pre, w57_pre, w58_pre, w59_pre; reg signed[SIZE_weights - 1:0] w61_pre, w62_pre, w63_pre, w64_pre, w65_pre, w66_pre, w67_pre, w68_pre, w69_pre; reg signed[SIZE_weights - 1:0] w71_pre, w72_pre, w73_pre, w74_pre, w75_pre, w76_pre, w77_pre, w78_pre, w79_pre; reg signed[SIZE_weights - 1:0] w81_pre, w82_pre, w83_pre, w84_pre, w85_pre, w86_pre, w87_pre, w88_pre, w89_pre; reg signed[SIZE_1 - 1:0] p11_pre, p12_pre, p13_pre, p14_pre, p15_pre, p16_pre, p17_pre, p18_pre, p19_pre; reg signed[SIZE_1 - 1:0] p21_pre, p22_pre, p23_pre, p24_pre, p25_pre, p26_pre, p27_pre, p28_pre, p29_pre; reg signed[SIZE_1 - 1:0] p31_pre, p32_pre, p33_pre, p34_pre, p35_pre, p36_pre, p37_pre, p38_pre, p39_pre; reg signed[SIZE_1 - 1:0] p41_pre, p42_pre, p43_pre, p44_pre, p45_pre, p46_pre, p47_pre, p48_pre, p49_pre; reg signed[SIZE_1 - 1:0] p51_pre, p52_pre, p53_pre, p54_pre, p55_pre, p56_pre, p57_pre, p58_pre, p59_pre; reg signed[SIZE_1 - 1:0] p61_pre, p62_pre, p63_pre, p64_pre, p65_pre, p66_pre, p67_pre, p68_pre, p69_pre; reg signed[SIZE_1 - 1:0] p71_pre, p72_pre, p73_pre, p74_pre, p75_pre, p76_pre, p77_pre, p78_pre, p79_pre; reg signed[SIZE_1 - 1:0] p81_pre, p82_pre, p83_pre, p84_pre, p85_pre, p86_pre, p87_pre, p88_pre, p89_pre; reg [3:0] marker; reg [6:0] lvl; reg [8:0] i; reg [8:0] j; reg [2:0] sh; reg signed [32-1:0] dp; reg signed [SIZE_1-1:0] dp_shift; reg signed [19-1:0]dp_check; always @(posedge clk) begin if (dense_en==1) begin re_p=1; case (marker) 2:begin if (i>(in>>3)+1) begin p11_pre = 0; p12_pre = 0; p13_pre = 0; p14_pre = 0; p15_pre = 0; p16_pre = 0; p17_pre = 0; p18_pre = 0; end else begin p11_pre = qp[SIZE_8 - 1:SIZE_7]; p12_pre = qp[SIZE_7 - 1:SIZE_6]; p13_pre = qp[SIZE_6 - 1:SIZE_5]; p14_pre = qp[SIZE_5 - 1:SIZE_4]; p15_pre = qp[SIZE_4 - 1:SIZE_3]; p16_pre = qp[SIZE_3 - 1:SIZE_2]; p17_pre = qp[SIZE_2 - 1:SIZE_1]; p18_pre = qp[SIZE_1 - 1:0]; end go=0; w11_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w12_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w13_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w14_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w15_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w16_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w17_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w18_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w19_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 2 + j*8; end 3:begin if (i>(in>>3)+1) begin p19_pre = 0; p21_pre = 0; p22_pre = 0; p23_pre = 0; p24_pre = 0; p25_pre = 0; p26_pre = 0; p27_pre = 0; end else begin p19_pre = qp[SIZE_8 - 1:SIZE_7]; p21_pre = qp[SIZE_7 - 1:SIZE_6]; p22_pre = qp[SIZE_6 - 1:SIZE_5]; p23_pre = qp[SIZE_5 - 1:SIZE_4]; p24_pre = qp[SIZE_4 - 1:SIZE_3]; p25_pre = qp[SIZE_3 - 1:SIZE_2]; p26_pre = qp[SIZE_2 - 1:SIZE_1]; p27_pre = qp[SIZE_1 - 1:0]; end if (i!=3) dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp; w21_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w22_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w23_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w24_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w25_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w26_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w27_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w28_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w29_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 3 + j*8; end 4:begin if (i>(in>>3)+1) begin p28_pre = 0; p29_pre = 0; p31_pre = 0; p32_pre = 0; p33_pre = 0; p34_pre = 0; p35_pre = 0; p36_pre = 0; end else begin p28_pre = qp[SIZE_8 - 1:SIZE_7]; p29_pre = qp[SIZE_7 - 1:SIZE_6]; p31_pre = qp[SIZE_6 - 1:SIZE_5]; p32_pre = qp[SIZE_5 - 1:SIZE_4]; p33_pre = qp[SIZE_4 - 1:SIZE_3]; p34_pre = qp[SIZE_3 - 1:SIZE_2]; p35_pre = qp[SIZE_2 - 1:SIZE_1]; p36_pre = qp[SIZE_1 - 1:0]; end go=1; w31_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w32_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w33_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w34_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w35_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w36_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w37_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w38_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w39_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 4 + j*8; p11=p11_pre; p12=p12_pre; p13=p13_pre; p21=p14_pre; p22=p15_pre; p23=p16_pre; p31=p17_pre; p32=p18_pre; p33=p19_pre; p41=p21_pre; p42=p22_pre; p43=p23_pre; p51=p24_pre; p52=p25_pre; p53=p26_pre; p61=p27_pre; p62=p28_pre; p63=p29_pre; p71=p31_pre; p72=p32_pre; p73=p33_pre; p81=p34_pre; p82=p35_pre; p83=p36_pre; w11=w11_pre; w12=w12_pre; w13=w13_pre; w21=w14_pre; w22=w15_pre; w23=w16_pre; w31=w17_pre; w32=w18_pre; w33=w19_pre; w41=w21_pre; w42=w22_pre; w43=w23_pre; w51=w24_pre; w52=w25_pre; w53=w26_pre; w61=w27_pre; w62=w28_pre; w63=w29_pre; w71=w31_pre; w72=w32_pre; w73=w33_pre; w81=w34_pre; w82=w35_pre; w83=w36_pre; end 5:begin if (i>(in>>3)+1) begin p37_pre = 0; p38_pre = 0; p39_pre = 0; p41_pre = 0; p42_pre = 0; p43_pre = 0; p44_pre = 0; p45_pre = 0; end else begin p37_pre = qp[SIZE_8 - 1:SIZE_7]; p38_pre = qp[SIZE_7 - 1:SIZE_6]; p39_pre = qp[SIZE_6 - 1:SIZE_5]; p41_pre = qp[SIZE_5 - 1:SIZE_4]; p42_pre = qp[SIZE_4 - 1:SIZE_3]; p43_pre = qp[SIZE_3 - 1:SIZE_2]; p44_pre = qp[SIZE_2 - 1:SIZE_1]; p45_pre = qp[SIZE_1 - 1:0]; end go=0; w41_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w42_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w43_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w44_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w45_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w46_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w47_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w48_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w49_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 5 + j*8; end 6:begin if (i>(in>>3)+1) begin p46_pre = 0; p47_pre = 0; p48_pre = 0; p49_pre = 0; p51_pre = 0; p52_pre = 0; p53_pre = 0; p54_pre = 0; end else begin p46_pre = qp[SIZE_8 - 1:SIZE_7]; p47_pre = qp[SIZE_7 - 1:SIZE_6]; p48_pre = qp[SIZE_6 - 1:SIZE_5]; p49_pre = qp[SIZE_5 - 1:SIZE_4]; p51_pre = qp[SIZE_4 - 1:SIZE_3]; p52_pre = qp[SIZE_3 - 1:SIZE_2]; p53_pre = qp[SIZE_2 - 1:SIZE_1]; p54_pre = qp[SIZE_1 - 1:0]; end dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp; w51_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w52_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w53_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w54_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w55_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w56_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w57_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w58_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w59_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 6 + j*8; end 7:begin if (i>(in>>3)+1) begin p55_pre = 0; p56_pre = 0; p57_pre = 0; p58_pre = 0; p59_pre = 0; p61_pre = 0; p62_pre = 0; p63_pre = 0; end else begin p55_pre = qp[SIZE_8 - 1:SIZE_7]; p56_pre = qp[SIZE_7 - 1:SIZE_6]; p57_pre = qp[SIZE_6 - 1:SIZE_5]; p58_pre = qp[SIZE_5 - 1:SIZE_4]; p59_pre = qp[SIZE_4 - 1:SIZE_3]; p61_pre = qp[SIZE_3 - 1:SIZE_2]; p62_pre = qp[SIZE_2 - 1:SIZE_1]; p63_pre = qp[SIZE_1 - 1:0]; end go=1; w61_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w62_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w63_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w64_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w65_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w66_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w67_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w68_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w69_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 7 + j*8; p11=p37_pre; p12=p38_pre; p13=p39_pre; p21=p41_pre; p22=p42_pre; p23=p43_pre; p31=p44_pre; p32=p45_pre; p33=p46_pre; p41=p47_pre; p42=p48_pre; p43=p49_pre; p51=p51_pre; p52=p52_pre; p53=p53_pre; p61=p54_pre; p62=p55_pre; p63=p56_pre; p71=p57_pre; p72=p58_pre; p73=p59_pre; p81=p61_pre; p82=p62_pre; p83=p63_pre; w11=w37_pre; w12=w38_pre; w13=w39_pre; w21=w41_pre; w22=w42_pre; w23=w43_pre; w31=w44_pre; w32=w45_pre; w33=w46_pre; w41=w47_pre; w42=w48_pre; w43=w49_pre; w51=w51_pre; w52=w52_pre; w53=w53_pre; w61=w54_pre; w62=w55_pre; w63=w56_pre; w71=w57_pre; w72=w58_pre; w73=w59_pre; w81=w61_pre; w82=w62_pre; w83=w63_pre; end 8:begin if (i>(in>>3)+1) begin p64_pre = 0; p65_pre = 0; p66_pre = 0; p67_pre = 0; p68_pre = 0; p69_pre = 0; p71_pre = 0; p72_pre = 0; end else begin p64_pre = qp[SIZE_8 - 1:SIZE_7]; p65_pre = qp[SIZE_7 - 1:SIZE_6]; p66_pre = qp[SIZE_6 - 1:SIZE_5]; p67_pre = qp[SIZE_5 - 1:SIZE_4]; p68_pre = qp[SIZE_4 - 1:SIZE_3]; p69_pre = qp[SIZE_3 - 1:SIZE_2]; p71_pre = qp[SIZE_2 - 1:SIZE_1]; p72_pre = qp[SIZE_1 - 1:0]; end go=0; j=j+1; w71_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w72_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w73_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w74_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w75_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w76_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w77_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w78_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w79_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; end 0:begin if (i>(in>>3)+1) begin p73_pre = 0; p74_pre = 0; p75_pre = 0; p76_pre = 0; p77_pre = 0; p78_pre = 0; p79_pre = 0; p81_pre = 0; end else begin p73_pre = qp[SIZE_8 - 1:SIZE_7]; p74_pre = qp[SIZE_7 - 1:SIZE_6]; p75_pre = qp[SIZE_6 - 1:SIZE_5]; p76_pre = qp[SIZE_5 - 1:SIZE_4]; p77_pre = qp[SIZE_4 - 1:SIZE_3]; p78_pre = qp[SIZE_3 - 1:SIZE_2]; p79_pre = qp[SIZE_2 - 1:SIZE_1]; p81_pre = qp[SIZE_1 - 1:0]; end we=0; re_w=1; if (i!=0) dp=Y1+Y2+Y3+Y4+Y5+Y6+Y7+Y8+dp; w81_pre=qw[SIZE_weights*9-1:SIZE_weights*8]; w82_pre=qw[SIZE_weights*8-1:SIZE_weights*7]; w83_pre=qw[SIZE_weights*7-1:SIZE_weights*6]; w84_pre=qw[SIZE_weights*6-1:SIZE_weights*5]; w85_pre=qw[SIZE_weights*5-1:SIZE_weights*4]; w86_pre=qw[SIZE_weights*4-1:SIZE_weights*3]; w87_pre=qw[SIZE_weights*3-1:SIZE_weights*2]; w88_pre=qw[SIZE_weights*2-1:SIZE_weights*1]; w89_pre=qw[SIZE_weights*1-1:SIZE_weights*0]; read_addressw = lvl*29 + 0 + j*8; end 1:begin if (i>(in>>3)+1) begin p82_pre = 0; p83_pre = 0; p84_pre = 0; p85_pre = 0; p86_pre = 0; p87_pre = 0; p88_pre = 0; p89_pre = 0; end else begin p82_pre = qp[SIZE_8 - 1:SIZE_7]; p83_pre = qp[SIZE_7 - 1:SIZE_6]; p84_pre = qp[SIZE_6 - 1:SIZE_5]; p85_pre = qp[SIZE_5 - 1:SIZE_4]; p86_pre = qp[SIZE_4 - 1:SIZE_3]; p87_pre = qp[SIZE_3 - 1:SIZE_2]; p88_pre = qp[SIZE_2 - 1:SIZE_1]; p89_pre = qp[SIZE_1 - 1:0]; end if (i!=1) go=1; p11=p64_pre; p12=p65_pre; p13=p66_pre; p21=p67_pre; p22=p68_pre; p23=p69_pre; p31=p71_pre; p32=p72_pre; p33=p73_pre; p41=p74_pre; p42=p75_pre; p43=p76_pre; p51=p77_pre; p52=p78_pre; p53=p79_pre; p61=p81_pre; p62=p82_pre; p63=p83_pre; p71=p84_pre; p72=p85_pre; p73=p86_pre; p81=p87_pre; p82=p88_pre; p83=p89_pre; w11=w64_pre; w12=w65_pre; w13=w66_pre; w21=w67_pre; w22=w68_pre; w23=w69_pre; w31=w71_pre; w32=w72_pre; w33=w73_pre; w41=w74_pre; w42=w75_pre; w43=w76_pre; w51=w77_pre; w52=w78_pre; w53=w79_pre; w61=w81_pre; w62=w82_pre; w63=w83_pre; w71=w84_pre; w72=w85_pre; w73=w86_pre; w81=w87_pre; w82=w88_pre; w83=w89_pre; read_addressw = lvl*29 + 1 + j*8; end default: $display("Check case dense"); endcase read_addressp=memstartp+i; if (marker!=8) marker=marker+1; else marker=0; i=i+1; if ((i>(in>>3)+4)&&(marker==4)) begin write_addressp=memstartzap+(lvl>>(num_conv>>1)); dp_check=dp[32-2:SIZE_1-2]; if ((dp_shift<0)&&(nozero==0)) dp_shift=0; if (dp_check>2**(SIZE_1-1)-1) dp_shift=2**(SIZE_1-1)-1; else dp_shift=dp_check; if (sh ==0) begin res=0; res[SIZE_8-1:SIZE_7]=dp_shift; end if (sh ==1) begin res[SIZE_7-1:SIZE_6]=dp_shift; end if (sh ==2) begin res[SIZE_6-1:SIZE_5]=dp_shift; end if (sh ==3) begin res[SIZE_5-1:SIZE_4]=dp_shift; end if (sh ==4) begin res[SIZE_4-1:SIZE_3]=dp_shift; end if (sh ==5) begin res[SIZE_3-1:SIZE_2]=dp_shift; end if (sh ==6) begin res[SIZE_2-1:SIZE_1]=dp_shift; end if (sh ==7) begin res[SIZE_1-1:0]=dp_shift; end lvl=lvl+1; i=0; j=0; dp=0; marker=0; sh=sh+1; if (sh==num_conv) sh=0; if ((sh==0)||(lvl==out)) we=1; if (lvl==out) STOP=1; end end else begin marker=0; i=0; j=0; sh=0; we=0; dp=0; res=0; re_p=0; re_w=0; STOP=0; lvl=0; end end endmodule ================================================ FILE: verilog/MobileNet_v3_conv_8_3x1/result.v ================================================ module result(clk,enable,STOP,memstartp,read_addressp,qp,re,RESULT); parameter SIZE_1=0; parameter SIZE_2=0; parameter SIZE_3=0; parameter SIZE_4=0; parameter SIZE_5=0; parameter SIZE_6=0; parameter SIZE_7=0; parameter SIZE_8=0; parameter SIZE_address_pix=0; input clk,enable; output reg STOP; input [SIZE_address_pix-1:0] memstartp; input [SIZE_8-1:0] qp; output reg re; output reg [SIZE_address_pix-1:0] read_addressp; output reg [1:0] RESULT; reg [2:0] marker; reg signed [SIZE_1-1:0] p1,p2; always @(posedge clk) begin if (enable==1) begin re=1; case (marker) 0: begin read_addressp=memstartp+0; end 1: begin end 2: begin p1=qp[SIZE_8-1:SIZE_7]; p2=qp[SIZE_7-1:SIZE_6]; RESULT=0; if (p2>=p1) RESULT=1; else RESULT=0; STOP=1; end default: $display("Check case result"); endcase marker=marker+1; end else begin re=0; marker=0; STOP=0; end end endmodule ================================================ FILE: verilog/OpenVino_MobileNet.qpf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition # Date created = 15:25:52 July 27, 2019 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "18.0" DATE = "15:25:52 July 27, 2019" # Revisions PROJECT_REVISION = "GENERAL" ================================================ FILE: verilog/RAM.v ================================================ module RAM_general( input clk_in, input clk_out, input clk_in_im, input clk_out_im, input clk_in_im_scale, input clk_out_im_scale, input [15:0] data_in_im, output reg [15:0] data_out_im, input [18:0] address_in_im, input [18:0] address_out_im, input we_image, input re_image, input [23:0] data_in_im_scale, output reg [23:0] data_out_im_scale, input [15:0] address_in_im_scale, input [15:0] address_out_im_scale, input we_image_scale, input re_image_scale, input [20:0] data_in_weights, output reg [20:0] data_out_weights, input [23:0] address_in_weights, input [23:0] address_out_weights, input we_weights, input re_weights ); reg signed [15:0] ram_image [0:70800-1]; reg signed [23:0] ram_scale_image [0:128*128-1]; reg signed [20:0] ram_weights [0:(208115+2736)]; always @(posedge clk_in) if (we_weights) ram_weights[address_in_weights] = data_in_weights; always @(posedge clk_out) if (re_weights) data_out_weights = ram_weights[address_out_weights]; always @(posedge clk_in_im) if (we_image) ram_image[address_in_im] = data_in_im; always @(posedge clk_out_im) if (re_image) data_out_im = ram_image[address_out_im]; always @(posedge clk_in_im_scale) if (we_image_scale) ram_scale_image[address_in_im_scale] = data_in_im_scale; always @(posedge clk_out_im_scale) if (re_image_scale) data_out_im_scale = ram_scale_image[address_out_im_scale]; endmodule ================================================ FILE: verilog/Seg7.v ================================================ module Seg7 (data,hex); input [3:0] data; output [6:0] hex; assign hex[0] = !(((data==0)||(data==2)||(data==3)||(data==5)||(data==6)||(data==7)||(data==8)||(data==9)||(data==10)||(data==12)||(data==14)||(data==15))?1'b1:1'b0); assign hex[1] = !(((data==0)||(data==1)||(data==2)||(data==3)||(data==4)||(data==7)||(data==8)||(data==9)||(data==10)||(data==13))?1'b1:1'b0); assign hex[2] = !(((data==0)||(data==1)||(data==3)||(data==4)||(data==5)||(data==6)||(data==7)||(data==8)||(data==9)||(data==10)||(data==11)||(data==13))?1'b1:1'b0); assign hex[3] = !(((data==0)||(data==2)||(data==3)||(data==5)||(data==6)||(data==8)||(data==9)||(data==11)||(data==12)||(data==13)||(data==14))?1'b1:1'b0); assign hex[4] = !(((data==0)||(data==2)||(data==6)||(data==8)||(data==10)||(data==11)||(data==12)||(data==13)||(data==14)||(data==15))?1'b1:1'b0); assign hex[5] = !(((data==0)||(data==4)||(data==5)||(data==6)||(data==8)||(data==9)||(data==10)||(data==11)||(data==12)||(data==14)||(data==15))?1'b1:1'b0); assign hex[6] = !(((data==2)||(data==3)||(data==4)||(data==5)||(data==6)||(data==8)||(data==9)||(data==10)||(data==11)||(data==13)||(data==14)||(data==15))?1'b1:1'b0); endmodule ================================================ FILE: verilog/UART/async.v ================================================ //////////////////////////////////////////////////////// // RS-232 RX and TX module // (c) fpga4fun.com & KNJN LLC - 2003 to 2016 // The RS-232 settings are fixed // TX: 8-bit data, 2 stop, no-parity // RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) //`define SIMULATION // in this mode, TX outputs one bit per clock cycle // and RX receives one bit per clock cycle (for fast simulations) //////////////////////////////////////////////////////// module async_transmitter( input clk, input TxD_start, input [7:0] TxD_data, output TxD, output TxD_busy ); // Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data // TxD_data is latched so that it doesn't have to stay valid while it is being sent parameter ClkFrequency = 25000000; // 25MHz parameter Baud = 115200; generate if(ClkFrequency> 1); case(TxD_state) 4'b0000: if(TxD_start) TxD_state <= 4'b0100; 4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit 4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0 4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1 4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2 4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3 4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4 4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5 4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6 4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7 4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1 4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2 default: if(BitTick) TxD_state <= 4'b0000; endcase end assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits endmodule //////////////////////////////////////////////////////// module async_receiver( input clk, input RxD, output reg RxD_data_ready = 0, output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted // We also detect if a gap occurs in the received stream of characters // That can be useful if multiple characters are sent in burst // so that multiple characters can be treated as a "packet" output RxD_idle, // asserted when no data has been received for a while output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high) ); parameter ClkFrequency = 25000000; // 25MHz parameter Baud = 115200; parameter Oversampling = 8; // needs to be a power of 2 // we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time // 8 times oversampling by default, use 16 for higher quality reception generate if(ClkFrequency>log2) log2=log2+1; end endfunction localparam l2o = log2(Oversampling); reg [l2o-2:0] OversamplingCnt = 0; always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1; wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1); `endif // now we can accumulate the RxD bits in a shift-register always @(posedge clk) case(RxD_state) 4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found? 4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow 4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0 4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1 4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2 4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3 4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4 4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5 4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6 4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7 4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit default: RxD_state <= 4'b0000; endcase always @(posedge clk) if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]}; //reg RxD_data_error = 0; always @(posedge clk) begin RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received //RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received end `ifdef SIMULATION assign RxD_idle = 0; `else reg [l2o+1:0] GapCnt = 0; always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1; assign RxD_idle = GapCnt[l2o+1]; always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0]; `endif endmodule //////////////////////////////////////////////////////// // dummy module used to be able to raise an assertion in Verilog module ASSERTION_ERROR(); endmodule //////////////////////////////////////////////////////// module BaudTickGen( input clk, enable, output tick // generate a tick at the specified baud rate * oversampling ); parameter ClkFrequency = 25000000; parameter Baud = 115200; parameter Oversampling = 1; function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte reg [AccWidth:0] Acc = 0; localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; assign tick = Acc[AccWidth]; endmodule //////////////////////////////////////////////////////// ================================================ FILE: verilog/UART/serialGPIO.v ================================================ module serialGPIO( input clk25, input RxD, output TxD, input reset, output reg [23:0] address, output reg signed [20:0] data, output reg write_enable, output reg start, output reg stop, output RxD_data_ready, input signed [20:0] data_tx, input enable_tx ); reg [7:0] GPout; reg [1:0] sh; wire [7:0] RxD_data; async_receiver RX(.clk(clk25), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data)); always @(posedge clk25) if(RxD_data_ready) GPout <= RxD_data; async_transmitter TX(.clk(clk25), .TxD(TxD), .TxD_start(enable_tx), .TxD_data(data_tx[7:0])); always @(posedge RxD_data_ready or negedge reset) if (!reset) begin address = -1; start=0; sh=0; write_enable=0; data=0; stop=0; end else begin if ((!(GPout == 255))&&(sh==0)) address = address + 1'b1; if (GPout == 191) begin start = 0; stop = 1; sh=0; write_enable=0; end if (start) begin if (sh==0) begin data=0; data[5:0]=GPout[5:0]; write_enable=0; end if (sh==1) begin data[11:6]=GPout[5:0]; end if (sh==2) begin data[17:12]=GPout[5:0]; end if (sh==3) begin data[19:18]=GPout[1:0]; //minus,data if (GPout[3]) data=-data; write_enable = 1'b1; end sh=sh+1; end if (GPout == 255) begin address = -1; start=1; sh=0; write_enable=0; data=0; stop=0; end end endmodule ================================================ FILE: verilog/ili9341/tft_ili9341.sv ================================================ /** Simple frame-buffer based driver for the ILI9341 TFT module */ module tft_ili9341( input clk, input tft_sdo, output wire tft_sck, output wire tft_sdi, output wire tft_dc, output reg tft_reset, output wire tft_cs, input[15:0] framebufferData, output wire framebufferClk ); parameter INPUT_CLK_MHZ = 120; /* recommended */ // Initial assignments initial tft_reset = 1'b1; // Assign pins and modules reg[8:0] spiData; reg spiDataSet = 1'b0; wire spiIdle; reg frameBufferLowNibble = 1'b1; assign framebufferClk = !frameBufferLowNibble; tft_ili9341_spi spi( .spiClk(clk), .data(spiData), .dataAvailable(spiDataSet), .tft_sck(tft_sck), .tft_sdi(tft_sdi), .tft_dc(tft_dc), .tft_cs(tft_cs), .idle(spiIdle)); // Init Sequence Data (based upon https://github.com/notro/fbtft/blob/master/fb_ili9341.c) localparam INIT_SEQ_LEN = 64; reg[6:0] initSeqCounter = 7'b0; reg[8:0] INIT_SEQ [0:INIT_SEQ_LEN-1] = '{ // Turn off Display {1'b0, 8'h28}, // Init (??) {1'b0, 8'hCF}, {1'b1, 8'h00}, {1'b1, 8'h83}, {1'b1, 8'h30}, {1'b0, 8'hED}, {1'b1, 8'h64}, {1'b1, 8'h03}, {1'b1, 8'h12}, {1'b1, 8'h81}, {1'b0, 8'hE8}, {1'b1, 8'h85}, {1'b1, 8'h01}, {1'b1, 8'h79}, {1'b0, 8'hCB}, {1'b1, 8'h39}, {1'b1, 8'h2C}, {1'b1, 8'h00}, {1'b1, 8'h34}, {1'b1, 8'h02}, {1'b0, 8'hF7}, {1'b1, 8'h20}, {1'b0, 8'hEA}, {1'b1, 8'h00}, {1'b1, 8'h00}, // Power Control {1'b0, 8'hC0}, {1'b1, 8'h26}, {1'b0, 8'hC1}, {1'b1, 8'h11}, // VCOM {1'b0, 8'hC5}, {1'b1, 8'h35}, {1'b1, 8'h3E}, {1'b0, 8'hC7}, {1'b1, 8'hBE}, // Memory Access Control {1'b0, 8'h3A}, {1'b1, 8'h55}, {1'b0, 8'h2A}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'h01}, {1'b1, 8'h3F}, {1'b0, 8'h2B}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'h00}, {1'b1, 8'hEF}, {1'b0, 8'h36}, {1'b1, 8'hE0}, // Frame Rate {1'b0, 8'hB1}, {1'b1, 8'h00}, {1'b1, 8'h1B}, // Gamma {1'b0, 8'h26}, {1'b1, 8'h01}, // Brightness {1'b0, 8'h51}, {1'b1, 8'hFF}, // Display {1'b0, 8'hB7}, {1'b1, 8'h07}, {1'b0, 8'hB6}, {1'b1, 8'h0A}, {1'b1, 8'h82}, {1'b1, 8'h27}, {1'b1, 8'h00}, {1'b0, 8'h29}, // Enable Display {1'b0, 8'h2C} // Start Memory-Write }; // state machine with delay + idle support (used for initialization) reg[23:0] remainingDelayTicks = 24'b0; enum logic[2:0] { START, HOLD_RESET, WAIT_FOR_POWERUP, SEND_INIT_SEQ, LOOP} state = START; always @ (posedge clk) begin // clear data flag first spiDataSet <= 1'b0; // always decrement delay ticks if (remainingDelayTicks > 0) begin remainingDelayTicks <= remainingDelayTicks - 1'b1; end else if (spiIdle && !spiDataSet) begin // advance state machine to next state, but only do this if we // didn't just clock in the last byte (since idle is not yet updated) case (state) // initialize all pins in START mode; reset the LCD START: begin tft_reset <= 1'b0; remainingDelayTicks <= 24'(INPUT_CLK_MHZ * 10); // min: 10us state <= HOLD_RESET; end // wait for RESET to kick in; then release pin & wait for power up HOLD_RESET: begin tft_reset <= 1'b1; // release pin remainingDelayTicks <= 24'(INPUT_CLK_MHZ * 120000); // min: 120ms state <= WAIT_FOR_POWERUP; frameBufferLowNibble <= 1'b0; // request first pixel end // if power up is completed -> sw reset WAIT_FOR_POWERUP: begin spiData <= {1'b0, 8'h11}; // take out of sleep mode spiDataSet <= 1'b1; remainingDelayTicks <= 24'(INPUT_CLK_MHZ * 5000); // min: 5ms state <= SEND_INIT_SEQ; frameBufferLowNibble <= 1'b1; end // setup the LCD by sending the init sequence SEND_INIT_SEQ: begin if (initSeqCounter < INIT_SEQ_LEN) begin spiData <= INIT_SEQ[initSeqCounter]; spiDataSet <= 1'b1; initSeqCounter <= initSeqCounter + 1'b1; end else begin state <= LOOP; remainingDelayTicks <= 24'(INPUT_CLK_MHZ * 10000); // min: 10ms end end // frame buffer loop default: begin spiData <= !frameBufferLowNibble ? {1'b1, framebufferData[15:8]} :{1'b1, framebufferData[7:0]}; spiDataSet <= 1'b1; frameBufferLowNibble <= !frameBufferLowNibble; end endcase end end endmodule ================================================ FILE: verilog/ili9341/tft_ili9341_spi.sv ================================================ // --- Byte-wise SPI + DC implementation // * Will copy data into internal buffer // * 'Idle' will be set to 0 once buffer copy is complete // * Data is only copied if 'dataAvailable' is set to 1 // * SPI CLK will stop (high state) if no data is being sent module tft_ili9341_spi( input spiClk, input[8:0] data, input dataAvailable, output wire tft_sck, output reg tft_sdi, output reg tft_dc, output wire tft_cs, output reg idle ); // Registers reg[0:2] counter = 3'b0; reg[8:0] internalData; reg internalSck; reg cs; initial internalSck <= 1'b1; initial idle <= 1'b1; initial cs <= 1'b0; // Combinational Assignments wire dataDc = internalData[8]; wire[0:7] dataShift = internalData[7:0]; // MSB first assign tft_sck = internalSck & cs; // only drive sck with an active CS assign tft_cs = !cs; // active low // Update SPI CLK + Output data always @ (posedge spiClk) begin // Store new data in internal register if (dataAvailable) begin internalData <= data; idle <= 1'b0; end // Change data if we're actively sending if (!idle) begin // Toggle Clock on every active tick internalSck <= !internalSck; // Check if SCK will be low next if (internalSck) begin // Update pins tft_dc <= dataDc; tft_sdi <= dataShift[counter]; cs <= 1'b1; // Advance counter counter <= counter + 1'b1; idle <= &counter; // we're just sending the last bit end end else begin internalSck <= 1'b1; // idle mode (also: sent last bit) if (internalSck) cs <= 1'b0; // idle for two bits in a row -> deactivate CS end end endmodule ================================================ FILE: verilog/pll_24_100/pll_24_100_0002.qip ================================================ set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_24_100_0002*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_24_100_0002*|altera_pll:altera_pll_i*|*" set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_24_100_0002*|altera_pll:altera_pll_i*|*" ================================================ FILE: verilog/pll_24_100/pll_24_100_0002.v ================================================ `timescale 1ns/10ps module pll_24_100_0002( // interface 'refclk' input wire refclk, // interface 'reset' input wire rst, // interface 'outclk0' output wire outclk_0, // interface 'outclk1' output wire outclk_1, // interface 'outclk2' output wire outclk_2, // interface 'locked' output wire locked ); altera_pll #( .fractional_vco_multiplier("false"), .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), .number_of_clocks(3), .output_clock_frequency0("24.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), .output_clock_frequency1("100.000000 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), .output_clock_frequency2("60.000000 MHz"), .phase_shift2("0 ps"), .duty_cycle2(50), .output_clock_frequency3("0 MHz"), .phase_shift3("0 ps"), .duty_cycle3(50), .output_clock_frequency4("0 MHz"), .phase_shift4("0 ps"), .duty_cycle4(50), .output_clock_frequency5("0 MHz"), .phase_shift5("0 ps"), .duty_cycle5(50), .output_clock_frequency6("0 MHz"), .phase_shift6("0 ps"), .duty_cycle6(50), .output_clock_frequency7("0 MHz"), .phase_shift7("0 ps"), .duty_cycle7(50), .output_clock_frequency8("0 MHz"), .phase_shift8("0 ps"), .duty_cycle8(50), .output_clock_frequency9("0 MHz"), .phase_shift9("0 ps"), .duty_cycle9(50), .output_clock_frequency10("0 MHz"), .phase_shift10("0 ps"), .duty_cycle10(50), .output_clock_frequency11("0 MHz"), .phase_shift11("0 ps"), .duty_cycle11(50), .output_clock_frequency12("0 MHz"), .phase_shift12("0 ps"), .duty_cycle12(50), .output_clock_frequency13("0 MHz"), .phase_shift13("0 ps"), .duty_cycle13(50), .output_clock_frequency14("0 MHz"), .phase_shift14("0 ps"), .duty_cycle14(50), .output_clock_frequency15("0 MHz"), .phase_shift15("0 ps"), .duty_cycle15(50), .output_clock_frequency16("0 MHz"), .phase_shift16("0 ps"), .duty_cycle16(50), .output_clock_frequency17("0 MHz"), .phase_shift17("0 ps"), .duty_cycle17(50), .pll_type("General"), .pll_subtype("General") ) altera_pll_i ( .rst (rst), .outclk ({outclk_2, outclk_1, outclk_0}), .locked (locked), .fboutclk ( ), .fbclk (1'b0), .refclk (refclk) ); endmodule ================================================ FILE: verilog/pll_24_100.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol (rect 0 0 160 224) (text "pll_24_100" (rect 50 -1 92 11)(font "Arial" (font_size 10))) (text "inst" (rect 8 208 20 220)(font "Arial" )) (port (pt 0 72) (input) (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) (line (pt 0 72)(pt 48 72)(line_width 1)) ) (port (pt 0 112) (input) (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 48 112)(line_width 1)) ) (port (pt 160 72) (output) (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) (line (pt 160 72)(pt 112 72)(line_width 1)) ) (port (pt 160 112) (output) (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) (line (pt 160 112)(pt 112 112)(line_width 1)) ) (port (pt 160 152) (output) (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) (line (pt 160 152)(pt 112 152)(line_width 1)) ) (port (pt 160 192) (output) (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) (text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8))) (line (pt 160 192)(pt 112 192)(line_width 1)) ) (drawing (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) (text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9))) (text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0))) (text " altera_pll " (rect 118 208 308 426)(font "Arial" )) (line (pt 48 32)(pt 112 32)(line_width 1)) (line (pt 112 32)(pt 112 208)(line_width 1)) (line (pt 48 208)(pt 112 208)(line_width 1)) (line (pt 48 32)(pt 48 208)(line_width 1)) (line (pt 49 52)(pt 49 76)(line_width 1)) (line (pt 50 52)(pt 50 76)(line_width 1)) (line (pt 49 92)(pt 49 116)(line_width 1)) (line (pt 50 92)(pt 50 116)(line_width 1)) (line (pt 111 52)(pt 111 76)(line_width 1)) (line (pt 110 52)(pt 110 76)(line_width 1)) (line (pt 111 92)(pt 111 116)(line_width 1)) (line (pt 110 92)(pt 110 116)(line_width 1)) (line (pt 111 132)(pt 111 156)(line_width 1)) (line (pt 110 132)(pt 110 156)(line_width 1)) (line (pt 111 172)(pt 111 196)(line_width 1)) (line (pt 110 172)(pt 110 196)(line_width 1)) (line (pt 0 0)(pt 160 0)(line_width 1)) (line (pt 160 0)(pt 160 224)(line_width 1)) (line (pt 0 224)(pt 160 224)(line_width 1)) (line (pt 0 0)(pt 0 224)(line_width 1)) ) ) ================================================ FILE: verilog/pll_24_100.cmp ================================================ component pll_24_100 is port ( refclk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic; -- clk outclk_1 : out std_logic; -- clk outclk_2 : out std_logic; -- clk locked : out std_logic -- export ); end component pll_24_100; ================================================ FILE: verilog/pll_24_100.ppf ================================================ ================================================ FILE: verilog/pll_24_100.qip ================================================ set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_TOOL_NAME "altera_pll" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "pll_24_100" -name MISC_FILE [file join $::quartus(qip_path) "pll_24_100.cmp"] set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_NAME "cGxsXzI0XzEwMA==" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_VERSION "MTguMA==" set_global_assignment -entity "pll_24_100" -library "pll_24_100" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_NAME "cGxsXzI0XzEwMF8wMDAy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_VERSION "MTguMA==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NjAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Niw2LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwxMywxMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMsMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1LDUsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwzMCwyMDAwLDYwMC4wIE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssZmFsc2U=::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" set_global_assignment -library "pll_24_100" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_24_100.v"] set_global_assignment -library "pll_24_100" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_24_100/pll_24_100_0002.v"] set_global_assignment -library "pll_24_100" -name QIP_FILE [file join $::quartus(qip_path) "pll_24_100/pll_24_100_0002.qip"] set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_TOOL_NAME "altera_pll" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "pll_24_100_0002" -library "pll_24_100" -name IP_TOOL_ENV "mwpim" ================================================ FILE: verilog/pll_24_100.sip ================================================ set_global_assignment -entity "pll_24_100" -library "lib_pll_24_100" -name IP_TOOL_NAME "altera_pll" set_global_assignment -entity "pll_24_100" -library "lib_pll_24_100" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "pll_24_100" -library "lib_pll_24_100" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "lib_pll_24_100" -name SPD_FILE [file join $::quartus(sip_path) "pll_24_100.spd"] set_global_assignment -library "lib_pll_24_100" -name MISC_FILE [file join $::quartus(sip_path) "pll_24_100_sim/pll_24_100.vo"] ================================================ FILE: verilog/pll_24_100.spd ================================================ ================================================ FILE: verilog/pll_24_100.v ================================================ // megafunction wizard: %PLL Intel FPGA IP v18.0% // GENERATION: XML // pll_24_100.v // Generated using ACDS version 18.0 614 `timescale 1 ps / 1 ps module pll_24_100 ( input wire refclk, // refclk.clk input wire rst, // reset.reset output wire outclk_0, // outclk0.clk output wire outclk_1, // outclk1.clk output wire outclk_2, // outclk2.clk output wire locked // locked.export ); pll_24_100_0002 pll_24_100_inst ( .refclk (refclk), // refclk.clk .rst (rst), // reset.reset .outclk_0 (outclk_0), // outclk0.clk .outclk_1 (outclk_1), // outclk1.clk .outclk_2 (outclk_2), // outclk2.clk .locked (locked) // locked.export ); endmodule // Retrieval info: // // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // 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info: // Retrieval info: // IPFS_FILES : pll_24_100.vo // RELATED_FILES: pll_24_100.v, pll_24_100_0002.v ================================================ FILE: verilog/pll_24_100_sim/aldec/rivierapro_setup.tcl ================================================ # (C) 2001-2019 Altera Corporation. All rights reserved. # Your use of Altera Corporation's design tools, logic functions and # other software and tools, and its AMPP partner logic functions, and # any output files any of the foregoing (including device programming # or simulation files), and any associated documentation or information # are expressly subject to the terms and conditions of the Altera # Program License Subscription Agreement, Altera MegaCore Function # License Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by Altera # or its authorized distributors. Please refer to the applicable # agreement for further details. # ACDS 18.0 614 win32 2019.08.23.14:15:47 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- # This script provides commands to simulate the following IP detected in # your Quartus project: # pll_24_100 # # Altera recommends that you source this Quartus-generated IP simulation # script from your own customized top-level script, and avoid editing this # generated script. # # To write a top-level script that compiles Altera simulation libraries and # the Quartus-generated IP in your project, along with your design and # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below # into a new file, e.g. named "aldec.do", and modify the text as directed. # # ---------------------------------------- # # TOP-LEVEL TEMPLATE - BEGIN # # # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to # # construct paths to the files required to simulate the IP in your Quartus # # project. By default, the IP script assumes that you are launching the # # simulator from the IP script location. If launching from another # # location, set QSYS_SIMDIR to the output directory you specified when you # # generated the IP script, relative to the directory from which you launch # # the simulator. # # # set QSYS_SIMDIR