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Repository: ZipCPU/autofpga
Branch: master
Commit: fdfd1b633e9c
Files: 131
Total size: 1.1 MB
Directory structure:
gitextract_n54jfvbv/
├── .gitignore
├── LICENSE
├── Makefile
├── README.md
├── auto-data/
│ ├── allclocks.txt
│ ├── bkram.txt
│ ├── buserr.txt
│ ├── clkcheck.txt
│ ├── clkcounter.txt
│ ├── crossbus.txt
│ ├── ddr3.txt
│ ├── edid.txt
│ ├── edidslvscope.txt
│ ├── exconsole.txt
│ ├── flash.txt
│ ├── flashcfg.txt
│ ├── global.txt
│ ├── gpio.txt
│ ├── gps.txt
│ ├── hdmi.txt
│ ├── i2ccpu.txt
│ ├── i2cdma.txt
│ ├── i2saudio.txt
│ ├── icape.txt
│ ├── legalgen.txt
│ ├── mdio.txt
│ ├── meganet.txt
│ ├── nexysv.xdc
│ ├── pic.txt
│ ├── pwrcount.txt
│ ├── rtccount.txt
│ ├── rtcdate.txt
│ ├── rtcgps.txt
│ ├── sdio.txt
│ ├── sdspi.txt
│ ├── spio.txt
│ ├── vadj33.txt
│ ├── version.txt
│ ├── wboledbw.txt
│ ├── wbpmic.txt
│ ├── wbscopc.txt
│ ├── wbscope.txt
│ ├── wbuarbiter.txt
│ ├── wbuart.txt
│ ├── wbubus.txt
│ ├── zipcpu.txt
│ └── zipmaster.txt
├── demo-out/
│ ├── board.h
│ ├── board.ld
│ ├── build.xdc
│ ├── iscachable.v
│ ├── main.v
│ ├── main_tb.cpp
│ ├── regdefs.cpp
│ ├── regdefs.h
│ ├── rtl.make.inc
│ ├── testb.h
│ └── toplevel.v
├── doc/
│ ├── 20200709-update.dia
│ ├── Makefile
│ ├── bus.md
│ ├── clocks.md
│ ├── constraints.md
│ ├── double.md
│ ├── goals.txt
│ ├── icd.txt
│ ├── ioports.md
│ ├── single.md
│ ├── slaves.md
│ └── src/
│ └── gpl-3.0.tex
└── sw/
├── .gitignore
├── Makefile
├── ast.cpp
├── ast.h
├── autofpga.cpp
├── automdata.h
├── autopdata.h
├── bitlib.cpp
├── bitlib.h
├── bldboardld.cpp
├── bldboardld.h
├── bldcachable.cpp
├── bldcachable.h
├── bldregdefs.cpp
├── bldregdefs.h
├── bldrtlmake.cpp
├── bldrtlmake.h
├── bldsim.cpp
├── bldsim.h
├── bldtestb.cpp
├── bldtestb.h
├── bus/
│ ├── axi.cpp
│ ├── axi.h
│ ├── axil.cpp
│ ├── axil.h
│ ├── wb.cpp
│ └── wb.h
├── businfo.cpp
├── businfo.h
├── clockinfo.cpp
├── clockinfo.h
├── expr.l
├── expr.ypp
├── gather.cpp
├── gather.h
├── genbus.cpp
├── genbus.h
├── globals.cpp
├── globals.h
├── ifdefs.cpp
├── ifdefs.h
├── keys.cpp
├── keys.h
├── kveval.cpp
├── kveval.h
├── legalnotice.cpp
├── legalnotice.h
├── mapdhash.cpp
├── mapdhash.h
├── mlist.cpp
├── mlist.h
├── msgs.cpp
├── msgs.h
├── parser.cpp
├── parser.h
├── plist.cpp
├── plist.h
├── predicates.cpp
├── predicates.h
├── subbus.cpp
└── subbus.h
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
legal.txt
.svn
xilinx
obj_dir
obj-pc
obj-zip
*.o
*.a
*.vcd
.swp
.*.swp
.*.swo
svn-commit*
*_tb
*_tb.dbl
*dbg.txt
autofpga.dbg
*dump.txt
*debug.txt
tags
cpudefs.h
20*-autofpga.tjz
core
================================================
FILE: LICENSE
================================================
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The Free Software Foundation may publish revised and/or new versions of
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Each version is given a distinguishing version number. If the
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If the Program specifies that a proxy can decide which future
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Later license versions may give you additional or different
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END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
{one line to give the program's name and a brief idea of what it does.}
Copyright (C) {year} {name of author}
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
{project} Copyright (C) {year} {fullname}
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
================================================
FILE: Makefile
================================================
################################################################################
##
## Filename: Makefile
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: A master project makefile. It tries to build all targets
## within the project, mostly by directing subdirectory makes.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
.PHONY: all
all: sw
YYMMDD:=`date +%Y%m%d`
.PHONY: archive
## {{{
archive:
tar --transform s,^,$(YYMMDD)-video/, -chjf $(YYMMDD)-autofpga.tjz sw/ auto-data/ demo-out/ doc/
## }}}
.PHONY: autofpga
autofpga: sw
.PHONY: sw
## {{{
sw:
$(MAKE) --no-print-directory --directory=sw
## }}}
.PHONY: clean
## {{{
clean:
$(MAKE) --no-print-directory --directory=sw clean
## }}}
================================================
FILE: README.md
================================================
# AutoFPGA - An FPGA Design Automation routine
After now having built several FPGA designs, such as the
[xulalx25soc](https://github.com/ZipCPU/xulalx25soc),
[s6soc](https://github.com/ZipCPU/s6soc),
[openarty](https://github.com/ZipCPU/openarty),
[zbasic](https://github.com/ZipCPU/zbasic),
[icozip](https://github.com/ZipCPU/icozip),
and even a Basys-3 design of my own that hasn't been published, I started
recognizing that all of these designs have a lot in common. In particular,
they all have a set of bus masters, such as the
[UART-to-wishbone](https://github.com/ZipCPU/zbasic/blob/master/rtl/wbubus.v)
bridge that I use, the [hexbus](https://github.com/ZipCPU/dbgbus) debugging
bus that offers a simpler version of the same, or even the
[zipcpu](https://github.com/ZipCPU/zipcpu).
Many of these designs have also started to use (and reuse) many of the
peripherals I've developed, such as
the generic [UART](https://github.com/ZipCPU/wbuart),
the [QSPI flash controller](https://github.com/ZipCPU/qspiflash),
the [SD-card controller](https://github.com/ZipCPU/sdspi),
the [block RAM controller](https://github.com/ZipCPU/openarty/blob/master/rtl/memdev.v),
the [RMII Ethernet Controller](https://github.com/ZipCPU/openarty/blob/master/rtl/enetpackets.v),
the [Real-Time Clock](https://github.com/ZipCPU/rtcclock), the [Real-Time
Date](https://github.com/ZipCPU/rtcclock/blob/master/rtl/rtcdate.v), the
[Organic LED controller](https://github.com/ZipCPU/openarty/blob/master/rtl/wboled.v),
Xilinx's [Internal Configuration Access
Port](https://github.com/ZipCPU/wbicapetwo), the [wishbone
scope](https://github.com/ZipCPU/wbscope), the [GPS controlled
clock](https://github.com/ZipCPU/openarty/blob/master/rtl/gpsclock.v),
or even the [PWM Audio Controller](https://github.com/ZipCPU/wbpwmaudio).
All of these peripherals have a very similar format when included within a
top level design, all of these require a certain amount of care and feeding
as part of that top level design, but yet rebuilding that top level design over
and over just to repeat this information becomes a pain.
Where things were really starting to get annoying is where the C++ information
was depending upon Verilog information. A classic example of this is the
base address of any bus components. However, if you add clock rate into
the mix, you can then also control things such as any default UART
configuration, default clock stepping information (for the RTC clock),
or even default video clock information--just by knowing the FPGA's clock rate
within your C++ environment.
Sharing information between Verilog and C++ then became one of the primary
reasons for creating AutoFPGA. While peripheral address decoding is typically
done in some [main Verilog
file](https://github.com/ZipCPU/openarty/blob/master/rtl/main.v),
other files depend upon what this peripheral decoding is. These other files
include the [host register definition
file](https://github.com/ZipCPU/openarty/blob/master/sw/host/regdefs.h) (used
for debugging access), the [register naming
file](https://github.com/ZipCPU/openarty/blob/master/sw/host/regdefs.cpp), the
[software board definition
file](https://github.com/ZipCPU/openarty/blob/master/sw/zlib/board.h) used
by newlib, the [linker
script](https://github.com/ZipCPU/openarty/blob/master/sw/board/board.ld) used
by the compiler, and even the [LaTeX
specification](https://github.com/ZipCPU/openarty/blob/master/doc/src/spec.tex)
for the board. Creating and updating all of these files by hand anytime I
create a new board file can get tedious. Further, every time a board is
reconfigured, the constraints file, whether
[XDC](https://github.com/ZipCPU/openarty/blob/master/arty.xdc) or
[UCF](https://github.com/ZipCPU/xulalx25soc/blob/master/xula.ucf) file, needs
to be updated to match the current constraints.
Solving this multi-language coordination problem is the purpose of AutoFPGA.
Unlike many of the other tools out there, such as Xilinx's board design flow,
AutoFPGA is not built with the clueless beginner in mind, neither is it built
to hide the details of what is going within the project it creates. Instead,
AutoFPGA is built with the sole purpose of alleviating any burden on the FPGA
designer who otherwise has to create and maintain coherency between multiple
design files.
That this program facilitates composing and building new designs from existing
components ... is just a bonus.
# Goal
The goal of AutoFPGA is to be able to take a series of bus component
configuration files and to compose a design consisting of the various bus
components, linked together in logic, having an appropriate bus interconnect
and more.
From a user's point of view, one would run AutoFPGA with a list of component
definition files, given on the command line, and to thus be able to generate
(or update?) the various design files discussed above:
- [rtl/toplevel.v](demo-out/toplevel.v)
- [rtl/main.v](demo-out/main.v)
- [rtl/make.inc](demo-out/rtl.make.inc)
- [rtl/iscachable.v](demo-out/iscachable.v) -- a function of bus address determining what addresses are cachable and which are not
- [sw/host/regdefs.h](demo-out/regdefs.h)
- [sw/host/regdefs.cpp](demo-out/regdefs.cpp)
- [sw/zlib/board.h](demo-out/board.h)
- [sw/zlib/board.ld](demo-out/board.ld)
- [build.xdc](demo-out/build.xdc) (Created by modifying an existing XDC file. LPF, PCF, and UCF files are also supported)
- [sim/verilated/testb.h](demo-out/testb.h)
- [sim/verilated/main_tb.h](demo-out/main_tb.cpp)
- doc/src/(component name).tex (Not started yet)
Specifically, the parser must determine:
- If any of the components used in the project need to be configured, and if
so, what the configuration parameters are and how they need to be set. For
example, the UART baud rate and RTC and GPS clock steps both need to be set
based upon the actual clock speed of the master clock. Placing [a
clock module](auto-data/clock.txt) within the design that sets up a clock and
declares its rate is the current method for accomplishing this. Designs using
more than one clock often have an
[allclocks.txt](https://github.com/ZipCPU/openarty/autodata/allclocks.txt)
file to define all of the various clocks used within a design.
- If peripherals have or create interrupts, those need to be found and
determined, and (even better) wired up.
- If an AutoFPGA configuration file describes one of the following classes of
items, then the file is wired up and connected to create the necessary bus
wiring as well.
* Bus masters
Are automatically connected to a crossbar with full access to all of the
slaves on the bus
* One-clock Peripherals (interrupt controller, etc.)
* Two-clock Peripherals (RTC clock, block RAM, scopes, etc.)
* Memory Peripherals
o These need a line within the linker script, and they need to define if
their memory region, within that linker script, has read, write, or
o Generic Peripherals ([flash](auto-data/flash.txt), SDRAM,
[MDIO](auto-data/mdio.txt), etc.)
- Peripheral files need to be able to describe more than one peripheral. For
example, the [GPS peripheral file](auto-data/gps.txt) has a GPS-Clock,
a companion test bench, GPS-TB, to measure the performance of the GPS clock,
and a serial port ([WBUART](https://github.com/ZipCPU/wbuart32)) to allow us
to read from the GPS and to write to it and so configure it. Of course ...
this also includes a parameter that must be set (baud rate) based upon the
global clock rate.
## Classes
Some peripherals might exist at multiple locations within a design.
For example, the WBUART serial component can be used to create multiple
serial ports within a design.
To handle this case, the WBUART configuration file may be subclassed within
other component configuration files by defining a key
@INCLUDEFILE=[wbuart.txt](auto-data/wbuart.txt). This will provide a set of
keys that the current file can then override (inherit from).
Unfortunately, this only works if the included file has only one component
defined within it.
## Math
Some peripherals need to be able to perform basic integer math on a given
value to determine an appropriate setting value. These peripherals need
access to variables. The classic examples are the baud rate, which depends
upon the clock rate, as well as the step size necessary for the RTC and the
GPS clocks, both of which also depend upon the master clock rate. Other
examples might include determining the size of the address space to assign
to a core based upon the memory size of the component and so forth.
This feature is currently fully supported using integer math.
## Legacy Updates
The original version of AutoFPGA supported only one bus master, one bus type,
and an interconnect with a known bug in it.
Specifically, the broken interconnect would allow a master to make requests
of one peripheral and then another before the first peripheral had responded,
while not preventing the requests from returning out of order.
Fixing this bug introduced several incompatible changes, therefore there is
an AutoFPGA `legacy` git tag defined to get back to the older version.
This newer version, however, now supports:
- Multiple bus types: [Wishbone (pipelined)](sw/bus/wb.cpp),
[AXI-Lite](sw/bus/axil.cpp), and [AXI](sw/bus/axi.cpp)
Additional busses may be supported by simply creating a C++ bus component
definition class for them.
- Full crossbar support, using bus helper files from my [WB2AXIP](https://github.com/ZipCPU/wb2axip) repository.
Much to my surprise, the full crossbar support has proved to be simpler, in
terms of logic elements used, than the legacy interconnect I had been using.
# Status
This project now has several designs built around it. These include the
[basic AutoFPGA-demo](https://github.com/ZipCPU/autofpga-demo) project,
[OpenArty](https://github.com/ZipCPU/openarty),
[ArrowZip](https://github.com/ZipCPU/arrowzip) (legacy AutoFPGA only),
[AXI DMA test bench](https://github.com/ZipCPU/axidmacheck),
[ICOZip](https://github.com/ZipCPU/icozip),
[SDR](https://github.com/ZipCPU/sdr) (a gateware defined radio),
[ZBasic](https://github.com/ZipCPU/zbasic),
[ZipStorm-mx](https://github.com/ZipCPU/zipstormmx) (legacy AutoFGPA only), and
[ZipVersa](https://github.com/ZipCPU/zipversa). There's also a rather nice
[Nexys Video project](https://github.com/ZipCPU/videozip) that I've used for
modifying and delivering to customers, although the current version on github
is currently a touch out of date. You can see the autogenerated logic generated
for this project in the [demo directory](demo-out/).
I've also used AutoFPGA to generate a design for the Cyclone-V on the DE-10
Nano, as well as a design for an [Arty Z7-20](https://github.com/ZipCPU/openz7).
In sum:
- Simple bus components ... just work. This includes both bus masters and bus
slaves. Not only that, the bus simplifier logic also "just works", with
the caveat below.
Note that the AXI SINGLE simplifier itself hasn't (yet) been built. (It's
waiting on a funded need.) For now, the [AXI DOUBLE bus
simplifier](https://github.com/ZipCPU/wb2axip/blob/master/rtl/axidouble.v)
should work quite well. To use it, just declare a bus slave to be a slave
of an AXI type bus, with SLAVE.TYPE set to SINGLE, then follow the rule
listed in the
[simplifier](https://github.com/ZipCPU/wb2axip/blob/master/rtl/axidouble.v).
The same applies to the AXI-lite simplifiers. Wishbone simplifiers, both
SINGLE and DOUBLE, are handled by logic inserted into `main.v`, rather
than referenced by `main.v`.
- Components with logic in the toplevel work nicely as well.
- AutoFPGA can now support multiple, dissimilar clock rates. Users just need
to specify a clock to generate it. The clock is then made available for
configuration files to reference. This includes creating a test bench
wrapper for Verilator that will drive a multi-clock simulation.
- Addresses get assigned in three groups, and processed in three groups:
simple `SINGLE` components having only one address, simple `DOUBLE`
components having more addresses but only a single clock delay, and all
other components and memories.
- Multiple bus support is now included, allowing you to create and attach
components through bus adapters. This will allow a request to transition
from one component to the next, while also keeping track of what the final
addresses are for reference from the top level bus.
This makes it possible for the SDRAM to be on one bus, supporting video
reads/writes, and for the CPU to be able to access that bus as
well--as a sub-bus of the main peripheral/memory bus.
- Interrupts get assigned to a named controller, and then C++ header files are
updated to reflect the interrupt assignments
- A simple integer mathematical expression evaluator exists, allowing simple
math expressions and print formats. This makes it possible to set a global
clock frequency value, and to then set baud rates and other clock dividers
from it.
- Only one type of address building is supported. I'd like to be able to
support others, but so far this has been sufficient for my first project.
o Likewise, the project only supports WB B4/pipelined. No support is
provided for WB B3/classic (yet), although creating such support shoud not
be difficult at all.
- AutoFPGA now builds a [ZipCPU Linker Script](demo-out/board.ld) for the
project. This script is highly configurable, and many of my projects contain
configurations for multiple linker scripts--depending upon which memories
I decide to include in the design, or which ones I want a particular piece of
software to use.
- The LaTeX specification table building isn't there ... yet.
# Sample component files
Component files now exist for many of the components I've been using regularly.
These include: a [Flash](auto-data/flash.txt) controller,
[block RAM](auto-data/bkram.txt), a [UART console](auto-data/wbuart.txt),
a very simple [GPIO controller](auto-data/gpio.txt),
[RMII ethernet controller](auto-data/enet.txt),
[MDIO ethernet control interface](auto-data/mdio.txt),
a [GPS UART and PPS-driven internal clock](auto-data/gps.txt),
a [Real-Time (GPS driven) Clock](auto-data/rtcgps.txt),
a [PS/2 Mouse](auto-data/wbmouse.txt),
an [OLED component](auto-data/wboledbw.txt), and more.
Many of these component cores exist and have their own repositories elsewhere.
For example, the wishbone UART core may be found
[here](https://github.com/ZipCPU/wbuart32), and you can find a [MIG-based,
Wishbone controlled SDRAM component
here](https://github.com/ZipCPU/openarty/blob/master/autodata/sdram.txt).
You can also find a AXI examples, such as [AXI S2MM stream-to-memory data
mover](https://github.com/ZipCPU/axidmacheck/blob/master/autodata/axis2mm.txt),
an [AXI MM2S memory-to-stream data
mover](https://github.com/ZipCPU/axidmacheck/blob/master/autodata/axis2mm.txt),
or an [AXM block RAM
component](https://github.com/ZipCPU/axidmacheck/blob/master/autodata/axiram.txt)
in the [AXI DMA test repository](https://github.com/ZipCPU/axidmacheck).
Building the cores themselves is not a part of this project, but rather
figuring out how to compose multiple cores into a top level design from
both cores and component descriptions.
# The ZipCPU blog
Several articles have now been written to date about AutoFPGA on the ZipCPU
blog. These includes:
1. [A brief introduction to AutoFPGA](https://zipcpu.com/zipcpu/2017/10/05/autofpga-intro.html)
2. [Using AutoFPGA to connect simple registers to a debugging bus](https://zipcpu.com/zipcpu/2017/10/06/autofpga-dataword.html)
This article is really out of date, in that it describes only the legacy
mode (one master, one bus type, etc.)
3. [AutoFPGA's linker script support gets an update](https://zipcpu.com/zipcpu/2018/12/22/autofpga-ld.html)
4. [Technology debt and AutoFPGA, the bill just came due](https://zipcpu.com/zipcpu/2019/08/22/tech-debt.html)
5. [Understanding AutoFPGA's address assignment algorithm](https://zipcpu.com/zipcpu/2019/09/03/address-assignment.html)
# Getting Started
The current best reference for AutoFPGA is the [icd.txt](doc/icd.txt) file,
which describes all of the various tags AutoFPGA understands and how they
can be used. I've also started working on an [intermediate
design](https://zipcpu.com/tutorial/intermediate.html)
tutorial based around AutoFPGA, so you might find that a useful place to start
as well.
# License
AutoFPGA is designed for release under the GPLv3 license. The AutoFPGA
generated code is yours, and free to be relicensed as you see fit.
# Commercial Applications
Should you find the GPLv3 license insufficient for your needs, other licenses
can be purchased from Gisselquist Technology, LLC. Given that the AutoFPGA
generated code is not encumbered by any license requirements, I really don't
expect any such requests.
Likewise, please contact us should you wish to guide, direct, or otherwise
fund the development of this project. You can contact me at my user name,
dgisselq, at the wonderful ieee.org host.
================================================
FILE: auto-data/allclocks.txt
================================================
################################################################################
##
## Filename: auto-data/allclocks.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Describe how to create the clocks necessary for the design
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2015-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=iclock
@ACCESS=ALLCLOCKS_PRESENT
@CLOCK.NAME=clk
@CLOCK.WIRE=i_clk
@CLOCK.FREQUENCY=100000000
@CLOCK.TOP=i_clk
@BDEFS.DEFN=
#define CLOCK_FREQUENCY_HZ @$(CLOCK.FREQUENCY)
#define CLKFREQHZ @$(CLOCK.FREQUENCY)
@REGDEFS.H.DEFNS=
#define CLKFREQHZ @$(CLOCK.FREQUENCY)
#
#
@PREFIX=masterclk
@TOP.DEFNS=
// Clock/reset definitions
// {{{
wire s_clk_200mhz, s_clk_200mhz_unbuffered,
sysclk_locked, sysclk_feedback, sysclk_feedback_buffered,
s_clk_250mhz, s_clk_250_unbuffered,
s_clk_125mhz, s_clk_125_unbuffered,
s_clk_125d, s_clk_125d_unbuffered,
s_clksync, s_clksync_unbuffered,
s_clk_400mhz, s_clk_400mhz_unbuffered, // Pixclk * 10
s_clk_80mhz_unbuffered, // 80MHz
netclk_locked, netclk_feedback, netclk_feedback_buffered;
wire i_clk_buffered;
wire clocks_locked;
wire dly_ctrl_ready;
reg [3:0] sysclk_stable, syncd_stable;
reg [4:0] pll_reset_sreg;
reg pll_reset;
// }}}
@TOP.PORTLIST=
@TOP.IODECL=
@TOP.MAIN=
// PLL generated clocks
s_clk_125mhz
@TOP.INSERT=
// Buffer the incoming clock
BUFG @$(PREFIX)clkbufi(.I(i_clk), .O(i_clk_buffered));
// pll_reset
initial { pll_reset, pll_reset_sreg } = -1;
always @(posedge i_clk_buffered)
{ pll_reset, pll_reset_sreg } <= { pll_reset_sreg, 1'b0 };
////////////////////////////////////////////////////////////////////////
//
// PLL #1: 100MHz, 200MHz, 400MHz, and 80MHz
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// But ... the delay controller requires a 200 MHz reference clock,
// the generic clock generator requires a 400MHz clock and a clock
// synchronized to it
PLLE2_BASE #(
// {{{
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10),
.CLKOUT0_DIVIDE(4), // 200 MHz
.CLKOUT1_DIVIDE(2), // 400 MHz
.CLKOUT2_DIVIDE(8), // 100 MHz
.CLKOUT3_DIVIDE(10) // 80 MHz
// }}}
) gen_sysclk(
// {{{
.CLKIN1(i_clk_buffered),
.CLKOUT0(s_clk_200mhz_unbuffered),
.CLKOUT1(s_clk_400mhz_unbuffered),
.CLKOUT2(s_clksync_unbuffered),
.CLKOUT3(s_clk_80mhz_unbuffered),
// .CLKOUT4(),
// .CLKOUT5(),
.PWRDWN(1'b0), .RST(pll_reset),
.CLKFBOUT(sysclk_feedback),
.CLKFBIN(sysclk_feedback_buffered),
.LOCKED(sysclk_locked)
// }}}
);
BUFG sysbuf( .I(s_clk_200mhz_unbuffered),.O(s_clk_200mhz));
BUFG clksync_buf(.I(s_clksync_unbuffered), .O(s_clksync));
BUFG clk4x_buf( .I(s_clk_400mhz_unbuffered),.O(s_clk_400mhz));
BUFG sys_feedback(.I(sysclk_feedback),.O(sysclk_feedback_buffered));
// }}}
////////////////////////////////////////////////////////////////////////
//
// PLL #2: 125MHz, 250MHz
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// The ethernet MAC requires a 125MHz clock
// We can't trust the RX 125MHz clock for this, since there's a
// possibility the RX 125MHz clock might arrive at a different rate.
//
PLLE2_BASE #(
// {{{
.CLKFBOUT_MULT(10),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10),
.CLKOUT0_DIVIDE(8), // 125 MHz
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(4), // 250 MHz
.CLKOUT1_PHASE(0)
// }}}
) gen_netclk(
// {{{
.CLKIN1(i_clk_buffered),
.CLKOUT0(s_clk_125_unbuffered),
.CLKOUT1(s_clk_250_unbuffered),
// .CLKOUT2(),
// .CLKOUT3(),
// .CLKOUT4(),
// .CLKOUT5(),
.PWRDWN(1'b0), .RST(pll_reset),
.CLKFBOUT(netclk_feedback),
.CLKFBIN(netclk_feedback_buffered),
.LOCKED(netclk_locked)
// }}}
);
BUFG netbuf(.I(s_clk_125_unbuffered), .O(s_clk_125mhz));
BUFG netbf5(.I(s_clk_250_unbuffered), .O(s_clk_250mhz));
BUFG netfb(.I(netclk_feedback), .O(netclk_feedback_buffered));
assign clocks_locked = (netclk_locked && sysclk_locked && dly_ctrl_ready);
// }}}
////////////////////////////////////////////////////////////////////////
//
// reg [3:0] sysclk_stable;
// {{{
initial sysclk_stable = 0;
always @(posedge i_clk_buffered or negedge clocks_locked)
if (!clocks_locked)
sysclk_stable <= 0;
else
sysclk_stable <= { sysclk_stable[2:0], 1'b1 };
initial syncd_stable = 0;
always @(posedge i_clk_buffered)
if (!sysclk_stable[3])
syncd_stable <= 0;
else
syncd_stable <= { syncd_stable[2:0], 1'b1 };
// }}}
////////////////////////////////////////////////////////////////////////
//
// IDELAYCTRL
IDELAYCTRL
u_delay_control (
.REFCLK(s_clk_200mhz),
.RST(!sysclk_locked),
.RDY(dly_ctrl_ready)
);
@MAIN.PORTLIST=
// Extra clocks
i_clk_125mhz
@MAIN.IODECL=
// Extra clocks
// Verilator lint_off UNUSED
input wire i_clk_125mhz;
// Verilator lint_on UNUSED
@MAIN.DEFNS=
wire i_net_tx_clk;
@MAIN.INSERT=
assign i_net_tx_clk = i_clk_125mhz;
@CLOCK.WIRE=i_clk_125mhz
@CLOCK.NAME=clk_125mhz
@CLOCK.FREQUENCY=125000000
@CLOCK.TOP=
@MAIN.IODECL=
input wire i_net_tx_clk;
@XDC.INSERT=
set_false_path -from [get_cells -hier -filter {NAME=~ pll_reset*}] -to [get_cells -hier -filter {NAME=~ net*/reset_pipe*}]
set_false_path -from [get_cells -hier -filter {NAME=~ pll_reset*}] -to [get_cells -hier -filter {NAME=~ net*/sync_reset*}]
================================================
FILE: auto-data/bkram.txt
================================================
################################################################################
##
## Filename: auto-data/bkram.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: To define the interface to a generic block RAM device for the
## purposes of autofpga.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=bkram
@DEVID=BKRAM
@$LGMEMSZ=20
@LGMEMSZ.FORMAT=%d
@$NADDR=(1<<(@$(THIS.LGMEMSZ)))/(@$(SLAVE.BUS.WIDTH)/8)
@$NBYTES=(1<<(@$THIS.LGMEMSZ))
@NBYTES.FORMAT=0x%08x
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wbwide
@MAIN.INSERT=
memdev #(
.LGMEMSZ(@$(THIS.LGMEMSZ)),
.DW(@$(SLAVE.BUS.WIDTH)),
.EXTRACLOCK(1)
) u_@$(PREFIX) (
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)),
.i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
@$(SLAVE.ANSIPORTLIST)
);
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) RAM
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@MEM.NAME= @$(PREFIX)
@BDEF.OSVAL=extern char _@$(MEM.NAME)[@$NBYTES];
@LD.PERM= wx
@LD.NAME= @$(MEM.NAME)
@RTL.MAKE.GROUP= @$(DEVID)
@RTL.MAKE.SUBD=
@RTL.MAKE.FILES= memdev.v
@$NADDRHX = @$NADDR
@NADDRHX.FORMAT= 0x%x
@SIM.INCLUDE=
#include "byteswap.h"
@SIM.DEFINES=
#ifndef VVAR
#ifdef ROOT_VERILATOR
#include "Vmain___024root.h"
#define VVAR(A) rootp->main__DOT_ ## A
#elif defined(NEW_VERILATOR)
#define VVAR(A) main__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
#endif
#define block_ram rootp->main__DOT__u_@$(PREFIX)__DOT__mem.m_storage
@$BUSBYTES=@$(SLAVE.BUS.WIDTH)/8
@SLAVE.ORDER=1
@SIM.LOAD=
start = start & (-4);
wlen = (wlen+3)&(-4);
// Need to byte swap data to get it into the memory
if (@$(SLAVE.BUS.WIDTH) == 32) {
char *bswapd = new char[len+8];
memcpy(bswapd, &buf[offset], wlen);
byteswapbuf(len>>2, (uint32_t *)bswapd);
memcpy(&m_core->block_ram[start], bswapd, wlen);
delete[] bswapd;
} else {
for(unsigned jk=0; jk<wlen; jk=jk+1) {
unsigned word_addr, subword_addr;
unsigned *wp;
char *cp;
word_addr = start+jk;
word_addr /= @$(SLAVE.BUS.WIDTH)/8;
wp = m_core->block_ram[word_addr];
cp = (char *)wp;
subword_addr = start+jk;
subword_addr = ~subword_addr;
subword_addr &= @$(SLAVE.BUS.WIDTH)/8-1;
// subword_addr = @$(SLAVE.BUS.WIDTH)/8-subword_addr;
cp[subword_addr] = buf[offset+jk];
}
}
================================================
FILE: auto-data/buserr.txt
================================================
################################################################################
##
## Filename: auto-data/buserr.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Provide a readable memory location containing the address of the
## last bus error.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=buserr
@NADDR=1
@SLAVE.TYPE=SINGLE
@SLAVE.BUS=wb32
@SINGLE.INPUT= r_bus_err
@CLOCK.NAME=clk
@$RWID=(@$(zip.MASTER.BUS.AWID) > @$(wbu.MASTER.BUS.AWID)) ? @$(zip.MASTER.BUS.AWID) : @$(wbu.MASTER.BUS.AWID)
@MAIN.DEFNS=
reg [@$(RWID)-1:0] r_@$(PREFIX)_addr;
@MAIN.INSERT=
always @(posedge @$(CLOCK.WIRE))
if (@$(zip.MASTER.PREFIX)_err)
begin
r_@$(PREFIX)_addr <= 0;
r_@$(PREFIX)_addr[@$(zip.MASTER.BUS.AWID)-1:0] <= @$(zip.MASTER.PREFIX)_addr[@$(zip.MASTER.BUS.AWID)-1:0];
end else if (@$(wbu.MASTER.PREFIX)_err)
begin
r_@$(PREFIX)_addr <= 0;
r_@$(PREFIX)_addr[@$(wbu.MASTER.BUS.AWID)-1:0] <= @$(wbu.MASTER.PREFIX)_addr[@$(wbu.MASTER.BUS.AWID)-1:0];
end
assign @$(SLAVE.PREFIX)_stall= 1'b0;
assign @$(SLAVE.PREFIX)_ack = @$(SLAVE.PREFIX)_stb;
assign @$(SLAVE.PREFIX)_idata = { {(30-@$(RWID)){1'b0}},
r_@$(PREFIX)_addr, 2'b00 };
@REGS.N=1
@REGS.0= 0 R_BUSERR BUSERR
@BDEF.IONAME=io_buserr
@BDEF.IOTYPE=unsigned
@BDEF.OSDEF=_BOARD_HAS_BUSERR
@BDEF.OSVAL=static volatile @$THIS.BDEF.IOTYPE *const _buserr = ((@$THIS.BDEF.IOTYPE *)@$[0x%08x](REGBASE));
================================================
FILE: auto-data/clkcheck.txt
================================================
################################################################################
##
## Filename: auto-data/clkcheck.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: To describe the clkcounter's interface for autofpga to work
## with.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=rtc_pps
@MAIN.DEFNS=
// Verilator lint_off UNUSED
reg @$(PREFIX);
reg [26:0] @$(PREFIX)_counter;
// Verilator lint_on UNUSED
@MAIN.INSERT=
initial @$(PREFIX) = 1'b0;
initial @$(PREFIX)_counter = 0;
always @(posedge i_clk)
if (@$(PREFIX)_counter > 0)
begin
@$(PREFIX)_counter <= @$(PREFIX)_counter - 1;
@$(PREFIX) <= 1'b0;
end else begin
@$(PREFIX)_counter <= 27'd100_000_000 - 1;
@$(PREFIX) <= 1'b1;
end
@PREFIX=rxeth0ck
@DEVID=RXETH0CK
@INCLUDEFILE=clkcounter.txt
@TSTCLOCK=i_eth0_rx_clk
@DEPENDS=MEGANET_ACCESS
##
@PREFIX=txclk
@DEVID=TXCLK
@INCLUDEFILE=clkcounter.txt
@DEPENDS=ALLCLOCKS_PRESENT
@TSTCLOCK=i_net_tx_clk
##
@PREFIX=adcclk
@DEVID=ADCCLK
@INCLUDEFILE=clkcounter.txt
@DEPENDS=ALLCLOCKS_PRESENT
@TSTCLOCK=i_clk_200mhz
##
## @PREFIX=pixclk
## @DEVID=PIXCLK
## @INCLUDEFILE=clkcounter.txt
## @DEPENDS=ALLCLOCKS_PRESENT
## @TSTCLOCK=i_pixclk
##
## @PREFIX=audioclk
## @DEVID=AUDIOCLK
## @INCLUDE=clkcounter.txt
## @TSTCLOCK=i_pixclk
================================================
FILE: auto-data/clkcounter.txt
================================================
################################################################################
##
## Filename: auto-data/clkcounter.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: The clkcounter peripheral counts the number of a given clocks
## ticks per second as defined by a second clock. This particular
## file tells us how to connect the clkcounter to the rest of the design
## using AutoFPGA.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=sysclk
@DEVID=SYSCLK
@ACCESS=@$(DEVID)
@NADDR= 1
@SLAVE.TYPE= SINGLE
@SLAVE.BUS=wb32
@TSTCLOCK=i_clk
# @SINGLE.INPUTS= ck_pps
@MAIN.DEFNS=
reg r_@$(PREFIX)_ack;
@MAIN.INSERT=
clkcounter #(
.CLOCKFREQ_HZ(0) // We'll count PPS externally
) clk@$(PREFIX)ctr(
.i_sys_clk(i_clk),
.i_tst_clk(@$(TSTCLOCK)),
.i_sys_pps(rtc_pps),
.o_sys_counts(@$(SLAVE.PREFIX)_idata)
);
initial r_@$(PREFIX)_ack = 0;
always @(posedge i_clk)
r_@$(PREFIX)_ack <= !i_reset && @$(SLAVE.PREFIX)_stb;
assign @$(SLAVE.PREFIX)_ack = r_@$(PREFIX)_ack;
assign @$(SLAVE.PREFIX)_stall = 1'b0;
@REGS.NOTE = // SYSCLK Clock Counter (measures clock speed)
@REGS.N = 1
@REGS.0 = 0 R_@$(DEVID) @$(DEVID)
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE= unsigned
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@XDC.INSERT=
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *clk@$(PREFIX)ctr/avgs*}] -to [ get_cells -hier -filter {NAME =~*clk@$(PREFIX)ctr/q_v*}] 8.0
================================================
FILE: auto-data/crossbus.txt
================================================
################################################################################
##
## Filename: auto-data/crossbus.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Provides access to the smaller 32-bit bus from the 512-bit bus.
## Accesses are limited to a single controller only, but perhaps
## this is okay since I don't expect anything but the CPU and the debugging
## port to control the 32-bit bus.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=crossbus
@SLAVE.TYPE=BUS
@SLAVE.BUS=wbwide
@SLAVE.ANSPREFIX=w
@SLAVE.ORDER=0
@ERROR.WIRE=@$(SLAVE.PREFIX)_err
## @$SLAVE.AWID=@$(MASTER.AWID) >> (@$(SLAVE.BUS_WIDTH)-@$(MASTER.BUS.WIDTH))
@MASTER.TYPE=SUBBUS
@MASTER.BUS=wb32
@OPT_LITTLE_ENDIAN=1'b0
@OPT_LOWLOGIC=1'b0
@MAIN.INSERT=
wbdown #(
// {{{
// Slave bus address width: @$(SLAVE.BUS.AWID)
// Slave address width : @$(SLAVE.AWID)
// Master address width : @$(MASTER.BUS.AWID)
.ADDRESS_WIDTH(@$(SLAVE.AWID)+$clog2(@$(SLAVE.BUS.WIDTH)/8)),
.WIDE_DW(@$(SLAVE.BUS.WIDTH)),
.SMALL_DW(@$(MASTER.BUS.WIDTH)),
.OPT_LITTLE_ENDIAN(@$(OPT_LITTLE_ENDIAN)),
.OPT_LOWLOGIC(@$(OPT_LOWLOGIC))
// }}}
) u_@$(PREFIX) (
// {{{
.i_clk(@$(MASTER.BUS.CLOCK.WIRE)),
.i_reset(@$(MASTER.BUS.CLOCK.RESET)),
// Slave/incoming
// {{{
.i_wcyc( @$(SLAVE.PREFIX)_cyc),
.i_wstb( @$(SLAVE.PREFIX)_stb),
.i_wwe( @$(SLAVE.PREFIX)_we),
.i_waddr( @$(SLAVE.PREFIX)_addr[@$(SLAVE.AWID)-1:0]),
.i_wdata( @$(SLAVE.PREFIX)_data),
.i_wsel( @$(SLAVE.PREFIX)_sel),
.o_wstall(@$(SLAVE.PREFIX)_stall),
.o_wack( @$(SLAVE.PREFIX)_ack),
.o_wdata( @$(SLAVE.PREFIX)_idata),
.o_werr( @$(SLAVE.PREFIX)_err),
// }}}
// Master/down-range/outgoing
// {{{
.o_scyc( @$(MASTER.PREFIX)_cyc),
.o_sstb( @$(MASTER.PREFIX)_stb),
.o_swe( @$(MASTER.PREFIX)_we),
.o_saddr( @$(MASTER.PREFIX)_addr[@$(MASTER.BUS.AWID)-1:0]),
.o_sdata( @$(MASTER.PREFIX)_data),
.o_ssel( @$(MASTER.PREFIX)_sel),
.i_sstall(@$(MASTER.PREFIX)_stall),
.i_sack( @$(MASTER.PREFIX)_ack),
.i_sdata( @$(MASTER.PREFIX)_idata),
.i_serr( @$(MASTER.PREFIX)_err)
// }}}
// }}}
);
================================================
FILE: auto-data/ddr3.txt
================================================
################################################################################
##
## Filename: auto-data/ddr3.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: To describe how to connect an open source DDR3 controller to
## the design, via the Wishbone bus.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
# Wishbone 1
@PREFIX=ddr3
@DEVID=SDRAM
@ACCESS=@$(DEVID)_ACCESS
## LGMEMSZ is the size of the SDRAM in bytes. For a 1GB DDR3 RAM: 30 => 1GB
@$LGMEMSZ=30
@LGMEMSZ.FORMAT=%d
@$NADDR=(1<< @$(LGMEMSZ))/(@$(SLAVE.BUS.WIDTH)/8)
@$NBYTES=(1<<(@$LGMEMSZ))
@NBYTES.FORMAT=0x%08x
@$MADDR= @$(REGBASE)
@MADDR.FORMAT=0x%08x
@$NLANES=@$(SLAVE.BUS.WIDTH)/64
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wbwide
@SLAVE.ORDER=100
@BUS=wbwide
@LD.PERM=wx
@LD.NAME=sdram
#
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$(NBYTES)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
@TOP.PORTLIST=
// DDR3 I/O port wires
o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n,
o_ddr3_vsel,
o_ddr3_cs_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n,
o_ddr3_ba, o_ddr3_a,
o_ddr3_odt, o_ddr3_dm,
io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq
@TOP.PARAM=
localparam real @$(DEVID)CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
DDR3_CLK_PERIOD = 2_500; //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
localparam @$(DEVID)ROW_BITS = 14, // width of row address
@$(DEVID)COL_BITS = 10, // width of column address
@$(DEVID)BA_BITS = 3, // width of bank address
@$(DEVID)DQ_BITS = 8, // Size of one octet
@$(DEVID)BYTE_LANES = @$(NLANES), //8 lanes of DQ
@$(DEVID)AUX_WIDTH = 4, //width of aux line (must be >= 4)
@$(DEVID)SERDES_RATIO = $rtoi(@$(DEVID)CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
@$(DEVID)CMD_LEN = 4 + 3 + @$(DEVID)BA_BITS + @$(DEVID)ROW_BITS;
@TOP.IODECL=
// I/O declarations for the DDR3 SDRAM
// {{{
output wire o_ddr3_reset_n;
output wire [0:0] o_ddr3_cke;
output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n;
output wire [0:0] o_ddr3_cs_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank
output wire o_ddr3_vsel;
output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n;
output wire [@$(DEVID)BA_BITS-1:0] o_ddr3_ba;
output wire [14:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant
output wire [0:0] o_ddr3_odt;
output wire [@$(DEVID)BYTE_LANES-1:0] o_ddr3_dm;
inout wire [(@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n;
inout wire [(@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES)-1:0] io_ddr3_dq;
// }}}
@TOP.DEFNS=
wire s_clk, s_reset;
reg [2:0] clk_reset_pipe;
// Wires connected to PHY interface of DDR3 controller
// {{{
genvar @$(PREFIX)gen_index;
wire [@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8-1:0] @$(PREFIX)_iserdes_data;
wire [@$(DEVID)BYTE_LANES*8-1:0] @$(PREFIX)_iserdes_dqs,
@$(PREFIX)_iserdes_bitslip_reference;
wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0]
@$(PREFIX)_cmd;
wire [@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8-1:0]
@$(PREFIX)_data;
wire [(@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8)/8-1:0]
@$(PREFIX)_dm;
wire [4:0] @$(PREFIX)_odelay_data_cntvaluein,
@$(PREFIX)_odelay_dqs_cntvaluein,
@$(PREFIX)_idelay_data_cntvaluein,
@$(PREFIX)_idelay_dqs_cntvaluein;
wire [@$(DEVID)BYTE_LANES-1:0] @$(PREFIX)_odelay_data_ld,
@$(PREFIX)_odelay_dqs_ld, @$(PREFIX)_idelay_data_ld,
@$(PREFIX)_idelay_dqs_ld, @$(PREFIX)_bitslip,
@$(PREFIX)_debug_read_dqs_p,
@$(PREFIX)_debug_read_dqs_n;
wire @$(PREFIX)_idelayctrl_rdy,
@$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control,
@$(PREFIX)_toggle_dqs, @$(PREFIX)_write_leveling_calib,
@$(PREFIX)_reset;
wire @$(PREFIX)_debug_clk_p, @$(PREFIX)_debug_clk_n;
// }}}
@TOP.MAIN=
// DDR3 Controller-PHY Interface
@$(PREFIX)_iserdes_data, @$(PREFIX)_iserdes_dqs,
@$(PREFIX)_iserdes_bitslip_reference,
@$(PREFIX)_idelayctrl_rdy,
@$(PREFIX)_cmd,
@$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control,
@$(PREFIX)_toggle_dqs, @$(PREFIX)_data, @$(PREFIX)_dm,
@$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein,
@$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein,
@$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld,
@$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld,
@$(PREFIX)_bitslip,
@$(PREFIX)_write_leveling_calib,
@$(PREFIX)_reset
@TOP.INSERT=
assign s_clk = s_clksync;
assign o_ddr3_vsel = 1'bz;
always @(posedge s_clk or negedge clocks_locked)
if (!clocks_locked)
clk_reset_pipe <= 3'h7;
else
clk_reset_pipe <= { clk_reset_pipe[1:0], 1'b0 };
assign s_reset = clk_reset_pipe[2];
// DDR3 PHY Instantiation
ddr3_phy #(
// {{{
.ROW_BITS(@$(DEVID)ROW_BITS), //width of row address
.BA_BITS(@$(DEVID)BA_BITS), //width of bank address
.DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ
.LANES(@$(DEVID)BYTE_LANES), //8 lanes of DQ
.CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device
.ODELAY_SUPPORTED(1)
// }}}
) ddr3_phy_inst (
// {{{
// clock and reset
.i_controller_clk(s_clksync),
.i_ddr3_clk(s_clk_400mhz),
.i_ref_clk(s_clk_200mhz),
.i_ddr3_clk_90(0), //required only when ODELAY_SUPPORTED is zero
.i_rst_n(!s_reset),
// Controller Interface
.i_controller_reset(@$(PREFIX)_reset),
.i_controller_cmd(@$(PREFIX)_cmd),
.i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control),
.i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control),
.i_controller_toggle_dqs(@$(PREFIX)_toggle_dqs),
.i_controller_data(@$(PREFIX)_data),
.i_controller_dm(@$(PREFIX)_dm),
.i_controller_odelay_data_cntvaluein(@$(PREFIX)_odelay_data_cntvaluein),
.i_controller_odelay_dqs_cntvaluein(@$(PREFIX)_odelay_dqs_cntvaluein),
.i_controller_idelay_data_cntvaluein(@$(PREFIX)_idelay_data_cntvaluein),
.i_controller_idelay_dqs_cntvaluein(@$(PREFIX)_idelay_dqs_cntvaluein),
.i_controller_odelay_data_ld(@$(PREFIX)_odelay_data_ld),
.i_controller_odelay_dqs_ld(@$(PREFIX)_odelay_dqs_ld),
.i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld),
.i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld),
.i_controller_bitslip(@$(PREFIX)_bitslip),
.i_controller_write_leveling_calib(@$(PREFIX)_write_leveling_calib),
.o_controller_iserdes_data(@$(PREFIX)_iserdes_data),
.o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs),
.o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference),
.o_controller_idelayctrl_rdy(@$(PREFIX)_idelayctrl_rdy),
// DDR3 I/O Interface
.o_ddr3_clk_p(o_ddr3_clk_p),
.o_ddr3_clk_n(o_ddr3_clk_n),
.o_ddr3_reset_n(o_ddr3_reset_n),
.o_ddr3_cke(o_ddr3_cke[0]), // CKE
.o_ddr3_cs_n(o_ddr3_cs_n[0]), // chip select signal (controls rank 1 only)
.o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
.o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
.o_ddr3_we_n(o_ddr3_we_n), // WE#
.o_ddr3_addr(o_ddr3_a[@$(DEVID)ROW_BITS-1:0]),
.o_ddr3_ba_addr(o_ddr3_ba),
.io_ddr3_dq(io_ddr3_dq),
.io_ddr3_dqs(io_ddr3_dqs_p),
.io_ddr3_dqs_n(io_ddr3_dqs_n),
.o_ddr3_dm(o_ddr3_dm),
.o_ddr3_odt(o_ddr3_odt[0]), // on-die termination
// DEBUG PHY
.o_ddr3_debug_read_dqs_p(@$(PREFIX)_debug_read_dqs_p),
.o_ddr3_debug_read_dqs_n(@$(PREFIX)_debug_read_dqs_n)
// }}}
);
generate for(@$(PREFIX)gen_index = @$(DEVID)ROW_BITS;
@$(PREFIX)gen_index < 15;
@$(PREFIX)gen_index = @$(PREFIX)gen_index + 1)
begin : GEN_UNUSED_@$(DEVID)_ASSIGN
assign o_ddr3_a[@$(PREFIX)gen_index] = 0;
end endgenerate
@MAIN.PORTLIST=
// DDR3 Controller Interface
i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs,
i_@$(PREFIX)_iserdes_bitslip_reference,
i_@$(PREFIX)_idelayctrl_rdy,
o_@$(PREFIX)_cmd,
o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control,
o_@$(PREFIX)_toggle_dqs, o_@$(PREFIX)_data, o_@$(PREFIX)_dm,
o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein,
o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein,
o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld,
o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld,
o_@$(PREFIX)_bitslip,
o_@$(PREFIX)_leveling_calib,
o_@$(PREFIX)_reset
@MAIN.PARAM=@$(TOP.PARAM)
@MAIN.IODECL=
// DDR3 Controller I/O declarations
// {{{
input wire [@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8-1:0] i_@$(PREFIX)_iserdes_data;
input wire [@$(DEVID)BYTE_LANES*8-1:0] i_@$(PREFIX)_iserdes_dqs;
input wire [@$(DEVID)BYTE_LANES*8-1:0] i_@$(PREFIX)_iserdes_bitslip_reference;
input wire i_@$(PREFIX)_idelayctrl_rdy;
output wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] o_@$(PREFIX)_cmd;
output wire o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control;
output wire o_@$(PREFIX)_toggle_dqs;
output wire [@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8-1:0] o_@$(PREFIX)_data;
output wire [(@$(DEVID)DQ_BITS*@$(DEVID)BYTE_LANES*8)/8-1:0] o_@$(PREFIX)_dm;
output wire [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein;
output wire [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein;
output wire [@$(DEVID)BYTE_LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld;
output wire [@$(DEVID)BYTE_LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld;
output wire [@$(DEVID)BYTE_LANES-1:0] o_@$(PREFIX)_bitslip;
output wire o_@$(PREFIX)_leveling_calib;
output wire o_@$(PREFIX)_reset;
// }}}
@MAIN.DEFNS=
// Verilator lint_off UNUSED
wire [@$(DEVID)AUX_WIDTH-1:0] @$(PREFIX)_aux_out;
wire [31:0] @$(PREFIX)_debug;
// Verilator lint_on UNUSED
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// DDR3 Controller instantiation
// {{{
ddr3_controller #(
// {{{
.CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(@$(DEVID)ROW_BITS), //width of row address
.COL_BITS(@$(DEVID)COL_BITS), //width of column address
.BA_BITS(@$(DEVID)BA_BITS), //width of bank address
.DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ
.LANES(@$(DEVID)BYTE_LANES), // byte lanes
.AUX_WIDTH(@$(DEVID)AUX_WIDTH), //width of aux line (must be >= 4)
.WB2_ADDR_BITS(7), //width of 2nd wishbone address bus
.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
.MICRON_SIM(0), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
.ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
.SECOND_WISHBONE(1) //set to 1 if 2nd wishbone is needed
// }}}
) u_@$(PREFIX) (
// {{{
.i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD
.i_rst_n(!i_reset), //200MHz input clock
// Wishbone 1 (Controller)
@$(SLAVE.ANSIPORTLIST),
.i_aux(0),
.o_aux(@$(PREFIX)_aux_out), // Leaving this empty would've caused a Verilator warning
// Wishbone 2 (PHY)
@$(ddr3_phy.SLAVE.ANSIPORTLIST),
//
// PHY interface
.i_phy_iserdes_data(i_@$(PREFIX)_iserdes_data),
.i_phy_iserdes_dqs(i_@$(PREFIX)_iserdes_dqs),
.i_phy_iserdes_bitslip_reference(i_@$(PREFIX)_iserdes_bitslip_reference),
.i_phy_idelayctrl_rdy(i_@$(PREFIX)_idelayctrl_rdy),
.o_phy_cmd(o_@$(PREFIX)_cmd),
.o_phy_dqs_tri_control(o_@$(PREFIX)_dqs_tri_control),
.o_phy_dq_tri_control(o_@$(PREFIX)_dq_tri_control),
.o_phy_toggle_dqs(o_@$(PREFIX)_toggle_dqs),
.o_phy_data(o_@$(PREFIX)_data),
.o_phy_dm(o_@$(PREFIX)_dm),
.o_phy_odelay_data_cntvaluein(o_@$(PREFIX)_odelay_data_cntvaluein),
.o_phy_odelay_dqs_cntvaluein(o_@$(PREFIX)_odelay_dqs_cntvaluein),
.o_phy_idelay_data_cntvaluein(o_@$(PREFIX)_idelay_data_cntvaluein),
.o_phy_idelay_dqs_cntvaluein(o_@$(PREFIX)_idelay_dqs_cntvaluein),
.o_phy_odelay_data_ld(o_@$(PREFIX)_odelay_data_ld),
.o_phy_odelay_dqs_ld(o_@$(PREFIX)_odelay_dqs_ld),
.o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld),
.o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld),
.o_phy_bitslip(o_@$(PREFIX)_bitslip),
.o_phy_write_leveling_calib(o_@$(PREFIX)_leveling_calib),
.o_phy_reset(o_@$(PREFIX)_reset),
// Debug port
.o_debug1(@$(PREFIX)_debug),
// Verilator lint_off PINCONNECTEMPTY
.o_debug2(),
.o_debug3()
// Verilator lint_on PINCONNECTEMPTY
// }}}
);
// }}}
##
##
@PREFIX=ddr3_phy
@DEVID=DDR3_PHY
@ACCESS=@$(DEVID)_ACCESS
@$NADDR=128
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb32
@SLAVE.ANSPREFIX=wb2_
#
@REGS.N=7
@REGS.0= 0 R_@$(DEVID) @$(DEVID) DPHYSTAT0
@REGS.1=1 R_@$(DEVID)STAT1 @$(DEVID)STAT1 DPHYSTAT1
@REGS.2=2 R_@$(DEVID)STAT2 @$(DEVID)STAT2 DPHYSTAT2
@REGS.3=3 R_@$(DEVID)STAT3 @$(DEVID)STAT3 DPHYSTAT3
@REGS.4=4 R_@$(DEVID)CTRLSTAT @$(DEVID)CTRLSTAT DCTRLSTAT
@REGS.5=17 R_@$(DEVID)RESET @$(DEVID)RESET DCTRLRESET
@REGS.6=19 R_@$(DEVID)DBGSEL @$(DEVID)DBGSEL DCTRLDBG
@BDEF.DEFN=
## Define the structure of your PHY controller here. How are the bits all
## layout out? What register names do you have? That should all go here.
typedef struct @$(DEVID)_S {
unsigned ph_something;
} @$(DEVID);
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=@$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@RTL.MAKE.GROUP=DDR3
@RTL.MAKE.SUBD=ddr3
@RTL.MAKE.FILES= ddr3_controller.v ddr3_phy.v
================================================
FILE: auto-data/edid.txt
================================================
################################################################################
##
## Filename: auto-data/edid.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Extended Display Identification Data. This peripheral is
## responsible for the ability to both read EDID from the
## downstream display, for forwarding it to the upstream (receive)
## display generator, and for making things available for the CPU to
## read.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2015-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=edid
@DEVID=EDID
@ACCESS=@$(DEVID)_ACCESS
@INCLUDEFILE=i2ccpu.txt
@IOSDA=io_hdmitx_sda
@IOSCL=io_hdmitx_scl
@INTERRUPT=edid_int
@INT.I2C.WIRE=
@INT.I2C.PIC=
@INT.EDID.WIRE=@$(INTERRUPT)
@INT.EDID.PIC=syspic
@BDEF.DEFN=
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE= I2CCPU
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// The EDID I2C Controller
// {{{
wbi2ccpu #(
.ADDRESS_WIDTH(@$(MASTER.BUS.AWID)),
.DATA_WIDTH(@$(MASTER.BUS.WIDTH)),
.AXIS_ID_WIDTH(@$(IDW))
) u_@$(PREFIX) (
// {{{
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)), .i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
@$(SLAVE.ANSIPORTLIST),
@$(MASTER.ANSIPORTLIST),
.i_i2c_sda(i_@$(PREFIX)_sda), .i_i2c_scl(i_@$(PREFIX)_scl),
.o_i2c_sda(o_@$(PREFIX)_sda), .o_i2c_scl(o_@$(PREFIX)_scl),
.M_AXIS_TVALID(@$(PREFIX)_valid), .M_AXIS_TREADY(@$(PREFIX)_ready),
.M_AXIS_TDATA(@$(PREFIX)_data), .M_AXIS_TLAST(@$(PREFIX)_last),
.M_AXIS_TID(@$(PREFIX)_id),
.i_sync_signal(rtc_pps),
//
.o_interrupt(@$(INTERRUPT)),
.o_debug(@$(PREFIX)_debug)
// }}}
);
// }}}
##
################################################################################
################################################################################
################################################################################
##
@PREFIX=edidslv
@DEVID=EDIDRX
@NADDR=64
@SLAVE.BUS=wb32
@SLAVE.TYPE=DOUBLE
@STREAM=edid
@IOSDA=io_hdmirx_sda
@IOSCL=io_hdmirx_scl
@TOP.PORTLIST=
// EDID RX definitions
@$(IOSCL), @$(IOSDA)
@TOP.IODECL=
// EDID RX definitions
inout wire @$(IOSCL), @$(IOSDA);
@TOP.DEFNS=
wire w_@$(PREFIX)_scl, w_@$(PREFIX)_sda;
@TOP.INSERT=
assign @$(IOSCL) = w_@$(PREFIX)_scl ? 1'bz : 1'b0;
assign @$(IOSDA) = w_@$(PREFIX)_sda ? 1'bz : 1'b0;
@TOP.MAIN=
// EDID RX definitions
@$(IOSCL), @$(IOSDA),
w_@$(PREFIX)_scl, w_@$(PREFIX)_sda
@MAIN.PORTLIST=
// EDID RX definitions
i_@$(PREFIX)_scl, i_@$(PREFIX)_sda,
o_@$(PREFIX)_scl, o_@$(PREFIX)_sda
@MAIN.IODECL=
// EDID RX definitions
input wire i_@$(PREFIX)_scl, i_@$(PREFIX)_sda;
output wire o_@$(PREFIX)_scl, o_@$(PREFIX)_sda;
@MAIN.DEFNS=
// Verilator lint_off UNUSED
wire [31:0] @$(PREFIX)_dbg;
// Verilator lint_on UNUSED
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// @$(DEVID)
// {{{
wbi2cslave #(
.AXIS_SUPPORT(1'b1),
.SLAVE_ADDRESS(7'h50)
) u_@$(PREFIX) (
.i_clk(i_clk), .i_reset(i_reset),
@$(SLAVE.ANSIPORTLIST),
.s_valid(@$(STREAM)_valid), .s_ready(@$(STREAM)_ready),
.s_data(@$(STREAM)_data), .s_last(@$(STREAM)_last),
.i_i2c_scl(i_@$(PREFIX)_scl), .i_i2c_sda(i_@$(PREFIX)_sda),
.o_i2c_scl(o_@$(PREFIX)_scl), .o_i2c_sda(o_@$(PREFIX)_sda),
.o_dbg(@$(PREFIX)_dbg)
);
// }}}
@REGS.N=1
@REGS.0=0 R_EDIDRX EDIDRX
@RTL.MAKE.FILES=wbi2cslave.v
@RTL.MAKE.GROUP=I2CSLV
@RTL.MAKE.SUBD=wbi2c
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=char
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
================================================
FILE: auto-data/edidslvscope.txt
================================================
################################################################################
##
## Filename: auto-data/edidslvscope.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Describes how to connect the EDID/I2C debugging port to a
## (compressed) wishbone scope, then to be connected to the bus
## by autofpga.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=edidslvscope
@DEVID=EDIDSLVSCOPE
@TARGET=edidslv
@TRIGGER=edidslv_dbg[31]
@DEBUG=edidslv_dbg[30:0]
@LOG_CAPTURE_SIZE=13
@INCLUDEFILE=wbscopc.txt
@INT.EDIDSLVSCOPE.PIC=altpic
@INT.EDIDSLVSCOPE.WIRE=@$(PREFIX)_int
@$DEFHOLDOFF=0
@MAIN.DEFNS=
================================================
FILE: auto-data/exconsole.txt
================================================
################################################################################
##
## Filename: auto-data/exconsole.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Provide access to both a debugging bus and a console port for
## the CPU. The debugging bus will be given 7-bit transfer codes
## with the high bit set, the console the same codes but with bit 8 clear.
##
## This particular version of the console uses the exbus debugging bus.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=wbu
@DEVID=DBGBUS
@ACCESS=EXBUS_MASTER
@MASTER.BUS=wbu
@MASTER.TYPE=HOST
@MASTER.PREFIX=@$(PREFIX)
@BUS.NAME=wbu
@BUS.CLOCK=clk
@BUS.WIDTH=32
@BUS.TYPE=wb
@BUS.OPT_DBLBUFFER=1
@$BAUDRATE=1000000
@OFF_TIL_ACCESS=1'b0
@CLOCK.NAME=clk
@CLOCK.RESET=i_reset
@$SETUP=(@$(CLOCK.FREQUENCY) + @$(BAUDRATE)/2) / @$BAUDRATE
@SETUP.FORMAT=24'h%x
@$BUS_ADDRESS_WIDTH=@$(MASTER.BUS.AWID)
@MAIN.PORTLIST=
// UART/host to wishbone interface
i_@$(PREFIX)_uart_rx, o_@$(PREFIX)_uart_tx
@MAIN.IODECL=
input wire i_@$(PREFIX)_uart_rx;
output wire o_@$(PREFIX)_uart_tx;
@MAIN.PARAM=
////////////////////////////////////////////////////////////////////////
//
// EXBUS parameters
// {{{
// Baudrate : @$[%9d](BAUDRATE)
// Clock : @$[%9d](CLOCK.FREQUENCY)
localparam [23:0] BUSUART = @$SETUP; // @$[%9d](BAUDRATE) baud
localparam @$(DEVID)BITS = $clog2(BUSUART);
// }}}
@MAIN.DEFNS=
////////////////////////////////////////////////////////////////////////
//
// EXBUS: USB-UART interface declarations
// {{{
//
wire [7:0] @$(PREFIX)_rx_data, @$(PREFIX)_tx_data;
wire @$(PREFIX)_rx_stb;
wire @$(PREFIX)_tx_stb, @$(PREFIX)_tx_busy;
// Verilator lint_off UNUSED
wire [0:0] ex_reset;
wire [1:0] ex_gpio;
// Verilator lint_on UNUSED
// }}}
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// EXBUS: USB-UART driven bus master and console
// {{{
// The Host USB interface, to be used by the WB-UART bus
rxuartlite #(
// {{{
.TIMER_BITS(@$(DEVID)BITS),
.CLOCKS_PER_BAUD(BUSUART[@$(DEVID)BITS-1:0])
// }}}
) rcv(
// {{{
.i_clk( @$(CLOCK.WIRE)),
.i_uart_rx(i_@$(PREFIX)_uart_rx),
.o_wr( @$(PREFIX)_rx_stb),
.o_data( @$(PREFIX)_rx_data)
// }}}
);
txuartlite #(
// {{{
.TIMING_BITS(@$(DEVID)BITS[4:0]),
.CLOCKS_PER_BAUD(BUSUART[@$(DEVID)BITS-1:0])
// }}}
) txv(
// {{{
.i_clk( @$(CLOCK.WIRE)),
.i_wr( @$(PREFIX)_tx_stb),
.i_data( @$(PREFIX)_tx_data),
.o_uart_tx(o_@$(PREFIX)_uart_tx),
.o_busy( @$(PREFIX)_tx_busy)
// }}}
);
`ifndef BUSPIC_ACCESS
wire w_bus_int;
assign w_bus_int = 1'b0;
`endif
// Verilator lint_off UNUSED
wire [29:0] @$(MASTER.PREFIX)_tmp_addr;
// Verilator lint_on UNUSED
exbuswb #(
// {{{
// .LGWATCHDOG(@$(DEVID)WATCHDOG)
.ADDRESS_WIDTH(@$(BUS_ADDRESS_WIDTH))
// }}}
) u_exbus(
// {{{
.i_clk(@$(CLOCK.WIRE)), .i_reset(@$(CLOCK.RESET)),
.o_reset(ex_reset),
.i_rx_stb(@$(PREFIX)_rx_stb), .i_rx_byte(@$(PREFIX)_rx_data),
.o_tx_stb(@$(PREFIX)_tx_stb), .o_tx_byte(@$(PREFIX)_tx_data),
.i_tx_busy(@$(PREFIX)_tx_busy),
//
.i_gpio(2'b00), .o_gpio(ex_gpio),
//
.i_console_stb(w_console_tx_stb),
.i_console_byte(w_console_tx_data),
.o_console_busy(w_console_busy),
.o_console_stb(w_console_rx_stb),
.o_console_byte(w_console_rx_data),
//
.o_wb_cyc(@$(MASTER.PREFIX)_cyc), .o_wb_stb(@$(MASTER.PREFIX)_stb),
.o_wb_we(@$(MASTER.PREFIX)_we),
.o_wb_addr(@$(MASTER.PREFIX)_addr),
.o_wb_data(@$(MASTER.PREFIX)_data),
.o_wb_sel(@$(MASTER.PREFIX)_sel),
.i_wb_stall(@$(MASTER.PREFIX)_stall),
.i_wb_ack(@$(MASTER.PREFIX)_ack),
.i_wb_data(@$(MASTER.PREFIX)_idata),
.i_wb_err(@$(MASTER.PREFIX)_err),
.i_interrupt(w_bus_int)
// }}}
);
// }}}
@REGDEFS.H.DEFNS=
#define BAUDRATE @$[%d](BAUDRATE)
@RTL.MAKE.GROUP= EXBUS
@RTL.MAKE.SUBD=exbus
@RTL.MAKE.FILES= exbuswb.v excompress.v exdecompress.v exdeword.v
exidle.v exmkword.v exwb.v exfifo.v
@SIM.INCLUDE=
#include "dbluartsim.h"
@SIM.CLOCK=@$(CLOCK.NAME)
@SIM.DEFNS=
DBLUARTSIM *m_@$(PREFIX);
@SIM.INIT=
m_@$(PREFIX) = new DBLUARTSIM();
m_@$(PREFIX)->setup(@$[%d](SETUP));
@SIM.TICK=
m_core->i_@$(PREFIX)_uart_rx = (*m_@$(PREFIX))(m_core->o_@$(PREFIX)_uart_tx);
================================================
FILE: auto-data/flash.txt
================================================
################################################################################
##
## Filename: auto-data/flash.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Describes the flash in our new data format.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=flash
@DEVID=FLASH
@ACCESS=@$(DEVID)_ACCESS
@$LGFLASHSZ=24
@$NADDR=(1<<(@$LGFLASHSZ-2))
@$NBYTES=(1<<@$LGFLASHSZ)
@NBYTES.FORMAT=0x%08x
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wbflash
@BUS.NAME=wbflash
@BUS.WIDTH=32
@BUS.TYPE=wb
@BUS.CLOCK=clk
@BUS.NULLSZ=0x100
@NDUMMY=6
@RDDELAY=2
@STARTUP_SCRIPT="spansion.hex"
@TOP.PORTLIST=
// Top level Quad-SPI I/O ports
o_@$(PREFIX)_cs_n, io_@$(PREFIX)_dat
@TOP.IODECL=
// Quad SPI flash
output wire o_@$(PREFIX)_cs_n;
inout wire [3:0] io_@$(PREFIX)_dat;
@TOP.DEFNS=
wire w_@$(PREFIX)_sck, w_@$(PREFIX)_cs_n;
wire [1:0] @$(PREFIX)_bmod;
wire [3:0] @$(PREFIX)_dat;
@TOP.MAIN=
// Quad SPI flash
w_@$(PREFIX)_cs_n, w_@$(PREFIX)_sck, @$(PREFIX)_dat, io_@$(PREFIX)_dat, @$(PREFIX)_bmod
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// QSPI Flash IO pin handling
// {{{
//
// Wires for setting up the QSPI flash wishbone peripheral
//
//
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
// 0? Normal serial mode, one bit in one bit out
// 10 Quad SPI mode, going out
// 11 Quad SPI mode coming from the device (read mode)
xqflex #(
.OPT_CLOCK(1'b0), .OPT_PHASE(1'b1)
) u_xqflex (
.i_clk(s_clk), .i_cs_n(w_@$(PREFIX)_cs_n), .i_sck(w_@$(PREFIX)_sck),
.i_dat(o_@$(PREFIX)_dat), .o_dat(i_@$(PREFIX)_dat), .i_bmod(@$(PREFIX)_bmod),
//
.o_cs_n(o_@$(PREFIX)_cs_n), .o_sck(o_@$(PREFIX)_sck), .io_dat(io_@$(PREFIX)_dat)
);
// The following primitive is necessary in many designs order to gain
// access to the o_@$(PREFIX)_sck pin. It's not necessary on the Arty,
// simply because they provide two pins that can drive the QSPI
// clock pin.
wire [3:0] su_nc; // Startup primitive, no connect
STARTUPE2 #(
// {{{
// Leave PROG_USR false to avoid activating the program
// event security feature. Notes state that such a feature
// requires encrypted bitstreams.
.PROG_USR("FALSE"),
// Sets the configuration clock frequency (in ns) for
// simulation.
.SIM_CCLK_FREQ(0.0)
// }}}
) STARTUPE2_inst (
// {{{
// CFGCLK, 1'b output: Configuration main clock output -- no
// connect
.CFGCLK(su_nc[0]),
// CFGMCLK, 1'b output: Configuration internal oscillator clock
// output
.CFGMCLK(su_nc[1]),
// EOS, 1'b output: Active high output indicating the End Of
// Startup.
.EOS(su_nc[2]),
// PREQ, 1'b output: PROGRAM request to fabric output
// Only enabled if PROG_USR is set. This lets the fabric
// know that a request has been made (either JTAG or pin
// pulled low) to program the device
.PREQ(su_nc[3]),
// CLK, 1'b input: User start-up clock input
.CLK(1'b0),
// GSR, 1'b input: Global Set/Reset input
.GSR(1'b0),
// GTS, 1'b input: Global 3-state input
.GTS(1'b0),
// KEYCLEARB, 1'b input: Clear AES Decrypter Key input from
// BBRAM
.KEYCLEARB(1'b0),
// PACK, 1-bit input: PROGRAM acknowledge input
// This pin is only enabled if PROG_USR is set. This
// allows the FPGA to acknowledge a request for reprogram
// to allow the FPGA to get itself into a reprogrammable
// state first.
.PACK(1'b0),
// USRCLKO, 1-bit input: User CCLK input -- This is why I am
// using this module at all.
.USRCCLKO(o_@$(PREFIX)_sck),
// USRCCLKTS, 1'b input: User CCLK 3-state enable input
// An active high here places the clock into a high
// impedence state. Since we wish to use the clock as an
// active output always, we drive this pin low.
.USRCCLKTS(1'b0),
// USRDONEO, 1'b input: User DONE pin output control
// Set this to "high" to make sure that the DONE LED pin
// is high.
.USRDONEO(1'b1),
// USRDONETS, 1'b input: User DONE 3-state enable output
// This enables the FPGA DONE pin to be active. Setting
// this active high sets the DONE pin to high impedence,
// setting it low allows the output of this pin to be as
// stated above.
.USRDONETS(1'b1)
// }}}
);
// }}}
@MAIN.PORTLIST=
// The Universal QSPI Flash
o_@$(PREFIX)_cs_n, o_@$(PREFIX)_sck, o_@$(PREFIX)_dat, i_@$(PREFIX)_dat, o_@$(PREFIX)_mod
@MAIN.IODECL=
// The Universal QSPI flash
output wire o_@$(PREFIX)_cs_n, o_@$(PREFIX)_sck;
output wire [3:0] o_@$(PREFIX)_dat;
input wire [3:0] i_@$(PREFIX)_dat;
output wire [1:0] o_@$(PREFIX)_mod;
@MAIN.DEFNS=
// Definitions for the @$(PREFIX) debug port
// Verilator lint_off UNUSED
wire @$(PREFIX)_dbg_trigger;
wire [31:0] @$(PREFIX)_debug;
// Verilator lint_on UNUSED
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// Flash controller
// {{{
qflexpress #(
// {{{
.LGFLASHSZ(@$LGFLASHSZ), .OPT_CLKDIV(1),
.OPT_ENDIANSWAP(0),
.NDUMMY(@$(NDUMMY)), .RDDELAY(@$(RDDELAY)),
.OPT_STARTUP_FILE(@$(STARTUP_SCRIPT)),
`ifdef FLASHCFG_ACCESS
.OPT_CFG(1'b1)
`else
.OPT_CFG(1'b0)
`endif
// }}}
) u_@$(PREFIX) (
// {{{
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)),
.i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
// Primary memory reading inputs
@$(SLAVE.ANSIPORTLIST),
// Configuration bus ports
@$(flashcfg.SLAVE.ANSIPORTLIST),
.o_qspi_sck(o_@$(PREFIX)_sck),
.o_qspi_cs_n(o_@$(PREFIX)_cs_n),
.o_qspi_mod(o_@$(PREFIX)_mod),
.o_qspi_dat(o_@$(PREFIX)_dat),
.i_qspi_dat(i_@$(PREFIX)_dat),
.o_dbg_trigger(flash_dbg_trigger),
.o_debug(flash_debug)
// }}}
);
// }}}
@MAIN.ALT=
assign o_@$(PREFIX)_sck = 1'b1;
assign o_@$(PREFIX)_cs_n = 1'b1;
assign o_@$(PREFIX)_mod = 2'b01;
assign o_@$(PREFIX)_dat = 4'b1111;
// Verilator lint_off UNUSED
wire @$(PREFIX)_unused = &{ 1'b0, i_@$(PREFIX)_dat };
// Verilator lint_on UNUSED
@MEM.NAME= flash
@MEM.ACCESS = rx
@REGS.N= 1
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
#define @$(DEVID)LGLEN @$LGFLASHSZ
//
#define FLASH_RDDELAY @$(RDDELAY)
#define FLASH_NDUMMY @$(NDUMMY)
//
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern int _@$(PREFIX)[1];
@LD.PERM= rx
@LD.NAME= @$(PREFIX)
@SIM.CLOCK=clk
@SIM.INCLUDE=
#include "flashsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
FLASHSIM *m_@$(MEM.NAME);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(MEM.NAME) = new FLASHSIM(FLASHLGLEN, false, @$RDDELAY, @$NDUMMY);
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_@$(PREFIX)_dat = m_@$(MEM.NAME)->simtick(
m_core->o_@$(PREFIX)_cs_n,
m_core->o_@$(PREFIX)_sck,
m_core->o_@$(PREFIX)_dat,
m_core->o_@$(PREFIX)_mod);
#endif // @$(ACCESS)
@SIM.LOAD=
m_@$(MEM.NAME)->load(start, &buf[offset], wlen);
@PREFIX=crossflash
@INCLUDEFILE=crossbus.txt
@MASTER.BUS=wbflash
================================================
FILE: auto-data/flashcfg.txt
================================================
################################################################################
##
## Filename: auto-data/flashcfg.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Describes the configuration interface of the flash in our new
## data format.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=flashcfg
@NADDR=1
@DEVID=FLASHCFG
@ACCESS=@$(DEVID)_ACCESS
@DEPENDS= FLASH_ACCESS
## Although this is really a SLAVE.TYPE=SINGLE interface, it receives its
## acknowledgements from the flash above. SLAVE.TYPE=SINGLE will create
## acknowledgements in the interconnect, resulting in bus errors. As a result,
## this must be a SLAVE.TYPE=OTHER
##
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb32
@SLAVE.ANSPREFIX=cfg_
@MAIN.INSERT=
// The Flash control interface is defined by the flash instantiation
// hence we don't need to do anything to define it here.
@REGS.NOTE= // FLASH erase/program configuration registers
@REGS.N= 1
@REGS.0= 0 R_@$(DEVID) @$(DEVID) QSPIC
@REGDEFS.H.INSERT=
// Flash control constants
#define QSPI_FLASH // This core and hardware support a Quad SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
@BDEF.IONAME= _@$(PREFIX)
@BDEF.OSDEF= _BOARD_HAS_@$(DEVID)
@BDEF.IOTYPE=unsigned
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) * const @$(BDEF.IONAME) = ((@$BDEF.IOTYPE *)(@$[0x%08x](REGBASE)));
##
@RTL.MAKE.GROUP= FLASH
@RTL.MAKE.SUBD=
@RTL.MAKE.FILES= qflexpress.v
================================================
FILE: auto-data/global.txt
================================================
################################################################################
##
## Filename: auto-data/global.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Capture any global configuration parameters
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2015-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@LEGAL=../auto-data/legalgen.txt
@PROJECT=AutoFPGA, a utility for composing FPGA designs from peripherals
#
# @KEYS.TRIMLIST is a list of all string keys that need to be trimmed (have
# spaces removed from either side) before being used
# @KEYS.INTLIST is a list of all things that need to be converted to integers
@KEYS.INTLIST= BUS_ADDRESS_WIDTH NADDR NPIC NSCOPES PIC.MAX REGS.N ID
@DEFAULT.BUS=wbwide
@$RESET_ADDRESS=@$flash.REGBASE+(@$flash.NADDR)
@RESET_ADDRESS.FORMAT=32'h%08x
@REGISTER.BUS=wbu
@VERILATOR_PREFIX=v
@REGDEFS.H.INSERT=
typedef struct {
unsigned m_addr;
const char *m_name;
} REGNAME;
extern const REGNAME *bregs;
extern const int NREGS;
// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
extern unsigned addrdecode(const char *v);
extern const char *addrname(const unsigned v);
@REGDEFS.CPP.INCLUDE=
#include <stdio.h>
#include <stdlib.h>
#include <strings.h>
#include <ctype.h>
@REGDEFS.CPP.INSERT=
#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
const REGNAME *bregs = raw_bregs;
const int NREGS = RAW_NREGS;
unsigned addrdecode(const char *v) {
if (isalpha(v[0])) {
for(int i=0; i<NREGS; i++)
if (strcasecmp(v, bregs[i].m_name)==0)
return bregs[i].m_addr;
fprintf(stderr, "Unknown register: %s\n", v);
exit(-2);
} else
return strtoul(v, NULL, 0);
}
const char *addrname(const unsigned v) {
for(int i=0; i<NREGS; i++)
if (bregs[i].m_addr == v)
return bregs[i].m_name;
return NULL;
}
@SIM.INCLUDE=
#include "verilated.h"
#include "Vmain.h"
#define BASECLASS Vmain
#include "design.h"
#include "regdefs.h"
#include "testb.h"
@PREFIX=wb32
@BUS.NAME=wb32
@BUS.TYPE=wb
@$BUS.WIDTH=32
@BUS.CLOCK=clk
@$BUS.NULLSZ=0x400
@PREFIX=wbwide
@BUS.NAME=wbwide
@BUS.WIDTH=128
@BUS.CLOCK=clk
@BUS.TYPE=wb
@BUS.RESET=i_reset
================================================
FILE: auto-data/gpio.txt
================================================
################################################################################
##
## Filename: auto-data/gpio.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=gpio
@DEVID=GPIO
@NADDR=1
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.TYPE=SINGLE
@SLAVE.BUS=wb32
@NUMOUTPUT=10
@NUMINPUT=8
@INT.GPIO.WIRE=gpio_int
@INT.GPIO.PIC=syspic
@TOP.PORTLIST=
// @$(DEVID) ports
o_hdmirx_hpa, // Hotplug assert
o_hdmirx_txen,
i_hdmitx_hpd_n, // Hotplug detect
o_sd_reset,
i_gps_3df,
o_oled_reset_n, o_oled_panel_en, o_oled_logic_en
@TOP.IODECL=
// @$(DEVID) ports
output wire o_hdmirx_hpa;
output wire o_hdmirx_txen;
input wire i_hdmitx_hpd_n; // Hotplug detect
output wire o_sd_reset;
input wire i_gps_3df;
output wire o_oled_reset_n, o_oled_panel_en, o_oled_logic_en;
@TOP.DEFNS=
// @$(DEVID) declarations. The two wire busses are just virtual lists
// of input (or output) ports.
wire [@$(NUMINPUT)-1:0] i_@$(PREFIX);
// Verilator lint_off UNUSED
// Two of our outputs, o_trace and o_halt, will be unused at the top
// level.
wire [@$(NUMOUTPUT)-1:0] o_@$(PREFIX);
// Verilator lint_on UNUSED
@TOP.MAIN=
// @$(DEVID) wires
i_@$(PREFIX), o_@$(PREFIX)
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// GPIO adjustments
// {{{
assign i_@$(PREFIX) = { 8'h0,
pxrx_locked,
sysclk_locked,
`ifdef GPSTRK_ACCESS
i_gps_3df,
`else
1'b0,
`endif
!i_hdmitx_hpd_n, // Hotplug detect
!i_sd_cd_n,
1'b0,
i_hdmitx_cec, i_hdmirx_cec };
assign o_hdmirx_txen = o_gpio[2];
assign o_hdmirx_hpa = o_gpio[3]; // Hotplug assert
assign o_sd_reset = !w_sdio_hwreset_n;
assign o_oled_reset_n = !o_gpio[5];
assign o_oled_panel_en = o_gpio[6];
assign o_oled_logic_en = o_gpio[7];
// These two pins are only used in simulation, and only within the
// MAIN RTL component.
// assign o_trace = o_gpio[8];
// assign o_halt = o_gpio[9];
// }}}
@MAIN.PORTLIST=
// @$(DEVID) ports
`ifdef VERILATOR
o_trace, o_halt,
`endif
i_@$(PREFIX), o_@$(PREFIX)
@MAIN.IODECL=
localparam NGPI = @$(NUMINPUT), NGPO=@$(NUMOUTPUT);
// @$(DEVID) ports
`ifdef VERILATOR
output wire o_trace;
output wire o_halt;
`endif
input [(NGPI-1):0] i_@$(PREFIX);
output wire [(NGPO-1):0] o_@$(PREFIX);
@MAIN.DEFNS=
wire sd_reset;
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// @$(DEVID)
// {{{
// This interface should allow us to control up to 16 @$(DEVID) inputs,
// and another 16 @$(DEVID) outputs. The interrupt trips when any of
// the inputs changes. (Sorry, which input isn't (yet) selectable.)
//
localparam [NGPO-1:0] INITIAL_@$(DEVID) = @$(NUMOUTPUT)'h13;
wbgpio #(
.NIN(NGPI), .NOUT(NGPO), .DEFAULT(INITIAL_@$(DEVID))
) u_@$(PREFIX) (
// {{{
.i_clk(i_clk),
@$(SLAVE.ANSIPORTLIST),
.i_gpio(i_@$(PREFIX)), .o_gpio(o_@$(PREFIX)),
.o_int(@$(PREFIX)_int)
// }}}
);
`ifdef SDIO_ACCESS
// This bit is used by the SDSPI controller, not the SDIO controller.
assign sd_reset = !o_sdio_hwreset_n;
`else
assign sd_reset = o_@$(PREFIX)[3];
`endif
`ifdef VERILATOR
wire verilator_halt;
assign o_trace = o_@$(PREFIX)[8];
assign verilator_halt = o_@$(PREFIX)[9];
assign o_halt = verilator_halt;
always @(posedge verilator_halt)
$finish;
`endif
// }}}
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) @$(DEVID) GPI GPO
@BDEF.DEFN=
//
// @$(DEVID) input wires
//
#define GPIO_HDMIRX_CEC 0x000010000
#define GPIO_HDMITX_CEC 0x000020000
#define GPIO_SD_DETECTED 0x000080000
#define GPIO_HDMITX_DETECT 0x000100000
#define GPIO_GPS_3DF 0x000200000
#define GPIO_SYSCLK_LOCKED 0x000400000
#define GPIO_VIDCLK_LOCKED 0x000800000
//
// @$(DEVID) output wires
//
#define @$(DEVID)_SET(WIRE) (((WIRE)<<16)|(WIRE))
#define @$(DEVID)_CLR(WIRE) ((WIRE)<<16)
//
#define GPIO_HDMIRX_CEC_SET 0x000010001
#define GPIO_HDMIRX_CEC_CLR 0x000010000
#define GPIO_HDMITX_CEC_SET 0x000020002
#define GPIO_HDMITX_CEC_CLR 0x000020000
//
#define GPIO_HDMIRX_TXEN 0x000000004
#define GPIO_HDMIRX_HPA 0x000000008
#define GPIO_SD_RESET 0x000000010
#define GPIO_OLED_RESET 0x000000020
#define GPIO_OLED_PANELEN 0x000000040
#define GPIO_OLED_LOGICEN 0x000000080
#define GPIO_TRACE 0x000000100
#define GPIO_TESTHALT 0x000000200
//
#define GPIO_EDID_SCL_SET GPIO_SET(GPIO_EDID_SCL)
#define GPIO_EDID_SCL_CLR GPIO_CLR(GPIO_EDID_SCL)
#define GPIO_EDID_SDA_SET GPIO_SET(GPIO_EDID_SDA)
#define GPIO_EDID_SDA_CLR GPIO_CLR(GPIO_EDID_SDA)
#define GPIO_HDMIRX_HPA_SET GPIO_SET(GPIO_HDMIRX_HPA)
#define GPIO_HDMIRX_HPA_CLR GPIO_CLR(GPIO_HDMIRX_HPA)
#define GPIO_SD_RESET_SET GPIO_SET(GPIO_SD_RESET)
#define GPIO_SD_RESET_CLR GPIO_CLR(GPIO_SD_RESET)
#define GPIO_HDMIRX_TXEN_SET GPIO_SET(GPIO_HDMIRX_TXEN)
#define GPIO_HDMIRX_TXEN_CLR GPIO_CLR(GPIO_HDMIRX_TXEN)
#define OLED_RESET GPIO_SET(GPIO_OLED_RESET)
#define OLED_RUN GPIO_CLR(GPIO_OLED_RESET)
#define OLED_PANELEN GPIO_SET(GPIO_OLED_PANELEN)
#define OLED_PANELDIS GPIO_CLR(GPIO_OLED_PANELEN)
#define OLED_LOGICEN GPIO_SET(GPIO_OLED_LOGICEN)
#define OLED_LOGICDIS GPIO_CLR(GPIO_OLED_LOGICEN)
#define GPIO_TRACE_SET GPIO_SET(GPIO_TRACE)
#define GPIO_TRACE_CLR GPIO_CLR(GPIO_TRACE)
#define GPIO_HALT_SET GPIO_SET(GPIO_TESTHALT)
#define GPIO_HALT_CLR GPIO_CLR(GPIO_TESTHALT)
@BDEF.IONAME= i_@$(PREFIX)
@BDEF.IOTYPE= unsigned
@BDEF.OSDEF= _BOARD_HAS_@$(DEVID)
@BDEF.OSVAL= static volatile @$(BDEF.IOTYPE) *const _@$(PREFIX) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@RTL.MAKE.FILES=wbgpio.v
@RTL.MAKE.GROUP=@$(DEVID)
================================================
FILE: auto-data/gps.txt
================================================
################################################################################
##
## Filename: auto-data/gps.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: This file describes the three interfaces created by the GPS:
## 1) a GPS-locked clock, 2) a "testbench" which is used to
## measure the performance of the GPS-locked lock, and 3) a wishbone
## controlled UART which can be used to read from the UART stream coming
## from the GPS.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@$GPSPORT_OFFSET=2
@PREFIX=gck
@DEVID=GPSTRK
@ACCESS=@$(DEVID)_ACCESS
@NADDR=4
@SLAVE.TYPE=DOUBLE
@SLAVE.BUS=wb32
@CLOCK.NAME=clk
@$CLKFREQHZ=@$(CLOCK.FREQUENCY)
@$GPS_STEP_EXPONENT=10
@$GPS_STEP=((((1<<60)/@$CLKFREQHZ)>>(@$.GPS_STEP_EXPONENT-4))&0x0fffffff)|((@$.GPS_STEP_EXPONENT&0x0f)<<28)
@GPS_STEP.FORMAT=32'h%08x
@MAIN.PORTLIST=
// The GPS 1PPS signal port
i_gps_pps
@MAIN.PARAM=
localparam [31:0] GPSCLOCK_DEFAULT_STEP = @$.GPS_STEP;
@MAIN.IODECL=
//The GPS Clock
input wire i_gps_pps;
@MAIN.DEFNS=
wire ck_pps;
wire gps_pps, gps_led, gps_locked, gps_tracking;
wire [63:0] gps_now, gps_err, gps_step;
wire [1:0] gps_dbg_tick;
@MAIN.INSERT=
// Verilator lint_off UNUSED
wire [1:0] ck_dbg;
// Verilator lint_on UNUSED
gpsclock #(
.DEFAULT_STEP(GPSCLOCK_DEFAULT_STEP)
) ppsck (
.i_clk(i_clk), .i_rst(1'b0), .i_pps(gps_pps), .o_pps(ck_pps),
.o_led(gps_led),
@$(SLAVE.ANSIPORTLIST),
.o_tracking(gps_tracking), .o_count(gps_now), .o_step(gps_step),
.o_err(gps_err), .o_locked(gps_locked), .o_dbg(ck_dbg)
);
assign @$(PREFIX)_pps = ck_pps;
@MAIN.ALT=
reg r_ck_pps;
reg [63:0] r_gps_now;
reg [31:0] r_gps_prior;
wire [47:0] pre_step;
assign pre_step = { 16'h00, (({GPSCLOCK_DEFAULT_STEP[27:0],20'h00})
>>GPSCLOCK_DEFAULT_STEP[31:28]) };
initial { r_ck_pps, r_gps_prior } = 33'h0;
always @(posedge i_clk)
{ r_ck_pps, r_gps_prior[31:0] } <= r_gps_prior + pre_step[31:0];
initial r_gps_now = 64'h0;
always @(posedge i_clk)
begin
r_gps_now[63:32] <= r_gps_now[63:32]+(r_ck_pps ? 32'h1:32'h0);
r_gps_now[31:0] <= r_gps_prior;
end
assign ck_pps = r_ck_pps;
assign gps_now = r_gps_now;
assign gps_err = 64'h0;
assign gps_step = pre_step;
assign gps_led = 1'b0;
assign gps_locked = 1'b0;
@INT.PPS.WIRE=@$(PREFIX)_pps
@INT.PPS.PIC=syspic
@REGS.NOTE= // GPS clock tracker, control loop settings registers
@REGS.N=4
@REGS.0= 0 R_GPS_ALPHA ALPHA
@REGS.1= 1 R_GPS_BETA BETA
@REGS.2= 2 R_GPS_GAMMA GAMMA
@REGS.3= 3 R_GPS_STEP STEP
@BDEF.DEFN=
typedef struct GPSTRACKER_S {
unsigned g_alpha, g_beta, g_gamma, g_step;
} GPSTRACKER;
@BDEF.INSERT=
#define SYSINT_PPS SYSINT(@$(INT.PPS.syspic.ID))
@BDEF.IONAME=_gps
@BDEF.IOTYPE= GPSTRACKER
@BDEF.OSVAL=
static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$BDEF.IOTYPE *)@$[0x%08x](REGBASE));
##
##
##
@PREFIX=gtb
@NADDR=8
@DEPENDS=GPSTRK_ACCESS
@SLAVE.TYPE=DOUBLE
@SLAVE.BUS=wb32
@CLOCK.NAME=clk
@MAIN.DEFNS=
wire tb_pps;
@MAIN.INSERT=
// Generate a PPS signal independent of the GPS--useful for testing
gpsclock_tb #(
.CLOCK_FREQUENCY_HZ(@$(CLOCK.FREQUENCY))
) ppstb(
.i_clk(i_clk), .i_lcl_pps(ck_pps), .o_pps(tb_pps),
@$(SLAVE.ANSIPORTLIST),
.i_err(gps_err), .i_count(gps_now), .i_step(gps_step)
);
assign gps_pps = tb_pps;
@MAIN.ALT=
assign gps_pps = i_gps_pps;
@REGS.NOTE= // GPS clock test bench registers, for measuring the clock trackers performance
@REGS.N=8
@REGS.0= 0 R_GPSTB_FREQ GPSFREQ
@REGS.1= 1 R_GPSTB_JUMP GPSJUMP
@REGS.2= 2 R_GPSTB_ERRHI ERRHI
@REGS.3= 3 R_GPSTB_ERRLO ERRLO
@REGS.4= 4 R_GPSTB_COUNTHI CNTHI
@REGS.5= 5 R_GPSTB_COUNTLO CNTLO
@REGS.6= 6 R_GPSTB_STEPHI STEPHI
@REGS.7= 7 R_GPSTB_STEPLO STEPLO
@BDEF.DEFN=
typedef struct GPSTB_S {
unsigned tb_maxcount, tb_jump;
unsigned long tb_err, tb_count, tb_step;
} GPSTB;
@BDEF.IONAME=_gpstb
@BDEF.IOTYPE=GPSTB
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
#
#
#
@PREFIX=gpsu
@INCLUDEFILE=wbuart.txt
@$BAUDRATE=9600
@CLOCK.NAME=clk
@$UARTSETUP=@$(CLOCK.FREQUENCY)/@$(BAUDRATE)
@ACCESS=GPSUART_ACCESS
@INT.INTLIST= GPSRX GPSTX GPSRXF GPSTXF
@INT.GPSRX.WIRE= gpsurx_int
@INT.GPSTX.WIRE= gpsutx_int
@INT.GPSRXF.WIRE= gpsurxf_int
@INT.GPSTXF.WIRE= gpsutxf_int
@INT.GPSRX.PIC= altpic
@INT.GPSTX.PIC= altpic
@INT.GPSRXF.PIC= altpic
@INT.GPSTXF.PIC= altpic
# Clear the other inherited wires, as we don't need them any more.
@INT.UARTRX.WIRE=
@INT.UARTTX.WIRE=
@INT.UARTRXF.WIRE=
@INT.UARTTXF.WIRE=
@INT.UARTRX.PIC=
@INT.UARTTX.PIC=
@INT.UARTRXF.PIC=
@INT.UARTTXF.PIC=
@BDEF.INSERT=
#define SYSINT_GPSRXF ALTINT(@$(INT.GPSRXF.syspic.ID))
#define SYSINT_GPSTXF ALTINT(@$(INT.GPSTXF.altpic.ID))
#define SYSINT_GPSRX ALTINT(@$(INT.GPSRX.altpic.ID))
#define SYSINT_GPSTX ALTINT(@$(INT.GPSTX.altpic.ID))
@TOP.PORTLIST=
// The GPS-UART
i_@$(PREFIX)_rx, o_@$(PREFIX)_tx
@MAIN.PORTLIST=
// The GPS-UART
i_@$(PREFIX)_rx, o_@$(PREFIX)_tx
@MAIN.IODECL=
input wire i_@$(PREFIX)_rx;
output wire o_@$(PREFIX)_tx;
@MAIN.DEFNS=
wire w_@$(PREFIX)_cts_n, w_@$(PREFIX)_rts_n;
assign w_@$(PREFIX)_cts_n=1'b1;
@RTS=w_@$(PREFIX)_rts_n
@CTS=w_@$(PREFIX)_cts_n
@REGS.NOTE= // GPS UART registers, similar to WBUART
@REGS.N=4
@REGS.0= 0 R_GPSU_SETUP GPSSETUP
@REGS.1= 1 R_GPSU_FIFO GPSFIFO
@REGS.2= 2 R_GPSU_UARTRX GPSRX
@REGS.3= 3 R_GPSU_UARTTX GPSTX
@BDEF.IONAME=_@$(PREFIX)
@BDEF.OSDEF=_BOARD_HAS_GPS_UART
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)(@$[0x%08x](REGBASE)));
@$SIM.PORTOFFSET=@/GPSPORT_OFFSET
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(PREFIX) = new UARTSIM(FPGAPORT+@$(SIM.PORTOFFSET));
m_@$(PREFIX)->setup(@$[0x%08x](UARTSETUP));
#endif // @$(ACCESS)
#
@RTL.MAKE.GROUP=GPS
@RTL.MAKE.FILES=gpsclock_tb.v gpsclock.v bigadd.v bigsub.v bigsmpy.v
================================================
FILE: auto-data/hdmi.txt
================================================
################################################################################
##
## Filename: auto-data/hdmi.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: To direct the build of the autofpga automatically generated
## files. The various configuration files are the *.txt files
## found in this directory.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=hdmi
@DEVID=VIDPIPE
@ACCESS=@$(DEVID)_ACCESS
@NADDR=1024
@SLAVE.BUS=wb32
@SLAVE.TYPE=OTHER
@MASTER.BUS=wbwide
@MASTER.TYPE=DMA
@MASTER.ANSPREFIX=dma_
@INT.VIDFRAME.WIRE=@$(PREFIX)_int
@INT.VIDFRAME.PIC=syspic
@TOP.PORTLIST=
i_hdmirx_clk_p, i_hdmirx_clk_n,
i_hdmirx_p, i_hdmirx_n,
o_hdmitx_clk_p, o_hdmitx_clk_n,
o_hdmitx_p, o_hdmitx_n
@TOP.IODECL=
input wire i_hdmirx_clk_p, i_hdmirx_clk_n;
input wire [2:0] i_hdmirx_p, i_hdmirx_n;
output wire o_hdmitx_clk_p, o_hdmitx_clk_n;
output wire [2:0] o_hdmitx_p, o_hdmitx_n;
@TOP.DEFNS=
wire [9:0] hdmirx_red, hdmirx_grn, hdmirx_blu;
wire [9:0] hdmitx_red, hdmitx_grn, hdmitx_blu;
wire [1:0] w_pxclk_cksel;
wire hdmirx_clk, hdmi_ck, hdmi_serdes_clk;
wire pxrx_locked, pix_reset_n, hdmirx_reset_n;
wire [15-1:0] set_hdmi_delay, actual_hdmi_delay;
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// HDMI
// {{{
// Ingest the HDMI data lines
// {{{
xhdmiin
u_hdmirx_red(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(hdmirx_reset_n),
.i_delay(set_hdmi_delay[14:10]),
.o_delay(actual_hdmi_delay[14:10]),
.i_hs_wire({ i_hdmirx_p[2], i_hdmirx_n[2] }),
.o_word(hdmirx_red)
);
xhdmiin
u_hdmirx_grn(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(hdmirx_reset_n),
.i_delay(set_hdmi_delay[9:5]),
.o_delay(actual_hdmi_delay[9:5]),
.i_hs_wire({ i_hdmirx_p[1], i_hdmirx_n[1] }),
.o_word(hdmirx_grn)
);
xhdmiin
u_hdmirx_blu(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(hdmirx_reset_n),
.i_delay(set_hdmi_delay[4:0]),
.o_delay(actual_hdmi_delay[4:0]),
.i_hs_wire({ i_hdmirx_p[0], i_hdmirx_n[0] }),
.o_word(hdmirx_blu)
);
// }}}
// Output the HDMI TX data lines
// {{{
xhdmiout
u_hdmitx_clk(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(pix_reset_n), .i_en(1'b1),
.i_word(10'b11111_00000),
.o_port({ o_hdmitx_clk_p, o_hdmitx_clk_n })
);
xhdmiout
u_hdmitx_red(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(pix_reset_n), .i_en(1'b1),
.i_word(hdmitx_red),
.o_port({ o_hdmitx_p[2], o_hdmitx_n[2] })
);
xhdmiout
u_hdmitx_grn(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(pix_reset_n), .i_en(1'b1),
.i_word(hdmitx_grn),
.o_port({ o_hdmitx_p[1], o_hdmitx_n[1] })
);
xhdmiout
u_hdmitx_blu(
.i_clk(hdmi_ck), .i_hsclk(hdmi_serdes_clk),
.i_reset_n(pix_reset_n), .i_en(1'b1),
.i_word(hdmitx_blu),
.o_port({ o_hdmitx_p[0], o_hdmitx_n[0] })
);
// }}}
// }}}
@TOP.MAIN=
// HDMI control ports
hdmirx_clk, hdmi_ck, // Depending on s_siclk
hdmirx_red, hdmirx_grn, hdmirx_blu,
hdmitx_red, hdmitx_grn, hdmitx_blu,
set_hdmi_delay, actual_hdmi_delay,
pix_reset_n, pxrx_locked, hdmirx_reset_n,
w_pxclk_cksel
@MAIN.PORTLIST=
// HDMI control ports
`ifndef VERILATOR
i_hdmiclk,
`endif
i_pixclk,
i_hdmi_red, i_hdmi_grn, i_hdmi_blu,
o_hdmi_red, o_hdmi_grn, o_hdmi_blu,
o_hdmi_iodelay, i_hdmi_iodelay,
o_pix_reset_n, i_pxpll_locked, o_hdmirx_reset_n,
o_pxclk_cksel
@MAIN.IODECL=
// @$(PREFIX) declarations
// {{{
`ifndef VERILATOR
input wire i_hdmiclk;
`endif
input wire i_pixclk;
input wire [9:0] i_hdmi_red, i_hdmi_grn, i_hdmi_blu;
output wire [9:0] o_hdmi_red, o_hdmi_grn, o_hdmi_blu;
output wire [14:0] o_hdmi_iodelay;
input wire [14:0] i_hdmi_iodelay;
output wire o_pix_reset_n, o_hdmirx_reset_n;
input wire i_pxpll_locked;
output wire [1:0] o_pxclk_cksel;
// }}}
@MAIN.DEFNS=
// Verilator lint_off UNUSED
`ifdef VERILATOR
wire i_hdmiclk;
`endif
wire hdmidbg_ce, hdmidbg_trigger;
wire [31:0] hdmiclr_debug;
// Verilator lint_on UNUSED
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// HDMI Video processing pipeline
// {{{
`ifdef VERILATOR
assign i_hdmiclk = i_pixclk;
`endif
vidpipe #(
.AW(@$(MASTER.BUS.AWID)),
.DW(@$(MASTER.BUS.WIDTH))
) u_@$(PREFIX) (
.i_clk(i_clk), .i_reset(i_reset),
@$(SLAVE.ANSIPORTLIST),
.i_hdmiclk(i_hdmiclk),
.i_altclk(i_pixclk),
.i_pixclk(i_pixclk),
.i_hdmi_red(i_hdmi_red), .i_hdmi_grn(i_hdmi_grn),
.i_hdmi_blu(i_hdmi_blu),
@$(MASTER.ANSIPORTLIST),
.o_hdmi_red(o_hdmi_red), .o_hdmi_grn(o_hdmi_grn),
.o_hdmi_blu(o_hdmi_blu),
.o_pix_reset_n(o_pix_reset_n),
.i_pxpll_locked(i_pxpll_locked),
.o_hdmirx_reset_n(o_hdmirx_reset_n),
.o_pxclk_sel(o_pxclk_cksel),
.o_iodelay(o_hdmi_iodelay),
.i_iodelay(i_hdmi_iodelay),
.o_interrupt(@$(INT.VIDFRAME.WIRE)),
//
.o_dbg_ce(hdmidbg_ce),
.o_dbg_trigger(hdmidbg_trigger),
.o_pixdebug(hdmiclr_debug)
);
// }}}
@REGS.NOTE=// HDMI video processing pipe registers
@REGS.N=23
@REGS.0= 0 R_@$(DEVID) @$(DEVID) VIDCTRL
@REGS.1= 1 R_HDMIFREQ HDMIFREQ
@REGS.2= 2 R_SIFREQ SIFREQ
@REGS.3= 3 R_PXFREQ PXFREQ
@REGS.4= 4 R_INSIZE INSIZE
@REGS.5= 5 R_INPORCH INPORCH
@REGS.6= 6 R_INSYNC INSYNC
@REGS.7= 7 R_INRAW INRAW
@REGS.8= 8 R_HDMISIZE HDMISIZE
@REGS.9= 9 R_HDMIPORCH HDMIPORCH
@REGS.10= 10 R_HDMISYNC HDMISYNC
@REGS.11= 11 R_HDMIRAW HDMIRAW
@REGS.12= 12 R_OVADDR OVADDR
@REGS.13= 13 R_OVSIZE OVSIZE
@REGS.14= 14 R_OVOFFSET OVOFFSET
@REGS.15= 15 R_FPS FPS
@REGS.16= 16 R_CAPTURE VCAPTURE
@REGS.17= 17 R_CAPBASE VCAPBASE
@REGS.18= 18 R_CAPWORDS VCAPWORDS
@REGS.19= 19 R_CAPPOSN VCAPPOSN
@REGS.20= 20 R_CAPSIZE VCAPSIZE
@REGS.21= 24 R_SYNCWORD VSYNCWORD
@REGS.22=512 R_CMAP CMAP
@BDEF.INCLUDE=
#include <stdint.h>
@BDEF.DEFN=
#ifndef @$(DEVID)_H
#define @$(DEVID)_H
#define VIDPIPE_RESET 0x000001
#define VIDPIPE_RXPLLCK 0x000002
#define VIDPIPE_LOCALCK 0x000000
#define VIDPIPE_RXCLOCK 0x000020
#define VIDPIPE_LCLSRC 0x000000
#define VIDPIPE_RXSRC 0x000040
#define VIDPIPE_RXSYNCD 0x010000
#define VIDPIPE_OVLYERR 0x020000
#define VIDCMAP_BW 0x000000
#define VIDCMAP_2GRAY 0x000100
#define VIDCMAP_4CMAP 0x000200
#define VIDCMAP_8CMAP 0x000300
#define VIDCMAP_8CLR 0x000400
#define VIDCMAP_16CLR 0x000500
#define VIDCMAP_24CLR 0x000600
#define VIDCMAP_32CLR 0x000700
typedef struct __attribute__((packed)) VIDMODE_S {
uint16_t m_height, m_width;
uint16_t m_vporch, m_hporch;
uint16_t m_vsync, m_hsync;
uint16_t m_raw_height, m_raw_width;
} VIDMODE;
typedef struct __attribute__((packed)) @$(DEVID)_S {
uint32_t v_control, v_hdmifreq, v_sifreq, v_pxfreq;
VIDMODE v_in, v_src;
const char *v_overlay;
uint16_t v_ovheight, v_ovwidth;
uint16_t v_ovypos, v_ovhpos;
unsigned v_fps;
uint32_t v_capture;
const char *v_capbase;
uint32_t v_capwords, v_capposn, v_capsize;
unsigned v_ovwords;
unsigned v_unused2[2];
unsigned v_syncword;
uint32_t v_unused[512-25];
uint32_t v_clrmap[256];
} @$(DEVID);
#endif // @$(DEVID)_H
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=@$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@RTL.MAKE.GROUP=HDMI
@RTL.MAKE.SUBD=video
@RTL.MAKE.FILES= axishdmi.v axisvoverlay.v hdmi2vga.v
hdmibitsync.v hdmipixelsync.v sync2stream.v synccount.v
tfrstb.v tmdsdecode.v tmdsencode.v vid_empty.v
vid_mux.v vidpipe.v vidstream2pix.v vid_wbframebuf.v
vid_crop.v xhdmiin_deserdes.v xhdmiin.v xhdmiout.v xpxclk.v
@CLOCK.NAME=pixclk
@CLOCK.WIRE=i_pixclk
@CLOCK.FREQUENCY=40000000
@SIM.CLOCK=pixclk
@SIM.INCLUDE=
#include "hdmisource.h"
#include "hdmisim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
HDMISOURCE *m_hdmirx;
HDMIWIN *m_hdmitx;
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_hdmirx = NULL;
m_hdmitx = NULL;
if (gbl_use_gui) {
m_hdmirx = new HDMISOURCE(800, 600);
m_hdmitx = new HDMIWIN(800, 600);
}
#endif // @$(ACCESS)
@SIM.METHODS=
void connect_idler(void) {
Glib::signal_idle().connect(
sigc::mem_fun((*this),&MAINTB::on_tick));
}
bool on_tick(void) {
for(int i=0; i<15; i++)
tick();
return true;
}
@SIM.TICK=
#ifdef @$(ACCESS)
// Simulate both an external HDMI source and monitor
if (gbl_use_gui) {
int r, g, b;
// HDMI input received by the design
(*m_hdmirx)(b, g, r);
m_core->i_hdmi_blu = b;
m_core->i_hdmi_grn = g;
m_core->i_hdmi_red = r;
m_core->i_pxpll_locked = 1;
// HDMI output, transmitted from the design
(*m_hdmitx)(m_core->o_hdmi_blu, m_core->o_hdmi_grn,
m_core->o_hdmi_red);
}
#endif // @$(ACCESS)
@XDC.INSERT=
##
## Can't (officially) go any faster than 119.05 MHz
## Yes, I know I've seen this board hit the 145 MHz required by 1080p, but Vivado's timing analyzer
## says we can't go that fast.
create_clock -period 10.8 -name PXCLK -waveform { 0.0 5.4 } -add [get_ports i_hdmirx_clk_p ]
## XCLKSW
## {{{
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~u_xpxclk/CLOCK_SWITCH.u_prepx/r_sel*}] -to [get_cells -hier -filter {NAME=~ u_xpxclk/CLOCK_SWITCH.u_prepx/u_bufg*}] 7.0
# set_case_analysis 1 [get_nets -hier -filter {NAME=~ w_pxclk_cksel[1]*}]
## }}}
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset_sys*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset_u*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset_sys*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset_pipe*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/genhdmi/pix_reset*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset_sys*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset_pipe*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset_sys*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset*}] -to [get_cells -hier -filter {NAME=~ u_hdmirx_*/reset_pipe*}] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/hdmi_reset*}] -to [get_cells -hier -filter {NAME=~ u_hdmirx_*/the_deserdes/reset_pipe*}] 10.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ u_hdmitx_*/reset_pipe*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ u_hdmitx_*/sync_reset_n*}] 6.0
##
## RXVIDXCLK
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/GEN_REGISTERED_READ.o_rd_empty*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/mem*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/GEN_REGISTERED_READ.o_rd_data*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rd_addr*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rgray*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rd_wgray*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/wgray_cross*}] 6.0
#
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_overlay/primary_skid/LOGIC.r_valid*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rd_addr*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_overlay/primary_skid/LOGIC.r_valid*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rgray*}] 6.0
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_overlay/primary_skid/LOGIC.r_valid*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/GEN_REGISTERED_READ.o_rd_data*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/wgray*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/wgray_cross*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/mem*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/GEN_REGISTERED_READ.o_rd_data*}] 6.0
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/rd_addr*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_rxvidxclk/GEN_REGISTERED_READ.o_rd_data*}] 6.0
##
## }}}
## u_new_frame
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_req*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_ack*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_pipe*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_pipe*}] 6.0
## }}}
##
## WB2PIX
## {{{
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/o_b_data*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/b_pipe*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_wb2pix/a_pipe*}] 6.0
## }}}
## PIX2WB
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/o_b_data*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_ack*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_pipe*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_req*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/o_b_data*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/b_pipe*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.u_pix2wb/a_pipe*}] 6.0
## }}}
##
## u_framebuf/GEN_ASYNC_FIFO.pxfifo
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/wgray_cross*}] 6.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset_sys*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] 6.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/rgray*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/rgray_cross*}] 7.0
#
#
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/rd_addr*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/rgray*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/rd_wgray*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.r_pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/GEN_REGISTERED_READ.o_rd_empty*}] 7.0
#
#
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/wgray*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/wgray_cross*}] 7.0
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/mem*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/GEN_REGISTERED_READ.o_rd_data*}] 7.0
##
# set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/mem*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_framebuf/GEN_ASYNC_FIFO.pxfifo/GEN_REGISTERED_READ.o_rd_data*}] 7.0
## }}}
## H2SYS
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/o_b_data*}] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/a_pipe*}] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2sys/b_pipe*}] 10.0
## }}}
## H2PIX
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/b_pipe*}] 6.7
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/b_req*}] 6.7
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/b_last*}] 6.7
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/o_b_data*}] 6.7
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/a_pipe*}] 6.7
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_h2pix/b_pipe*}] 6.7
## }}}
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_hdmi2vga/bitsync/*sync/pixloc/REQUIRE_QUALITY.o_val*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pre_wb_data*}] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_hdmi2vga/bitsync/*sync/sync_valid*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pre_wb_data*}] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_HDMIIN_TO_AXIVID.u_hdmi2vga/bitsync/all_locked*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pre_wb_data*}] 10.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_pipe*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_new_frame/b_pipe*}] 7.0
##
## PX2SYS
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/u_px2sys/a_req*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/u_px2sys/a_ack*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/u_px2sys/a_pipe*}] 7.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/u_px2sys/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_hdmi/u_px2sys/a_pipe*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_px2sys/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_px2sys/b_pipe*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_px2sys/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_px2sys/o_b_data*}] 7.0
## }}}
##
## SYS2PX
##{{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/b_req*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/b_last*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/pix_reset*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/b_pipe*}] 7.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/a_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/o_b_data*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/b_last*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/a_pipe*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/a_req*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/b_pipe*}] 7.0
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/o_b_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/genhdmi/vpos*}] 7.0
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_sys2px/o_b_data*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/genhdmi/hpos*}] 7.0
## }}}
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_mem2pix/cmap_reg*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/GEN_FRAMEBUF.u_mem2pix/cmap*reg*}] 7.0
## CLKCOUNTER
## {{{
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~thedesign/u_@$(PREFIX)/u_pixclk_counter/avgs*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_pixclk_counter/q_v*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~thedesign/u_@$(PREFIX)/u_siclk_counter/avgs*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_siclk_counter/q_v*}] 7.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~thedesign/u_@$(PREFIX)/u_hdmiclk_counter/avgs*}] -to [get_cells -hier -filter {NAME=~ thedesign/u_@$(PREFIX)/u_hdmiclk_counter/q_v*}] 7.0
## }}}
@PREFIX=pxclk
@SLAVE.TYPE=other
@SLAVE.BUS=wb32
@NADDR=128
@TOP.DEFNS=
wire [31:0] @$(PREFIX)_debug;
wire w_@$(PREFIX)_cyc, w_@$(PREFIX)_stb, w_@$(PREFIX)_we,
w_@$(PREFIX)_stall, w_@$(PREFIX)_ack;
wire [6:0] w_@$(PREFIX)_addr;
wire [31:0] w_@$(PREFIX)_data, w_@$(PREFIX)_idata;
wire [3:0] w_@$(PREFIX)_sel;
@TOP.MAIN=
w_@$(PREFIX)_cyc, w_@$(PREFIX)_stb, w_@$(PREFIX)_we,
w_@$(PREFIX)_addr, w_@$(PREFIX)_data, w_@$(PREFIX)_sel,
w_@$(PREFIX)_stall, w_@$(PREFIX)_ack, w_@$(PREFIX)_idata
@MAIN.PORTLIST=
o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we,
o_@$(PREFIX)_addr, o_@$(PREFIX)_data, o_@$(PREFIX)_sel,
i_@$(PREFIX)_stall, i_@$(PREFIX)_ack, i_@$(PREFIX)_idata
@MAIN.IODECL=
output wire o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we;
output wire [6:0] o_@$(PREFIX)_addr;
output wire [31:0] o_@$(PREFIX)_data;
output wire [3:0] o_@$(PREFIX)_sel;
input wire i_@$(PREFIX)_stall, i_@$(PREFIX)_ack;
input wire [31:0] i_@$(PREFIX)_idata;
@TOP.PORTLIST=
@TOP.IODECL=
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// HDMI Clock generation
// {{{
xpxclk
u_xpxclk (
.i_sysclk(s_clk), // System clock
.i_cksel(w_pxclk_cksel), // Clock select switch
//
.i_hdmirx_clk_p(i_hdmirx_clk_p), // HDMI RX input clock
.i_hdmirx_clk_n(i_hdmirx_clk_n),
.i_lcl_pixclk(s_clk_80mhz_unbuffered), // Locally generated clk
.i_siclk(s_clk_80mhz_unbuffered),
//
.o_hdmick_locked(pxrx_locked),
.o_hdmirx_clk(hdmirx_clk), // Clk for measurement only
.o_pixclk(hdmi_ck), // Pixel clock
.o_hdmick(hdmi_serdes_clk), // HS pixel clock
//
.i_wb_clk(s_clk),
//
.i_wb_cyc(w_@$(PREFIX)_cyc), .i_wb_stb(w_@$(PREFIX)_stb),
.i_wb_we(w_@$(PREFIX)_we),
.i_wb_addr(w_@$(PREFIX)_addr[7-1:0]),
.i_wb_data(w_@$(PREFIX)_data), // 32 bits wide
.i_wb_sel(w_@$(PREFIX)_sel), // 32/8 bits wide
.o_wb_stall(w_@$(PREFIX)_stall),.o_wb_ack(w_@$(PREFIX)_ack),
.o_wb_data(w_@$(PREFIX)_idata),
//
.o_debug(@$(PREFIX)_debug)
);
// }}}
@MAIN.INSERT=
assign o_@$(PREFIX)_cyc = @$(SLAVE.PREFIX)_cyc;
assign o_@$(PREFIX)_stb = @$(SLAVE.PREFIX)_stb;
assign o_@$(PREFIX)_we = @$(SLAVE.PREFIX)_we;
assign o_@$(PREFIX)_addr = @$(SLAVE.PREFIX)_addr[6:0];
assign o_@$(PREFIX)_data = @$(SLAVE.PREFIX)_data;
assign o_@$(PREFIX)_sel = @$(SLAVE.PREFIX)_sel;
assign @$(SLAVE.PREFIX)_stall = i_@$(PREFIX)_stall;
assign @$(SLAVE.PREFIX)_ack = i_@$(PREFIX)_ack;
assign @$(SLAVE.PREFIX)_idata = i_@$(PREFIX)_idata;
@REGS.NOTE=// HDMI pixel clock PLL reconfiguration port
@REGS.N=1
@REGS.0= 0 R_PXPLL PXPLL
## @BDEF.DEFN=
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=unsigned
@BDEF.OSDEF=_BOARD_HAS_PXPLL
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME)=((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
@SIM.CLOCK=clk
@SIM.TICK=
m_core->i_@$(PREFIX)_stall = 0;
m_core->i_@$(PREFIX)_ack = m_core->o_@$(PREFIX)_stb;
m_core->i_@$(PREFIX)_idata = m_core->o_@$(PREFIX)_data;
================================================
FILE: auto-data/i2ccpu.txt
================================================
################################################################################
##
## Filename: auto-data/i2ccpu.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Drive and control the I2C bus
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=i2c
@DEVID=I2CCPU
@NADDR=4
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.BUS=wb32
@SLAVE.TYPE=DOUBLE
@SLAVE.PREFIX=@$(SLAVE.BUS.NAME)_@$(PREFIX)s
@MASTER.TYPE=CPU
@MASTER.BUS=wbwide
@MASTER.PREFIX=@$(MASTER.BUS.NAME)_@$(PREFIX)m
@SGP=@$(BUS.PREFIX)
@WBP=@$(SLAVE.BUS.PREFIX)
@MASTER.ANSPREFIX=pf_
@IOSDA=io_sda
@IOSCL=io_scl
@IDW=2
@INTERRUPT=i2c_int
@INT.I2C.WIRE=@$(INTERRUPT)
@INT.I2C.PIC=syspic
@TOP.PORTLIST=
@$(IOSCL), @$(IOSDA)
@TOP.IODECL=
inout wire @$(IOSCL), @$(IOSDA);
@TOP.DEFNS=
// I2CCPU definitions
// {{{
wire i_@$(PREFIX)_sda, i_@$(PREFIX)_scl,
o_@$(PREFIX)_sda, o_@$(PREFIX)_scl;
// }}}
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// I2C IO buffers
// {{{
// We need these in order to (properly) ensure the high impedance
// states (pull ups) of the I2C I/O lines. Our goals are:
//
// o_@$(PREFIX)_X io_@$(PREFIX)_X Derived:T
// 1'b0 1'b0 1'b0
// 1'b1 1'bz 1'b1
//
IOBUF @$(PREFIX)sclp(
// {{{
.I(1'b0),
.T(o_@$(PREFIX)_scl),
.O(i_@$(PREFIX)_scl),
.IO(@$(IOSCL))
// }}}
);
IOBUF @$(PREFIX)sdap(
// {{{
.I(1'b0),
.T(o_@$(PREFIX)_sda),
.O(i_@$(PREFIX)_sda),
.IO(@$(IOSDA))
// }}}
);
// }}}
@TOP.MAIN=
// I2CCPU
i_@$(PREFIX)_sda, i_@$(PREFIX)_scl,
o_@$(PREFIX)_sda, o_@$(PREFIX)_scl
@MAIN.PORTLIST=
i_@$(PREFIX)_sda, i_@$(PREFIX)_scl,
o_@$(PREFIX)_sda, o_@$(PREFIX)_scl
@MAIN.IODECL=
// I2C Port declarations
// {{{
input wire i_@$(PREFIX)_sda, i_@$(PREFIX)_scl;
output wire o_@$(PREFIX)_sda, o_@$(PREFIX)_scl;
// }}}
@MAIN.DEFNS=
// I2C Controller
// {{{
// Verilator lint_off UNUSED
localparam @$(DEVID)_WIDTH=(@$(IDW) == 0) ? 1 : @$(IDW);
wire @$(PREFIX)_valid, @$(PREFIX)_ready, @$(PREFIX)_last;
wire [7:0] @$(PREFIX)_data;
wire [@$(DEVID)_WIDTH-1:0] @$(PREFIX)_id;
wire [31:0] @$(PREFIX)_debug;
// Verilator lint_on UNUSED
// }}}
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// The I2C Controller
// {{{
wbi2ccpu #(
.ADDRESS_WIDTH(@$(MASTER.BUS.AWID)),
.DATA_WIDTH(@$(MASTER.BUS.WIDTH)),
.AXIS_ID_WIDTH(@$(IDW))
) u_@$(PREFIX) (
// {{{
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)), .i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
@$(SLAVE.ANSIPORTLIST),
@$(MASTER.ANSIPORTLIST),
.i_i2c_sda(i_@$(PREFIX)_sda), .i_i2c_scl(i_@$(PREFIX)_scl),
.o_i2c_sda(o_@$(PREFIX)_sda), .o_i2c_scl(o_@$(PREFIX)_scl),
.M_AXIS_TVALID(@$(PREFIX)_valid), .M_AXIS_TREADY(@$(PREFIX)_ready),
.M_AXIS_TDATA(@$(PREFIX)_data), .M_AXIS_TLAST(@$(PREFIX)_last),
.M_AXIS_TID(@$(PREFIX)_id),
.i_sync_signal(rtc_pps),
//
.o_interrupt(@$(INTERRUPT)),
.o_debug(@$(PREFIX)_debug)
// }}}
);
assign @$(PREFIX)_ready = (!@$(PREFIX)_valid) || (1'b0
|| (@$(PREFIX)_id == 0) // NULL address
|| (@$(PREFIX)_id == 1)
`ifdef I2CDMA_ACCESS
|| (@$(PREFIX)_id == 2 && i2cdma_ready)
`else
|| (@$(PREFIX)_id == 2)
`endif
|| (@$(PREFIX)_id > 2));
// }}}
@MAIN.ALT=
assign o_@$(PREFIX)_scl = 1'b1;
assign o_@$(PREFIX)_sda = 1'b1;
##
## regdefs.h / regdefs.cpp
##
@REGS.N=4
@REGS.NOTE=// I2C Controller registers
@REGS.0= 0 R_@$(DEVID) @$(DEVID) @$(DEVID)_CTRL @$(DEVID)CTRL
@REGS.1= 1 R_@$(DEVID)_OVW @$(DEVID)_OVW @$(DEVID)_OVERRIDE
@REGS.2= 2 R_@$(DEVID)_ADDR @$(DEVID)_ADDR @$(DEVID)_ADDRESS
@REGS.3= 3 R_@$(DEVID)_CKCOUNT @$(DEVID)CLK @$(DEVID)_CKCOUNT
##
## board.h
##
@BDEF.DEFN=
////////////////////////////////////////////////////////////////////////
//
// I2C CPU data structures
// {{{
////////////////////////////////////////////////////////////////////////
//
//
#ifndef @$(DEVID)_H
#define @$(DEVID)_H
#define I2CC_WAITING 0x00800000 // True if waiting for synch signal
#define I2CC_HALT 0x00400000 // Halt request
#define I2CC_ABORT 0x00200000 // Abort
#define I2CC_ERROR 0x00100000
#define I2CC_HARDHALT 0x00080000
#define I2CC_SCL 0x00000200
#define I2CC_SDA 0x00000100
#define I2CC_STOPPED I2CC_HARDHALT
#define I2CC_FAULT (I2CC_ERROR | I2CC_ABORT)
#define I2CC_CLEAR (I2CC_FAULT | I2CC_HALT)
// For the manual port
#define I2CC_MANSCL 0x00008000
#define I2CC_MANSDA 0x00004000
#define I2CC_MANUAL 0x00000800
#define I2CC_TVALID 0x00000200
#define I2CC_TLAST 0x00000100
typedef struct @$(DEVID)_S {
volatile unsigned ic_control,
ic_override,
ic_address,
ic_clkcount;
} @$(DEVID);
#endif // @$(DEVID)_H
// }}}
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=@$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME)=((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
##
## Makefile insert info
##
@RTL.MAKE.GROUP=@$(DEVID)
@RTL.MAKE.SUBD=wbi2c
## RTL.MAKE.FILES *shoul* also include dblfetch, but that's a part of the CPU
## directory, so we don't include it here a second time
@RTL.MAKE.FILES=wbi2ccpu.v axisi2c.v
##
## Makefile insert info
##
@SIM.CLOCK=clk
@SIM.TICK=
m_core->i_@$(PREFIX)_scl = m_core->o_@$(PREFIX)_scl;
m_core->i_@$(PREFIX)_sda = m_core->o_@$(PREFIX)_sda;
================================================
FILE: auto-data/i2cdma.txt
================================================
################################################################################
##
## Filename: auto-data/i2cdma.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Connect an (optional) DMA to the main I2C bus.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=i2cdma
@DEVID=I2CDMA
@ACCESS=@$(DEVID)_ACCESS
@NADDR=4
@SLAVE.BUS=wb32
@SLAVE.TYPE=DOUBLE
@MASTER.BUS=wbwide
@MASTER.TYPE=DMA
@MASTER.ANSPREFIX=dma_
@STREAM=i2c
@MAIN.DEFNS=
wire @$(PREFIX)_ready;
@MAIN.INSERT=
wbi2cdma #(
.AW(@$(MASTER.BUS.AWID)), .DW(@$(MASTER.BUS.WIDTH)), .SW(8),
.OPT_LITTLE_ENDIAN(1'b0)
) u_@$(PREFIX) (
// {{{
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)),
.i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
//
@$(SLAVE.ANSIPORTLIST),
.S_VALID(@$(STREAM)_valid && @$(STREAM)_id == 2),
.S_READY(@$(PREFIX)_ready),
.S_DATA(@$(STREAM)_data), .S_LAST(@$(STREAM)_last),
@$(MASTER.ANSIPORTLIST)
// }}}
);
@MAIN.ALT=
assign @$(PREFIX)_ready = 1'b0;
@RTL.MAKE.GROUP=@$(DEVID)
@RTL.MAKE.SUBD=wbi2c
@RTL.MAKE.FILES=wbi2cdma.v
@REGS.N=4
@REGS.0=0 R_@$(DEVID) @$(DEVID)
@REGS.1=1 R_@$(DEVID)_ADDR @$(DEVID)ADDR
@REGS.2=2 R_@$(DEVID)_BASE @$(DEVID)BASE
@REGS.3=3 R_@$(DEVID)_LEN @$(DEVID)LEN
##
## board.h
##
@BDEF.DEFN=
#ifndef @$(DEVID)_H
#define @$(DEVID)_H
////////////////////////////////////////////////////////////////////////
//
// I2C DMA data structures
// {{{
////////////////////////////////////////////////////////////////////////
//
//
typedef struct @$(DEVID)_S {
unsigned id_control, id_current, id_base, id_memlen;
} @$(DEVID);
#endif // @$(DEVID)_H
// }}}
@BDEF.IONAME=_@$(PREFIX)
@BDEF.IOTYPE=@$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME)=((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE));
##
================================================
FILE: auto-data/i2saudio.txt
================================================
################################################################################
##
## Filename: auto-data/i2saudio.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=i2saudio
@ACCESS=I2SAUDIO
@DEPENDS=ARBITRARY_CLOCK_GENERATOR_ACCESS
@DEVID=AUDIO
@SOURCE=audio_in
@SINK=audio_out
@NADDR=1
@MAIN.PORTLIST=
o_i2s_lrclk, o_i2s_bclk, o_i2s_mclk, o_i2s_dac, i_i2s_adc
@MAIN.IODECL=
output wire o_i2s_lrclk, o_i2s_bclk, o_i2s_mclk, o_i2s_dac;
input wire i_i2s_adc;
@MAIN.DEFNS=
////////////////////////////////////////////////////////////////////////
//
// I2S Audio signal definitions
// {{{
wire w_@$(PREFIX)_en;
// Verilator lint_off UNUSED
//
// These wires may or may not be connected to anything ...
wire w_@$(SINK)_valid, w_@$(SINK)_ready, w_@$(SINK)_last;
wire [23:0] w_@$(SINK)_data;
//
// w_@$(SOURCE)... comes from the microphone (if present)
wire w_@$(SOURCE)_valid, w_@$(SOURCE)_ready,
w_@$(SOURCE)_last;
wire [23:0] w_@$(SOURCE)_data;
wire [31:0] w_@$(PREFIX)_debug;
// Verilator lint_on UNUSED
// }}}
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// I2S Audio signal handler
// {{{
assign o_i2s_mclk = i_genclk_clk;
assign w_@$(PREFIX)_en = 1'b1;
axisi2s #(
.BDIV(4'h1)
) u_@$(PREFIX) (
// {{{
.S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset),
//
// Inputs to drive the speakers
.S_AXIS_TVALID(w_@$(SINK)_valid),
.S_AXIS_TREADY(w_@$(SINK)_ready),
.S_AXIS_TDATA(w_@$(SINK)_data),
.S_AXIS_TLAST(w_@$(SINK)_last),
//
// Outputs from the microphone
.M_AXIS_TVALID(w_@$(SOURCE)_valid),
.M_AXIS_TREADY(w_@$(SOURCE)_ready),
.M_AXIS_TDATA(w_@$(SOURCE)_data),
.M_AXIS_TLAST(w_@$(SOURCE)_last),
//
.i_mclk(o_i2s_mclk),
.i_clken(w_@$(PREFIX)_en),
.o_lrclk(o_i2s_lrclk),
.o_bclk(o_i2s_bclk),
.i_adc(i_i2s_adc),
.o_dac(o_i2s_dac),
.o_debug(w_@$(PREFIX)_debug)
// }}}
);
`ifndef AUDIOSINK_ACCESS
assign w_@$(SINK)_valid = 0;
assign w_@$(SINK)_data = 0;
assign w_@$(SINK)_last = 0;
`endif
`ifndef AUDIOSOURCE_ACCESS
assign w_@$(SOURCE)_ready = 1;
`endif
// }}}
@MAIN.ALT=
////////////////////////////////////////////////////////////////////////
//
// (No) I2S Audio signal handler (option)
// {{{
`ifndef AUDIOSINK_ACCESS
assign w_@$(SINK)_valid = 0;
assign w_@$(SINK)_data = 0;
assign w_@$(SINK)_last = 0;
`endif
assign w_@$(SINK)_ready = 0;
assign w_@$(SOURCE)_valid = 0;
assign w_@$(SOURCE)_data = 0;
assign w_@$(SOURCE)_last = 0;
`ifndef AUDIOSOURCE_ACCESS
assign w_@$(SOURCE)_ready = 0;
`endif
// }}}
@XDC.INSERT=
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ sdrami/r_sys_reset* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/mclk_reset* }] 10.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/rgray* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/rgray_cross* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/wgray* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/wgray_cross* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/mem_reg* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_adc_fifo/GEN_REGISTERED_READ.o_rd_data* }] 8.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/mem_reg* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/GEN_REGISTERED_READ.o_rd_data* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/rgray* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/rgray_cross* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/wgray* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/wgray_cross* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/u_dac_fifo/wr_rgray* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/r_dac_data* }] 8.0
##
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_lrclk* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_pipe* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_bclk* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_pipe* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_dac* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_pipe* }] 8.0
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *xgenclki/GEN_PLL.pll* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_pipe* }] 8.0
set_false_path -hold -from [get_cells -hier -filter {NAME=~ *xgenclki/GEN_PLL.pll* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_pipe* }]
set_false_path -hold -from [get_cells -hier -filter {NAME=~ *xgenclki/GEN_PLL.pll* }] -rise_to [get_clocks -filter {NAME=~ *clk_pll_i* }]
##
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_lrclk* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_debug* }] 8.0
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_bclk* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_debug* }] 8.0
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/lli2si/o_dac* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_debug* }] 8.0
## set_max_delay -datapath_only -from [get_cells -hier -filter {NAME=~ *xgenclki/GEN_PLL.pll* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_debug* }] 8.0
## set_false_path -hold -from [get_cells -hier -filter {NAME=~ *xgenclki/GEN_PLL.pll* }] -to [get_cells -hier -filter {NAME=~ *u_@$(PREFIX)/xclk_debug* }]
@RTL.MAKE.GROUP=AUDIO
@RTL.MAKE.SUBD=audio
@RTL.MAKE.FILES=axisi2s.v lli2s.v
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
================================================
FILE: auto-data/icape.txt
================================================
################################################################################
##
## Filename: auto-data/icape.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: A description of how to connect the wbicapetwo interface for
## Xilinx's ICAPE2 interface to a wishbone bus.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=icape
@NADDR=32
@ACCESS=CFG_ACCESS
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb32
@MAIN.PARAM=
localparam ICAPE_LGDIV=3;
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// ICAPE2 driver/controller
// {{{
////////////////////////////////////////////////////////////////////////
//
//
`ifdef VERILATOR
reg r_@$(PREFIX)_ack;
initial r_@$(PREFIX)_ack = 1'b0;
always @(posedge i_clk)
r_@$(PREFIX)_ack <= @$(SLAVE.PREFIX)_stb;
assign @$(SLAVE.PREFIX)_ack = r_@$(PREFIX)_ack;
assign @$(SLAVE.PREFIX)_stall = 1'b0;
assign @$(SLAVE.PREFIX)_idata = 32'h00;
`else
wbicapetwo #(
.LGDIV(ICAPE_LGDIV)
) u_@$(PREFIX) (
// {{{
.i_clk(i_clk), .i_reset(i_reset),
@$(SLAVE.ANSIPORTLIST)
// }}}
);
`endif
// }}}
@REGS.NOTE=// FPGA CONFIG REGISTERS: 0x4e0-0x4ff
@REGS.N=20
@REGS.0= 0 R_CFG_CRC FPGACRC
@REGS.1= 1 R_CFG_FAR FPGAFAR
@REGS.2= 2 R_CFG_FDRI FPGAFDRI
@REGS.3= 3 R_CFG_FDRO FPGAFDRO
@REGS.4= 4 R_CFG_CMD FPGACMD
@REGS.5= 5 R_CFG_CTL0 FPGACTL0
@REGS.6= 6 R_CFG_MASK FPGAMASK
@REGS.7= 7 R_CFG_STAT FPGASTAT
@REGS.8= 8 R_CFG_LOUT FPGALOUT
@REGS.9= 9 R_CFG_COR0 FPGACOR0
@REGS.10= 10 R_CFG_MFWR FPGAMFWR
@REGS.11= 11 R_CFG_CBC FPGACBC
@REGS.12= 12 R_CFG_IDCODE FPGAIDCODE
@REGS.13= 13 R_CFG_AXSS FPGAAXSS
@REGS.14= 14 R_CFG_COR1 FPGACOR1
@REGS.15= 16 R_CFG_WBSTAR WBSTAR
@REGS.16= 17 R_CFG_TIMER CFGTIMER
@REGS.17= 22 R_CFG_BOOTSTS BOOTSTS
@REGS.18= 24 R_CFG_CTL1 FPGACTL1
@REGS.19= 31 R_CFG_BSPI FPGABSPI
@BDEF.DEFN=
// Offsets for the ICAPE2 interface
#define CFG_CRC 0
#define CFG_FAR 1
#define CFG_FDRI 2
#define CFG_FDRO 3
#define CFG_CMD 4
#define CFG_CTL0 5
#define CFG_MASK 6
#define CFG_STAT 7
#define CFG_LOUT 8
#define CFG_COR0 9
#define CFG_MFWR 10
#define CFG_CBC 11
#define CFG_IDCODE 12
#define CFG_AXSS 13
#define CFG_COR1 14
#define CFG_WBSTAR 16
#define CFG_TIMER 17
#define CFG_BOOTSTS 22
#define CFG_CTL1 24
#define CFG_BSPI 31
@BDEF.IONAME=_icape[32]
@BDEF.IOTYPE=unsigned
@BDEF.OSDEF=_BOARD_HAS_ICAPETWO
@BDEF.OSVAL=static volatile @$THIS.BDEF.IOTYPE *const _icape = ((unsigned *)@$[0x%08x](REGBASE));
@RTL.MAKE.GROUP=ICAP
@RTL.MAKE.SUBD=
@RTL.MAKE.FILES=wbicapetwo.v
================================================
FILE: auto-data/legalgen.txt
================================================
////////////////////////////////////////////////////////////////////////////////
//
// Filename: auto-data/legalgen.txt
//
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
// {{{
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2024, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
================================================
FILE: auto-data/mdio.txt
================================================
################################################################################
##
## Filename: auto-data/mdio.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: This file describes how the network MDIO core is to be
## connected to the rest of the design, for use by the autofpga
## program.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=mdio
@NADDR=1024
@ACCESS=NETCTRL_ACCESS
@SLAVE.TYPE=OTHER
@SLAVE.BUS=wb32
@TOP.PORTLIST=
// Toplevel ethernet MDIO ports
o_eth_mdclk, io_eth_mdio
@TOP.IODECL=
// Ethernet control (MDIO)
output wire o_eth_mdclk;
inout wire io_eth_mdio;
@TOP.DEFNS=
// Ethernet control (MDIO)
wire w_mdio, w_mdwe;
@TOP.MAIN=
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio
@TOP.INSERT=
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
@MAIN.PORTLIST=
// The ethernet MDIO wires
o_mdclk, o_mdio, o_mdwe, i_mdio
@MAIN.IODECL=
// Ethernet control (MDIO)
output wire o_mdclk, o_mdio, o_mdwe;
input wire i_mdio;
@MAIN.DEFNS=
// Verilator lint_off UNUSED
wire[31:0] @$(PREFIX)_debug;
// Verilator lint_on UNUSED
@MAIN.INSERT=
enetctrl #(
.CLKBITS(6)
) u_@$(PREFIX) (
.i_clk(i_clk), .i_reset(i_reset),
@$(SLAVE.ANSIPORTLIST),
.o_mdclk(o_mdclk), .o_mdio(o_mdio), .i_mdio(i_mdio),
.o_mdwe(o_mdwe), .o_debug(@$(PREFIX)_debug)
);
@MAIN.ALT=
assign o_mdclk = 1'b1;
assign o_mdio = 1'b1;
assign o_mdwe = 1'b0;
@REGS.NOTE= // Ethernet configuration (MDIO) port
@REGS.N=30
@REGS.0= 0 R_MDIO_BMCR BMCR
@REGS.1= 1 R_MDIO_BMSR BMSR
@REGS.2= 2 R_MDIO_PHYIDR1 PHYIDR1
@REGS.3= 3 R_MDIO_PHYIDR2 PHYIDR2
@REGS.4= 4 R_MDIO_ANAR ANAR
@REGS.5= 5 R_MDIO_ANLPAR ANLPAR
@REGS.6= 6 R_MDIO_ANER ANER
@REGS.7= 7 R_MDIO_ANNPTR ANNPTR
@REGS.8= 8 R_MDIO_ANNPRR ANNPRR
@REGS.9= 9 R_MDIO_GBCR GBCR
@REGS.10= 10 R_MDIO_GBSR GBSR
@REGS.11= 13 R_MDIO_MACR MACR
@REGS.12= 14 R_MDIO_MAADR MAADR
@REGS.13= 15 R_MDIO_GBESR GBESR
@REGS.14= 16 R_MDIO_PHYCR PHYCR
@REGS.15= 17 R_MDIO_PHYSR PHYSR
@REGS.16= 18 R_MDIO_INER INER
@REGS.17= 19 R_MDIO_INSR INSR
## 20-23 are reserved
@REGS.18=24 R_MDIO_RXERC RXERC
## 25-26 are reserved
@REGS.19=27 R_MDIO_LDPSR LDPSR
@REGS.20=30 R_MDIO_EPAGSR EPAGSR
@REGS.21=31 R_MDIO_PAGSEL PAGSEL
##
@REGS.22=0 R_XMDIO_PC1R XPC1R
@REGS.23=1 R_XMDIO_PS1R XPS1R
@REGS.24=20 R_XMDIO_EEECR XEEECR
@REGS.25=16 R_XMDIO_EEEWER XEEEWER
@REGS.26=60 R_XMDIO_EEEAR XEEEAR
@REGS.27=61 R_XMDIO_EEELPAR XEEELPAR
@REGS.28=26 R_XMDIO_LACR XLACR
@REGS.29=28 R_XMDIO_LCR XLCR
@REGS.30=45 R_XMDIO_ACCR XACCR
@BDEF.DEFN=
//
// The Ethernet MDIO interface
//
#define MDIO_BMCR 0x00
#define MDIO_BMSR 0x01
#define MDIO_PHYIDR1 0x02 // PHY ID Register #1
#define MDIO_PHYIDR2 0x03 // PHY ID Register #2
#define MDIO_ANAR 0x04 // Autonegotiation advertisement
#define MDIO_ANLPAR 0x05 // Autonegotiation link partner ability
#define MDIO_ANER 0x06 // Autonegotiation expansion
#define MDIO_ANNPTR 0x07 // Autonegotiation next page
#define MDIO_ANNPRR 0x08 // Autonegotiation link partner next page
#define MDIO_GBCR 0x09 // 1GBase-T Control
#define MDIO_GBSR 0x0a // 1GBase-T Status
#define MDIO_MACR 0x0d // MMD Access control
#define MDIO_MAADR 0x0e // MMD Access register/data
#define MDIO_GBESR 0x0f
#define MDIO_PHYCR 0x10
#define MDIO_PHYSR 0x11
#define MDIO_INER 0x12
#define MDIO_INSR 0x13
#define MDIO_LDPSR 0x1b
#define MDIO_EPAGSR 0x1e
#define MDIO_PAGSEL 0x1f
#define XMDIO_PC1R 0x00
#define XMDIO_PS1R 0x01
#define XMDIO_EEECR 0x14
#define XMDIO_EEEWER 0x10
// #define XMDIO_EEEAR 0x
// #define XMDIO_EEELPAR 0x18
#define XMDIO_LACR 0x1a
#define XMDIO_LCR 0x1c
// #define XMDIO_ACCR 0x1b
typedef struct ENETMDIO_S {
unsigned e_v[32][32];
} ENETMDIO;
@BDEF.IOTYPE= ENETMDIO
@BDEF.IONAME= io_netmdio
@BDEF.OSDEF= _BOARD_HAS_NETMDIO
@BDEF.OSVAL= static volatile @$THIS.BDEF.IOTYPE *const _mdio = ((@$THIS.BDEF.IOTYPE *)@$[0x%08x](REGBASE));
@SIM.CLOCK=clk
@SIM.INCLUDE=
#include "enetctrlsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
ENETCTRLSIM *m_mdio;
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_mdio = new ENETCTRLSIM;
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_mdio = (*m_mdio)((m_core->i_reset)?1:0,
m_core->o_mdclk,
((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1);
#else
m_core->i_mdio = ((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1;
#endif // @$(ACCESS)
@RTL.MAKE.SUBD=ethernet
@RTL.MAKE.GROUP=ENETMDIO
@RTL.MAKE.FILES=enetctrl.v
================================================
FILE: auto-data/meganet.txt
================================================
################################################################################
##
## Filename: auto-data/meganet.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2015-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=net
@DEVID=MEGANET
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.BUS=wb32
@NADDR=32
@SLAVE.TYPE=OTHER
@$BASEPORT=6782
@$UARTDBGPORT=@$(BASEPORT)
@$UARTPORT=@$(BASEPORT)+1
@$UDPDBGPORT=@$(BASEPORT)+2
@$DATAPORT=@$(BASEPORT)+3
@$HWMAC.0=0x82
@$HWMAC.1=0x33
@$HWMAC.2=0x48
@$HWMAC.3=0x02
@$HWMAC.4=0xe1
@$HWMAC.5=0xc8
@$IPADDR.0=192
@$IPADDR.1=168
@$IPADDR.2=15
@$IPADDR.3=29
@TOP.PORTLIST=
// Ethernet control (packets) lines
o_@$(PREFIX)_reset_n,
i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rx_ctl, i_@$(PREFIX)_rxd,
o_@$(PREFIX)_tx_clk, o_@$(PREFIX)_tx_ctl, o_@$(PREFIX)_txd
@TOP.IODECL=
// MegaNet I/O port declarations
// {{{
output wire o_@$(PREFIX)_reset_n;
input wire i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rx_ctl;
input wire [3:0] i_@$(PREFIX)_rxd;
output wire o_@$(PREFIX)_tx_clk, o_@$(PREFIX)_tx_ctl;
output wire [3:0] o_@$(PREFIX)_txd;
// }}}
@TOP.DEFNS=
// Mega Net definitions
// {{{
wire [7:0] w_@$(PREFIX)_rxd, w_@$(PREFIX)_txd;
wire w_@$(PREFIX)_rxdv, w_@$(PREFIX)_rxerr,
w_@$(PREFIX)_txctl;
wire [1:0] w_@$(PREFIX)_tx_clk;
reg @$(PREFIX)_last_tck;
// }}}
@TOP.MAIN=
// Ethernet (RGMII) connections
o_net_reset_n,
i_net_rx_clk, w_net_rxdv, w_net_rxdv ^ w_net_rxerr, w_net_rxd,
w_net_tx_clk, w_net_txctl, w_net_txd
@TOP.INSERT=
// RGMII control
// {{{
xiddr @$(PREFIX)rx0(i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rxd[0], { w_@$(PREFIX)_rxd[4], w_@$(PREFIX)_rxd[0] });
xiddr @$(PREFIX)rx1(i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rxd[1], { w_@$(PREFIX)_rxd[5], w_@$(PREFIX)_rxd[1] });
xiddr @$(PREFIX)rx2(i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rxd[2], { w_@$(PREFIX)_rxd[6], w_@$(PREFIX)_rxd[2] });
xiddr @$(PREFIX)rx3(i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rxd[3], { w_@$(PREFIX)_rxd[7], w_@$(PREFIX)_rxd[3] });
xiddr @$(PREFIX)rxc(i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rx_ctl, { w_@$(PREFIX)_rxdv, w_@$(PREFIX)_rxerr });
//
// All of the below is about delaying the clock 90 degrees from the data
//
xoserdes @$(PREFIX)tx0(s_clk_125mhz, pll_reset, s_clk_250mhz, { {(2){w_@$(PREFIX)_txd[0]}}, {(2){w_@$(PREFIX)_txd[4]}} }, o_@$(PREFIX)_txd[0]);
xoserdes @$(PREFIX)tx1(s_clk_125mhz, pll_reset, s_clk_250mhz, { {(2){w_@$(PREFIX)_txd[1]}}, {(2){w_@$(PREFIX)_txd[5]}} }, o_@$(PREFIX)_txd[1]);
xoserdes @$(PREFIX)tx2(s_clk_125mhz, pll_reset, s_clk_250mhz, { {(2){w_@$(PREFIX)_txd[2]}}, {(2){w_@$(PREFIX)_txd[6]}} }, o_@$(PREFIX)_txd[2]);
xoserdes @$(PREFIX)tx3(s_clk_125mhz, pll_reset, s_clk_250mhz, { {(2){w_@$(PREFIX)_txd[3]}}, {(2){w_@$(PREFIX)_txd[7]}} }, o_@$(PREFIX)_txd[3]);
always @(posedge s_clk_125mhz)
@$(PREFIX)_last_tck <= w_@$(PREFIX)_tx_clk[0];
xoserdes @$(PREFIX)txc(s_clk_125mhz, pll_reset, s_clk_250mhz, {(4){w_@$(PREFIX)_txctl}}, o_@$(PREFIX)_tx_ctl );
xoserdes @$(PREFIX)txck(s_clk_125mhz, pll_reset, s_clk_250mhz, {@$(PREFIX)_last_tck, {(2){w_@$(PREFIX)_tx_clk[1]}},w_@$(PREFIX)_tx_clk[0]},o_@$(PREFIX)_tx_clk);
// xoserdes @$(PREFIX)txck(s_clk_125mhz, pll_reset, s_clk_250mhz, { {(2){w_@$(PREFIX)_tx_clk[1]}},{(2){w_@$(PREFIX)_tx_clk[0]}} }, o_@$(PREFIX)_tx_clk);
// }}}
@MAIN.PORTLIST=
// Ethernet control (packets) lines
o_@$(PREFIX)_reset_n,
// eth_int_b // Interrupt, leave floating
// eth_pme_b // Power management event, leave floating
i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rx_dv, i_@$(PREFIX)_rx_err, i_@$(PREFIX)_rxd,
o_@$(PREFIX)_tx_clk, o_@$(PREFIX)_tx_ctl, o_@$(PREFIX)_txd
@MAIN.PARAM=
parameter [15:0] UDP_DBGPORT = @$(UDPDBGPORT);
localparam [47:0] DEF_HWMAC = 48'h@$[%02x](HWMAC.0)_@$[%02x](HWMAC.1)_@$[%02x](HWMAC.2)_@$[%02x](HWMAC.3)_@$[%02x](HWMAC.4)_@$[%02x](HWMAC.5);
localparam [31:0] DEF_IPADDR = { 8'd@$(IPADDR.0), 8'd@$(IPADDR.1), 8'd@$(IPADDR.2), 8'd@$(IPADDR.3) };
@MAIN.IODECL=
// Ethernet (RGMII) control
// {{{
// Verilator lint_off SYNCASYNCNET
output wire o_net_reset_n;
// Verilator lint_on SYNCASYNCNET
input wire i_@$(PREFIX)_rx_clk, i_@$(PREFIX)_rx_dv, i_@$(PREFIX)_rx_err;
input wire [7:0] i_@$(PREFIX)_rxd;
output wire [1:0] o_@$(PREFIX)_tx_clk;
output wire o_@$(PREFIX)_tx_ctl;
output wire [7:0] o_@$(PREFIX)_txd;
// }}}
@MAIN.DEFNS=
// Ethernet (RGMII) control
// {{{
// Verilator lint_off UNUSED
wire [47:0] @$(PREFIX)_hwmac, @$(PREFIX)_last_ping_hwmac;
wire [31:0] @$(PREFIX)_ip_addr, @$(PREFIX)_last_ping_ipaddr;
wire @$(PREFIX)cpurx_valid, @$(PREFIX)cpurx_ready;
wire [31:0] @$(PREFIX)cpurx_data;
wire [1:0] @$(PREFIX)cpurx_bytes;
wire @$(PREFIX)cpurx_last, @$(PREFIX)cpurx_abort;
wire @$(PREFIX)cputx_valid, @$(PREFIX)cputx_ready,
@$(PREFIX)cputx_last, @$(PREFIX)cputx_abort;
wire [31:0] @$(PREFIX)cputx_data;
wire [1:0] @$(PREFIX)cputx_bytes;
wire @$(PREFIX)_dbg_valid, @$(PREFIX)_dbg_ready,
@$(PREFIX)_dbg_last;
wire [31:0] @$(PREFIX)_dbg_data;
wire [1:0] @$(PREFIX)_dbg_bytes;
wire @$(PREFIX)_high_speed;
wire @$(PREFIX)_debug_clk;
wire [31:0] @$(PREFIX)_debug;
wire ign_rxpkt_@$(PREFIX)_ready;
// Verilator lint_on UNUSED
// }}}
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// MegaNET @$(DEVID)
// {{{
////////////////////////////////////////////////////////////////////////
//
//
meganet #(
// {{{
.DEF_HWMAC(DEF_HWMAC),
.DEF_IPADDR(DEF_IPADDR),
.UDP_DBGPORT(UDP_DBGPORT)
// }}}
) u_@$(PREFIX) (
// {{{
.S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset),
//
.o_hwmac(@$(PREFIX)_hwmac), .o_ipaddr(@$(PREFIX)_ip_addr),
.o_ping_hwmac(@$(PREFIX)_last_ping_hwmac),
.o_ping_ipaddr(@$(PREFIX)_last_ping_ipaddr),
// Wishbone port
// {{{
@$(SLAVE.ANSIPORTLIST),
// }}}
// ifdef @$(DEVID)CPUTX_ACCESS
// {{{
.S_CPU_VALID(@$(PREFIX)cputx_valid),
.S_CPU_READY(@$(PREFIX)cputx_ready),
.S_CPU_DATA(@$(PREFIX)cputx_data),
.S_CPU_BYTES(@$(PREFIX)cputx_bytes),
.S_CPU_LAST(@$(PREFIX)cputx_last),
.S_CPU_ABORT(@$(PREFIX)cputx_abort),
// }}}
`ifdef NETBUS_ACCESS
// {{{
.S_DBG_VALID(@$(PREFIX)bus_valid),
.S_DBG_READY(@$(PREFIX)bus_ready),
.S_DBG_DATA(@$(PREFIX)bus_pkdata),
// .S_DBG_BYTES(@$(PREFIX)bus_bytes),
.S_DBG_LAST(@$(PREFIX)bus_last),
`else
.S_DBG_VALID(1'b0),
.S_DBG_READY(@$(PREFIX)_dbg_ready),
.S_DBG_DATA(32'h0),
.S_DBG_LAST(1'b1),
`endif
// }}}
// Data interface
// {{{
.S_DATA_VALID(1'b0),
.S_DATA_READY(ign_rxpkt_@$(PREFIX)_ready),
.S_DATA
gitextract_n54jfvbv/
├── .gitignore
├── LICENSE
├── Makefile
├── README.md
├── auto-data/
│ ├── allclocks.txt
│ ├── bkram.txt
│ ├── buserr.txt
│ ├── clkcheck.txt
│ ├── clkcounter.txt
│ ├── crossbus.txt
│ ├── ddr3.txt
│ ├── edid.txt
│ ├── edidslvscope.txt
│ ├── exconsole.txt
│ ├── flash.txt
│ ├── flashcfg.txt
│ ├── global.txt
│ ├── gpio.txt
│ ├── gps.txt
│ ├── hdmi.txt
│ ├── i2ccpu.txt
│ ├── i2cdma.txt
│ ├── i2saudio.txt
│ ├── icape.txt
│ ├── legalgen.txt
│ ├── mdio.txt
│ ├── meganet.txt
│ ├── nexysv.xdc
│ ├── pic.txt
│ ├── pwrcount.txt
│ ├── rtccount.txt
│ ├── rtcdate.txt
│ ├── rtcgps.txt
│ ├── sdio.txt
│ ├── sdspi.txt
│ ├── spio.txt
│ ├── vadj33.txt
│ ├── version.txt
│ ├── wboledbw.txt
│ ├── wbpmic.txt
│ ├── wbscopc.txt
│ ├── wbscope.txt
│ ├── wbuarbiter.txt
│ ├── wbuart.txt
│ ├── wbubus.txt
│ ├── zipcpu.txt
│ └── zipmaster.txt
├── demo-out/
│ ├── board.h
│ ├── board.ld
│ ├── build.xdc
│ ├── iscachable.v
│ ├── main.v
│ ├── main_tb.cpp
│ ├── regdefs.cpp
│ ├── regdefs.h
│ ├── rtl.make.inc
│ ├── testb.h
│ └── toplevel.v
├── doc/
│ ├── 20200709-update.dia
│ ├── Makefile
│ ├── bus.md
│ ├── clocks.md
│ ├── constraints.md
│ ├── double.md
│ ├── goals.txt
│ ├── icd.txt
│ ├── ioports.md
│ ├── single.md
│ ├── slaves.md
│ └── src/
│ └── gpl-3.0.tex
└── sw/
├── .gitignore
├── Makefile
├── ast.cpp
├── ast.h
├── autofpga.cpp
├── automdata.h
├── autopdata.h
├── bitlib.cpp
├── bitlib.h
├── bldboardld.cpp
├── bldboardld.h
├── bldcachable.cpp
├── bldcachable.h
├── bldregdefs.cpp
├── bldregdefs.h
├── bldrtlmake.cpp
├── bldrtlmake.h
├── bldsim.cpp
├── bldsim.h
├── bldtestb.cpp
├── bldtestb.h
├── bus/
│ ├── axi.cpp
│ ├── axi.h
│ ├── axil.cpp
│ ├── axil.h
│ ├── wb.cpp
│ └── wb.h
├── businfo.cpp
├── businfo.h
├── clockinfo.cpp
├── clockinfo.h
├── expr.l
├── expr.ypp
├── gather.cpp
├── gather.h
├── genbus.cpp
├── genbus.h
├── globals.cpp
├── globals.h
├── ifdefs.cpp
├── ifdefs.h
├── keys.cpp
├── keys.h
├── kveval.cpp
├── kveval.h
├── legalnotice.cpp
├── legalnotice.h
├── mapdhash.cpp
├── mapdhash.h
├── mlist.cpp
├── mlist.h
├── msgs.cpp
├── msgs.h
├── parser.cpp
├── parser.h
├── plist.cpp
├── plist.h
├── predicates.cpp
├── predicates.h
├── subbus.cpp
└── subbus.h
SYMBOL INDEX (321 symbols across 45 files)
FILE: demo-out/board.h
type I2CCPU (line 112) | typedef struct I2CCPU_S {
type WBUART (line 148) | typedef struct WBUART_S {
type VIDMODE (line 179) | typedef struct __attribute__((packed)) VIDMODE_S {
type VIDPIPE (line 186) | typedef struct __attribute__((packed)) VIDPIPE_S {
type WBSCOPE (line 217) | typedef struct WBSCOPE_S {
type DDR3_PHY (line 248) | typedef struct DDR3_PHY_S {
type I2CDMA (line 264) | typedef struct I2CDMA_S {
type GPSTB (line 272) | typedef struct GPSTB_S {
type ENETSTREAM (line 282) | typedef struct ENETSTREAM_S {
type RTCLIGHT (line 297) | typedef struct RTCLIGHT_S {
type SDIO_S (line 370) | struct SDIO_S
type GPSTRACKER (line 377) | typedef struct GPSTRACKER_S {
type ENETMDIO (line 417) | typedef struct ENETMDIO_S {
type OLEDBW (line 423) | typedef struct OLEDBW_S {
type WBMIC (line 435) | typedef struct WBMIC_S {
type SDIO_S (line 531) | struct SDIO_S
type SDIO_S (line 531) | struct SDIO_S
FILE: demo-out/main_tb.cpp
class MAINTB (line 109) | class MAINTB : public TESTB<Vmain> {
method MAINTB (line 133) | MAINTB(void) {
method reset (line 202) | void reset(void) {
method trace (line 218) | void trace(const char *vcd_trace_file_name) {
method close (line 225) | void close(void) {
method tick (line 229) | void tick(void) {
method sim_clk_tick (line 238) | virtual void sim_clk_tick(void) {
method sim_pixclk_tick (line 324) | virtual void sim_pixclk_tick(void) {
method sim_net_rx_clk_tick (line 353) | virtual void sim_net_rx_clk_tick(void) {
method sim_clk_125mhz_tick (line 381) | virtual void sim_clk_125mhz_tick(void) {
method tick_clk (line 391) | virtual void tick_clk(void) {
method tick_pixclk (line 401) | virtual void tick_pixclk(void) {
method tick_net_rx_clk (line 410) | virtual void tick_net_rx_clk(void) {
method tick_clk_125mhz (line 419) | virtual void tick_clk_125mhz(void) {
method load (line 433) | bool load(uint32_t addr, const char *buf, uint32_t len) {
method connect_idler (line 531) | void connect_idler(void) {
method on_tick (line 536) | bool on_tick(void) {
method loadelf (line 544) | void loadelf(const char *elfname) {
method cpu_dbg_write (line 568) | void cpu_dbg_write(const uint32_t addr, const uint32_t data) {
method cpu_dbg_read (line 595) | uint32_t cpu_dbg_read(const uint32_t addr) {
FILE: demo-out/regdefs.cpp
function addrdecode (line 318) | unsigned addrdecode(const char *v) {
FILE: demo-out/regdefs.h
type REGNAME (line 378) | typedef struct {
FILE: demo-out/testb.h
function TESTB (line 80) | TESTB(void) {
function virtual (line 96) | virtual ~TESTB(void) {
function trace (line 128) | void trace(const char *vcdname) {
function virtual (line 142) | virtual bool pausetrace(bool pausetrace) {
function virtual (line 154) | virtual bool pausetrace(void) {
function virtual (line 164) | virtual void closetrace(void) {
function virtual (line 182) | virtual void eval(void) {
function virtual (line 194) | virtual void tick(void) {
function virtual (line 248) | virtual void sim_clk_tick(void) {
function virtual (line 257) | virtual void sim_pixclk_tick(void) {
function virtual (line 266) | virtual void sim_net_rx_clk_tick(void) {
function virtual (line 275) | virtual void sim_clk_125mhz_tick(void) {
function virtual (line 284) | virtual bool done(void) {
function virtual (line 302) | virtual void reset(void) {
FILE: sw/ast.cpp
function AST (line 94) | AST *AST_BRANCH::copy(void) {
function AST (line 114) | AST *AST_SINGLEOP::copy(void) {
function AST (line 139) | AST *AST_TRIOP::copy(void) {
function AST (line 150) | AST *AST_NUMBER::copy(void) {
function AST (line 173) | AST *AST_IDENTIFIER::copy(void) {
FILE: sw/ast.h
function class (line 48) | class AST {
function class (line 59) | class AST_BRANCH : public AST {
function class (line 80) | class AST_SINGLEOP : public AST {
function class (line 95) | class AST_TRIOP : public AST {
function class (line 113) | class AST_NUMBER : public AST {
function class (line 125) | class AST_IDENTIFIER : public AST {
function AST (line 144) | inline AST *copy(AST *a) { return a->copy(); }
FILE: sw/autofpga.cpp
class INTINFO (line 96) | class INTINFO {
method INTINFO (line 102) | INTINFO(void) { i_name = NULL; i_wire = NULL; i_id = 0; }
method INTINFO (line 103) | INTINFO(STRINGP nm, STRINGP wr, unsigned id)
method INTINFO (line 105) | INTINFO(STRING &nm, STRING &wr, unsigned id) : i_id(id) {
class PICINFO (line 120) | class PICINFO {
method PICINFO (line 144) | PICINFO(MAPDHASH &pic) {
method add (line 166) | void add(MAPDHASH &psrc, STRINGP iname) {
method add (line 194) | void add(unsigned id, MAPDHASH &psrc, STRINGP iname) {
method assignids (line 234) | void assignids(void) {
method INTP (line 273) | INTP getint(unsigned iid) {
function count_pics (line 289) | int count_pics(MAPDHASH &info) {
function assign_int_to_pics (line 310) | void assign_int_to_pics(const STRING &iname, MAPDHASH &ihash) {
function assign_interrupts (line 347) | void assign_interrupts(MAPDHASH &master) {
function writeout (line 420) | void writeout(FILE *fp, MAPDHASH &master, const STRING &ky) {
function build_board_h (line 444) | void build_board_h( MAPDHASH &master, FILE *fp, STRING &fname) {
function build_latex_tbls (line 545) | void build_latex_tbls( MAPDHASH &master) {
function build_toplevel_v (line 563) | void build_toplevel_v( MAPDHASH &master, FILE *fp, STRING &fname) {
function build_main_v (line 754) | void build_main_v( MAPDHASH &master, FILE *fp, STRING &fname) {
function STRINGP (line 1162) | STRINGP remove_comments(STRINGP s) {
function build_outfile_aux (line 1186) | void build_outfile_aux(MAPDHASH &info, STRINGP fname, STRINGP data) {
function build_other_files (line 1208) | void build_other_files(MAPDHASH &info) {
function FILE (line 1226) | FILE *open_in(MAPDHASH &info, const STRING &fname) {
function get_portlist (line 1253) | void get_portlist(MAPDHASH &master, PORTLIST &ports) {
function build_xdc (line 1296) | void build_xdc(MAPDHASH &master, FILE *fp, STRING &fname) {
function build_pcf (line 1412) | void build_pcf(MAPDHASH &master, FILE *fp, STRING &fname) {
function build_lpf (line 1511) | void build_lpf(MAPDHASH &master, FILE *fp, STRING &fname) {
function build_ucf (line 1618) | void build_ucf(MAPDHASH &master, FILE *fp, STRING &fname) {
function main (line 1716) | int main(int argc, char **argv) {
FILE: sw/automdata.h
type BUSMASTER (line 42) | typedef struct BUSMASTER_S {
FILE: sw/autopdata.h
type REGINFO (line 42) | typedef struct REGINFO_S {
type AUTOPDATA (line 48) | typedef struct AUTOPDATA_S {
FILE: sw/bitlib.cpp
function nextlg (line 48) | unsigned nextlg(const unsigned long vl) {
function popc (line 61) | unsigned popc(const unsigned vl) {
FILE: sw/bldboardld.cpp
function build_script_ld (line 69) | static void build_script_ld(MAPDHASH &master, MAPDHASH &busmaster, FILE ...
function build_ld_files (line 322) | void build_ld_files(MAPDHASH &master, STRINGP subd) {
FILE: sw/bldcachable.cpp
function print_cachable (line 57) | static void print_cachable(FILE *fp, BUSINFO *bi,
function build_cachable_core_v (line 111) | void build_cachable_core_v(MAPDHASH &master, MAPDHASH &busmaster,
function build_cachable_v (line 166) | void build_cachable_v(MAPDHASH &master, STRINGP subd) {
FILE: sw/bldregdefs.cpp
function get_longest_defname (line 66) | int get_longest_defname(APLIST *alist) {
function write_regdefs (line 139) | void write_regdefs(FILE *fp, APLIST *alist, unsigned longest_defname) {
function build_regdefs_h (line 221) | void build_regdefs_h( MAPDHASH &master, FILE *fp, STRING &fname) {
function get_longest_uname (line 354) | unsigned get_longest_uname(APLIST *alist) {
function write_regnames (line 407) | void write_regnames(FILE *fp, APLIST *alist,
function build_regdefs_cpp (line 458) | void build_regdefs_cpp(MAPDHASH &master, FILE *fp, STRING &fname) {
FILE: sw/bldrtlmake.cpp
function build_rtl_make_inc (line 70) | void build_rtl_make_inc(MAPDHASH &master, FILE *fp, STRING &fname) {
FILE: sw/bldsim.cpp
function tb_same_clock (line 63) | bool tb_same_clock(MAPDHASH &info, STRINGP ckname) {
function tb_tick (line 101) | bool tb_tick(MAPDHASH &info, STRINGP ckname, FILE *fp) {
function tb_dbg_condition (line 151) | bool tb_dbg_condition(MAPDHASH &info, STRINGP ckname, FILE *fp) {
function tb_debug (line 195) | bool tb_debug(MAPDHASH &info, STRINGP ckname, FILE *fp) {
function build_main_tb_cpp (line 244) | void build_main_tb_cpp(MAPDHASH &master, FILE *fp, STRING &fname) {
FILE: sw/bldtestb.cpp
function build_testb_h (line 50) | void build_testb_h(MAPDHASH &master, FILE *fp, STRING &fname) {
FILE: sw/bus/axi.cpp
function compare_idwidths (line 250) | bool compare_idwidths(BMASTERP a, BMASTERP b) {
function BUSINFO (line 346) | BUSINFO *AXIBUS::create_sio(void) {
function BUSINFO (line 389) | BUSINFO *AXIBUS::create_dio(void) {
function STRINGP (line 1502) | STRINGP AXIBUS::master_portlist(BMASTERP m) {
function STRINGP (line 1561) | STRINGP AXIBUS::iansi(BMASTERP m) {
function STRINGP (line 1565) | STRINGP AXIBUS::oansi(BMASTERP m) {
function STRINGP (line 1569) | STRINGP AXIBUS::master_ansprefix(BMASTERP m) {
function STRINGP (line 1573) | STRINGP AXIBUS::master_ansi_portlist(BMASTERP m) {
function STRINGP (line 1628) | STRINGP AXIBUS::slave_ansprefix(PERIPHP p) {
function STRINGP (line 1632) | STRINGP AXIBUS::slave_portlist(PERIPHP p) {
function STRINGP (line 1697) | STRINGP AXIBUS::slave_ansi_portlist(PERIPHP p) {
function STRINGP (line 1767) | STRINGP AXIBUSCLASS::name(void) {
function STRINGP (line 1771) | STRINGP AXIBUSCLASS::longname(void) {
function GENBUS (line 1793) | GENBUS *AXIBUSCLASS::create(BUSINFO *bi) {
FILE: sw/bus/axi.h
function class (line 46) | class AXIBUS : public AXILBUS {
function class (line 99) | class AXIBUSCLASS : public BUSCLASS {
FILE: sw/bus/axil.cpp
function BUSINFO (line 288) | BUSINFO *AXILBUS::create_sio(void) {
function BUSINFO (line 334) | BUSINFO *AXILBUS::create_dio(void) {
function STRINGP (line 534) | STRINGP AXILBUS::master_name(int k) {
function STRINGP (line 1254) | STRINGP AXILBUS::master_portlist(BMASTERP m) {
function STRINGP (line 1295) | STRINGP AXILBUS::iansi(BMASTERP m) {
function STRINGP (line 1299) | STRINGP AXILBUS::oansi(BMASTERP m) {
function STRINGP (line 1303) | STRINGP AXILBUS::master_ansprefix(BMASTERP m) {
function STRINGP (line 1307) | STRINGP AXILBUS::master_ansi_portlist(BMASTERP m) {
function STRINGP (line 1344) | STRINGP AXILBUS::slave_ansprefix(PERIPHP m) {
function STRINGP (line 1348) | STRINGP AXILBUS::slave_portlist(PERIPHP p) {
function STRINGP (line 1394) | STRINGP AXILBUS::slave_ansi_portlist(PERIPHP p) {
function STRINGP (line 1446) | STRINGP AXILBUSCLASS::name(void) {
function STRINGP (line 1450) | STRINGP AXILBUSCLASS::longname(void) {
function GENBUS (line 1472) | GENBUS *AXILBUSCLASS::create(BUSINFO *bi) {
FILE: sw/bus/axil.h
function class (line 45) | class AXILBUS : public GENBUS {
function class (line 97) | class AXILBUSCLASS : public BUSCLASS {
FILE: sw/bus/wb.cpp
function BUSINFO (line 297) | BUSINFO *WBBUS::create_sio(void) {
function BUSINFO (line 343) | BUSINFO *WBBUS::create_dio(void) {
function STRINGP (line 1291) | STRINGP WBBUS::master_portlist(BMASTERP) {
function STRINGP (line 1307) | STRINGP WBBUS::iansi(BMASTERP) {
function STRINGP (line 1311) | STRINGP WBBUS::oansi(BMASTERP) {
function STRINGP (line 1315) | STRINGP WBBUS::master_ansprefix(BMASTERP) {
function STRINGP (line 1319) | STRINGP WBBUS::master_ansi_portlist(BMASTERP) {
function STRINGP (line 1335) | STRINGP WBBUS::slave_ansprefix(PERIPHP p) {
function STRINGP (line 1340) | STRINGP WBBUS::slave_portlist(PERIPHP p) {
function STRINGP (line 1372) | STRINGP WBBUS::slave_ansi_portlist(PERIPHP p) {
function STRINGP (line 1415) | STRINGP WBBUSCLASS::name(void) {
function STRINGP (line 1419) | STRINGP WBBUSCLASS::longname(void) {
function GENBUS (line 1439) | GENBUS *WBBUSCLASS::create(BUSINFO *bi) {
FILE: sw/bus/wb.h
function class (line 44) | class WBBUS : public GENBUS {
function class (line 94) | class WBBUSCLASS : public BUSCLASS {
FILE: sw/businfo.cpp
function STRINGP (line 97) | STRINGP BUSINFO::name(void) {
function STRINGP (line 109) | STRINGP BUSINFO::prefix(STRINGP p) {
function STRINGP (line 126) | STRINGP BUSINFO::btype(void) {
function STRINGP (line 139) | STRINGP BUSINFO::reset_wire(void) {
function PERIPH (line 201) | PERIPH *BUSINFO::add(PERIPHP p) {
function PERIPH (line 226) | PERIPH *BUSINFO::add(MAPDHASH *phash) {
function PERIPHP (line 272) | PERIPHP BUSINFO::operator[](unsigned k) {
function STRINGP (line 472) | STRINGP BUSINFO::slave_portlist(PERIPHP p) {
function STRINGP (line 478) | STRINGP BUSINFO::slave_iansi(PERIPHP p) {
function STRINGP (line 484) | STRINGP BUSINFO::slave_oansi(PERIPHP p) {
function STRINGP (line 490) | STRINGP BUSINFO::slave_ansprefix(PERIPHP p) {
function STRINGP (line 496) | STRINGP BUSINFO::slave_ansi_portlist(PERIPHP p) {
function STRINGP (line 502) | STRINGP BUSINFO::master_portlist(BMASTERP b) {
function STRINGP (line 508) | STRINGP BUSINFO::master_ansi_portlist(BMASTERP b) {
function need_translator (line 531) | bool need_translator(BUSINFO *s, BUSINFO *m) {
function BUSINFO (line 544) | BUSINFO *BUSLIST::find_bus_of_peripheral(MAPDHASH *phash) {
function BUSINFO (line 552) | BUSINFO *find_bus_of_peripheral(MAPDHASH *phash) {
function BUSINFO (line 556) | BUSINFO *BUSLIST::find_bus(MAPDHASH *hash) {
function BUSINFO (line 569) | BUSINFO *find_bus(MAPDHASH *hash) {
function BUSINFO (line 573) | BUSINFO *BUSLIST::find_bus(STRINGP name) {
function BUSINFO (line 588) | BUSINFO *find_bus(STRINGP name) {
function BUSINFO (line 776) | BUSINFO *BUSLIST::newbus_aux(STRINGP component, MAPDHASH *bp) {
function BUSINFO (line 813) | BUSINFO *BUSLIST::newbus_aux(STRINGP component, STRINGP bn) {
function assign_addresses (line 865) | void assign_addresses(void) {
function writeout_bus_defns_v (line 877) | void writeout_bus_defns_v(FILE *fp) {
function writeout_bus_logic_v (line 924) | void writeout_bus_logic_v(FILE *fp) {
function assign_bus_slave (line 934) | void assign_bus_slave(MAPDHASH &master, MAPDHASH *bus_slave) {
function assign_bus_master (line 1007) | void assign_bus_master(MAPDHASH &master, MAPDHASH *bus_master) {
function GENBUS (line 1075) | GENBUS *BUSINFO::generator(void) {
function build_bus_list (line 1145) | void build_bus_list(MAPDHASH &master) {
function dump_global_buslist (line 1267) | void dump_global_buslist(void) {
FILE: sw/businfo.h
function class (line 61) | class BUSINFO {
function word_address_width (line 112) | int word_address_width(void) {
function byte_address_width (line 119) | int byte_address_width(void) {
function addmaster (line 133) | void addmaster(MAPDHASH *hash) {
function class (line 169) | class BUSLIST : public std::vector<BUSINFO *> {
FILE: sw/clockinfo.cpp
function CLOCKINFO (line 67) | CLOCKINFO *CLOCKINFO::new_clock(STRINGP name) {
function STRINGP (line 114) | STRINGP CLOCKINFO::reset(void) {
function add_to_clklist (line 213) | void add_to_clklist(MAPDHASH *ckmap) {
function CLOCKINFO (line 421) | CLOCKINFO *getclockinfo(STRING &clock_name) {
function CLOCKINFO (line 433) | CLOCKINFO *getclockinfo(STRINGP clock_name) {
function expand_clock (line 444) | void expand_clock(MAPDHASH &info) {
function expand_clock (line 484) | void expand_clock(MAPT &elm) {
function find_clocks (line 489) | void find_clocks(MAPDHASH &master) {
FILE: sw/clockinfo.h
function class (line 47) | class CLOCKINFO {
type std (line 90) | typedef std::vector<CLOCKINFO> CLKLIST;
FILE: sw/gather.cpp
function gather_peripherals (line 65) | void gather_peripherals(APLIST *alist, BUSINFO *bus, PLIST *plist, unsig...
function APLIST (line 95) | APLIST *gather_peripherals(BUSINFO *bus) {
function APLIST (line 103) | APLIST *full_gather(void) {
FILE: sw/gather.h
type std (line 47) | typedef std::vector<PERIPHP> APLIST;
FILE: sw/genbus.cpp
function STRINGP (line 113) | STRINGP GENBUS::name(void) {
FILE: sw/genbus.h
function class (line 65) | class GENBUS {
function class (line 113) | class BUSCLASS {
FILE: sw/ifdefs.cpp
function build_access_ifdefs_v (line 70) | void build_access_ifdefs_v(MAPDHASH &master, FILE *fp) {
FILE: sw/kveval.cpp
function get_named_kvpair (line 49) | bool get_named_kvpair(MAPSTACK &stack, MAPDHASH &here, STRING &key,
function get_named_value (line 108) | bool get_named_value(MAPSTACK &stack, MAPDHASH &here, STRING &key,
function STRINGP (line 123) | STRINGP get_named_string(MAPSTACK &stack, MAPDHASH &here, STRING &key) {
function expr_eval (line 139) | void expr_eval(MAPSTACK &stack, MAPDHASH &here, MAPDHASH &sub, MAPT &exp...
function find_any_unevaluated_sub (line 164) | bool find_any_unevaluated_sub(MAPSTACK &stack, MAPDHASH *here,
function find_any_unevaluated (line 215) | void find_any_unevaluated(MAPDHASH &info) {
function subresults_into (line 231) | bool subresults_into(MAPSTACK stack, MAPDHASH *here, STRINGP &sval) {
function STRINGP (line 325) | STRINGP genstr(STRING fmt, int val) {
function resolve_ast_expressions (line 341) | bool resolve_ast_expressions(MAPDHASH &exmap) {
function substitute_any_results_sub (line 399) | bool substitute_any_results_sub(MAPSTACK &stack, MAPDHASH *here,
function substitute_any_results (line 433) | bool substitute_any_results(MAPDHASH &info) {
function reeval (line 439) | void reeval(MAPDHASH &info) {
function reeval (line 447) | void reeval(MAPDHASH *info) {
FILE: sw/kveval.h
type std (line 48) | typedef std::vector<MAPDHASH *> MAPSTACK;
FILE: sw/legalnotice.cpp
function legal_notice (line 80) | void legal_notice(MAPDHASH &info, FILE *fp, STRING &fname,
FILE: sw/mapdhash.cpp
function MAPT (line 53) | MAPT operator+(MAPT a, MAPT b) {
function MAPT (line 129) | MAPT operator+(MAPT a, const STRING b) {
function STRING (line 154) | STRING *trim(const STRING &s) {
function splitkey (line 170) | bool splitkey(const STRING &ky, STRING &mkey, STRING &subky) {
function addtomap (line 183) | void addtomap(MAPDHASH &fm, STRING ky, STRING vl) {
function mapdump_aux (line 314) | void mapdump_aux(FILE *fp, MAPDHASH &fm, int offset) {
function mapdump (line 352) | void mapdump(FILE *fp, MAPDHASH &fm) {
function mapdump (line 359) | void mapdump(MAPDHASH &fm) {
function mapdump (line 363) | void mapdump(FILE *fp, MAPT &elm) {
function mergemaps (line 385) | void mergemaps(MAPDHASH &master, MAPDHASH &sub) {
function trimkey (line 430) | void trimkey(MAPDHASH &mp, const STRING &sky) {
function trimall (line 457) | void trimall(MAPDHASH &mp, const STRING &sky) {
function trimbykeylist (line 490) | void trimbykeylist(MAPDHASH &mp, const STRING &kylist) {
function trimbykeylist (line 505) | void trimbykeylist(MAPT &elm, const STRING &kylist) {
function cvtintbykeylist (line 516) | void cvtintbykeylist(MAPDHASH &mp, const STRING &kylist) {
function cvtintbykeylist (line 539) | void cvtintbykeylist(MAPT &elm, const STRING &kylist) {
function cvtint (line 550) | void cvtint(MAPDHASH &mp, const STRING &sky) {
function findkey_aux (line 578) | MAPDHASH::iterator findkey_aux(MAPDHASH &master, const STRING &ky, const...
function findkey (line 621) | MAPDHASH::iterator findkey(MAPDHASH &master, const STRING &ky) {
function MAPDHASH (line 626) | MAPDHASH *getmap(MAPDHASH &master, const STRING &ky) {
function MAPDHASH (line 637) | MAPDHASH *getmap(MAPDHASH *mp, const STRING &ky) {
function STRINGP (line 643) | STRINGP getstring(MAPDHASH &m) {
function STRINGP (line 656) | STRINGP getstring(MAPDHASH &master, const STRING &ky) {
function STRINGP (line 697) | STRINGP getstring(MAPDHASH *m, const STRING &ky) {
function STRINGP (line 703) | STRINGP getstring(MAPT &m, const STRING &ky) {
function setstring (line 709) | void setstring(MAPDHASH &master, const STRING &ky, STRINGP strp) {
function setstring (line 763) | void setstring(MAPDHASH &master, const STRING &ky, const STRING &str) {
function setstring (line 767) | void setstring(MAPDHASH *mp, const STRING &ky, STRINGP strp) {
function setstring (line 772) | void setstring(MAPDHASH *mp, const STRING &ky, const STRING &str) {
function setstring (line 777) | void setstring(MAPT &m, const STRING &ky, STRINGP strp) {
function getvalue (line 781) | bool getvalue(MAPDHASH &map, int &value) {
function getvalue (line 817) | bool getvalue(MAPDHASH &master, const STRING &ky, int &value) {
function getvalue (line 845) | bool getvalue(MAPDHASH *mp, const STRING &ky, int &value) {
function setvalue (line 851) | void setvalue(MAPDHASH &master, const STRING &ky, int value) {
function MAPDHASH (line 910) | MAPDHASH *copy(MAPDHASH *top) {
function flatten_maps (line 933) | void flatten_maps(MAPDHASH &node, MAPDHASH &sub, STRING &here) {
function flatten_aux (line 991) | void flatten_aux(MAPDHASH &master, MAPDHASH &sub, STRING &here) {
function flatten (line 1059) | void flatten(MAPDHASH &master) {
FILE: sw/mapdhash.h
type std (line 59) | typedef std::string *STRINGP, STRING;
type std (line 60) | typedef std::unordered_map<STRING,struct
type MAPT (line 62) | typedef struct MAPT_S {
type std (line 73) | typedef std::pair<STRING,MAPT> KEYVALUE;
FILE: sw/mlist.cpp
function STRINGP (line 46) | STRINGP BMASTER::name(void) {
function STRINGP (line 50) | STRINGP BMASTER::bus_prefix(void) {
FILE: sw/mlist.h
function class (line 55) | class BMASTER {
type BMASTER (line 66) | typedef BMASTER *BMASTERP;
type std (line 68) | typedef std::vector<BMASTERP> MLIST;
type MLIST (line 71) | typedef MLIST *MLISTP;
FILE: sw/msgs.h
function class (line 51) | class MSGS {
function close (line 57) | void close(void) { if (m_dump) ::fclose(m_dump); m_dump = NULL; }
function flush (line 58) | void flush(void) { if (m_dump) fflush(m_dump); }
function status (line 67) | int status(void) { return (m_err)?EXIT_FAILURE : EXIT_SUCCESS; }
FILE: sw/parser.cpp
function STRING (line 55) | STRING *rawline(FILE *fp) {
function STRING (line 77) | STRING *getline(FILE *fp) {
function iskeyline (line 95) | bool iskeyline(STRING &s) {
function MAPDHASH (line 101) | MAPDHASH *genhash(STRING &prefix) {
function MAPDHASH (line 113) | MAPDHASH *gensubhash(MAPDHASH *top, STRING &prefix) {
function process_keyvalue_pair (line 145) | void process_keyvalue_pair(MAPDHASH *parent, const STRING &search, STRIN...
function MAPDHASH (line 182) | MAPDHASH *parsefile(FILE *fp, const STRING &search) {
function FILE (line 285) | FILE *open_data_file(const char *fname) {
function FILE (line 295) | FILE *search_and_open(const char *fname, const STRING &search) {
function MAPDHASH (line 324) | MAPDHASH *parsefile(const char *fname, const STRING &search) {
function MAPDHASH (line 340) | MAPDHASH *parsefile(const STRING &fname, const STRING &search) {
FILE: sw/plist.cpp
function STRINGP (line 191) | STRINGP PERIPH::bus_prefix(void) {
function compare_naddr (line 245) | bool compare_naddr(PERIPHP a, PERIPHP b) {
function compare_address (line 287) | bool compare_address(PERIPHP a, PERIPHP b) {
function compare_regaddr (line 295) | bool compare_regaddr(PERIPHP a, PERIPHP b) {
FILE: sw/plist.h
function class (line 55) | class PERIPH {
type PERIPH (line 88) | typedef PERIPH *PERIPHP;
function get_address_width (line 109) | unsigned get_address_width(void) {
type PLIST (line 121) | typedef PLIST *PLISTP;
FILE: sw/predicates.cpp
function isbusmaster (line 72) | bool isbusmaster(MAPDHASH &phash) {
function issubbus (line 88) | bool issubbus(MAPDHASH &phash) {
function isarbiter (line 107) | bool isarbiter(MAPDHASH &phash) { return issubbus(phash); }
function isbusmaster (line 112) | bool isbusmaster(MAPT &pmap) {
function isperipheral (line 123) | bool isperipheral(MAPDHASH &phash) {
function isperipheral (line 128) | bool isperipheral(MAPT &pmap) {
function ispic (line 139) | bool ispic(MAPDHASH &phash) {
function ispic (line 143) | bool ispic(MAPT &pmap) {
function ismemory (line 150) | bool ismemory(MAPDHASH &phash) {
function ismemory (line 161) | bool ismemory(MAPT &pmap) {
function refbus (line 170) | bool refbus(MAPDHASH &phash) {
function refbus (line 178) | bool refbus(MAPT &pmap) {
function refclock (line 188) | bool refclock(MAPDHASH &phash) {
function refclock (line 197) | bool refclock(MAPT &pmap) {
function has_cpu (line 204) | bool has_cpu(MAPDHASH &phash) {
function read_only_option (line 221) | bool read_only_option(STRINGP op) {
function write_only_option (line 240) | bool write_only_option(STRINGP op) {
FILE: sw/subbus.h
function class (line 45) | class SUBBUS : public PERIPH {
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]
// ... and 1 more files (download for full content)
About this extraction
This page contains the full source code of the ZipCPU/autofpga GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 131 files (1.1 MB), approximately 377.1k tokens, and a symbol index with 321 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.