[ { "path": ".gitignore", "content": "# exclude all object files\nsrc/*.o\nsrc/riscvsim/*.o\nsrc/slirp/*.o\n\n# exclude all dependency files\nsrc/*.d\nsrc/riscvsim/*.d\nsrc/slirp/*.d\n\n# exclude stats, log and trace files\nsrc/*.csv\nsrc/*.log\nsrc/*.trace\n\n# exclude executables\nsrc/marss-riscv\nsrc/sim-stats-display\nsrc/build_filelist\nsrc/splitimg\n\n# exclude libraries\nsrc/*.so\nsrc/*.a\n" }, { "path": ".gitmodules", "content": "" }, { "path": "Changelog.md", "content": "# Version 4.1a\n\n - Added\n\t - Model a arbitrary fixed latency between LLC cache and Memory controller\n - Changed\n\t - For Ramulator and DRAMSim3, memory access request is split into MEM_BUS_WIDTH sized parts and latency for each part is queried\n - Fixed\n\t - Rounding mode (rm) must be calculated again before executing FP instruction during simulation\n\n# Version 4.0a\n\n - Added\n\t - Comprehensive logging support\n\t - Command-line option `-sim-file-path` to specify a top-level directory to store statistics and log files\n\t - Command-line option `-sim-file-prefix` to specify prefix appended to all simulator generated files\n\t - Command-line option `-sim-emulate-after-icount` to specify the number of instruction to simulate after starting simulation mode\n\t - [DRAMsim3](https://github.com/umd-memsys/DRAMSim3) support\n\t - [Ramulator](https://github.com/CMU-SAFARI/ramulator) support\n\t - Sample MARSS-RISCV configuration files for a 64-bit RISC-V In-order and Out-of-order SoC in [configs](./configs) folder\n\t - More performance counters to count different types of load instructions (byte, half-word, word, double-word)\n\t - Time-stamp to all the statistics files generated by the simulator\n\t - Specify latency in CPU cycles for RISC-V `SYSTEM` class instructions in the config file\n\t - Counter to track the number of CPU pipeline flushes\n\t - Counters to tracks each type of software exceptions and hardware interrupt processed during simulation\n\t - Parallel build support for Makefile\n\t - During the simulation, `mtime` is calculated using simulation clock cycles\n\t - Specify frequency for CPU and RTC device via the config file\n\t - Add option `flush_on_context_switch` in the config file to enable/disable flushing of BPU on a context switch\n\t - Start fetching the target from the next cycle on branch misprediction\n\t - Load for non-word quantities (byte and half-word) take an extra one cycle on cache-hit\n\t - Add function to invalidate entries in mem_request_queue on the miss-speculated path\n- Changed\n\t - Re-factor and modularize simulator code-base\n\t - STORE type instructions submit write-request to L1-data cache and exit memory stage in a single cycle\n\t - Delay for reading/writing page-table entries is now simulated via L1-Data cache\n\t - Print IPC for all the RISC-V CPU modes after simulation completes to the console and log file\n\t - In-order core doesn't support parallel execution in multiple functional units\n\t - Replace hot-cold LRU eviction policy with bit-PLRU eviction policy for BTB and caches\n\t - Improve the format of TinyEMU config file\n\t - Update [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)\n\t - Update README.md\n\t - Page walk delays are simulated via L1 D$\n\t - Removed [DRAMsim2](https://github.com/umd-memsys/DRAMSim2) support\n - Fixed\n\t - Memory leaks\n\t - Don't start simulating DRAM access delay until cache lookup delay is simulated\n\t - Branch entry is added to BTB, only after the branch is resolved\n\n# Version 3.1a\n\n - Added\n\t - Print TLB stats to the terminal after the simulation completes\n\t - Specify latency for each FPU ALU instruction (`fadd`, `fsub`, `fmul`, `fdiv`, `fmin`, `fmax`, `fcvt`, `cvt`, `fle`, `flt`, `feq`, `fsgnj`, `fqsrt`, `fmv`, `fclass`) via TinyEMU config file \n\t - Figure showing the high-level overview of MARSS-RISCV in README.md \n- Changed\n\t - Simplify the base DRAM model\n\t\t - All memory accesses simulate a fixed latency `mem_access_latency`\n\t\t - Any subsequent accesses to the same physical page occupies a lower delay, which is roughly 60 percent of the fixed `mem_access_latency`\n\t\t - More info [here](https://marss-riscv-docs.readthedocs.io/en/latest/)\n\t - Parallel operation of functional units can be enabled or disabled in the in-order core via TinyEMU config file\n\t - Clean exception handling code\n\t - Simulate page table entry read/write delays directly via memory controller using a configurable fixed latency `pte_rw_latency`\n\t - Don't stall the pipeline stage for the write request to complete on the memory controller\n\t - Make FPU-ALU non-pipelined\n\t - Rename `dram_dispatch_queue` to`mem_request_queue`\n\t - Update [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)\n\t - Update README.md\n\t - Update TinyEMU config file [here](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz)\n - Fixed\n\t - memory leaks\n\n# Version 3.0a\n\n - Added\n\t - Support for separate RISC-V Bios and Kernel\n\t - Command line option `flush-sim-mem` to flush simulator memory hierarchy on every fresh simulation run\n\t - Command line option `sim-trace` to generate instruction commit trace during simulation\n\t - Distinct configurable read-hit and write-hit latency for all the caches\n\t - Return address stack (RAS)\n\t - Branch prediction and speculative execution support for out of order core\n\t - Print performance counters on terminal when the simulation completes\n\t - More performance counters:\n\t\t - Instruction types\n\t\t - ecall\n\t\t - page walks for loads, stores and instructions\n\t\t - memory controller delay for data and instructions\n\t\t - hardware interrupts\n - Changed\n\t - Port to TinyEMU version `2019-12-21`\n\t - For bimodal branch predictor, store prediction bits in a separate Branch history table (BHT)\n\t - For in-order core, non-memory instructions can forward their result from MEM stage in addition to EX stage\n\t - For in-order core, relaxed interlocking on WAW data hazard\n\t - Simplified out of order core design, ROB slots are now used as physical registers along with a single rename table and a single global issue queue\n - Fixed\n\t - Correctly calculated the rounding mode for floating pointing instruction decoding\n\t - Converted `c.addiw` result buffer into `int32_t` on 64-bit simulation\n\t - Set the data type to `unint64_t` for 64-bit simulation, for the buffer which holds the memory address for atomic instructions\n\t - Issue #13 and #14 (thanks to Okhotnikov Grigory)\n\n# Version 2.0a\n\n - Added\n\t - Added [DRAMSim2](https://github.com/umd-memsys/DRAMSim2) support\n - Changed\n\t - Flush all the CPU caches and DRAM models for every new simulation run\n - Fixed\n\t - Issue #8: useless cleaning of local variables\n\n# Version 1.1a\n - Added\n\t- Add 16550A UART support (thanks to Marc Gauthier)\n\t- Add a timestamp suffix to the stats file\n - Changed\n\t- Reworked the dram latency parameters to match the Sifive HiFive U540 Board\n\t- Increased the dram dispatch queue size from 32 to 64\n - Fixed\n\t- Calculation of hardware page walk latency\n\t- Miscalculation in page fault counters\n\t- Issue #2: memory leaks in copy_file\n\t- Issue #3: 'log' instead 'log2'\n" }, { "path": "LICENSE.md", "content": "MIT License\n\nCopyright (c) 2016-2017 Fabrice Bellard\nCopyright (c) 2017-2019 Gaurav Kothari\nCopyright (c) 2018-2019 Parikshit Sarnaik\nCopyright (c) 2019 Göktürk Yüksek\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n" }, { "path": "README.md", "content": "## MARSS-RISCV: Micro-Architectural System Simulator for RISC-V\n\nMARSS-RISCV (Micro-ARchitectural System Simulator - RISCV) is an **open-source, cycle-level single-core full-system (Linux) micro-architectural simulator** for the [RISC-V](https://riscv.org/specifications/) ISA built on top of [TinyEMU emulator](https://bellard.org/tinyemu) developed by Fabrice Bellard and utilizes the configuration code, RISC-V CPU state, physical memory, MMU, and all the devices emulated by TinyEMU.\n\nIt consists of detailed cycle-level models of a generic RISC-V In-order and Out-of-order processor with a branch prediction unit, TLBs, cache-hierarchy, and a simplistic DRAM model. It comes integrated with [DRAMSim3](https://github.com/umd-memsys/DRAMSim3) and [Ramulator](https://github.com/CMU-SAFARI/ramulator), which are cycle-accurate DRAM simulators. It can simulate the entire RISC-V software stack (from the bootloader and kernel to the user level applications, including system calls) cycle-by-cycle along with the real-time I/O without any modifications and provides simulation statistics for all the RISC-V CPU privilege modes (user, supervisor, and machine). Hence, it makes MARSS-RISCV, a full system simulation framework that simulates an entire RISC-V system-on-a-chip (SoC) cycle-by-cycle.\n\nIt is currently being developed and maintained by [CAPS](https://github.com/bucaps/) (Computer Architecture and Power-Aware Systems Research Group) at the State University of New York at Binghamton. Our simulator is currently in alpha status as we are validating the cycle accuracy using various development boards. The figure below shows a high-level overview of the MARSS-RISCV simulation framework.\n\n

\n \n

\n\n## Table of contents\n- [Features](#features)\n- [Getting started with the simulator running a Linux guest](#getting-started-with-the-simulator-running-a-linux-guest)\n- [Running full system simulations](#running-full-system-simulations)\n- [Viewing live simulation stats](#viewing-live-simulation-stats)\n- [Generating simulation trace](#generating-simulation-trace)\n- [Future work](#future-work)\n- [Technical notes](#technical-notes)\n- [Authors](#authors)\n- [Acknowledgment](#acknowledgment)\n- [License](#license)\n\n## Features \n- **Full system simulator** which simulates the entire system on a cycle-by-cyle basis, including the bootloader, kernel, libraries, interrupt handlers, and user-level applications\n- **Configurable RISC-V CPU** with cycle-level, in-order and out-of-order processor models\n- **Multiple execution units** with configurable latencies (execution units can be configured to run iteratively or in a pipelined fashion)\n- **Simulates memory access delay for instructions, data and page table walk** via three direct-mapped TLBs (for code, loads and stores), two-level cache hierarchy with various allocation and miss handling policies and following DRAM memory models: A simplistic base DRAM model (which simulates a fixed delay for every main memory access), [DRAMSim3](https://github.com/umd-memsys/DRAMSim3), and [Ramulator](https://github.com/CMU-SAFARI/ramulator)\n- **Branch predictor** which supports Bi-modal and 2-level adaptive (Gshare, Gselect, GAg, GAp, PAg, PAp) predictors and a Return address stack (RAS)\n- **RISC-V ISA support** includes `RV32GC` and `RV64GC` (user-level ISA version `2.2`, privileged architecture version `1.10`)\n- **Emulated devices** include standard platform-level interrupt controller (PLIC), core local interrupter (CLINT), real-time clock device (RTC), universal asynchronous receiver/transmitter (UART), VirtIO, NIC, block device, and 9P filesystem\n- **Single JSON configuration file** to configure TinyEMU and simulator parameters, specify RISC-V BIOS and kernel individually\n- **Easy to install, use and hack** with a small codebase\n\nFor more details regarding the microarchitecture of the simulated CPU, branch predictor, memory hierarchy and simulator configuration, refer to [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)\n\n## Getting started with the simulator running a Linux guest\n\n### System requirements\n* 32-bit or 64-bit Linux machine\n* Libcurl, OpenSSL and SDL Libraries\n* Standard C and C++ compiler\n\n### Installing the dependencies\nMake sure that you have all the dependencies (`ssl`, `sdl`, and `curl` libraries) installed on the system. For Debian-based (including Ubuntu) systems, the packages are: `build-essential`, `libssl-dev`, `libsdl1.2-dev`, `libcurl4-openssl-dev`. \n```console\n$ sudo apt-get update\n$ sudo apt-get install build-essential\n$ sudo apt-get install libssl-dev\n$ sudo apt-get install libsdl1.2-dev\n$ sudo apt-get install libcurl4-openssl-dev\n```\n### Compiling the simulator\n\nFirst, clone the simulator repository:\n\n```console\n$ git clone https://github.com/bucaps/marss-riscv\n```\nThen, `cd` into the simulator source directory:\n\n```console\n$ cd marss-riscv/src/\n```\nSet the `CONFIG_XLEN` variable in the Makefile to the desired `XLEN` as required. Supported `XLEN` values are `32` and `64`. Default is `64`.\n\nThen, compile the simulator using:\n\n```console\n$ make\n```\n\n### Preparing the bootloader, kernel and userland image\nThe simplest way to start is by using a pre-built bootloader, kernel, and userland image. The pre-built 32-bit and 64-bit RISC-V userland, bootloader, and kernel are available here: [marss-riscv-images.tar.gz](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz)\n\nThe userland image needs to be decompressed before running the simulator:\n\n```console\n$ wget https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz\n$ tar -xvzf marss-riscv-images.tar.gz\n$ cd marss-riscv-images/riscv64-unknown-linux-gnu/\n$ xz -d -k -T 0 riscv64.img.xz\n```\n\nWhen decompression finishes, jump to the marss-riscv `src` folder and launch the simulator with:\n\n```console\n$ ./marss-riscv ../configs/riscv64_inorder_soc.cfg\n```\n\nSimulation and TinyEMU SoC parameters are configured using the TinyEMU JSON configuration file provided in the [configs](/configs) directory. We have provided sample configuration files for 64-bit RISC-V single-core in-order and out-of-order SoC. The following table provides a summary of various simulation related command-line options supported by MARSS-RISCV.\n\n| Options | Arguments | Description |\n|-----------------------------|--------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n| `-rw` | - | By default, the simulator will boot in `snapshot` mode, meaning it will **not** retain the file system changes after it is shut down. In order to persist the changes, pass `-rw` command-line argument to the simulator. |\n| `-simstart` | - | By default, guest boots in emulation mode, to start TinyEMU (boot kernel) in simulation mode run with `-simstart` command-line option. |\n| `-sim-stats-display` | `posix-shm-name` | Dump simulation performance stats to a shared memory location `posix-shm-name`, read by sim-stats-display tool. First, open a new terminal before executing the simulator and launch `sim-stats-display` tool with `posix-shm-name` as an argument. Then start the simulator on a different terminal with `-sim-stats-display` command-line option with `posix-shm-name` as an argument. |\n| `-sim-mem-model` | `base`, `dramsim3`, `ramulator` | To specify which memory model to use, run with command line option `-sim-mem-model` and specify either `base`, `dramsim3`, or `ramulator`. The default is `base`. For DRAMSim3 and Ramulator, the paths to `config file` can be specified in the TinyEMU config file. |\n| `-sim-flush-mem` | - | Flush simulator memory hierarchy on every new simulation run |\n| `-sim-flush-bpu` | - | Flush branch prediction unit on every new simulation run |\n| `-sim-file-path` | `directory path` | Path of the directory to store stats, log, dramsim3 stats, ramulator stats, and trace files. Default is current directory `.`, the user must create the directory before starting MARSS-RISCV. |\n| `-sim-file-prefix` | `prefix` | Prefix appended to stats, log, and trace file names. Default prefix used for all the simulator generated files is `sim`. (E.g., sim_.csv (for stats), sim.log, sim.trace) |\n| `-sim-trace` | | Generate instruction commit trace in during simulation. Trace is generated in file named `_trace.txt` |\n| `-sim-emulate-after-icount` | `icount` | Switch to emulation mode after simulating `icount` instructions every time simulation starts. |\n\n\nIt may also be desirable to increase the userland image (has roughly 200MB of available free space by default). More information about how to increase the size of the userland image is in the `readme.txt` file, which comes with the [images archive](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz).\n\nOnce the guest boots, we need to initialize the environment. Normally, this should happen automatically, but due to an unresolved bug, it needs to done explicitly:\n\n```console\n# export PYTHONPATH=/usr/lib64/python2.7/site-packages/\n# env-update\n```\n\nThe system is ready for use and has a working GCC compiler, ssh, git, and virtual network interface. However, there is no host-to-guest routing, so it is not possible to ssh into the guest.\n\nBy default, `Ctrl-C` will not kill the simulator. The command `halt` will cleanly shutdown the guest. Alternatively, pass the `-ctrlc` command-line argument to the simulator, which will allow it to be killed using `Ctrl-C`.\n\nAfter gaining access to the guest machine terminal, refer to the next section for running simulations.\n\n## Running full system simulations\n\n### Using checkpoints\nThe simulator supports two distinct custom instructions, `SIM_START()` and `SIM_STOP()`, which inform MARSS-RISCV to enable and disable simulation mode, respectively, when encountered during instruction processing. To implement these instructions, we have used two different unused registers from user mode CSR address space, `0x800`, and `0x801`. When the simulation is disabled, MARSS-RISCV runs in the emulation mode. \n\nWith these two custom instructions as checkpoints, it is possible to simulate any section in the source code. However, after inserting these markers, the source code must be recompiled inside the guest OS using the installed GCC toolchain. Alternatively, users can compile the programs on their host machine using the RISC-V toolchain and import them onto the disk image.\n\nAfter the simulator executes `SIM_STOP()` instruction, simulation mode is disabled, and all the performance stats are saved in the file `sim_stats_file` as configured in the simulator configuration file. The code below shows a simple hello world program with checkpoints instructions. \n\n```c\n/* hello_world.c */\n\n#include \n\n#define SIM_START() asm(\"csrs 0x800,zero\")\n#define SIM_STOP() asm(\"csrs 0x801,zero\")\n\nint main()\n{\n SIM_START();\n printf(\"Hello World\\n\");\n SIM_STOP();\n return 0;\n}\n```\n\n### Using the simulate script\nAlternatively, users can use the simulation script (`simulate.c`) provided [here](https://github.com/bucaps/marss-riscv-utils/blob/master/simulate.c), which forks a child process. The child enters the simulation mode and execs the command. The parent process waits for the child to complete and then switches MARSS-RISCV back to emulation mode. With this script, it is possible to simulate any program without the need to modify and recompile the source code. Since the child switches to simulation mode before calling `exec()`, `exec()` also runs in the simulation. Hence, performance statistics generated at the end of the simulation will also include stats for `exec()`.\n\n### Running benchmarks\nWe have provided a detailed step-by-step comprehensive tutorial [here](https://marss-riscv-docs.readthedocs.io/en/latest/sections/running-full-system.html) to run the benchmarks on the simulator. This tutorial configures MARSS-RISCV to simulate a simple 5-stage 32-bit in-order RISC-V processor and run [CoreMark](https://github.com/eembc/coremark), an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU).\n\n## Viewing live simulation stats\nUsers can view live simulation stats using the provided `sim-stats-display` tool. First, open a new terminal before executing the simulator and launch `sim-stats-display` with a shared memory name of the user's choice as an argument:\n\n```console\n$ ./sim-stats-display marss-riscv-test-shm\n```\nThen launch the simulator on a different terminal with `-sim-stats-display marss-riscv-test-shm` command-line option.\n\n## Generating simulation trace\nTo generate instruction, commit trace of the programs running in the simulation, run MARSS-RISCV with `-sim-trace` command-line option.\n\nSample trace generated is shown below:\n```bash\ncycle=112 pc=0x6aaaadf8 insn=0x85be863a c.mv a2,a4 mode=PRV_U\ncycle=113 pc=0x6aaaadfa insn=0x250385be c.mv a1,a5 mode=PRV_U\ncycle=115 pc=0x6aaaadfc insn=0xfa842503 lw a0,s0,-88 mode=PRV_U\n\n```\n\n## Technical notes\nThis section refers to technical notes for [TinyEMU](https://bellard.org/tinyemu). For simulator specific technical details refer: [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)\n\n### Floating point emulation\nThe floating-point emulation is bit-exact and supports all the specified instructions for 32-bit and 64-bit floating-point numbers. It uses the new SoftFP library.\n\n### HTIF console\nThe standard HTIF console uses registers at variable addresses, which are deduced by loading specific ELF symbols. TinyEMU does not rely on an ELF loader, so it is much simpler to use registers at fixed addresses (0x40008000). A small modification was made in the \"riscv-pk\" boot loader to support it. The HTIF console is only used to display boot messages and to power off the virtual system. The OS should use the VirtIO console.\n\n### Network usage\nThe easiest way is to use the \"user\" mode network driver. No specific configuration is necessary. TinyEMU also supports a \"tap\" network driver to redirect the network traffic from a VirtIO network adapter. You can look at the ``netinit.sh`` script to create the tap network interface and to redirect the virtual traffic to the Internet through a NAT. The exact configuration may depend on the Linux distribution and local firewall configuration. The TinyEMU configuration file must include:\n\n``eth0: { driver: \"tap\", ifname: \"tap0\" }``\n\nFurthermore, configure the network in the guest system with:\n```console\n$ ifconfig eth0 192.168.3.2\n$ route add -net 0.0.0.0 gw 192.168.3.1 eth0\n```\n\n### Network filesystem\nTinyEMU supports the VirtIO 9P filesystem to access local or remote filesystems. For remote filesystems, it makes HTTP requests to download the files. The protocol is compatible with the vfsync utility. In the ``mount`` command, ``/dev/rootN`` must be used as a device name where ``N`` is the index of the filesystem. When ``N=0``, it is omitted.\n\nThe build_filelist tool builds the file list from a root directory. A simple web server is enough to serve the files. The ``.preload`` file gives a list of files to preload when opening a given file.\n\n### Network block device\nTinyEMU supports an HTTP block device. The disk image is split into small files. Use the ``splitimg`` utility to generate images. The URL of the JSON blk.txt file must be provided as a disk image filename.\n\n## Authors\n* Copyright (c) 2017-2020 Gaurav Kothari {gkothar1@binghamton.edu}\n* Copyright (c) 2018-2019 Parikshit Sarnaik {psarnai1@binghamton.edu}\n\nTinyEMU:\n* Copyright (c) 2016-2019 Fabrice Bellard\n\n## Acknowledgment\n* This work was supported in part by DARPA through an award from the SSITH program. \n* Thanks to Fabrice Bellard for the development of TinyEMU. \n* We want to thank Gokturk Yuksek, Ravi Theja Gollapudi, and Kanad Ghose for assistance with the internal details of TinyEMU and the development of the MARSS-RISCV simulator.\n* Thanks to all the people working on the RISC-V project.\n* For DRAMSim3, refer [here](https://github.com/umd-memsys/DRAMSim3).\n* For Ramulator, refer [here](https://github.com/CMU-SAFARI/ramulator).\n\n## License\n* This project is licensed under the MIT License - refer to the [LICENSE.md](LICENSE.md) file for details.\n* The SLIRP library has a two clause BSD license.\n* DRAMSim3 has a MIT License.\n* Ramulator has a MIT License.\n" }, { "path": "configs/riscv64_inorder_soc.cfg", "content": "/* VM configuration file */\n{\n\tversion: 1,\n\tmachine: \"riscv64\", /* riscv32, riscv64 */\n\tmemory_size: 2048, /* MB */\n\tbios: \"riscv64-unknown-linux-gnu/bbl64.bin\",\n\tkernel: \"riscv64-unknown-linux-gnu/kernel-riscv64.bin\",\n\tcmdline: \"console=hvc0 root=/dev/vda rw\",\n\tdrive0: { file: \"riscv64-unknown-linux-gnu/riscv64.img\" },\n\teth0: { driver: \"user\" },\n\n\tcore: {\n\t\tname: \"64-bit inorder riscv CPU\",\n\t\ttype: \"incore\", /* incore, oocore */\n\t\tcpu_freq_mhz: 1000,\n\t\trtc_freq_mhz: 10,\n\n\t\tincore : {\n\t\t\tnum_cpu_stages: 5, /* 5, 6 */\n\t\t},\n\n\t\toocore: {\n\t\t\tiq_size: 16,\n\t\t\tiq_issue_ports: 3,\n\t\t\trob_size: 64,\n\t\t\trob_commit_ports:4,\n\t\t\tlsq_size: 16,\n\t\t},\n\n\t\t/* Note: Latencies for functional units, caches and memory are specified in CPU cycles */\n\t\tfunctional_units: {\n\t\t\tnum_alu_stages: 1,\n\t\t\talu_stage_latency: \"1\",\n\t\n\t\t\tnum_mul_stages: 1,\n\t\t\tmul_stage_latency: \"4\",\n\t\n\t\t\tnum_div_stages: 1,\n\t\t\tdiv_stage_latency: \"67\",\n\t\n\t\t\t/* Note: This will create a pipelined FP-FMA unit with 4 stages with a\n\t\t\t * latency of 1 CPU cycle(s) per stage */\n\t\t\tnum_fpu_fma_stages: 4,\n\t\t\tfpu_fma_stage_latency: \"1,1,1,1\",\n\t\n\t\t\t/* Note: FP-ALU is non-pipelined */\n\t\t\tfpu_alu_stage_latency: {\n\t\t\t\tfadd: 2,\n\t\t\t\tfsub: 2,\n\t\t\t\tfmul: 2,\n\t\t\t\tfdiv: 8,\n\t\t\t\tfsqrt: 8,\n\t\t\t\tfsgnj: 2,\n\t\t\t\tfmin: 4,\n\t\t\t\tfmax: 4,\n\t\t\t\tfeq: 2,\n\t\t\t\tflt: 2,\n\t\t\t\tfle: 2,\n\t\t\t\tcvt: 2,\n\t\t\t\tfcvt: 2,\n\t\t\t\tfmv: 2,\n\t\t\t\tfclass: 1,\n\t\t\t},\n\n\t\t\t/* Latency for RISC-V SYSTEM opcode instructions (includes CSR and privileged instructions)*/\n\t\t\tsystem_insn_latency: 3,\n\t\t},\n\t\n\t\tbpu: {\n\t\t\tenable: \"true\", /* true, false */\n\t\t\tflush_on_context_switch: \"false\", /* true, false */\n\n\t\t\tbtb: {\n\t\t\t\tsize: 32,\n\t\t\t\tways: 2,\n\t\t\t\teviction_policy: \"lru\", /* lru, random */\n\t\t\t},\n\t\n\t\t\tbpu_type: \"bimodal\", /* bimodal, adaptive */\n\t\n\t\t\tbimodal: {\n\t\t\t\tbht_size: 256,\n\t\t\t},\n\t\n\t\t\tadaptive: {\n\t\t\t\tght_size: 1,\n\t\t\t\tpht_size: 1,\n\t\t\t\thistory_bits: 2,\n\t\t\t\taliasing_func_type: \"xor\", /* xor, and, none */\n\n\t\t\t /* Given config for adaptive predictor will create a Gshare predictor:\n\t\t\t\t*\t1) global history table consisting of one entry, entry includes a 2-bit history register\n\t\t\t\t*\t2) pattern history table consisting of one entry, entry includes an array of 4 saturating counters\n\t\t\t\t* \t3) value of history register will be `xor` ed with branch PC to index into the array of saturating counters\n\t\t\t\t*/\n\t\t\t},\n\t\n\t\t\tras_size: 6, /* value 0 disables RAS */\n\t\t},\n\t\n\t\tcaches: {\n\t\t\tenable_l1_caches: \"true\", /* true, false */\n\t\t\tallocate_on_write_miss: \"true\", /* true, false */\n\t\t\twrite_policy: \"writeback\", /* writeback, writethrough */\n\t\t\tline_size: 64, /* Bytes */\n\t\n\t\t\ticache: {\n\t\t\t\tsize: 32, /* KB */\n\t\t\t\tways: 4,\n\t\t\t\tlatency: 1,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\t\n\t\t\tdcache: {\n\t\t\t\tsize: 32, /* KB */\n\t\t\t\tways: 8,\n\t\t\t\tlatency: 1,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\t\n\t\t\tl2_shared_cache: {\n\t\t\t\tenable: \"true\",\n\t\t\t\tsize: 256, /* KB */\n\t\t\t\tways: 16,\n\t\t\t\tlatency: 5,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\t\t},\n\t},\n\n\tmemory: {\n\t\ttlb_size: 32,\n\n\t\t/* Memory controller burst-length in bytes */ \n\t\t/* Note: This is automatically set to cache line size if caches are enabled */\n\t\tburst_length: 64, /* Bytes */\n\n\t\tbase_dram_model: {\n\t\t\tmem_access_latency: 50,\n\t\t},\n\n\t\tdramsim3: {\n\t\t\tconfig_file: \"DRAMsim3/configs/DDR4_4Gb_x16_2400.ini\",\n\t\t},\n\n\t\tramulator: {\n\t\t\tconfig_file: \"ramulator/configs/DDR4-config.cfg\",\n\t\t},\n\t},\n}" }, { "path": "configs/riscv64_outoforder_soc.cfg", "content": "/* VM configuration file */\n{\n\tversion: 1,\n\tmachine: \"riscv64\", /* riscv32, riscv64 */\n\tmemory_size: 2048, /* MB */\n\tbios: \"riscv64-unknown-linux-gnu/bbl64.bin\",\n\tkernel: \"riscv64-unknown-linux-gnu/kernel-riscv64.bin\",\n\tcmdline: \"console=hvc0 root=/dev/vda rw\",\n\tdrive0: { file: \"riscv64-unknown-linux-gnu/riscv64.img\" },\n\teth0: { driver: \"user\" },\n\n\tcore: {\n\t\tname: \"64-bit out-of-order riscv CPU\",\n\t\ttype: \"oocore\", /* incore, oocore */\n\t\tcpu_freq_mhz: 1000,\n\t\trtc_freq_mhz: 10,\n\n\t\tincore : {\n\t\t\tnum_cpu_stages: 5, /* 5, 6 */\n\t\t},\n\n\t\toocore: {\n\t\t\tiq_size: 16,\n\t\t\tiq_issue_ports: 3,\n\t\t\trob_size: 64,\n\t\t\trob_commit_ports:4,\n\t\t\tlsq_size: 16,\n\t\t},\n\n\t\t/* Note: Latencies for functional units, caches and memory are specified in CPU cycles */\n\t\tfunctional_units: {\n\t\t\tnum_alu_stages: 1,\n\t\t\talu_stage_latency: \"1\",\n\n\t\t\tnum_mul_stages: 1,\n\t\t\tmul_stage_latency: \"4\",\n\n\t\t\tnum_div_stages: 1,\n\t\t\tdiv_stage_latency: \"67\",\n\n\t\t\t/* Note: This will create a pipelined FP-FMA unit with 4 stages with a\n\t\t\t * latency of 1 CPU cycle(s) per stage */\n\t\t\tnum_fpu_fma_stages: 4,\n\t\t\tfpu_fma_stage_latency: \"1,1,1,1\",\n\n\t\t\t/* Note: FP-ALU is non-pipelined */\n\t\t\tfpu_alu_stage_latency: {\n\t\t\t\tfadd: 2,\n\t\t\t\tfsub: 2,\n\t\t\t\tfmul: 2,\n\t\t\t\tfdiv: 8,\n\t\t\t\tfsqrt: 8,\n\t\t\t\tfsgnj: 2,\n\t\t\t\tfmin: 4,\n\t\t\t\tfmax: 4,\n\t\t\t\tfeq: 2,\n\t\t\t\tflt: 2,\n\t\t\t\tfle: 2,\n\t\t\t\tcvt: 2,\n\t\t\t\tfcvt: 2,\n\t\t\t\tfmv: 2,\n\t\t\t\tfclass: 1,\n\t\t\t},\n\n\t\t\t/* Latency for RISC-V SYSTEM opcode instructions (includes CSR and privileged instructions)*/\n\t\t\tsystem_insn_latency: 3,\n\t\t},\n\n\t\tbpu: {\n\t\t\tenable: \"true\", /* true, false */\n\t\t\tflush_on_context_switch: \"false\", /* true, false */\n\n\t\t\tbtb: {\n\t\t\t\tsize: 32,\n\t\t\t\tways: 2,\n\t\t\t\teviction_policy: \"lru\", /* lru, random */\n\t\t\t},\n\n\t\t\tbpu_type: \"bimodal\", /* bimodal, adaptive */\n\n\t\t\tbimodal: {\n\t\t\t\tbht_size: 256,\n\t\t\t},\n\n\t\t\tadaptive: {\n\t\t\t\tght_size: 1,\n\t\t\t\tpht_size: 1,\n\t\t\t\thistory_bits: 2,\n\t\t\t\taliasing_func_type: \"xor\", /* xor, and, none */\n\n\t\t\t /* Given config for adaptive predictor will create a Gshare predictor:\n\t\t\t\t*\t1) global history table consisting of one entry, entry includes a 2-bit history register\n\t\t\t\t*\t2) pattern history table consisting of one entry, entry includes an array of 4 saturating counters\n\t\t\t\t* \t3) value of history register will be `xor` ed with branch PC to index into the array of saturating counters\n\t\t\t\t*/\n\t\t\t},\n\n\t\t\tras_size: 6, /* value 0 disables RAS */\n\t\t},\n\n\t\tcaches: {\n\t\t\tenable_l1_caches: \"true\", /* true, false */\n\t\t\tallocate_on_write_miss: \"true\", /* true, false */\n\t\t\twrite_policy: \"writeback\", /* writeback, writethrough */\n\t\t\tline_size: 64, /* Bytes */\n\n\t\t\ticache: {\n\t\t\t\tsize: 32, /* KB */\n\t\t\t\tways: 4,\n\t\t\t\tlatency: 1,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\n\t\t\tdcache: {\n\t\t\t\tsize: 32, /* KB */\n\t\t\t\tways: 8,\n\t\t\t\tlatency: 1,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\n\t\t\tl2_shared_cache: {\n\t\t\t\tenable: \"true\",\n\t\t\t\tsize: 256, /* KB */\n\t\t\t\tways: 16,\n\t\t\t\tlatency: 5,\n\t\t\t\teviction: \"lru\", /* lru, random */\n\t\t\t},\n\t\t},\n\t},\n\n\tmemory: {\n\t\ttlb_size: 32,\n\n\t\t/* Memory controller burst-length in bytes */ \n\t\t/* Note: This is automatically set to cache line size if caches are enabled */\n\t\tburst_length: 64, /* Bytes */\n\n\t\tbase_dram_model: {\n\t\t\tmem_access_latency: 50,\n\t\t},\n\n\t\tdramsim3: {\n\t\t\tconfig_file: \"DRAMsim3/configs/DDR4_4Gb_x16_2400.ini\",\n\t\t},\n\n\t\tramulator: {\n\t\t\tconfig_file: \"ramulator/configs/DDR4-config.cfg\",\n\t\t},\n\t},\n}" }, { "path": "src/DRAMsim3/.clang-format", "content": "---\nLanguage: Cpp\n# BasedOnStyle: Google\nAccessModifierOffset: -1\nAlignAfterOpenBracket: Align\nAlignConsecutiveAssignments: false\nAlignConsecutiveDeclarations: false\nAlignEscapedNewlines: Left\nAlignOperands: true\nAlignTrailingComments: true\nAllowAllParametersOfDeclarationOnNextLine: true\nAllowShortBlocksOnASingleLine: false\nAllowShortCaseLabelsOnASingleLine: false\nAllowShortFunctionsOnASingleLine: All\nAllowShortIfStatementsOnASingleLine: true\nAllowShortLoopsOnASingleLine: true\nAlwaysBreakAfterDefinitionReturnType: None\nAlwaysBreakAfterReturnType: None\nAlwaysBreakBeforeMultilineStrings: true\nAlwaysBreakTemplateDeclarations: true\nBinPackArguments: true\nBinPackParameters: true\nBraceWrapping: \n AfterClass: false\n AfterControlStatement: false\n AfterEnum: false\n AfterFunction: false\n AfterNamespace: false\n AfterObjCDeclaration: false\n AfterStruct: false\n AfterUnion: false\n AfterExternBlock: false\n BeforeCatch: false\n BeforeElse: false\n IndentBraces: false\n SplitEmptyFunction: true\n SplitEmptyRecord: true\n SplitEmptyNamespace: true\nBreakBeforeBinaryOperators: None\nBreakBeforeBraces: Attach\nBreakBeforeInheritanceComma: false\nBreakBeforeTernaryOperators: true\nBreakConstructorInitializersBeforeComma: false\nBreakConstructorInitializers: BeforeColon\nBreakAfterJavaFieldAnnotations: false\nBreakStringLiterals: true\nColumnLimit: 80\nCommentPragmas: '^ IWYU pragma:'\nCompactNamespaces: false\nConstructorInitializerAllOnOneLineOrOnePerLine: true\nConstructorInitializerIndentWidth: 4\nContinuationIndentWidth: 4\nCpp11BracedListStyle: true\nDerivePointerAlignment: true\nDisableFormat: false\nExperimentalAutoDetectBinPacking: false\nFixNamespaceComments: true\nForEachMacros: \n - foreach\n - Q_FOREACH\n - BOOST_FOREACH\nIncludeBlocks: Preserve\nIncludeCategories: \n - Regex: '^'\n Priority: 2\n - Regex: '^<.*\\.h>'\n Priority: 1\n - Regex: '^<.*'\n Priority: 2\n - Regex: '.*'\n Priority: 3\nIncludeIsMainRegex: '([-_](test|unittest))?$'\nIndentCaseLabels: true\nIndentPPDirectives: None\nIndentWidth: 4\nIndentWrappedFunctionNames: false\nJavaScriptQuotes: Leave\nJavaScriptWrapImports: true\nKeepEmptyLinesAtTheStartOfBlocks: false\nMacroBlockBegin: ''\nMacroBlockEnd: ''\nMaxEmptyLinesToKeep: 1\nNamespaceIndentation: None\nObjCBlockIndentWidth: 2\nObjCSpaceAfterProperty: false\nObjCSpaceBeforeProtocolList: false\nPenaltyBreakAssignment: 2\nPenaltyBreakBeforeFirstCallParameter: 1\nPenaltyBreakComment: 300\nPenaltyBreakFirstLessLess: 120\nPenaltyBreakString: 1000\nPenaltyExcessCharacter: 1000000\nPenaltyReturnTypeOnItsOwnLine: 200\nPointerAlignment: Left\nRawStringFormats: \n - Delimiter: pb\n Language: TextProto\n BasedOnStyle: google\nReflowComments: true\nSortIncludes: true\nSortUsingDeclarations: true\nSpaceAfterCStyleCast: false\nSpaceAfterTemplateKeyword: true\nSpaceBeforeAssignmentOperators: true\nSpaceBeforeParens: ControlStatements\nSpaceInEmptyParentheses: false\nSpacesBeforeTrailingComments: 2\nSpacesInAngles: false\nSpacesInContainerLiterals: true\nSpacesInCStyleCastParentheses: false\nSpacesInParentheses: false\nSpacesInSquareBrackets: false\nStandard: Auto\nTabWidth: 8\nUseTab: Never\n...\n\n" }, { "path": "src/DRAMsim3/.gitignore", "content": "# project files\nbuild/\ndebug_build/\ndata/\next/SuperLU_MT_3.1/\nobj\ndramsim3\ndramsim3test\ndramsim3main\n*.log\nrelease\n.idea\n*.pyc\n*.vh\n.vs/\n\n# Compiled Object files\n*.slo\n*.lo\n*.o\n*.obj\n\n# Precompiled Headers\n*.gch\n*.pch\n\n# Compiled Dynamic libraries\n*.so\n*.dylib\n*.dll\n\n# Fortran module files\n*.mod\n*.smod\n\n# Compiled Static libraries\n*.lai\n*.la\n*.a\n*.lib\n\n# Executables\n*.exe\n*.out\n*.app\n\n# IDEs / Editors\n.vscode/\n" }, { "path": "src/DRAMsim3/.gitmodules", "content": "[submodule \"ext/SuperLU_MT_3.1\"]\n\tpath = ext/SuperLU_MT_3.1\n\turl = https://github.com/umd-memsys/SuperLU_MT_3.1.git\n\tignore = dirty\n" }, { "path": "src/DRAMsim3/.travis.yml", "content": "dist: trusty\n#sudo: required\nsudo: false\n\nlanguage: cpp\nwarnings_are_errors: true\n\ncompiler:\n# - gcc\n - clang\n\n#addons:\n# apt:\n# packages:\n# - gcc-4.9\n# - clang-3.5\n# - cmake\n\nscript:\n - mkdir build\n - cd build\n - cmake ..\n - make -j4\n" }, { "path": "src/DRAMsim3/CMakeLists.txt", "content": "cmake_minimum_required(VERSION 3.0.0)\nproject(dramsim3)\n\nset(default_build_type \"Release\")\nif(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)\n message(STATUS \"Setting build type to '${default_build_type}' as none was specified.\")\n set(CMAKE_BUILD_TYPE \"${default_build_type}\" CACHE\n STRING \"Choose the type of build.\" FORCE)\n # Set the possible values of build type for cmake-gui\n set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS\n \"Debug\" \"Release\" \"MinSizeRel\" \"RelWithDebInfo\")\nendif()\n\nadd_library(inih INTERFACE)\ntarget_include_directories(inih INTERFACE ext/headers)\n\nadd_library(format INTERFACE)\ntarget_include_directories(format INTERFACE ext/fmt/include)\ntarget_compile_definitions(format INTERFACE FMT_HEADER_ONLY=1)\n\n# argparsing library, only used in main program not the library\nadd_library(args INTERFACE)\ntarget_include_directories(args INTERFACE ext/headers)\n\nadd_library(json INTERFACE)\ntarget_include_directories(json INTERFACE ext/headers)\n\n# Main DRAMSim Lib\nadd_library(dramsim3 SHARED\n src/bankstate.cc\n src/channel_state.cc\n src/command_queue.cc\n src/common.cc\n src/configuration.cc\n src/controller.cc\n src/dram_system.cc\n src/hmc.cc\n src/refresh.cc\n src/simple_stats.cc\n src/timing.cc\n src/memory_system.cc\n)\n\nif (THERMAL)\n # dependency check\n # sudo apt-get install libatlas-base-dev on ubuntu\n find_package(BLAS REQUIRED)\n find_package(OpenMP REQUIRED)\n # YOU need to build superlu on your own. Do the following:\n # git submodule update --init\n # cd ext/SuperLU_MT_3.1 && make lib\n find_library(SUPERLU\n NAME superlu_mt_OPENMP libsuperlu_mt_OPENMP\n HINTS ${PROJECT_SOURCE_DIR}/ext/SuperLU_MT_3.1/lib/\n )\n\n target_link_libraries(dramsim3\n PRIVATE ${SUPERLU} f77blas atlas m ${OpenMP_C_FLAGS}\n )\n target_sources(dramsim3\n PRIVATE src/thermal.cc src/sp_ienv.c src/thermal_solver.c\n )\n target_compile_options(dramsim3 PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS})\n\n add_executable(thermalreplay src/thermal_replay.cc)\n target_link_libraries(thermalreplay dramsim3 inih)\n target_compile_options(thermalreplay PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS})\nendif (THERMAL)\n\nif (CMD_TRACE)\n target_compile_options(dramsim3 PRIVATE -DCMD_TRACE)\nendif (CMD_TRACE)\n\nif (ADDR_TRACE)\n target_compile_options(dramsim3 PRIVATE -DADDR_TRACE)\nendif (ADDR_TRACE)\n\n\ntarget_include_directories(dramsim3 INTERFACE src)\ntarget_compile_options(dramsim3 PRIVATE -Wall)\ntarget_link_libraries(dramsim3 PRIVATE inih format)\nset_target_properties(dramsim3 PROPERTIES\n LIBRARY_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR}\n CXX_STANDARD 11\n CXX_STANDARD_REQUIRED YES\n CXX_EXTENSIONS NO\n)\n\n# trace CPU, .etc\nadd_executable(dramsim3main src/main.cc src/cpu.cc)\ntarget_link_libraries(dramsim3main PRIVATE dramsim3 args)\ntarget_compile_options(dramsim3main PRIVATE)\nset_target_properties(dramsim3main PROPERTIES\n CXX_STANDARD 11\n CXX_STANDARD_REQUIRED YES\n CXX_EXTENSIONS NO\n)\n\n# Unit testing\nadd_library(Catch INTERFACE)\ntarget_include_directories(Catch INTERFACE ext/headers)\n\nadd_executable(dramsim3test EXCLUDE_FROM_ALL\n tests/test_config.cc\n tests/test_dramsys.cc\n tests/test_hmcsys.cc # IDK somehow this can literally crush your computer\n)\ntarget_link_libraries(dramsim3test Catch dramsim3)\ntarget_include_directories(dramsim3test PRIVATE src/)\n\n# We have to use this custome command because there's a bug in cmake\n# that if you do `make test` it doesn't build your updated test files\n# so we're stucking with `make dramsim3test` for now\nadd_custom_command(\n TARGET dramsim3test POST_BUILD\n COMMAND dramsim3test\n WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}\n DEPENDS dramsim3test dramsim3\n)\n" }, { "path": "src/DRAMsim3/LICENSE", "content": "Copyright (c) 2019, University of Maryland Memory-Systems Research\n\nPermission is hereby granted, free of charge, to any person obtaining a\ncopy of this software and associated documentation files (the\n\"Software\"), to deal in the Software without restriction, including\nwithout limitation the rights to use, copy, modify, merge, publish,\ndistribute, sublicense, and/or sell copies of the Software, and to\npermit persons to whom the Software is furnished to do so, subject to\nthe following conditions:\n\nThe above copyright notice and this permission notice shall be included\nin all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\nOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\nMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\nIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\nCLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\nTORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\nSOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE." }, { "path": "src/DRAMsim3/Makefile", "content": "# ONLY use this makefile if you do NOT have a cmake 3.0+ version\n\nCC=gcc\nCXX=g++\n\nFMT_LIB_DIR=ext/fmt/include\nINI_LIB_DIR=ext/headers\nJSON_LIB_DIR=ext/headers\nARGS_LIB_DIR=ext/headers\n\nINC=-Isrc/ -I$(FMT_LIB_DIR) -I$(INI_LIB_DIR) -I$(ARGS_LIB_DIR) -I$(JSON_LIB_DIR)\nCXXFLAGS=-Wall -O2 -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1\n\nLIB_NAME=libdramsim3.so\nEXE_NAME=dramsim3main.out\nSTATIC_LIB_NAME=libdramsim3.a\n\nSRCS = src/bankstate.cc src/channel_state.cc src/command_queue.cc src/common.cc \\\n\t\tsrc/configuration.cc src/controller.cc src/dram_system.cc src/hmc.cc \\\n\t\tsrc/memory_system.cc src/refresh.cc src/simple_stats.cc src/timing.cc\n\nEXE_SRCS = src/cpu.cc src/main.cc\n\nOBJECTS = $(addsuffix .o, $(basename $(SRCS)))\nEXE_OBJS = $(addsuffix .o, $(basename $(EXE_SRCS)))\nEXE_OBJS := $(EXE_OBJS) $(OBJECTS)\n\n\nall: $(LIB_NAME) $(EXE_NAME)\n\n$(EXE_NAME): $(EXE_OBJS)\n\t$(CXX) $(CXXFLAGS) -o $@ $^\n\n$(LIB_NAME): $(OBJECTS)\n\t$(CXX) -g -shared -Wl,-soname,$@ -o $@ $^\n\n$(STATIC_LIB_NAME): $(OBJECTS)\n\t$(AR) rcs $@ $(OBJECTS)\n\n%.o : %.cc\n\t$(CXX) $(CXXFLAGS) -o $@ -c $<\n\n%.o : %.c\n\t$(CC) -fPIC -O2 -o $@ -c $<\n\nclean:\n\t-rm -f $(EXE_OBJS) $(LIB_NAME) $(EXE_NAME)" }, { "path": "src/DRAMsim3/README.md", "content": "[![Build Status](https://travis-ci.com/umd-memsys/DRAMsim3.svg?branch=master)](https://travis-ci.com/umd-memsys/DRAMsim3)\n\n# About DRAMsim3\n\nDRAMsim3 models the timing paramaters and memory controller behavior for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected oriented model that includes a parameterized DRAM bank model, DRAM controllers, command queues and system-level interfaces to interact with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed to be accurate, portable and parallel.\n \nIf you use this simulator in your work, please consider cite:\n\n[1] S. Li, Z. Yang, D. Reddy, A. Srivastava and B. Jacob, \"DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator,\" in IEEE Computer Architecture Letters. [Link](https://ieeexplore.ieee.org/document/8999595)\n\nSee [Related Work](#related-work) for more work done with this simulator.\n\n\n## Building and running the simulator\n\nThis simulator by default uses a CMake based build system.\nThe advantage in using a CMake based build system is portability and dependency management.\nWe require CMake 3.0+ to build this simulator.\nIf `cmake-3.0` is not available,\nwe also supply a Makefile to build the most basic version of the simulator.\n\n### Building\n\nDoing out of source builds with CMake is recommended to avoid the build files cluttering the main directory.\n\n```bash\n# cmake out of source build\nmkdir build\ncd build\ncmake ..\n\n# Build dramsim3 library and executables\nmake -j4\n\n# Alternatively, build with thermal module enabled\ncmake .. -DTHERMAL=1\n\n```\n\nThe build process creates `dramsim3main` and executables in the `build` directory.\nBy default, it also creates `libdramsim3.so` shared library in the project root directory.\n\n### Running\n\n```bash\n# help\n./build/dramsim3main -h\n\n# Running random stream with a config file\n./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini --stream random -c 100000 \n\n# Running a trace file\n./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100000 -t sample_trace.txt\n\n# Running with gem5\n--mem-type=dramsim3 --dramsim3-ini=configs/DDR4_4Gb_x4_2133.ini\n\n```\n\nThe output can be directed to another directory by `-o` option\nor can be configured in the config file.\nYou can control the verbosity in the config file as well.\n\n### Output Visualization\n\n`scripts/plot_stats.py` can visualize some of the output (requires `matplotlib`):\n\n```bash\n# generate histograms from overall output\npython3 scripts/plot_stats dramsim3.json\n\n# or\n# generate time series for a variety stats from epoch outputs\npython3 scripts/plot_stats dramsim3epoch.json\n```\n\nCurrently stats from all channels are squashed together for cleaner plotting.\n\n### Integration with other simulators\n\n**Gem5** integration: works with a forked Gem5 version, see https://github.com/umd-memsys/gem5 at `dramsim3` branch for reference.\n\n**SST** integration: see http://git.ece.umd.edu/shangli/sst-elements/tree/dramsim3 for reference. We will try to merge to official SST repo.\n\n**ZSim** integration: see http://git.ece.umd.edu/shangli/zsim/tree/master for reference.\n\n## Simulator Design\n\n### Code Structure\n\n```\n├── configs # Configs of various protocols that describe timing constraints and power consumption.\n├── ext # \n├── scripts # Tools and utilities\n├── src # DRAMsim3 source files\n├── tests # Tests of each model, includes a short example trace\n├── CMakeLists.txt\n├── Makefile\n├── LICENSE\n└── README.md\n\n├── src \n bankstate.cc: Records and manages DRAM bank timings and states which is modeled as a state machine.\n channelstate.cc: Records and manages channel timings and states.\n command_queue.cc: Maintains per-bank or per-rank FIFO queueing structures, determine which commands in the queues can be issued in this cycle.\n configuration.cc: Initiates, manages system and DRAM parameters, including protocol, DRAM timings, address mapping policy and power parameters.\n controller.cc: Maintains the per-channel controller, which manages a queue of pending memory transactions and issues corresponding DRAM commands, \n follows FR-FCFS policy.\n cpu.cc: Implements 3 types of simple CPU: \n 1. Random, can handle random CPU requests at full speed, the entire parallelism of DRAM protocol can be exploited without limits from address mapping and scheduling pocilies. \n 2. Stream, provides a streaming prototype that is able to provide enough buffer hits.\n 3. Trace-based, consumes traces of workloads, feed the fetched transactions into the memory system.\n dram_system.cc: Initiates JEDEC or ideal DRAM system, registers the supplied callback function to let the front end driver know that the request is finished. \n hmc.cc: Implements HMC system and interface, HMC requests are translates to DRAM requests here and a crossbar interconnect between the high-speed links and the memory controllers is modeled.\n main.cc: Handles the main program loop that reads in simulation arguments, DRAM configurations and tick cycle forward.\n memory_system.cc: A wrapper of dram_system and hmc.\n refresh.cc: Raises refresh request based on per-rank refresh or per-bank refresh.\n timing.cc: Initiate timing constraints.\n```\n\n## Experiments\n\n### Verilog Validation\n\nFirst we generate a DRAM command trace.\nThere is a `CMD_TRACE` macro and by default it's disabled.\nUse `cmake .. -DCMD_TRACE=1` to enable the command trace output build and then\nwhenever a simulation is performed the command trace file will be generated.\n\nNext, `scripts/validation.py` helps generate a Verilog workbench for Micron's Verilog model\nfrom the command trace file.\nCurrently DDR3, DDR4, and LPDDR configs are supported by this script.\n\nRun\n\n```bash\n./script/validataion.py DDR4.ini cmd.trace\n```\n\nTo generage Verilog workbench.\nOur workbench format is compatible with ModelSim Verilog simulator,\nother Verilog simulators may require a slightly different format.\n\n\n## Related Work\n\n[1] Li, S., Yang, Z., Reddy D., Srivastava, A. and Jacob, B., (2020) DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator, IEEE Computer Architecture Letters.\n\n[2] Jagasivamani, M., Walden, C., Singh, D., Kang, L., Li, S., Asnaashari, M., ... & Yeung, D. (2019). Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die. IEEE Micro, 39(6), 64-72.\n\n[3] Li, S., Reddy, D., & Jacob, B. (2018, October). A performance & power comparison of modern high-speed DRAM architectures. In Proceedings of the International Symposium on Memory Systems (pp. 341-353).\n\n[4] Li, S., Verdejo, R. S., Radojković, P., & Jacob, B. (2019, September). Rethinking cycle accurate DRAM simulation. In Proceedings of the International Symposium on Memory Systems (pp. 184-191).\n\n[5] Li, S., & Jacob, B. (2019, September). Statistical DRAM modeling. In Proceedings of the International Symposium on Memory Systems (pp. 521-530).\n\n[6] Li, S. (2019). Scalable and Accurate Memory System Simulation (Doctoral dissertation).\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_1Gb_x8_1333.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 16384\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.5\nAL = 0\nCL = 10\nCWL = 7\ntRCD = 10\ntRP = 10\ntRAS = 24\ntRFC = 74\ntREFI = 5200\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntWTR_S = 5\ntFAW = 20\ntWR = 10\ntCCD_S = 4\ntRTP = 5\ntCKE = 4\ntCKESR = 1\ntXS = 81\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 33\nIDD2P = 12\nIDD2N = 17\nIDD3P = 14\nIDD3N = 23\nIDD4W = 77\nIDD4R = 72\nIDD5AB = 155\nIDD6x = 12\n\n[system]\nchannel_size = 2048\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\ntrans_queue_size = 32\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\n\n[other]\nepoch_period = 666666\noutput_level = 1\n\n[thermal]\nloc_mapping = 30,30,30,29:27,26:13,12:3\npower_epoch_period = 10000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x16_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 208\ntRFC2 = 208\ntRFC4 = 208\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 5\ntRRD_L = 5\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 32\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 216\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 66\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 32\nIDD3P = 38\nIDD3N = 47\nIDD4W = 171\nIDD4R = 235\nIDD5AB = 235\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x16_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 243\ntRFC4 = 243\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 33\ntWR = 15\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 73\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 35\nIDD3P = 41\nIDD3N = 49\nIDD4W = 190\nIDD4R = 252\nIDD5AB = 242\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x4_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 2048\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 208\ntRFC2 = 208\ntRFC4 = 208\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 5\ntRRD_L = 5\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 24\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 216\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 55\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 32\nIDD3P = 38\nIDD3N = 38\nIDD4W = 118\nIDD4R = 147\nIDD5AB = 235\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x4_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 2048\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 243\ntRFC4 = 243\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 5\ntRRD_L = 5\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 26\ntWR = 15\ntWR2 = 15\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 62\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 35\nIDD3P = 41\nIDD3N = 41\nIDD4W = 133\nIDD4R = 164\nIDD5AB = 242\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x8_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 208\ntRFC2 = 208\ntRFC4 = 208\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 5\ntRRD_L = 5\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 24\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 216\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 55\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 32\nIDD3P = 38\nIDD3N = 38\nIDD4W = 125\nIDD4R = 157\nIDD5AB = 235\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_4Gb_x8_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 243\ntRFC4 = 243\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 5\ntRRD_L = 5\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 26\ntWR = 15\ntWR2 = 15\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 62\nIPP0 = 0.0\nIDD2P = 18\nIDD2N = 35\nIDD3P = 41\nIDD3N = 41\nIDD4W = 141\nIDD4R = 174\nIDD5AB = 242\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x16_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 280\ntRFC2 = 280\ntRFC4 = 280\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 32\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 288\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 67\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 36\nIDD3P = 36\nIDD3N = 51\nIDD4W = 185\nIDD4R = 185\nIDD5AB = 270\nIDD6x = 24\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x16_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 328\ntRFC2 = 328\ntRFC4 = 328\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 33\ntWR = 15\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 338\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 69\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 38\nIDD3P = 38\nIDD3N = 53\nIDD4W = 195\nIDD4R = 195\nIDD5AB = 275\nIDD6x = 24\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x4_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 4096\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 280\ntRFC2 = 280\ntRFC4 = 280\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 32\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 288\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 67\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 36\nIDD3P = 36\nIDD3N = 51\nIDD4W = 125\nIDD4R = 125\nIDD5AB = 245\nIDD6x = 24\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x4_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 4096\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 328\ntRFC2 = 328\ntRFC4 = 328\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 33\ntWR = 15\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 338\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 69\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 38\nIDD3P = 38\nIDD3N = 53\nIDD4W = 135\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 24\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x8_1600.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 2048\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 11\nCWL = 8\ntRCD = 11\ntRP = 11\ntRAS = 28\ntRFC = 280\ntRFC2 = 280\ntRFC4 = 280\nREFI = 6240\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 32\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntCKESR = 5\ntXS = 288\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 67\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 36\nIDD3P = 36\nIDD3N = 51\nIDD4W = 125\nIDD4R = 125\nIDD5AB = 245\nIDD6x = 24\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR3_8Gb_x8_1866.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 2048\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 9\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 328\ntRFC2 = 328\ntRFC4 = 328\nREFI = 7290\ntRPRE = 0\ntWPRE = 0\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 33\ntWR = 15\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 6\ntXS = 338\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 69\nIPP0 = 0.0\nIDD2P = 11\nIDD2N = 38\nIDD3P = 38\nIDD3N = 53\nIDD4W = 135\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 24\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 150\ntRFC4 = 103\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 5\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 28\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.6\nIDD2P = 27\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 220\nIDD4R = 180\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 6\ntRRD_L = 7\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 32\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.6\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 250\nIDD4R = 195\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 6\ntRRD_L = 7\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 32\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.6\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 250\nIDD4R = 195\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 8\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 36\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.6\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 285\nIDD4R = 205\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 0\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 8\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 36\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.6\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 285\nIDD4R = 205\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 9\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 40\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 70\nIPP0 = 3.6\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 310\nIDD4R = 225\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x16_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 9\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 40\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 70\nIPP0 = 3.6\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 310\nIDD4R = 225\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 150\ntRFC4 = 103\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 5\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 16\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 140\nIDD4R = 125\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 16\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 155\nIDD4R = 135\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 16\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 155\nIDD4R = 135\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 16\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 60\nIPP0 = 3.0\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 175\nIDD4R = 145\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\ncmd_queue_size = 8\ntrans_queue_size = 32\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 16\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 60\nIPP0 = 3.0\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 175\nIDD4R = 145\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 16\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.0\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 195\nIDD4R = 170\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x4_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 16\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.0\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 195\nIDD4R = 170\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 243\ntRFC2 = 150\ntRFC4 = 103\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 5\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 22\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 253\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 140\nIDD4R = 125\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 23\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 155\nIDD4R = 135\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 278\ntRFC2 = 171\ntRFC4 = 118\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 23\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 289\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 55\nIPP0 = 3.0\nIDD2P = 27\nIDD2N = 42\nIDD3P = 40\nIDD3N = 55\nIDD4W = 155\nIDD4R = 135\nIDD5AB = 170\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 26\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 60\nIPP0 = 3.0\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 175\nIDD4R = 145\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 312\ntRFC2 = 192\ntRFC4 = 132\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 26\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 324\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 60\nIPP0 = 3.0\nIDD2P = 29\nIDD2N = 45\nIDD3P = 40\nIDD3N = 60\nIDD4W = 175\nIDD4R = 145\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 28\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.0\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 195\nIDD4R = 170\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_4Gb_x8_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 347\ntRFC2 = 214\ntRFC4 = 147\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 28\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 360\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIPP0 = 3.0\nIDD2P = 34\nIDD2N = 50\nIDD3P = 40\nIDD3N = 65\nIDD4W = 195\nIDD4R = 170\nIDD5AB = 175\nIDD6x = 20\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 327\ntRFC2 = 243\ntRFC4 = 150\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 5\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 28\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 337\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 75\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 39\nIDD3N = 44\nIDD4W = 225\nIDD4R = 225\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 6\ntRRD_L = 7\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 32\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 75\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 39\nIDD3N = 44\nIDD4W = 225\nIDD4R = 225\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 6\ntRRD_L = 7\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 32\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 75\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 39\nIDD3N = 44\nIDD4W = 225\nIDD4R = 225\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 8\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 36\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 80\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 41\nIDD3N = 47\nIDD4W = 228\nIDD4R = 243\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 8\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 36\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 80\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 41\nIDD3N = 47\nIDD4W = 228\nIDD4R = 243\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 9\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 40\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 85\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 43\nIDD3N = 50\nIDD4W = 244\nIDD4R = 263\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 9\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 40\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 85\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 43\nIDD3N = 50\nIDD4W = 244\nIDD4R = 263\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2933.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 21\nCWL = 16\ntRCD = 21\ntRP = 21\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 8\ntRRD_L = 10\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 44\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 90\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 45\nIDD3N = 53\nIDD4W = 261\nIDD4R = 283\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_2933_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 20\nCWL = 16\ntRCD = 20\ntRP = 20\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 8\ntRRD_L = 10\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 44\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 90\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 45\nIDD3N = 53\nIDD4W = 261\nIDD4R = 283\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x16_3200.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 0.63\nAL = 0\nCL = 22\nCWL = 16\ntRCD = 22\ntRP = 22\ntRAS = 52\ntRFC = 560\ntRFC2 = 416\ntRFC4 = 256\ntREFI = 12480\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 9\ntRRD_L = 11\ntWTR_S = 4\ntWTR_L = 12\ntFAW = 48\ntWR = 24\ntWR2 = 25\ntRTP = 12\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 576\ntXP = 10\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 95\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 37\nIDD3P = 47\nIDD3N = 56\nIDD4W = 278\nIDD4R = 302\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1587301\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 327\ntRFC2 = 243\ntRFC4 = 150\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 5\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 16\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 337\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 40\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 30\nIDD3N = 35\nIDD4W = 95\nIDD4R = 100\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 16\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 40\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 30\nIDD3N = 35\nIDD4W = 95\nIDD4R = 100\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 16\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 40\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 30\nIDD3N = 35\nIDD4W = 95\nIDD4R = 100\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 16\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 43\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 32\nIDD3N = 38\nIDD4W = 103\nIDD4R = 110\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 16\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 43\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 32\nIDD3N = 38\nIDD4W = 103\nIDD4R = 110\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 16\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 46\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 34\nIDD3N = 41\nIDD4W = 112\nIDD4R = 121\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 16\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 46\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 34\nIDD3N = 41\nIDD4W = 112\nIDD4R = 121\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2933.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 21\nCWL = 16\ntRCD = 21\ntRP = 21\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 16\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 49\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 36\nIDD3N = 44\nIDD4W = 121\nIDD4R = 132\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_2933_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 20\nCWL = 16\ntRCD = 20\ntRP = 20\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 16\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 49\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 36\nIDD3N = 44\nIDD4W = 121\nIDD4R = 132\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x4_3200.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 131072\ncolumns = 1024\ndevice_width = 4\nBL = 8\n\n[timing]\ntCK = 0.63\nAL = 0\nCL = 22\nCWL = 16\ntRCD = 22\ntRP = 22\ntRAS = 52\ntRFC = 560\ntRFC2 = 416\ntRFC4 = 256\ntREFI = 12480\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 12\ntFAW = 16\ntWR = 24\ntWR2 = 25\ntRTP = 12\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 576\ntXP = 10\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 52\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 37\nIDD3P = 38\nIDD3N = 47\nIDD4W = 130\nIDD4R = 143\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 32768\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1587301\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_1866.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 13\nCWL = 10\ntRCD = 13\ntRP = 13\ntRAS = 32\ntRFC = 327\ntRFC2 = 243\ntRFC4 = 150\ntREFI = 7285\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 5\ntWTR_S = 3\ntWTR_L = 7\ntFAW = 22\ntWR = 14\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 5\ntCKE = 5\ntCKESR = 6\ntXS = 337\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 45\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 35\nIDD3N = 40\nIDD4W = 115\nIDD4R = 125\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2133.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 16\nCWL = 11\ntRCD = 16\ntRP = 16\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 23\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 45\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 35\nIDD3N = 40\nIDD4W = 115\nIDD4R = 125\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2133_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.94\nAL = 0\nCL = 15\nCWL = 11\ntRCD = 15\ntRP = 15\ntRAS = 36\ntRFC = 374\ntRFC2 = 278\ntRFC4 = 171\ntREFI = 8328\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 8\ntFAW = 23\ntWR = 16\ntWR2 = 17\ntRTP = 8\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 385\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 45\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 33\nIDD3P = 35\nIDD3N = 40\nIDD4W = 115\nIDD4R = 125\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1063829\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 12\ntRCD = 17\ntRP = 17\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 26\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 48\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 37\nIDD3N = 43\nIDD4W = 123\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n[thermal]\nloc_mapping = 33,33,32-31,30-29,26:13-27-28,12:3\npower_epoch_period = 100000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 0; 0: x direction first, 1: y direction first\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2400_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 16\nCWL = 12\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9360\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 26\ntWR = 18\ntWR2 = 19\ntRTP = 9\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 48\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 37\nIDD3N = 43\nIDD4W = 123\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2666.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 19\nCWL = 14\ntRCD = 19\ntRP = 19\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 28\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 51\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 39\nIDD3N = 46\nIDD4W = 132\nIDD4R = 146\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2666_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.75\nAL = 0\nCL = 18\nCWL = 14\ntRCD = 18\ntRP = 18\ntRAS = 43\ntRFC = 467\ntRFC2 = 347\ntRFC4 = 214\ntREFI = 10398\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 7\ntWTR_S = 4\ntWTR_L = 10\ntFAW = 28\ntWR = 20\ntWR2 = 21\ntRTP = 10\ntCCD_S = 4\ntCCD_L = 7\ntCKE = 7\ntCKESR = 8\ntXS = 480\ntXP = 8\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 51\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 35\nIDD3P = 39\nIDD3N = 46\nIDD4W = 132\nIDD4R = 146\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1333333\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2933.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 21\nCWL = 16\ntRCD = 21\ntRP = 21\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 31\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 54\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 41\nIDD3N = 49\nIDD4W = 141\nIDD4R = 157\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_2933_2.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.68\nAL = 0\nCL = 20\nCWL = 16\ntRCD = 20\ntRP = 20\ntRAS = 47\ntRFC = 514\ntRFC2 = 382\ntRFC4 = 235\ntREFI = 11439\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 11\ntFAW = 31\ntWR = 22\ntWR2 = 23\ntRTP = 11\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 528\ntXP = 9\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 54\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 36\nIDD3P = 41\nIDD3N = 49\nIDD4W = 141\nIDD4R = 157\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1470588\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/DDR4_8Gb_x8_3200.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.63\nAL = 0\nCL = 22\nCWL = 16\ntRCD = 22\ntRP = 22\ntRAS = 52\ntRFC = 560\ntRFC2 = 416\ntRFC4 = 256\ntREFI = 12480\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 8\ntWTR_S = 4\ntWTR_L = 12\ntFAW = 34\ntWR = 24\ntWR2 = 25\ntRTP = 12\ntCCD_S = 4\ntCCD_L = 8\ntCKE = 8\ntCKESR = 9\ntXS = 576\ntXP = 10\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 57\nIPP0 = 3.0\nIDD2P = 25\nIDD2N = 37\nIDD3P = 43\nIDD3N = 52\nIDD4W = 150\nIDD4R = 168\nIDD5AB = 250\nIDD6x = 30\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1587301\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/GDDR5X_8Gb_x32.ini", "content": "[dram_structure]\nprotocol = GDDR5X\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 64\ndevice_width = 32\nBL = 16\nbankgroup_enable = false\n\n[timing]\ntCK = 0.666 (1/1.5)\nCL = 24\nCWL = 7\ntRCDRD = 18\ntRCDWR = 15\ntRP = 18\ntRAS = 42\ntRFC = 98\ntREFI = 11699\ntRPRE = 1; read preamble\ntWPRE = 1; TODO figure this out, should be 1 or 2\ntRRD_S = 9\ntRRD_L = 9\ntWTR_S = 8\ntWTR_L = 8\ntFAW = 35\ntWR = 18\ntCCD_S = 2\ntCCD_L = 3\ntXS = 116\ntCKE = 16\ntCKSRE = 8\ntXP = 12\ntRTRS = 0\ntRTP_L = 3\ntRTP_S = 3\ntPPD = 2\nt32AW = 280\n\n[power]\nVDD = 1.35\nIDD0 = 500\nIDD2P = 220\nIDD2N = 260\nIDD3P = 330\nIDD3N = 480\nIDD4W = 2320\nIDD4R = 2160\nIDD5AB = 600\nIDD5PB = 60\nIDD6x = 65\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 128\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1501501\noutput_level = 1\n\n[thermal]\npower_epoch_period = 1000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\n\n" }, { "path": "src/DRAMsim3/configs/GDDR5_1Gb_x32.ini", "content": "[dram_structure]\nprotocol = GDDR5\nbankgroups = 4\nbanks_per_group = 4\nrows = 4096\ncolumns = 64\ndevice_width = 32\nBL = 8\nbankgroup_enable = false\n\n[timing]\ntCK = 0.667\nCL = 24\nCWL = 7\ntRCDRD = 18\ntRCDWR = 15\ntRP = 18\ntRAS = 42\ntRFC = 98\ntREFI = 11699\ntRPRE = 1; read preamble\ntWPRE = 1; TODO figure this out, should be 1 or 2\ntRRD_S = 9\ntRRD_L = 9\ntWTR_S = 8\ntWTR_L = 8\ntFAW = 35\ntWR = 18\ntCCD_S = 2\ntCCD_L = 3\ntXS = 116\ntCKE = 16\ntCKESR = 8\ntXP = 12\ntRTRS = 0\ntRTP_L = 3\ntRTP_S = 3\ntPPD = 2\nt32AW = 280\n\n[power]\nVDD = 1.5\nIDD0 = 490\nIDD2P = 210\nIDD2N = 250\nIDD3P = 310\nIDD3N = 450\nIDD4W = 1160\nIDD4R = 1080\nIDD5AB = 450\nIDD5PB = 45\nIDD6x = 60\n\n[system]\nchannel_size = 1024\nchannels = 1\nbus_width = 256\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1499250\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/GDDR5_8Gb_x32.ini", "content": "[dram_structure]\nprotocol = GDDR5\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 128\ndevice_width = 32\nBL = 8\nbankgroup_enable = false\n\n[timing]\ntCK = 0.667\nCL = 24\nCWL = 7\ntRCDRD = 24\ntRCDWR = 20\ntRP = 24\ntRAS = 56\ntRFC = 74\ntREFI = 3800\ntRPRE = 1; read preamble\ntWPRE = 1; TODO figure this out, should be 1 or 2\ntRRD_S = 10\ntRRD_L = 10\ntWTR_S = 10\ntWTR_L = 10\ntFAW = 40\ntWR = 24\ntCCD_S = 2\ntCCD_L = 3\ntXS = 94\ntCKESR = 2\ntXP = 12\ntRTRS = 1\ntRTP_L = 2\ntRTP_S = 2\ntPPD = 5\nt32AW = 360\ntRFCb = 30\ntREFIb = 238\n\n[power]\nVDD = 1.5\nIDD0 = 71\nIDD2P = 45\nIDD2N = 60\nIDD3P = 50\nIDD3N = 61\nIDD4W = 231\nIDD4R = 248\nIDD5AB = 286\nIDD5PB = 45\nIDD6x = 35\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 128\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1499250\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/GDDR6_8Gb_x16.ini", "content": "[dram_structure]\nprotocol = GDDR6\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 128\ndevice_width = 16\nBL = 16\nbankgroup_enable = false\n\n[timing]\ntCK = 0.66\nCL = 24\nCWL = 16\ntRCDRD = 24\ntRCDWR = 20\ntRP = 24\ntRAS = 54\ntRFC = 126\ntREFI = 11862\ntRPRE = 1; read preamble\ntWPRE = 1; TODO figure this out, should be 1 or 2\ntRRD_S = 9\ntRRD_L = 9\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 32\ntWR = 16\ntCCD_S = 3\ntCCD_L = 4\ntXS = 132\ntCKESR = 8\ntXP = 12\ntRTRS = 1\ntRTP_L = 3\ntRTP_S = 3\ntPPD = 2\nt32AW = 420\ntRFCb = 30\ntREFIb = 238\n\n[power]\nVDD = 1.35\nIDD0 = 71\nIDD2P = 45\nIDD2N = 60\nIDD3P = 50\nIDD3N = 61\nIDD4W = 231\nIDD4R = 248\nIDD5AB = 286\nIDD5PB = 45\nIDD6x = 35\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 128\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1499250\noutput_level = 1\n\n;16n prefetch" }, { "path": "src/DRAMsim3/configs/HBM1_4Gb_x128.ini", "content": "[dram_structure]\nprotocol = HBM\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 64\ndevice_width = 128\nBL = 4\nnum_dies = 4\n\n[timing]\ntCK = 2\nCL = 7\nCWL = 2\ntRCDRD = 7\ntRCDWR = 7\ntRP = 7\ntRAS = 17\ntRFC = 130\ntREFI = 1950\ntREFIb = 64\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 2\ntRRD_L = 3\ntWTR_S = 3\ntWTR_L = 4\ntFAW = 15\ntWR = 8\ntCCD_S = 1\ntCCD_L = 1\ntXS = 134\ntCKE = 4\ntCKSRE = 5\ntXP = 4\ntRTP_L = 3\ntRTP_S = 2\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIDD2P = 28\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 440\nIDD4R = 360\nIDD5AB = 250\nIDD6x = 31\n\n[system]\nchannel_size = 512\nchannels = 8\nbus_width = 128\naddress_mapping = rorabgbachco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = False\n\n[other]\nepoch_period = 500000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/HBM2_4Gb_x128.ini", "content": "[dram_structure]\nprotocol = HBM\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 64\ndevice_width = 128\nBL = 4\nnum_dies = 4\n\n[timing]\ntCK = 1\nCL = 14\nCWL = 4\ntRCDRD = 14\ntRCDWR = 14\ntRP = 14\ntRAS = 34\ntRFC = 260\ntREFI = 3900\ntREFIb = 128\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 6\ntWTR_L = 8\ntFAW = 30\ntWR = 16\ntCCD_S = 1\ntCCD_L = 2\ntXS = 268\ntCKE = 8\ntCKSRE = 10\ntXP = 8\ntRTP_L = 6\ntRTP_S = 4\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIDD2P = 28\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 500\nIDD4R = 390\nIDD5AB = 250\nIDD6x = 31\n\n[system]\nchannel_size = 512\nchannels = 8\nbus_width = 128\naddress_mapping = rorabgbachco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = False\n\n[other]\nepoch_period = 1000000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/HBM2_8Gb_x128.ini", "content": "[dram_structure]\nprotocol = HBM\nbankgroups = 4\nbanks_per_group = 4\nrows = 32768\ncolumns = 64\ndevice_width = 128\nBL = 4\nnum_dies = 4\n\n[timing]\ntCK = 1\nCL = 14\nCWL = 4\ntRCDRD = 14\ntRCDWR = 14\ntRP = 14\ntRAS = 34\ntRFC = 260\ntREFI = 3900\ntREFIb = 128\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 6\ntWTR_L = 8\ntFAW = 30\ntWR = 16\ntCCD_S = 1\ntCCD_L = 2\ntXS = 268\ntCKE = 8\ntCKSRE = 10\ntXP = 8\ntRTP_L = 6\ntRTP_S = 4\n\n[power]\nVDD = 1.2\nIDD0 = 65\nIDD2P = 28\nIDD2N = 40\nIDD3P = 40\nIDD3N = 55\nIDD4W = 500\nIDD4R = 390\nIDD5AB = 250\nIDD6x = 31\n\n[system]\nchannel_size = 1024\nchannels = 8\nbus_width = 128\naddress_mapping = rorabgbachco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = False\n\n[other]\nepoch_period = 1000000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/HBM_4Gb_x128.ini", "content": "[dram_structure]\nprotocol = HBM\nbankgroups = 4\nbanks_per_group = 4\nrows = 16384\ncolumns = 64\ndevice_width = 128\nBL = 4\nnum_dies = 4\n\n[timing]\ntCK = 2\nAL = 0\nCL = 7\nCWL = 4\ntRCDRD = 7\ntRCDWR = 6\ntRP = 7\ntRAS = 17\ntRFC = \ntREFI = 1950\ntRPRE = 1; read preamble\ntWPRE = 1; TODO figure this out, should be 1 or 2\ntRRD_S = 4\ntRRD_L = 5\ntWTR_S = 2\ntWTR_L = 4\ntFAW = 20\ntWR = 8\ntCCD_S = 2\ntCCD_L = 3\ntXS = 0\ntCKSRE = 0\ntXP = 5\ntRTP_L = 7\ntRTP_S = 6\ntPPD = 5\nt32AW = 330\ntRFCb = \ntREFIb = \ntRREFD = \ntRFCPB = \n\n[power]\nVDD = 1.2\nIDD0 = 48\nIDD2P = 25\nIDD2N = 34\nIDD3P = 37\nIDD3N = 43\nIDD4W = 123\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 31\n\n[system]\nchannel_size = 512\nchannels = 8\nbus_width = 128\naddress_mapping = rorabgbachco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = False\n\n[other]\nepoch_period = 500000\noutput_level = 1\n\n[thermal]\npower_epoch_period = 10000; power epoch period (# cycle)\nlogic_bg_power = 5\nlogic_max_power = 25\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 1024;\nmat_dim_y = 1024;\nbank_order = 1; 0: x direction first, 1: y direction first\nbank_layer_order = 0;\n\n" }, { "path": "src/DRAMsim3/configs/HMC2_8GB_4Lx16.ini", "content": "[hmc]\nnum_links = 4\nlink_width = 16\nlink_speed = 25000\nblock_size = 64\nxbar_queue_depth = 32\n\n[dram_structure]\nprotocol = HMC\nbankgroups = 1\nbanks_per_group = 16\nrows = 65536\ncolumns = 64\ndevice_width = 32\nnum_dies = 8\n\n[timing]\ntCK = 0.8\nCL = 17\nCWL = 17\ntRCD = 17\ntRP = 17\ntRAS = 34\ntRFC = 420\ntREFI = 9364; average periodic refresh interval, 3.9us\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 3\ntFAW = 27\ntWR = 19\ntCCD_S = 6\ntCCD_L = 6\ntXS = 12\ntCKSRE = 1\ntXP = 8\ntRTP_L = 10\ntRTP_S = 10\ntRTRS = 0\n\n[power]\nVDD = 1.2\nIDD0 = 25\nIDD2P = 17\nIDD2N = 19\nIDD3P = 20\nIDD3N = 21\nIDD4W = 61\nIDD4R = 64\nIDD5AB = 150\nIDD6x = 21\n\n[system]\nchannel_size = 256\nchannels = 32\nbus_width = 32\naddress_mapping = rocorabgbach\nqueue_structure = PER_BANK\nrow_buf_policy = CLOSE_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = True\n\n[thermal]\npower_epoch_period = 10000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\nbank_layer_order = 0;\n\n[other]\nepoch_period = 1250000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/HMC_2GB_4Lx16.ini", "content": "[hmc]\nnum_links = 4\nlink_width = 16\nlink_speed = 10000\nblock_size = 64\nxbar_queue_depth = 6\n\n[dram_structure]\nprotocol = HMC\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 64\ndevice_width = 32\nnum_dies = 4\n\n[timing]\ntCK = 0.8\nCL = 17\nCWL = 17\ntRCD = 17\ntRP = 17\ntRAS = 34\ntRFC = 420\ntREFI = 9364; average periodic refresh interval, 3.9us\ntRRD_S = 4\ntRRD_L = 4\ntWTR_S = 3\ntWTR_L = 3\ntFAW = 27\ntWR = 17\ntCCD_S = 6\ntCCD_L = 6\ntXS = 12\ntCKSRE = 1\ntXP = 8\ntRTP_L = 8\ntRTP_S = 8\ntRTRS = 0\n\n[power]\nVDD = 1.2\nIDD0 = 25\nIDD2P = 17\nIDD2N = 19\nIDD3P = 20\nIDD3N = 21\nIDD4W = 61\nIDD4R = 64\nIDD5AB = 150\nIDD6x = 21\n\n[system]\nchannel_size = 128\nchannels = 16\nbus_width = 32\naddress_mapping = rocorabgbach\nqueue_structure = PER_BANK\nrow_buf_policy = CLOSE_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = True\n\n[other]\nepoch_period = 1250000\noutput_level = 1\n\n[thermal]\npower_epoch_period = 10000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\nbank_layer_order = 0;\n\n" }, { "path": "src/DRAMsim3/configs/HMC_2GB_4Lx16_dummy.ini", "content": "[hmc]\nnum_links = 4\nlink_width = 16\nlink_speed = 10000\nblock_size = 128\nxbar_queue_depth = 6\n\n[dram_structure]\nprotocol = HMC\nbankgroups = 1\nbanks_per_group = 8\nrows = 65536\ncolumns = 64\ndevice_width = 32\nBL = 2\nnum_dies = 4\n\n[timing]\ntCK = 0.8\nCL = 17\nCWL = 17\ntRCD = 17\ntRP = 17\ntRAS = 34\ntRFC = 420\ntREFI = 9364; average periodic refresh interval, 3.9us\ntRRD_S = 4\ntRRD_L = 4\ntWTR_S = 3\ntWTR_L = 3\ntFAW = 27\ntWR = 17\ntCCD_S = 6\ntCCD_L = 6\ntXS = 12\ntCKSRE = 1\ntXP = 8\ntRTP_L = 8\ntRTP_S = 8\ntRTRS = 0\n\n[power]\nVDD = 1.2\nIDD0 = 25\nIDD2P = 17\nIDD2N = 19\nIDD3P = 20\nIDD3N = 21\nIDD4W = 61\nIDD4R = 64\nIDD5AB = 150\nIDD6x = 21\n\n[system]\nchannel_size = 128\nchannels = 16\nbus_width = 32\naddress_mapping = rocorabgbach\nqueue_structure = PER_BANK\nrow_buf_policy = CLOSE_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = True\n\n[other]\nepoch_period = 1250000\noutput_level = 1\n\n[thermal]\npower_epoch_period = 10000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\nbank_layer_order = 0;\n\n" }, { "path": "src/DRAMsim3/configs/HMC_4GB_4Lx16.ini", "content": "[hmc]\nnum_links = 4\nlink_width = 16\nlink_speed = 15000\nblock_size = 64\nxbar_queue_depth = 6\n\n[dram_structure]\nprotocol = HMC\nbankgroups = 1\nbanks_per_group = 16\nrows = 65536\ncolumns = 64\ndevice_width = 32\nnum_dies = 4\n\n[timing]\ntCK = 0.8\nCL = 17\nCWL = 17\ntRCD = 17\ntRP = 17\ntRAS = 34\ntRFC = 420\ntREFI = 9364; average periodic refresh interval, 3.9us\ntRRD_S = 4\ntRRD_L = 4\ntWTR_S = 3\ntWTR_L = 3\ntFAW = 27\ntWR = 17\ntCCD_S = 6\ntCCD_L = 6\ntXS = 12\ntCKSRE = 1\ntXP = 8\ntRTP_L = 8\ntRTP_S = 8\ntRTRS = 0\n\n[power]\nVDD = 1.2\nIDD0 = 25\nIDD2P = 17\nIDD2N = 19\nIDD3P = 20\nIDD3N = 21\nIDD4W = 61\nIDD4R = 64\nIDD5AB = 150\nIDD6x = 21\n\n[system]\nchannel_size = 256\nchannels = 16\nbus_width = 32\naddress_mapping = rocorabgbach\nqueue_structure = PER_BANK\nrow_buf_policy = CLOSE_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\nunified_queue = True\n\n[other]\nepoch_period = 1250000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/LPDDR3_8Gb_x32_1333.ini", "content": "[dram_structure]\nprotocol = LPDDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 32\nBL = 8\n\n[timing]\ntCK = 1.5\nAL = 0\nCL = 10\nCWL = 8\ntRCD = 12\ntRP = 12\ntRAS = 28\ntRFC = 140\ntRFCb = 60\ntRFC2 = 140\ntRFC4 = 140\nREFI = 2600\ntREFIb = 325\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 7\ntRRD_L = 7\ntWTR_S = 5\ntWTR_L = 5\ntFAW = 34\ntWR = 10\ntWR2 = 10\ntRTP = 5\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 5\ntCKESR = 10\ntXS = 147\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 40.0\nIPP0 = 0\nIDD2P = 1.3\nIDD2N = 20.0\nIDD3P = 7\nIDD3N = 20.5\nIDD4W = 215\nIDD4R = 220\nIDD5AB = 150\nIDD6x = 20.5\n\n[system]\nchannel_size = 2048\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 666666\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/LPDDR3_8Gb_x32_1600.ini", "content": "[dram_structure]\nprotocol = LPDDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 32\nBL = 8\n\n[timing]\ntCK = 1.25\nAL = 0\nCL = 12\nCWL = 9\ntRCD = 15\ntRP = 15\ntRAS = 34\ntRFC = 168\ntRFCb = 72\ntRFC2 = 168\ntRFC4 = 168\nREFI = 3120\ntREFIb = 390\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 8\ntRRD_L = 8\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 40\ntWR = 12\ntWR2 = 12\ntRTP = 6\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 6\ntCKESR = 12\ntXS = 176\ntXP = 6\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 40.0\nIPP0 = 0\nIDD2P = 1.3\nIDD2N = 20.5\nIDD3P = 7\nIDD3N = 21.0\nIDD4W = 245\nIDD4R = 250\nIDD5AB = 150\nIDD6x = 21.0\n\n[system]\nchannel_size = 2048\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 800000\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/LPDDR3_8Gb_x32_1866.ini", "content": "[dram_structure]\nprotocol = LPDDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 32\nBL = 8\n\n[timing]\ntCK = 1.07\nAL = 0\nCL = 14\nCWL = 11\ntRCD = 17\ntRP = 17\ntRAS = 40\ntRFC = 196\ntRFCb = 85\ntRFC2 = 196\ntRFC4 = 196\nREFI = 3645\ntREFIb = 456\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 10\ntRRD_L = 10\ntWTR_S = 7\ntWTR_L = 7\ntFAW = 47\ntWR = 15\ntWR2 = 15\ntRTP = 7\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 7\ntCKESR = 15\ntXS = 206\ntXP = 7\ntRTRS = 1\n\n[power]\nVDD = 1.2\nIDD0 = 41.5\nIPP0 = 0\nIDD2P = 1.3\nIDD2N = 21.5\nIDD3P = 7\nIDD3N = 22.0\nIDD4W = 285\nIDD4R = 290\nIDD5AB = 150\nIDD6x = 22.0\n\n[system]\nchannel_size = 2048\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 934579\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/LPDDR4_8Gb_x16_2400.ini", "content": "[dram_structure]\nprotocol = LPDDR4\nbankgroups = 2\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 16\nBL = 16\n\n[timing]\ntCK = 0.83\nAL = 0\nCL = 17\nCWL = 14\ntRCD = 15\ntRP = 15\ntRAS = 32\ntRFC = 392\ntRFC2 = 268\ntRFC4 = 172\ntREFI = 8660\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 8\ntRRD_L = 8\ntWTR_S = 8\ntWTR_L = 16\ntFAW = 32\ntWR = 30\ntWR2 = 32\ntRTP = 12\ntCCD_S = 4\ntCCD_L = 6\ntCKE = 6\ntCKESR = 7\ntXS = 432\ntXP = 6\ntRTRS = 1\ntPPD = 2\n\n[power]\nVDD = 1.2\nIDD0 = 80\nIPP0 = 4.0\nIDD2P = 25\nIDD2N = 34\nIDD3P = 41\nIDD3N = 47\nIDD4W = 228\nIDD4R = 243\nIDD5AB = 280\nIDD6x = 30\n\n[system]\nchannel_size = 8192\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrefresh_policy = RANK_LEVEL_STAGGERED\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 1204819\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/ST-1.2x.ini", "content": "; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) \n;\n;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416\n\n;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:\n\n;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n\n;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.\n\n;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”\n\n; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. \n\n[dram_structure]\nprotocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL=4\n\n[timing]\ntCK = 1.25;\nCL = 11;\nCWL = 11\nAL = 0;\ntRCDRD=14 \ntRCDWR=14 \ntRP=14 \ntRAS=20\ntRFC = 1\ntREFI = 6240\ntRRD_S = 6\ntRRD_L = 6\ntWTR_S = 2\ntWTR_L = 2\ntFAW = 29\ntWR = 12\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntXP = 5\ntRTP_L = 6\ntRTP_S = 6\n; tRC=34\ntRTRS=1 \n\n; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations.\n[power]\nVDD = 1.5\nIDD0=1305; \nIDD1=1395; \nIDD2P=846; \nIDD2Q=1030; \nIDD2N=1050; \nIDD3Pf=60; \nIDD3Ps=60; \nIDD3N=1310; \nIDD4W=1765; \nIDD4R=230; \nIDD5=1940; \nIDD6=246; \nIDD6L=246; \nIDD7=2160; \n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rorabgbachco\nqueue_structure = PER_RANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 16\ntrans_queue_size = 32\n\n[other]\nepoch_period = 100000\noutput_level = 1\n" }, { "path": "src/DRAMsim3/configs/ST-1.5x.ini", "content": "; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) \n;\n;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416\n\n;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:\n\n;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n\n;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.\n\n;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”\n\n; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.5x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. \n\n[dram_structure]\nprotocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL=4\n\n[timing]\ntCK = 1.25;\nCL = 11;\nCWL = 11\nAL = 0;\ntRCDRD=17\ntRCDWR=17\ntRP=17\ntRAS=23\ntRFC = 1\ntREFI = 6240\ntRRD_S = 8\ntRRD_L = 8\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 36\ntWR = 12\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntXP = 5\ntRTP_L = 6\ntRTP_S = 6\n; tRC=40\ntRTRS=1\nREFRESH_PERIOD=7800; \n\n; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations. \n[power]\nVDD=1.5\nIDD0=1305; \nIDD1=1395; \nIDD2P=846; \nIDD2Q=1030; \nIDD2N=1050; \nIDD3Pf=60; \nIDD3Ps=60; \nIDD3N=1310; \nIDD4W=1765; \nIDD4R=230; \nIDD5=1940; \nIDD6=246; \nIDD6L=246; \nIDD7=2160; \n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rorabgbachco\nqueue_structure = PER_RANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 16\ntrans_queue_size = 32\n\n[other]\nepoch_period = 100000\noutput_level = 1\n" }, { "path": "src/DRAMsim3/configs/ST-2.0x.ini", "content": "; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC) \n;\n;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416\n\n;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:\n\n;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n\n;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.\n\n;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”\n\n; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations. \n\n[dram_structure]\nprotocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol\nbankgroups = 1\nbanks_per_group = 8\nrows = 32768\ncolumns = 1024\ndevice_width = 8\nBL=4\n\n[timing]\ntCK = 1.25;\nCL = 11;\nCWL = 11\nAL = 0;\ntRCDRD=22\ntRCDWR=22\ntRP=22\ntRAS=28\ntRFC = 1\ntREFI = 6240\ntRRD_S = 10\ntRRD_L = 10\ntWTR_S = 6\ntWTR_L = 6\ntFAW = 36\ntWR = 48\ntCCD_S = 4\ntCCD_L = 4\ntCKE = 4\ntXP = 5\ntRTP_L = 6\ntRTP_S = 6\n; tRC=50\ntRTRS=1\nREFRESH_PERIOD=7800\n\n; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations.\n[power]\nVDD=1.5; \nIDD0=1305; \nIDD1=1395; \nIDD2P=846; \nIDD2Q=1030; \nIDD2N=1050; \nIDD3Pf=60; \nIDD3Ps=60; \nIDD3N=1310; \nIDD4W=1765; \nIDD4R=230; \nIDD5=1940; \nIDD6=246; \nIDD6L=246; \nIDD7=2160; \n\n\n[system]\nchannel_size = 4096\nchannels = 1\nbus_width = 64\naddress_mapping = rorabgbachco\nqueue_structure = PER_RANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 16\ntrans_queue_size = 32\n\n[other]\nepoch_period = 100000\noutput_level = 1" }, { "path": "src/DRAMsim3/configs/ddr3_debug.ini", "content": "[dram_structure]\nprotocol = DDR3\nbankgroups = 1\nbanks_per_group = 8\nrows = 16384\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 1.5\nAL = 0\nCL = 10\nCWL = 7\ntRCD = 10\ntRP = 10\ntRAS = 24\ntRFC = 74\ntREFI = 5200\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntWTR_S = 5\ntFAW = 20\ntWR = 10\ntCCD_S = 4\ntRTP = 5\ntCKE = 4\ntCKESR = 1\ntXS = 81\ntXP = 5\ntRTRS = 1\n\n[power]\nVDD = 1.35\nIDD0 = 33\nIDD2P = 12\nIDD2N = 17\nIDD3P = 14\nIDD3N = 23\nIDD4W = 77\nIDD4R = 72\nIDD5AB = 155\nIDD6x = 12\n\n[system]\nchannel_size = 2048\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nepoch_period = 666666\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/ddr4_debug.ini", "content": "[dram_structure]\nprotocol = DDR4\nbankgroups = 4\nbanks_per_group = 4\nrows = 65536\ncolumns = 1024\ndevice_width = 8\nBL = 8\n\n[timing]\ntCK = 0.833\nAL = 0\nCL = 16\nCWL = 16\ntRCD = 16\ntRP = 16\ntRAS = 39\ntRFC = 420\ntRFC2 = 312\ntRFC4 = 192\ntREFI = 9364\ntRPRE = 1\ntWPRE = 1\ntRRD_S = 4\ntRRD_L = 6\ntWTR_S = 3\ntWTR_L = 9\ntFAW = 26\ntWR = 19\ntWR2 = 1\ntCCD_S = 4\ntCCD_L = 6\ntXS = 12\ntCKSRE = 12\ntXP = 8\ntRFCb = 20\ntREFIb = 1950\nactivation_window_depth = 4\ntRREFD = 5\ntRTRS = 2\ntRTP = 10\ntCAS = 3\ntCWD = 3\n\n[power]\nVDD = 1.2\nIDD0 = 48\nIDD2P = 25\nIDD2N = 34\nIDD3P = 37\nIDD3N = 44.0\nIDD4W = 123\nIDD4R = 135\nIDD5AB = 250\nIDD6x = 31\n\n[system]\nchannel_size = 16384\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nvalidation_output = ddr4_verification.log\nepoch_period = 1200480\noutput_level = 1\n\n" }, { "path": "src/DRAMsim3/configs/lpddr_2Gb_x16.ini", "content": "[dram_structure]\nprotocol = LPDDR\nbankgroups = 1\nbanks_per_group = 4\nrows = 16384\ncolumns = 2048\ndevice_width = 16\nBL = 8\n\n[timing]\ntCK = 4.8\nAL = 0\nCL = 3\nCWL = 3\ntRCD = 4\ntRP = 3\ntRAS = 9\ntRFC = 15\ntREFI = 1625\ntRPRE = 1\ntWPRE = 1\ntRRD_L = 3\ntWTR_L = 2\ntFAW = 4\ntWR = 3\ntCCD_L = 0\ntRTP = 0\ntXP = 2\ntCKE = 1\ntRTRS = 1\ntCMD = 1\nactivation_window_depth = 4\n\n[system]\nchannel_size = 1024\nchannels = 1\nbus_width = 64\naddress_mapping = rochrababgco\nqueue_structure = PER_BANK\nrow_buf_policy = OPEN_PAGE\ncmd_queue_size = 8\ntrans_queue_size = 32\n\n[other]\nvalidation_output = lpddr_verification.log\nepoch_period = 208333\noutput_level = 1\n\n[thermal]\npower_epoch_period = 10000; power epoch period (# cycle)\nchip_dim_x = 0.008; chip size in x dimension [m]\nchip_dim_y = 0.008; chip size in y dimension [m]\namb_temp = 40; The ambient temperature in [C]\nmat_dim_x = 512;\nmat_dim_y = 512;\nbank_order = 1; 0: x direction first, 1: y direction first\n\n" }, { "path": "src/DRAMsim3/ext/fmt/LICENSE.rst", "content": "Copyright (c) 2012 - 2016, Victor Zverovich\n\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n" }, { "path": "src/DRAMsim3/ext/fmt/include/fmt/core.h", "content": "// Formatting library for C++ - the core API\n//\n// Copyright (c) 2012 - present, Victor Zverovich\n// All rights reserved.\n//\n// For the license information refer to format.h.\n\n#ifndef FMT_CORE_H_\n#define FMT_CORE_H_\n\n#include \n#include // std::FILE\n#include \n#include \n#include \n#include \n\n// The fmt library version in the form major * 10000 + minor * 100 + patch.\n#define FMT_VERSION 50202\n\n#ifdef __has_feature\n# define FMT_HAS_FEATURE(x) __has_feature(x)\n#else\n# define FMT_HAS_FEATURE(x) 0\n#endif\n\n#if defined(__has_include) && !defined(__INTELLISENSE__) && \\\n !(defined(__INTEL_COMPILER) && __INTEL_COMPILER < 1600)\n# define FMT_HAS_INCLUDE(x) __has_include(x)\n#else\n# define FMT_HAS_INCLUDE(x) 0\n#endif\n\n#ifdef __has_cpp_attribute\n# define FMT_HAS_CPP_ATTRIBUTE(x) __has_cpp_attribute(x)\n#else\n# define FMT_HAS_CPP_ATTRIBUTE(x) 0\n#endif\n\n#if defined(__GNUC__) && !defined(__clang__)\n# define FMT_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)\n#else\n# define FMT_GCC_VERSION 0\n#endif\n\n#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)\n# define FMT_HAS_GXX_CXX11 FMT_GCC_VERSION\n#else\n# define FMT_HAS_GXX_CXX11 0\n#endif\n\n#ifdef _MSC_VER\n# define FMT_MSC_VER _MSC_VER\n#else\n# define FMT_MSC_VER 0\n#endif\n\n// Check if relaxed C++14 constexpr is supported.\n// GCC doesn't allow throw in constexpr until version 6 (bug 67371).\n#ifndef FMT_USE_CONSTEXPR\n# define FMT_USE_CONSTEXPR \\\n (FMT_HAS_FEATURE(cxx_relaxed_constexpr) || FMT_MSC_VER >= 1910 || \\\n (FMT_GCC_VERSION >= 600 && __cplusplus >= 201402L))\n#endif\n#if FMT_USE_CONSTEXPR\n# define FMT_CONSTEXPR constexpr\n# define FMT_CONSTEXPR_DECL constexpr\n#else\n# define FMT_CONSTEXPR inline\n# define FMT_CONSTEXPR_DECL\n#endif\n\n#ifndef FMT_USE_CONSTEXPR11\n# define FMT_USE_CONSTEXPR11 \\\n (FMT_USE_CONSTEXPR || FMT_GCC_VERSION >= 406 || FMT_MSC_VER >= 1900)\n#endif\n#if FMT_USE_CONSTEXPR11\n# define FMT_CONSTEXPR11 constexpr\n#else\n# define FMT_CONSTEXPR11\n#endif\n\n#ifndef FMT_OVERRIDE\n# if FMT_HAS_FEATURE(cxx_override) || \\\n (FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1900\n# define FMT_OVERRIDE override\n# else\n# define FMT_OVERRIDE\n# endif\n#endif\n\n#if FMT_HAS_FEATURE(cxx_explicit_conversions) || \\\n FMT_GCC_VERSION >= 405 || FMT_MSC_VER >= 1800\n# define FMT_USE_EXPLICIT 1\n# define FMT_EXPLICIT explicit\n#else\n# define FMT_USE_EXPLICIT 0\n# define FMT_EXPLICIT\n#endif\n\n#ifndef FMT_NULL\n# if FMT_HAS_FEATURE(cxx_nullptr) || \\\n (FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1600\n# define FMT_NULL nullptr\n# define FMT_USE_NULLPTR 1\n# else\n# define FMT_NULL NULL\n# endif\n#endif\n#ifndef FMT_USE_NULLPTR\n# define FMT_USE_NULLPTR 0\n#endif\n\n// Check if exceptions are disabled.\n#if (defined(__GNUC__) && !defined(__EXCEPTIONS)) || \\\n FMT_MSC_VER && !_HAS_EXCEPTIONS\n# define FMT_EXCEPTIONS 0\n#else\n# define FMT_EXCEPTIONS 1\n#endif\n\n// Define FMT_USE_NOEXCEPT to make fmt use noexcept (C++11 feature).\n#ifndef FMT_USE_NOEXCEPT\n# define FMT_USE_NOEXCEPT 0\n#endif\n\n#if FMT_USE_NOEXCEPT || FMT_HAS_FEATURE(cxx_noexcept) || \\\n (FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1900\n# define FMT_DETECTED_NOEXCEPT noexcept\n# define FMT_HAS_CXX11_NOEXCEPT 1\n#else\n# define FMT_DETECTED_NOEXCEPT throw()\n# define FMT_HAS_CXX11_NOEXCEPT 0\n#endif\n\n#ifndef FMT_NOEXCEPT\n# if FMT_EXCEPTIONS || FMT_HAS_CXX11_NOEXCEPT\n# define FMT_NOEXCEPT FMT_DETECTED_NOEXCEPT\n# else\n# define FMT_NOEXCEPT\n# endif\n#endif\n\n#ifndef FMT_BEGIN_NAMESPACE\n# if FMT_HAS_FEATURE(cxx_inline_namespaces) || FMT_GCC_VERSION >= 404 || \\\n FMT_MSC_VER >= 1900\n# define FMT_INLINE_NAMESPACE inline namespace\n# define FMT_END_NAMESPACE }}\n# else\n# define FMT_INLINE_NAMESPACE namespace\n# define FMT_END_NAMESPACE } using namespace v5; }\n# endif\n# define FMT_BEGIN_NAMESPACE namespace fmt { FMT_INLINE_NAMESPACE v5 {\n#endif\n\n#if !defined(FMT_HEADER_ONLY) && defined(_WIN32)\n# ifdef FMT_EXPORT\n# define FMT_API __declspec(dllexport)\n# elif defined(FMT_SHARED)\n# define FMT_API __declspec(dllimport)\n# endif\n#endif\n#ifndef FMT_API\n# define FMT_API\n#endif\n\n#ifndef FMT_ASSERT\n# define FMT_ASSERT(condition, message) assert((condition) && message)\n#endif\n\n// libc++ supports string_view in pre-c++17.\n#if (FMT_HAS_INCLUDE() && \\\n (__cplusplus > 201402L || defined(_LIBCPP_VERSION))) || \\\n (defined(_MSVC_LANG) && _MSVC_LANG > 201402L && _MSC_VER >= 1910)\n# include \n# define FMT_STRING_VIEW std::basic_string_view\n#elif FMT_HAS_INCLUDE() && __cplusplus >= 201402L\n# include \n# define FMT_STRING_VIEW std::experimental::basic_string_view\n#endif\n\n// std::result_of is defined in in gcc 4.4.\n#if FMT_GCC_VERSION && FMT_GCC_VERSION <= 404\n# include \n#endif\n\nFMT_BEGIN_NAMESPACE\nnamespace internal {\n\n// An implementation of declval for pre-C++11 compilers such as gcc 4.\ntemplate \ntypename std::add_rvalue_reference::type declval() FMT_NOEXCEPT;\n\ntemplate \nstruct result_of;\n\ntemplate \nstruct result_of {\n // A workaround for gcc 4.4 that doesn't allow F to be a reference.\n typedef typename std::result_of<\n typename std::remove_reference::type(Args...)>::type type;\n};\n\n// Casts nonnegative integer to unsigned.\ntemplate \nFMT_CONSTEXPR typename std::make_unsigned::type to_unsigned(Int value) {\n FMT_ASSERT(value >= 0, \"negative value\");\n return static_cast::type>(value);\n}\n\n/** A contiguous memory buffer with an optional growing ability. */\ntemplate \nclass basic_buffer {\n private:\n basic_buffer(const basic_buffer &) = delete;\n void operator=(const basic_buffer &) = delete;\n\n T *ptr_;\n std::size_t size_;\n std::size_t capacity_;\n\n protected:\n // Don't initialize ptr_ since it is not accessed to save a few cycles.\n basic_buffer(std::size_t sz) FMT_NOEXCEPT: size_(sz), capacity_(sz) {}\n\n basic_buffer(T *p = FMT_NULL, std::size_t sz = 0, std::size_t cap = 0)\n FMT_NOEXCEPT: ptr_(p), size_(sz), capacity_(cap) {}\n\n /** Sets the buffer data and capacity. */\n void set(T *buf_data, std::size_t buf_capacity) FMT_NOEXCEPT {\n ptr_ = buf_data;\n capacity_ = buf_capacity;\n }\n\n /** Increases the buffer capacity to hold at least *capacity* elements. */\n virtual void grow(std::size_t capacity) = 0;\n\n public:\n typedef T value_type;\n typedef const T &const_reference;\n\n virtual ~basic_buffer() {}\n\n T *begin() FMT_NOEXCEPT { return ptr_; }\n T *end() FMT_NOEXCEPT { return ptr_ + size_; }\n\n /** Returns the size of this buffer. */\n std::size_t size() const FMT_NOEXCEPT { return size_; }\n\n /** Returns the capacity of this buffer. */\n std::size_t capacity() const FMT_NOEXCEPT { return capacity_; }\n\n /** Returns a pointer to the buffer data. */\n T *data() FMT_NOEXCEPT { return ptr_; }\n\n /** Returns a pointer to the buffer data. */\n const T *data() const FMT_NOEXCEPT { return ptr_; }\n\n /**\n Resizes the buffer. If T is a POD type new elements may not be initialized.\n */\n void resize(std::size_t new_size) {\n reserve(new_size);\n size_ = new_size;\n }\n\n /** Clears this buffer. */\n void clear() { size_ = 0; }\n\n /** Reserves space to store at least *capacity* elements. */\n void reserve(std::size_t new_capacity) {\n if (new_capacity > capacity_)\n grow(new_capacity);\n }\n\n void push_back(const T &value) {\n reserve(size_ + 1);\n ptr_[size_++] = value;\n }\n\n /** Appends data to the end of the buffer. */\n template \n void append(const U *begin, const U *end);\n\n T &operator[](std::size_t index) { return ptr_[index]; }\n const T &operator[](std::size_t index) const { return ptr_[index]; }\n};\n\ntypedef basic_buffer buffer;\ntypedef basic_buffer wbuffer;\n\n// A container-backed buffer.\ntemplate \nclass container_buffer : public basic_buffer {\n private:\n Container &container_;\n\n protected:\n void grow(std::size_t capacity) FMT_OVERRIDE {\n container_.resize(capacity);\n this->set(&container_[0], capacity);\n }\n\n public:\n explicit container_buffer(Container &c)\n : basic_buffer(c.size()), container_(c) {}\n};\n\n// Extracts a reference to the container from back_insert_iterator.\ntemplate \ninline Container &get_container(std::back_insert_iterator it) {\n typedef std::back_insert_iterator bi_iterator;\n struct accessor: bi_iterator {\n accessor(bi_iterator iter) : bi_iterator(iter) {}\n using bi_iterator::container;\n };\n return *accessor(it).container;\n}\n\nstruct error_handler {\n FMT_CONSTEXPR error_handler() {}\n FMT_CONSTEXPR error_handler(const error_handler &) {}\n\n // This function is intentionally not constexpr to give a compile-time error.\n FMT_API void on_error(const char *message);\n};\n\ntemplate \nstruct no_formatter_error : std::false_type {};\n} // namespace internal\n\n#if FMT_GCC_VERSION && FMT_GCC_VERSION < 405\ntemplate \nstruct is_constructible: std::false_type {};\n#else\ntemplate \nstruct is_constructible : std::is_constructible {};\n#endif\n\n/**\n An implementation of ``std::basic_string_view`` for pre-C++17. It provides a\n subset of the API. ``fmt::basic_string_view`` is used for format strings even\n if ``std::string_view`` is available to prevent issues when a library is\n compiled with a different ``-std`` option than the client code (which is not\n recommended).\n */\ntemplate \nclass basic_string_view {\n private:\n const Char *data_;\n size_t size_;\n\n public:\n typedef Char char_type;\n typedef const Char *iterator;\n\n FMT_CONSTEXPR basic_string_view() FMT_NOEXCEPT : data_(FMT_NULL), size_(0) {}\n\n /** Constructs a string reference object from a C string and a size. */\n FMT_CONSTEXPR basic_string_view(const Char *s, size_t count) FMT_NOEXCEPT\n : data_(s), size_(count) {}\n\n /**\n \\rst\n Constructs a string reference object from a C string computing\n the size with ``std::char_traits::length``.\n \\endrst\n */\n basic_string_view(const Char *s)\n : data_(s), size_(std::char_traits::length(s)) {}\n\n /** Constructs a string reference from a ``std::basic_string`` object. */\n template \n FMT_CONSTEXPR basic_string_view(\n const std::basic_string &s) FMT_NOEXCEPT\n : data_(s.data()), size_(s.size()) {}\n\n#ifdef FMT_STRING_VIEW\n FMT_CONSTEXPR basic_string_view(FMT_STRING_VIEW s) FMT_NOEXCEPT\n : data_(s.data()), size_(s.size()) {}\n#endif\n\n /** Returns a pointer to the string data. */\n FMT_CONSTEXPR const Char *data() const { return data_; }\n\n /** Returns the string size. */\n FMT_CONSTEXPR size_t size() const { return size_; }\n\n FMT_CONSTEXPR iterator begin() const { return data_; }\n FMT_CONSTEXPR iterator end() const { return data_ + size_; }\n\n FMT_CONSTEXPR void remove_prefix(size_t n) {\n data_ += n;\n size_ -= n;\n }\n\n // Lexicographically compare this string reference to other.\n int compare(basic_string_view other) const {\n size_t str_size = size_ < other.size_ ? size_ : other.size_;\n int result = std::char_traits::compare(data_, other.data_, str_size);\n if (result == 0)\n result = size_ == other.size_ ? 0 : (size_ < other.size_ ? -1 : 1);\n return result;\n }\n\n friend bool operator==(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) == 0;\n }\n friend bool operator!=(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) != 0;\n }\n friend bool operator<(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) < 0;\n }\n friend bool operator<=(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) <= 0;\n }\n friend bool operator>(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) > 0;\n }\n friend bool operator>=(basic_string_view lhs, basic_string_view rhs) {\n return lhs.compare(rhs) >= 0;\n }\n};\n\ntypedef basic_string_view string_view;\ntypedef basic_string_view wstring_view;\n\n/**\n \\rst\n The function ``to_string_view`` adapts non-intrusively any kind of string or\n string-like type if the user provides a (possibly templated) overload of\n ``to_string_view`` which takes an instance of the string class\n ``StringType`` and returns a ``fmt::basic_string_view``.\n The conversion function must live in the very same namespace as\n ``StringType`` to be picked up by ADL. Non-templated string types\n like f.e. QString must return a ``basic_string_view`` with a fixed matching\n char type.\n\n **Example**::\n\n namespace my_ns {\n inline string_view to_string_view(const my_string &s) {\n return { s.data(), s.length() };\n }\n }\n\n std::string message = fmt::format(my_string(\"The answer is {}\"), 42);\n \\endrst\n */\ntemplate \ninline basic_string_view\n to_string_view(basic_string_view s) { return s; }\n\ntemplate \ninline basic_string_view\n to_string_view(const std::basic_string &s) { return s; }\n\ntemplate \ninline basic_string_view to_string_view(const Char *s) { return s; }\n\n#ifdef FMT_STRING_VIEW\ntemplate \ninline basic_string_view\n to_string_view(FMT_STRING_VIEW s) { return s; }\n#endif\n\n// A base class for compile-time strings. It is defined in the fmt namespace to\n// make formatting functions visible via ADL, e.g. format(fmt(\"{}\"), 42).\nstruct compile_string {};\n\ntemplate \nstruct is_compile_string : std::is_base_of {};\n\ntemplate <\n typename S,\n typename Enable = typename std::enable_if::value>::type>\nFMT_CONSTEXPR basic_string_view\n to_string_view(const S &s) { return s; }\n\ntemplate \nclass basic_format_arg;\n\ntemplate \nclass basic_format_args;\n\n// A formatter for objects of type T.\ntemplate \nstruct formatter {\n static_assert(internal::no_formatter_error::value,\n \"don't know how to format the type, include fmt/ostream.h if it provides \"\n \"an operator<< that should be used\");\n\n // The following functions are not defined intentionally.\n template \n typename ParseContext::iterator parse(ParseContext &);\n template \n auto format(const T &val, FormatContext &ctx) -> decltype(ctx.out());\n};\n\ntemplate \nstruct convert_to_int: std::integral_constant<\n bool, !std::is_arithmetic::value && std::is_convertible::value> {};\n\nnamespace internal {\n\nstruct dummy_string_view { typedef void char_type; };\ndummy_string_view to_string_view(...);\nusing fmt::v5::to_string_view;\n\n// Specifies whether S is a string type convertible to fmt::basic_string_view.\ntemplate \nstruct is_string : std::integral_constant()))>::value> {};\n\ntemplate \nstruct char_t {\n typedef decltype(to_string_view(declval())) result;\n typedef typename result::char_type type;\n};\n\ntemplate \nstruct named_arg_base;\n\ntemplate \nstruct named_arg;\n\nenum type {\n none_type, named_arg_type,\n // Integer types should go first,\n int_type, uint_type, long_long_type, ulong_long_type, bool_type, char_type,\n last_integer_type = char_type,\n // followed by floating-point types.\n double_type, long_double_type, last_numeric_type = long_double_type,\n cstring_type, string_type, pointer_type, custom_type\n};\n\nFMT_CONSTEXPR bool is_integral(type t) {\n FMT_ASSERT(t != internal::named_arg_type, \"invalid argument type\");\n return t > internal::none_type && t <= internal::last_integer_type;\n}\n\nFMT_CONSTEXPR bool is_arithmetic(type t) {\n FMT_ASSERT(t != internal::named_arg_type, \"invalid argument type\");\n return t > internal::none_type && t <= internal::last_numeric_type;\n}\n\ntemplate \nstruct string_value {\n const Char *value;\n std::size_t size;\n};\n\ntemplate \nstruct custom_value {\n const void *value;\n void (*format)(const void *arg, Context &ctx);\n};\n\n// A formatting argument value.\ntemplate \nclass value {\n public:\n typedef typename Context::char_type char_type;\n\n union {\n int int_value;\n unsigned uint_value;\n long long long_long_value;\n unsigned long long ulong_long_value;\n double double_value;\n long double long_double_value;\n const void *pointer;\n string_value string;\n string_value sstring;\n string_value ustring;\n custom_value custom;\n };\n\n FMT_CONSTEXPR value(int val = 0) : int_value(val) {}\n value(unsigned val) { uint_value = val; }\n value(long long val) { long_long_value = val; }\n value(unsigned long long val) { ulong_long_value = val; }\n value(double val) { double_value = val; }\n value(long double val) { long_double_value = val; }\n value(const char_type *val) { string.value = val; }\n value(const signed char *val) {\n static_assert(std::is_same::value,\n \"incompatible string types\");\n sstring.value = val;\n }\n value(const unsigned char *val) {\n static_assert(std::is_same::value,\n \"incompatible string types\");\n ustring.value = val;\n }\n value(basic_string_view val) {\n string.value = val.data();\n string.size = val.size();\n }\n value(const void *val) { pointer = val; }\n\n template \n explicit value(const T &val) {\n custom.value = &val;\n custom.format = &format_custom_arg;\n }\n\n const named_arg_base &as_named_arg() {\n return *static_cast*>(pointer);\n }\n\n private:\n // Formats an argument of a custom type, such as a user-defined class.\n template \n static void format_custom_arg(const void *arg, Context &ctx) {\n // Get the formatter type through the context to allow different contexts\n // have different extension points, e.g. `formatter` for `format` and\n // `printf_formatter` for `printf`.\n typename Context::template formatter_type::type f;\n auto &&parse_ctx = ctx.parse_context();\n parse_ctx.advance_to(f.parse(parse_ctx));\n ctx.advance_to(f.format(*static_cast(arg), ctx));\n }\n};\n\n// Value initializer used to delay conversion to value and reduce memory churn.\ntemplate \nstruct init {\n T val;\n static const type type_tag = TYPE;\n\n FMT_CONSTEXPR init(const T &v) : val(v) {}\n FMT_CONSTEXPR operator value() const { return value(val); }\n};\n\ntemplate \nFMT_CONSTEXPR basic_format_arg make_arg(const T &value);\n\n#define FMT_MAKE_VALUE(TAG, ArgType, ValueType) \\\n template \\\n FMT_CONSTEXPR init make_value(ArgType val) { \\\n return static_cast(val); \\\n }\n\n#define FMT_MAKE_VALUE_SAME(TAG, Type) \\\n template \\\n FMT_CONSTEXPR init make_value(Type val) { return val; }\n\nFMT_MAKE_VALUE(bool_type, bool, int)\nFMT_MAKE_VALUE(int_type, short, int)\nFMT_MAKE_VALUE(uint_type, unsigned short, unsigned)\nFMT_MAKE_VALUE_SAME(int_type, int)\nFMT_MAKE_VALUE_SAME(uint_type, unsigned)\n\n// To minimize the number of types we need to deal with, long is translated\n// either to int or to long long depending on its size.\ntypedef std::conditional::type\n long_type;\nFMT_MAKE_VALUE(\n (sizeof(long) == sizeof(int) ? int_type : long_long_type), long, long_type)\ntypedef std::conditional::type ulong_type;\nFMT_MAKE_VALUE(\n (sizeof(unsigned long) == sizeof(unsigned) ? uint_type : ulong_long_type),\n unsigned long, ulong_type)\n\nFMT_MAKE_VALUE_SAME(long_long_type, long long)\nFMT_MAKE_VALUE_SAME(ulong_long_type, unsigned long long)\nFMT_MAKE_VALUE(int_type, signed char, int)\nFMT_MAKE_VALUE(uint_type, unsigned char, unsigned)\n\n// This doesn't use FMT_MAKE_VALUE because of ambiguity in gcc 4.4.\ntemplate \nFMT_CONSTEXPR typename std::enable_if<\n std::is_same::value,\n init>::type make_value(Char val) { return val; }\n\ntemplate \nFMT_CONSTEXPR typename std::enable_if<\n !std::is_same::value,\n init>::type make_value(char val) { return val; }\n\nFMT_MAKE_VALUE(double_type, float, double)\nFMT_MAKE_VALUE_SAME(double_type, double)\nFMT_MAKE_VALUE_SAME(long_double_type, long double)\n\n// Formatting of wide strings into a narrow buffer and multibyte strings\n// into a wide buffer is disallowed (https://github.com/fmtlib/fmt/pull/606).\nFMT_MAKE_VALUE(cstring_type, typename C::char_type*,\n const typename C::char_type*)\nFMT_MAKE_VALUE(cstring_type, const typename C::char_type*,\n const typename C::char_type*)\n\nFMT_MAKE_VALUE(cstring_type, signed char*, const signed char*)\nFMT_MAKE_VALUE_SAME(cstring_type, const signed char*)\nFMT_MAKE_VALUE(cstring_type, unsigned char*, const unsigned char*)\nFMT_MAKE_VALUE_SAME(cstring_type, const unsigned char*)\nFMT_MAKE_VALUE_SAME(string_type, basic_string_view)\nFMT_MAKE_VALUE(string_type,\n typename basic_string_view::type,\n basic_string_view)\nFMT_MAKE_VALUE(string_type, const std::basic_string&,\n basic_string_view)\nFMT_MAKE_VALUE(pointer_type, void*, const void*)\nFMT_MAKE_VALUE_SAME(pointer_type, const void*)\n\n#if FMT_USE_NULLPTR\nFMT_MAKE_VALUE(pointer_type, std::nullptr_t, const void*)\n#endif\n\n// Formatting of arbitrary pointers is disallowed. If you want to output a\n// pointer cast it to \"void *\" or \"const void *\". In particular, this forbids\n// formatting of \"[const] volatile char *\" which is printed as bool by\n// iostreams.\ntemplate \ntypename std::enable_if::value>::type\n make_value(const T *) {\n static_assert(!sizeof(T), \"formatting of non-void pointers is disallowed\");\n}\n\ntemplate \ninline typename std::enable_if<\n std::is_enum::value && convert_to_int::value,\n init>::type\n make_value(const T &val) { return static_cast(val); }\n\ntemplate \ninline typename std::enable_if<\n is_constructible, T>::value &&\n !internal::is_string::value,\n init, string_type>>::type\n make_value(const T &val) { return basic_string_view(val); }\n\ntemplate \ninline typename std::enable_if<\n !convert_to_int::value && !std::is_same::value &&\n !std::is_convertible>::value &&\n !is_constructible, T>::value &&\n !internal::is_string::value,\n // Implicit conversion to std::string is not handled here because it's\n // unsafe: https://github.com/fmtlib/fmt/issues/729\n init>::type\n make_value(const T &val) { return val; }\n\ntemplate \ninit\n make_value(const named_arg &val) {\n basic_format_arg arg = make_arg(val.value);\n std::memcpy(val.data, &arg, sizeof(arg));\n return static_cast(&val);\n}\n\ntemplate \nFMT_CONSTEXPR11 typename std::enable_if<\n internal::is_string::value,\n init, string_type>>::type\n make_value(const S &val) {\n // Handle adapted strings.\n static_assert(std::is_same<\n typename C::char_type, typename internal::char_t::type>::value,\n \"mismatch between char-types of context and argument\");\n return to_string_view(val);\n}\n\n// Maximum number of arguments with packed types.\nenum { max_packed_args = 15 };\n\ntemplate \nclass arg_map;\n} // namespace internal\n\n// A formatting argument. It is a trivially copyable/constructible type to\n// allow storage in basic_memory_buffer.\ntemplate \nclass basic_format_arg {\n private:\n internal::value value_;\n internal::type type_;\n\n template \n friend FMT_CONSTEXPR basic_format_arg\n internal::make_arg(const T &value);\n\n template \n friend FMT_CONSTEXPR typename internal::result_of::type\n visit_format_arg(Visitor &&vis, const basic_format_arg &arg);\n\n friend class basic_format_args;\n friend class internal::arg_map;\n\n typedef typename Context::char_type char_type;\n\n public:\n class handle {\n public:\n explicit handle(internal::custom_value custom): custom_(custom) {}\n\n void format(Context &ctx) const { custom_.format(custom_.value, ctx); }\n\n private:\n internal::custom_value custom_;\n };\n\n FMT_CONSTEXPR basic_format_arg() : type_(internal::none_type) {}\n\n FMT_EXPLICIT operator bool() const FMT_NOEXCEPT {\n return type_ != internal::none_type;\n }\n\n internal::type type() const { return type_; }\n\n bool is_integral() const { return internal::is_integral(type_); }\n bool is_arithmetic() const { return internal::is_arithmetic(type_); }\n};\n\nstruct monostate {};\n\n/**\n \\rst\n Visits an argument dispatching to the appropriate visit method based on\n the argument type. For example, if the argument type is ``double`` then\n ``vis(value)`` will be called with the value of type ``double``.\n \\endrst\n */\ntemplate \nFMT_CONSTEXPR typename internal::result_of::type\n visit_format_arg(Visitor &&vis, const basic_format_arg &arg) {\n typedef typename Context::char_type char_type;\n switch (arg.type_) {\n case internal::none_type:\n break;\n case internal::named_arg_type:\n FMT_ASSERT(false, \"invalid argument type\");\n break;\n case internal::int_type:\n return vis(arg.value_.int_value);\n case internal::uint_type:\n return vis(arg.value_.uint_value);\n case internal::long_long_type:\n return vis(arg.value_.long_long_value);\n case internal::ulong_long_type:\n return vis(arg.value_.ulong_long_value);\n case internal::bool_type:\n return vis(arg.value_.int_value != 0);\n case internal::char_type:\n return vis(static_cast(arg.value_.int_value));\n case internal::double_type:\n return vis(arg.value_.double_value);\n case internal::long_double_type:\n return vis(arg.value_.long_double_value);\n case internal::cstring_type:\n return vis(arg.value_.string.value);\n case internal::string_type:\n return vis(basic_string_view(\n arg.value_.string.value, arg.value_.string.size));\n case internal::pointer_type:\n return vis(arg.value_.pointer);\n case internal::custom_type:\n return vis(typename basic_format_arg::handle(arg.value_.custom));\n }\n return vis(monostate());\n}\n\ntemplate \nFMT_CONSTEXPR typename internal::result_of::type\n visit(Visitor &&vis, const basic_format_arg &arg) {\n return visit_format_arg(std::forward(vis), arg);\n}\n\n// Parsing context consisting of a format string range being parsed and an\n// argument counter for automatic indexing.\ntemplate \nclass basic_parse_context : private ErrorHandler {\n private:\n basic_string_view format_str_;\n int next_arg_id_;\n\n public:\n typedef Char char_type;\n typedef typename basic_string_view::iterator iterator;\n\n explicit FMT_CONSTEXPR basic_parse_context(\n basic_string_view format_str, ErrorHandler eh = ErrorHandler())\n : ErrorHandler(eh), format_str_(format_str), next_arg_id_(0) {}\n\n // Returns an iterator to the beginning of the format string range being\n // parsed.\n FMT_CONSTEXPR iterator begin() const FMT_NOEXCEPT {\n return format_str_.begin();\n }\n\n // Returns an iterator past the end of the format string range being parsed.\n FMT_CONSTEXPR iterator end() const FMT_NOEXCEPT { return format_str_.end(); }\n\n // Advances the begin iterator to ``it``.\n FMT_CONSTEXPR void advance_to(iterator it) {\n format_str_.remove_prefix(internal::to_unsigned(it - begin()));\n }\n\n // Returns the next argument index.\n FMT_CONSTEXPR unsigned next_arg_id();\n\n FMT_CONSTEXPR bool check_arg_id(unsigned) {\n if (next_arg_id_ > 0) {\n on_error(\"cannot switch from automatic to manual argument indexing\");\n return false;\n }\n next_arg_id_ = -1;\n return true;\n }\n void check_arg_id(basic_string_view) {}\n\n FMT_CONSTEXPR void on_error(const char *message) {\n ErrorHandler::on_error(message);\n }\n\n FMT_CONSTEXPR ErrorHandler error_handler() const { return *this; }\n};\n\ntypedef basic_parse_context parse_context;\ntypedef basic_parse_context wparse_context;\n\nnamespace internal {\n// A map from argument names to their values for named arguments.\ntemplate \nclass arg_map {\n private:\n arg_map(const arg_map &) = delete;\n void operator=(const arg_map &) = delete;\n\n typedef typename Context::char_type char_type;\n\n struct entry {\n basic_string_view name;\n basic_format_arg arg;\n };\n\n entry *map_;\n unsigned size_;\n\n void push_back(value val) {\n const internal::named_arg_base &named = val.as_named_arg();\n map_[size_] = entry{named.name, named.template deserialize()};\n ++size_;\n }\n\n public:\n arg_map() : map_(FMT_NULL), size_(0) {}\n void init(const basic_format_args &args);\n ~arg_map() { delete [] map_; }\n\n basic_format_arg find(basic_string_view name) const {\n // The list is unsorted, so just return the first matching name.\n for (entry *it = map_, *end = map_ + size_; it != end; ++it) {\n if (it->name == name)\n return it->arg;\n }\n return {};\n }\n};\n\n// A type-erased reference to an std::locale to avoid heavy include.\nclass locale_ref {\n private:\n const void *locale_; // A type-erased pointer to std::locale.\n friend class locale;\n\n public:\n locale_ref() : locale_(FMT_NULL) {}\n\n template \n explicit locale_ref(const Locale &loc);\n\n template \n Locale get() const;\n};\n\ntemplate \nclass context_base {\n public:\n typedef OutputIt iterator;\n\n private:\n basic_parse_context parse_context_;\n iterator out_;\n basic_format_args args_;\n locale_ref loc_;\n\n protected:\n typedef Char char_type;\n typedef basic_format_arg format_arg;\n\n context_base(OutputIt out, basic_string_view format_str,\n basic_format_args ctx_args,\n locale_ref loc = locale_ref())\n : parse_context_(format_str), out_(out), args_(ctx_args), loc_(loc) {}\n\n // Returns the argument with specified index.\n format_arg do_get_arg(unsigned arg_id) {\n format_arg arg = args_.get(arg_id);\n if (!arg)\n parse_context_.on_error(\"argument index out of range\");\n return arg;\n }\n\n // Checks if manual indexing is used and returns the argument with\n // specified index.\n format_arg get_arg(unsigned arg_id) {\n return this->parse_context().check_arg_id(arg_id) ?\n this->do_get_arg(arg_id) : format_arg();\n }\n\n public:\n basic_parse_context &parse_context() { return parse_context_; }\n basic_format_args args() const { return args_; }\n\n internal::error_handler error_handler() {\n return parse_context_.error_handler();\n }\n\n void on_error(const char *message) { parse_context_.on_error(message); }\n\n // Returns an iterator to the beginning of the output range.\n iterator out() { return out_; }\n iterator begin() { return out_; } // deprecated\n\n // Advances the begin iterator to ``it``.\n void advance_to(iterator it) { out_ = it; }\n\n locale_ref locale() { return loc_; }\n};\n\ntemplate \nstruct get_type {\n typedef decltype(make_value(\n declval::type&>())) value_type;\n static const type value = value_type::type_tag;\n};\n\ntemplate \nFMT_CONSTEXPR11 unsigned long long get_types() { return 0; }\n\ntemplate \nFMT_CONSTEXPR11 unsigned long long get_types() {\n return get_type::value | (get_types() << 4);\n}\n\ntemplate \nFMT_CONSTEXPR basic_format_arg make_arg(const T &value) {\n basic_format_arg arg;\n arg.type_ = get_type::value;\n arg.value_ = make_value(value);\n return arg;\n}\n\ntemplate \ninline typename std::enable_if>::type\n make_arg(const T &value) {\n return make_value(value);\n}\n\ntemplate \ninline typename std::enable_if>::type\n make_arg(const T &value) {\n return make_arg(value);\n}\n} // namespace internal\n\n// Formatting context.\ntemplate \nclass basic_format_context :\n public internal::context_base<\n OutputIt, basic_format_context, Char> {\n public:\n /** The character type for the output. */\n typedef Char char_type;\n\n // using formatter_type = formatter;\n template \n struct formatter_type { typedef formatter type; };\n\n private:\n internal::arg_map map_;\n\n basic_format_context(const basic_format_context &) = delete;\n void operator=(const basic_format_context &) = delete;\n\n typedef internal::context_base base;\n typedef typename base::format_arg format_arg;\n using base::get_arg;\n\n public:\n using typename base::iterator;\n\n /**\n Constructs a ``basic_format_context`` object. References to the arguments are\n stored in the object so make sure they have appropriate lifetimes.\n */\n basic_format_context(OutputIt out, basic_string_view format_str,\n basic_format_args ctx_args,\n internal::locale_ref loc = internal::locale_ref())\n : base(out, format_str, ctx_args, loc) {}\n\n format_arg next_arg() {\n return this->do_get_arg(this->parse_context().next_arg_id());\n }\n format_arg get_arg(unsigned arg_id) { return this->do_get_arg(arg_id); }\n\n // Checks if manual indexing is used and returns the argument with the\n // specified name.\n format_arg get_arg(basic_string_view name);\n};\n\ntemplate \nstruct buffer_context {\n typedef basic_format_context<\n std::back_insert_iterator>, Char> type;\n};\ntypedef buffer_context::type format_context;\ntypedef buffer_context::type wformat_context;\n\n/**\n \\rst\n An array of references to arguments. It can be implicitly converted into\n `~fmt::basic_format_args` for passing into type-erased formatting functions\n such as `~fmt::vformat`.\n \\endrst\n */\ntemplate \nclass format_arg_store {\n private:\n static const size_t NUM_ARGS = sizeof...(Args);\n\n // Packed is a macro on MinGW so use IS_PACKED instead.\n static const bool IS_PACKED = NUM_ARGS < internal::max_packed_args;\n\n typedef typename std::conditional, basic_format_arg>::type value_type;\n\n // If the arguments are not packed, add one more element to mark the end.\n static const size_t DATA_SIZE =\n NUM_ARGS + (IS_PACKED && NUM_ARGS != 0 ? 0 : 1);\n value_type data_[DATA_SIZE];\n\n friend class basic_format_args;\n\n static FMT_CONSTEXPR11 long long get_types() {\n return IS_PACKED ?\n static_cast(internal::get_types()) :\n -static_cast(NUM_ARGS);\n }\n\n public:\n#if FMT_USE_CONSTEXPR11\n static FMT_CONSTEXPR11 long long TYPES = get_types();\n#else\n static const long long TYPES;\n#endif\n\n#if (FMT_GCC_VERSION && FMT_GCC_VERSION <= 405) || \\\n (FMT_MSC_VER && FMT_MSC_VER <= 1800)\n // Workaround array initialization issues in gcc <= 4.5 and MSVC <= 2013.\n format_arg_store(const Args &... args) {\n value_type init[DATA_SIZE] =\n {internal::make_arg(args)...};\n std::memcpy(data_, init, sizeof(init));\n }\n#else\n format_arg_store(const Args &... args)\n : data_{internal::make_arg(args)...} {}\n#endif\n};\n\n#if !FMT_USE_CONSTEXPR11\ntemplate \nconst long long format_arg_store::TYPES = get_types();\n#endif\n\n/**\n \\rst\n Constructs an `~fmt::format_arg_store` object that contains references to\n arguments and can be implicitly converted to `~fmt::format_args`. `Context`\n can be omitted in which case it defaults to `~fmt::context`.\n \\endrst\n */\ntemplate \ninline format_arg_store\n make_format_args(const Args &... args) { return {args...}; }\n\ntemplate \ninline format_arg_store\n make_format_args(const Args &... args) { return {args...}; }\n\n/** Formatting arguments. */\ntemplate \nclass basic_format_args {\n public:\n typedef unsigned size_type;\n typedef basic_format_arg format_arg;\n\n private:\n // To reduce compiled code size per formatting function call, types of first\n // max_packed_args arguments are passed in the types_ field.\n unsigned long long types_;\n union {\n // If the number of arguments is less than max_packed_args, the argument\n // values are stored in values_, otherwise they are stored in args_.\n // This is done to reduce compiled code size as storing larger objects\n // may require more code (at least on x86-64) even if the same amount of\n // data is actually copied to stack. It saves ~10% on the bloat test.\n const internal::value *values_;\n const format_arg *args_;\n };\n\n typename internal::type type(unsigned index) const {\n unsigned shift = index * 4;\n unsigned long long mask = 0xf;\n return static_cast(\n (types_ & (mask << shift)) >> shift);\n }\n\n friend class internal::arg_map;\n\n void set_data(const internal::value *values) { values_ = values; }\n void set_data(const format_arg *args) { args_ = args; }\n\n format_arg do_get(size_type index) const {\n format_arg arg;\n long long signed_types = static_cast(types_);\n if (signed_types < 0) {\n unsigned long long num_args =\n static_cast(-signed_types);\n if (index < num_args)\n arg = args_[index];\n return arg;\n }\n if (index > internal::max_packed_args)\n return arg;\n arg.type_ = type(index);\n if (arg.type_ == internal::none_type)\n return arg;\n internal::value &val = arg.value_;\n val = values_[index];\n return arg;\n }\n\n public:\n basic_format_args() : types_(0) {}\n\n /**\n \\rst\n Constructs a `basic_format_args` object from `~fmt::format_arg_store`.\n \\endrst\n */\n template \n basic_format_args(const format_arg_store &store)\n : types_(static_cast(store.TYPES)) {\n set_data(store.data_);\n }\n\n /**\n \\rst\n Constructs a `basic_format_args` object from a dynamic set of arguments.\n \\endrst\n */\n basic_format_args(const format_arg *args, size_type count)\n : types_(-static_cast(count)) {\n set_data(args);\n }\n\n /** Returns the argument at specified index. */\n format_arg get(size_type index) const {\n format_arg arg = do_get(index);\n if (arg.type_ == internal::named_arg_type)\n arg = arg.value_.as_named_arg().template deserialize();\n return arg;\n }\n\n unsigned max_size() const {\n long long signed_types = static_cast(types_);\n return static_cast(\n signed_types < 0 ?\n -signed_types : static_cast(internal::max_packed_args));\n }\n};\n\n/** An alias to ``basic_format_args``. */\n// It is a separate type rather than a typedef to make symbols readable.\nstruct format_args : basic_format_args {\n template \n format_args(Args &&... arg)\n : basic_format_args(std::forward(arg)...) {}\n};\nstruct wformat_args : basic_format_args {\n template \n wformat_args(Args &&... arg)\n : basic_format_args(std::forward(arg)...) {}\n};\n\n#ifndef FMT_USE_ALIAS_TEMPLATES\n# define FMT_USE_ALIAS_TEMPLATES FMT_HAS_FEATURE(cxx_alias_templates)\n#endif\n#if FMT_USE_ALIAS_TEMPLATES\n/** String's character type. */\ntemplate \nusing char_t = typename std::enable_if::value,\n typename internal::char_t::type>::type;\n#define FMT_CHAR(S) fmt::char_t\n\ntemplate \nusing enable_if_string_t =\n typename std::enable_if::value, T>::type;\n#define FMT_ENABLE_IF_STRING(S, T) enable_if_string_t\n#else\ntemplate \nstruct char_t : std::enable_if<\n internal::is_string::value, typename internal::char_t::type> {};\n#define FMT_CHAR(S) typename char_t::type\n\n#define FMT_ENABLE_IF_STRING(S, T) \\\n typename std::enable_if::value, T>::type\n#endif\n\nnamespace internal {\ntemplate \nstruct named_arg_base {\n basic_string_view name;\n\n // Serialized value.\n mutable char data[\n sizeof(basic_format_arg::type>)];\n\n named_arg_base(basic_string_view nm) : name(nm) {}\n\n template \n basic_format_arg deserialize() const {\n basic_format_arg arg;\n std::memcpy(&arg, data, sizeof(basic_format_arg));\n return arg;\n }\n};\n\ntemplate \nstruct named_arg : named_arg_base {\n const T &value;\n\n named_arg(basic_string_view name, const T &val)\n : named_arg_base(name), value(val) {}\n};\n\ntemplate \ninline typename std::enable_if::value>::type\n check_format_string(const S &) {}\ntemplate \ntypename std::enable_if::value>::type\n check_format_string(S);\n\ntemplate \nstruct checked_args : format_arg_store<\n typename buffer_context::type, Args...> {\n typedef typename buffer_context::type context;\n\n checked_args(const S &format_str, const Args &... args):\n format_arg_store(args...) {\n internal::check_format_string(format_str);\n }\n\n basic_format_args operator*() const { return *this; }\n};\n\ntemplate \nstd::basic_string vformat(\n basic_string_view format_str,\n basic_format_args::type> args);\n\ntemplate \ntypename buffer_context::type::iterator vformat_to(\n internal::basic_buffer &buf, basic_string_view format_str,\n basic_format_args::type> args);\n}\n\n/**\n \\rst\n Returns a named argument to be used in a formatting function.\n\n **Example**::\n\n fmt::print(\"Elapsed time: {s:.2f} seconds\", fmt::arg(\"s\", 1.23));\n \\endrst\n */\ntemplate \ninline internal::named_arg arg(string_view name, const T &arg) {\n return {name, arg};\n}\n\ntemplate \ninline internal::named_arg arg(wstring_view name, const T &arg) {\n return {name, arg};\n}\n\n// Disable nested named arguments, e.g. ``arg(\"a\", arg(\"b\", 42))``.\ntemplate \nvoid arg(S, internal::named_arg) = delete;\n\ntemplate \nstruct is_contiguous: std::false_type {};\n\ntemplate \nstruct is_contiguous >: std::true_type {};\n\ntemplate \nstruct is_contiguous >: std::true_type {};\n\n/** Formats a string and writes the output to ``out``. */\ntemplate \ntypename std::enable_if<\n is_contiguous::value, std::back_insert_iterator>::type\n vformat_to(\n std::back_insert_iterator out,\n const S &format_str,\n basic_format_args::type> args) {\n internal::container_buffer buf(internal::get_container(out));\n internal::vformat_to(buf, to_string_view(format_str), args);\n return out;\n}\n\ntemplate \ninline typename std::enable_if<\n is_contiguous::value && internal::is_string::value,\n std::back_insert_iterator>::type\n format_to(std::back_insert_iterator out, const S &format_str,\n const Args &... args) {\n internal::checked_args ca(format_str, args...);\n return vformat_to(out, to_string_view(format_str), *ca);\n}\n\ntemplate \ninline std::basic_string vformat(\n const S &format_str,\n basic_format_args::type> args) {\n return internal::vformat(to_string_view(format_str), args);\n}\n\n/**\n \\rst\n Formats arguments and returns the result as a string.\n\n **Example**::\n\n #include \n std::string message = fmt::format(\"The answer is {}\", 42);\n \\endrst\n*/\ntemplate \ninline std::basic_string format(\n const S &format_str, const Args &... args) {\n return internal::vformat(\n to_string_view(format_str),\n *internal::checked_args(format_str, args...));\n}\n\nFMT_API void vprint(std::FILE *f, string_view format_str, format_args args);\nFMT_API void vprint(std::FILE *f, wstring_view format_str, wformat_args args);\n\n/**\n \\rst\n Prints formatted data to the file *f*. For wide format strings,\n *f* should be in wide-oriented mode set via ``fwide(f, 1)`` or\n ``_setmode(_fileno(f), _O_U8TEXT)`` on Windows.\n\n **Example**::\n\n fmt::print(stderr, \"Don't {}!\", \"panic\");\n \\endrst\n */\ntemplate \ninline FMT_ENABLE_IF_STRING(S, void)\n print(std::FILE *f, const S &format_str, const Args &... args) {\n vprint(f, to_string_view(format_str),\n internal::checked_args(format_str, args...));\n}\n\nFMT_API void vprint(string_view format_str, format_args args);\nFMT_API void vprint(wstring_view format_str, wformat_args args);\n\n/**\n \\rst\n Prints formatted data to ``stdout``.\n\n **Example**::\n\n fmt::print(\"Elapsed time: {0:.2f} seconds\", 1.23);\n \\endrst\n */\ntemplate \ninline FMT_ENABLE_IF_STRING(S, void)\n print(const S &format_str, const Args &... args) {\n vprint(to_string_view(format_str),\n internal::checked_args(format_str, args...));\n}\nFMT_END_NAMESPACE\n\n#endif // FMT_CORE_H_\n" }, { "path": "src/DRAMsim3/ext/fmt/include/fmt/format-inl.h", "content": "// Formatting library for C++\n//\n// Copyright (c) 2012 - 2016, Victor Zverovich\n// All rights reserved.\n//\n// For the license information refer to format.h.\n\n#ifndef FMT_FORMAT_INL_H_\n#define FMT_FORMAT_INL_H_\n\n#include \"format.h\"\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include // for std::ptrdiff_t\n#include // for std::memmove\n#if !defined(FMT_STATIC_THOUSANDS_SEPARATOR)\n# include \n#endif\n\n#if FMT_USE_WINDOWS_H\n# if !defined(FMT_HEADER_ONLY) && !defined(WIN32_LEAN_AND_MEAN)\n# define WIN32_LEAN_AND_MEAN\n# endif\n# if defined(NOMINMAX) || defined(FMT_WIN_MINMAX)\n# include \n# else\n# define NOMINMAX\n# include \n# undef NOMINMAX\n# endif\n#endif\n\n#if FMT_EXCEPTIONS\n# define FMT_TRY try\n# define FMT_CATCH(x) catch (x)\n#else\n# define FMT_TRY if (true)\n# define FMT_CATCH(x) if (false)\n#endif\n\n#ifdef _MSC_VER\n# pragma warning(push)\n# pragma warning(disable: 4127) // conditional expression is constant\n# pragma warning(disable: 4702) // unreachable code\n// Disable deprecation warning for strerror. The latter is not called but\n// MSVC fails to detect it.\n# pragma warning(disable: 4996)\n#endif\n\n// Dummy implementations of strerror_r and strerror_s called if corresponding\n// system functions are not available.\ninline fmt::internal::null<> strerror_r(int, char *, ...) {\n return fmt::internal::null<>();\n}\ninline fmt::internal::null<> strerror_s(char *, std::size_t, ...) {\n return fmt::internal::null<>();\n}\n\nFMT_BEGIN_NAMESPACE\n\nnamespace {\n\n#ifndef _MSC_VER\n# define FMT_SNPRINTF snprintf\n#else // _MSC_VER\ninline int fmt_snprintf(char *buffer, size_t size, const char *format, ...) {\n va_list args;\n va_start(args, format);\n int result = vsnprintf_s(buffer, size, _TRUNCATE, format, args);\n va_end(args);\n return result;\n}\n# define FMT_SNPRINTF fmt_snprintf\n#endif // _MSC_VER\n\n#if defined(_WIN32) && defined(__MINGW32__) && !defined(__NO_ISOCEXT)\n# define FMT_SWPRINTF snwprintf\n#else\n# define FMT_SWPRINTF swprintf\n#endif // defined(_WIN32) && defined(__MINGW32__) && !defined(__NO_ISOCEXT)\n\ntypedef void (*FormatFunc)(internal::buffer &, int, string_view);\n\n// Portable thread-safe version of strerror.\n// Sets buffer to point to a string describing the error code.\n// This can be either a pointer to a string stored in buffer,\n// or a pointer to some static immutable string.\n// Returns one of the following values:\n// 0 - success\n// ERANGE - buffer is not large enough to store the error message\n// other - failure\n// Buffer should be at least of size 1.\nint safe_strerror(\n int error_code, char *&buffer, std::size_t buffer_size) FMT_NOEXCEPT {\n FMT_ASSERT(buffer != FMT_NULL && buffer_size != 0, \"invalid buffer\");\n\n class dispatcher {\n private:\n int error_code_;\n char *&buffer_;\n std::size_t buffer_size_;\n\n // A noop assignment operator to avoid bogus warnings.\n void operator=(const dispatcher &) {}\n\n // Handle the result of XSI-compliant version of strerror_r.\n int handle(int result) {\n // glibc versions before 2.13 return result in errno.\n return result == -1 ? errno : result;\n }\n\n // Handle the result of GNU-specific version of strerror_r.\n int handle(char *message) {\n // If the buffer is full then the message is probably truncated.\n if (message == buffer_ && strlen(buffer_) == buffer_size_ - 1)\n return ERANGE;\n buffer_ = message;\n return 0;\n }\n\n // Handle the case when strerror_r is not available.\n int handle(internal::null<>) {\n return fallback(strerror_s(buffer_, buffer_size_, error_code_));\n }\n\n // Fallback to strerror_s when strerror_r is not available.\n int fallback(int result) {\n // If the buffer is full then the message is probably truncated.\n return result == 0 && strlen(buffer_) == buffer_size_ - 1 ?\n ERANGE : result;\n }\n\n // Fallback to strerror if strerror_r and strerror_s are not available.\n int fallback(internal::null<>) {\n errno = 0;\n buffer_ = strerror(error_code_);\n return errno;\n }\n\n public:\n dispatcher(int err_code, char *&buf, std::size_t buf_size)\n : error_code_(err_code), buffer_(buf), buffer_size_(buf_size) {}\n\n int run() {\n return handle(strerror_r(error_code_, buffer_, buffer_size_));\n }\n };\n return dispatcher(error_code, buffer, buffer_size).run();\n}\n\nvoid format_error_code(internal::buffer &out, int error_code,\n string_view message) FMT_NOEXCEPT {\n // Report error code making sure that the output fits into\n // inline_buffer_size to avoid dynamic memory allocation and potential\n // bad_alloc.\n out.resize(0);\n static const char SEP[] = \": \";\n static const char ERROR_STR[] = \"error \";\n // Subtract 2 to account for terminating null characters in SEP and ERROR_STR.\n std::size_t error_code_size = sizeof(SEP) + sizeof(ERROR_STR) - 2;\n typedef internal::int_traits::main_type main_type;\n main_type abs_value = static_cast(error_code);\n if (internal::is_negative(error_code)) {\n abs_value = 0 - abs_value;\n ++error_code_size;\n }\n error_code_size += internal::count_digits(abs_value);\n writer w(out);\n if (message.size() <= inline_buffer_size - error_code_size) {\n w.write(message);\n w.write(SEP);\n }\n w.write(ERROR_STR);\n w.write(error_code);\n assert(out.size() <= inline_buffer_size);\n}\n\nvoid report_error(FormatFunc func, int error_code,\n string_view message) FMT_NOEXCEPT {\n memory_buffer full_message;\n func(full_message, error_code, message);\n // Use Writer::data instead of Writer::c_str to avoid potential memory\n // allocation.\n std::fwrite(full_message.data(), full_message.size(), 1, stderr);\n std::fputc('\\n', stderr);\n}\n} // namespace\n\nFMT_FUNC size_t internal::count_code_points(basic_string_view s) {\n const char8_t *data = s.data();\n size_t num_code_points = 0;\n for (size_t i = 0, size = s.size(); i != size; ++i) {\n if ((data[i] & 0xc0) != 0x80)\n ++num_code_points;\n }\n return num_code_points;\n}\n\n#if !defined(FMT_STATIC_THOUSANDS_SEPARATOR)\nnamespace internal {\n\ntemplate \nlocale_ref::locale_ref(const Locale &loc) : locale_(&loc) {\n static_assert(std::is_same::value, \"\");\n}\n\ntemplate \nLocale locale_ref::get() const {\n static_assert(std::is_same::value, \"\");\n return locale_ ? *static_cast(locale_) : std::locale();\n}\n\ntemplate \nFMT_FUNC Char thousands_sep_impl(locale_ref loc) {\n return std::use_facet >(\n loc.get()).thousands_sep();\n}\n}\n#else\ntemplate \nFMT_FUNC Char internal::thousands_sep(locale_ref) {\n return FMT_STATIC_THOUSANDS_SEPARATOR;\n}\n#endif\n\nFMT_FUNC void system_error::init(\n int err_code, string_view format_str, format_args args) {\n error_code_ = err_code;\n memory_buffer buffer;\n format_system_error(buffer, err_code, vformat(format_str, args));\n std::runtime_error &base = *this;\n base = std::runtime_error(to_string(buffer));\n}\n\nnamespace internal {\ntemplate \nint char_traits::format_float(\n char *buffer, std::size_t size, const char *format, int precision, T value) {\n return precision < 0 ?\n FMT_SNPRINTF(buffer, size, format, value) :\n FMT_SNPRINTF(buffer, size, format, precision, value);\n}\n\ntemplate \nint char_traits::format_float(\n wchar_t *buffer, std::size_t size, const wchar_t *format, int precision,\n T value) {\n return precision < 0 ?\n FMT_SWPRINTF(buffer, size, format, value) :\n FMT_SWPRINTF(buffer, size, format, precision, value);\n}\n\ntemplate \nconst char basic_data::DIGITS[] =\n \"0001020304050607080910111213141516171819\"\n \"2021222324252627282930313233343536373839\"\n \"4041424344454647484950515253545556575859\"\n \"6061626364656667686970717273747576777879\"\n \"8081828384858687888990919293949596979899\";\n\n#define FMT_POWERS_OF_10(factor) \\\n factor * 10, \\\n factor * 100, \\\n factor * 1000, \\\n factor * 10000, \\\n factor * 100000, \\\n factor * 1000000, \\\n factor * 10000000, \\\n factor * 100000000, \\\n factor * 1000000000\n\ntemplate \nconst uint32_t basic_data::POWERS_OF_10_32[] = {\n 1, FMT_POWERS_OF_10(1)\n};\n\ntemplate \nconst uint32_t basic_data::ZERO_OR_POWERS_OF_10_32[] = {\n 0, FMT_POWERS_OF_10(1)\n};\n\ntemplate \nconst uint64_t basic_data::ZERO_OR_POWERS_OF_10_64[] = {\n 0,\n FMT_POWERS_OF_10(1),\n FMT_POWERS_OF_10(1000000000ull),\n 10000000000000000000ull\n};\n\n// Normalized 64-bit significands of pow(10, k), for k = -348, -340, ..., 340.\n// These are generated by support/compute-powers.py.\ntemplate \nconst uint64_t basic_data::POW10_SIGNIFICANDS[] = {\n 0xfa8fd5a0081c0288, 0xbaaee17fa23ebf76, 0x8b16fb203055ac76,\n 0xcf42894a5dce35ea, 0x9a6bb0aa55653b2d, 0xe61acf033d1a45df,\n 0xab70fe17c79ac6ca, 0xff77b1fcbebcdc4f, 0xbe5691ef416bd60c,\n 0x8dd01fad907ffc3c, 0xd3515c2831559a83, 0x9d71ac8fada6c9b5,\n 0xea9c227723ee8bcb, 0xaecc49914078536d, 0x823c12795db6ce57,\n 0xc21094364dfb5637, 0x9096ea6f3848984f, 0xd77485cb25823ac7,\n 0xa086cfcd97bf97f4, 0xef340a98172aace5, 0xb23867fb2a35b28e,\n 0x84c8d4dfd2c63f3b, 0xc5dd44271ad3cdba, 0x936b9fcebb25c996,\n 0xdbac6c247d62a584, 0xa3ab66580d5fdaf6, 0xf3e2f893dec3f126,\n 0xb5b5ada8aaff80b8, 0x87625f056c7c4a8b, 0xc9bcff6034c13053,\n 0x964e858c91ba2655, 0xdff9772470297ebd, 0xa6dfbd9fb8e5b88f,\n 0xf8a95fcf88747d94, 0xb94470938fa89bcf, 0x8a08f0f8bf0f156b,\n 0xcdb02555653131b6, 0x993fe2c6d07b7fac, 0xe45c10c42a2b3b06,\n 0xaa242499697392d3, 0xfd87b5f28300ca0e, 0xbce5086492111aeb,\n 0x8cbccc096f5088cc, 0xd1b71758e219652c, 0x9c40000000000000,\n 0xe8d4a51000000000, 0xad78ebc5ac620000, 0x813f3978f8940984,\n 0xc097ce7bc90715b3, 0x8f7e32ce7bea5c70, 0xd5d238a4abe98068,\n 0x9f4f2726179a2245, 0xed63a231d4c4fb27, 0xb0de65388cc8ada8,\n 0x83c7088e1aab65db, 0xc45d1df942711d9a, 0x924d692ca61be758,\n 0xda01ee641a708dea, 0xa26da3999aef774a, 0xf209787bb47d6b85,\n 0xb454e4a179dd1877, 0x865b86925b9bc5c2, 0xc83553c5c8965d3d,\n 0x952ab45cfa97a0b3, 0xde469fbd99a05fe3, 0xa59bc234db398c25,\n 0xf6c69a72a3989f5c, 0xb7dcbf5354e9bece, 0x88fcf317f22241e2,\n 0xcc20ce9bd35c78a5, 0x98165af37b2153df, 0xe2a0b5dc971f303a,\n 0xa8d9d1535ce3b396, 0xfb9b7cd9a4a7443c, 0xbb764c4ca7a44410,\n 0x8bab8eefb6409c1a, 0xd01fef10a657842c, 0x9b10a4e5e9913129,\n 0xe7109bfba19c0c9d, 0xac2820d9623bf429, 0x80444b5e7aa7cf85,\n 0xbf21e44003acdd2d, 0x8e679c2f5e44ff8f, 0xd433179d9c8cb841,\n 0x9e19db92b4e31ba9, 0xeb96bf6ebadf77d9, 0xaf87023b9bf0ee6b,\n};\n\n// Binary exponents of pow(10, k), for k = -348, -340, ..., 340, corresponding\n// to significands above.\ntemplate \nconst int16_t basic_data::POW10_EXPONENTS[] = {\n -1220, -1193, -1166, -1140, -1113, -1087, -1060, -1034, -1007, -980, -954,\n -927, -901, -874, -847, -821, -794, -768, -741, -715, -688, -661,\n -635, -608, -582, -555, -529, -502, -475, -449, -422, -396, -369,\n -343, -316, -289, -263, -236, -210, -183, -157, -130, -103, -77,\n -50, -24, 3, 30, 56, 83, 109, 136, 162, 189, 216,\n 242, 269, 295, 322, 348, 375, 402, 428, 455, 481, 508,\n 534, 561, 588, 614, 641, 667, 694, 720, 747, 774, 800,\n 827, 853, 880, 907, 933, 960, 986, 1013, 1039, 1066\n};\n\ntemplate const char basic_data::FOREGROUND_COLOR[] = \"\\x1b[38;2;\";\ntemplate const char basic_data::BACKGROUND_COLOR[] = \"\\x1b[48;2;\";\ntemplate const char basic_data::RESET_COLOR[] = \"\\x1b[0m\";\ntemplate const wchar_t basic_data::WRESET_COLOR[] = L\"\\x1b[0m\";\n\n// A handmade floating-point number f * pow(2, e).\nclass fp {\n private:\n typedef uint64_t significand_type;\n\n // All sizes are in bits.\n static FMT_CONSTEXPR_DECL const int char_size =\n std::numeric_limits::digits;\n // Subtract 1 to account for an implicit most significant bit in the\n // normalized form.\n static FMT_CONSTEXPR_DECL const int double_significand_size =\n std::numeric_limits::digits - 1;\n static FMT_CONSTEXPR_DECL const uint64_t implicit_bit =\n 1ull << double_significand_size;\n\n public:\n significand_type f;\n int e;\n\n static FMT_CONSTEXPR_DECL const int significand_size =\n sizeof(significand_type) * char_size;\n\n fp(): f(0), e(0) {}\n fp(uint64_t f, int e): f(f), e(e) {}\n\n // Constructs fp from an IEEE754 double. It is a template to prevent compile\n // errors on platforms where double is not IEEE754.\n template \n explicit fp(Double d) {\n // Assume double is in the format [sign][exponent][significand].\n typedef std::numeric_limits limits;\n const int double_size = static_cast(sizeof(Double) * char_size);\n const int exponent_size =\n double_size - double_significand_size - 1; // -1 for sign\n const uint64_t significand_mask = implicit_bit - 1;\n const uint64_t exponent_mask = (~0ull >> 1) & ~significand_mask;\n const int exponent_bias = (1 << exponent_size) - limits::max_exponent - 1;\n auto u = bit_cast(d);\n auto biased_e = (u & exponent_mask) >> double_significand_size;\n f = u & significand_mask;\n if (biased_e != 0)\n f += implicit_bit;\n else\n biased_e = 1; // Subnormals use biased exponent 1 (min exponent).\n e = static_cast(biased_e - exponent_bias - double_significand_size);\n }\n\n // Normalizes the value converted from double and multiplied by (1 << SHIFT).\n template \n void normalize() {\n // Handle subnormals.\n auto shifted_implicit_bit = implicit_bit << SHIFT;\n while ((f & shifted_implicit_bit) == 0) {\n f <<= 1;\n --e;\n }\n // Subtract 1 to account for hidden bit.\n auto offset = significand_size - double_significand_size - SHIFT - 1;\n f <<= offset;\n e -= offset;\n }\n\n // Compute lower and upper boundaries (m^- and m^+ in the Grisu paper), where\n // a boundary is a value half way between the number and its predecessor\n // (lower) or successor (upper). The upper boundary is normalized and lower\n // has the same exponent but may be not normalized.\n void compute_boundaries(fp &lower, fp &upper) const {\n lower = f == implicit_bit ?\n fp((f << 2) - 1, e - 2) : fp((f << 1) - 1, e - 1);\n upper = fp((f << 1) + 1, e - 1);\n upper.normalize<1>(); // 1 is to account for the exponent shift above.\n lower.f <<= lower.e - upper.e;\n lower.e = upper.e;\n }\n};\n\n// Returns an fp number representing x - y. Result may not be normalized.\ninline fp operator-(fp x, fp y) {\n FMT_ASSERT(x.f >= y.f && x.e == y.e, \"invalid operands\");\n return fp(x.f - y.f, x.e);\n}\n\n// Computes an fp number r with r.f = x.f * y.f / pow(2, 64) rounded to nearest\n// with half-up tie breaking, r.e = x.e + y.e + 64. Result may not be normalized.\nFMT_API fp operator*(fp x, fp y);\n\n// Returns cached power (of 10) c_k = c_k.f * pow(2, c_k.e) such that its\n// (binary) exponent satisfies min_exponent <= c_k.e <= min_exponent + 3.\nFMT_API fp get_cached_power(int min_exponent, int &pow10_exponent);\n\nFMT_FUNC fp operator*(fp x, fp y) {\n // Multiply 32-bit parts of significands.\n uint64_t mask = (1ULL << 32) - 1;\n uint64_t a = x.f >> 32, b = x.f & mask;\n uint64_t c = y.f >> 32, d = y.f & mask;\n uint64_t ac = a * c, bc = b * c, ad = a * d, bd = b * d;\n // Compute mid 64-bit of result and round.\n uint64_t mid = (bd >> 32) + (ad & mask) + (bc & mask) + (1U << 31);\n return fp(ac + (ad >> 32) + (bc >> 32) + (mid >> 32), x.e + y.e + 64);\n}\n\nFMT_FUNC fp get_cached_power(int min_exponent, int &pow10_exponent) {\n const double one_over_log2_10 = 0.30102999566398114; // 1 / log2(10)\n int index = static_cast(std::ceil(\n (min_exponent + fp::significand_size - 1) * one_over_log2_10));\n // Decimal exponent of the first (smallest) cached power of 10.\n const int first_dec_exp = -348;\n // Difference between 2 consecutive decimal exponents in cached powers of 10.\n const int dec_exp_step = 8;\n index = (index - first_dec_exp - 1) / dec_exp_step + 1;\n pow10_exponent = first_dec_exp + index * dec_exp_step;\n return fp(data::POW10_SIGNIFICANDS[index], data::POW10_EXPONENTS[index]);\n}\n\nFMT_FUNC bool grisu2_round(\n char *buffer, size_t &size, size_t max_digits, uint64_t delta,\n uint64_t remainder, uint64_t exp, uint64_t diff, int &exp10) {\n while (remainder < diff && delta - remainder >= exp &&\n (remainder + exp < diff || diff - remainder > remainder + exp - diff)) {\n --buffer[size - 1];\n remainder += exp;\n }\n if (size > max_digits) {\n --size;\n ++exp10;\n if (buffer[size] >= '5')\n return false;\n }\n return true;\n}\n\n// Generates output using Grisu2 digit-gen algorithm.\nFMT_FUNC bool grisu2_gen_digits(\n char *buffer, size_t &size, uint32_t hi, uint64_t lo, int &exp,\n uint64_t delta, const fp &one, const fp &diff, size_t max_digits) {\n // Generate digits for the most significant part (hi).\n while (exp > 0) {\n uint32_t digit = 0;\n // This optimization by miloyip reduces the number of integer divisions by\n // one per iteration.\n switch (exp) {\n case 10: digit = hi / 1000000000; hi %= 1000000000; break;\n case 9: digit = hi / 100000000; hi %= 100000000; break;\n case 8: digit = hi / 10000000; hi %= 10000000; break;\n case 7: digit = hi / 1000000; hi %= 1000000; break;\n case 6: digit = hi / 100000; hi %= 100000; break;\n case 5: digit = hi / 10000; hi %= 10000; break;\n case 4: digit = hi / 1000; hi %= 1000; break;\n case 3: digit = hi / 100; hi %= 100; break;\n case 2: digit = hi / 10; hi %= 10; break;\n case 1: digit = hi; hi = 0; break;\n default:\n FMT_ASSERT(false, \"invalid number of digits\");\n }\n if (digit != 0 || size != 0)\n buffer[size++] = static_cast('0' + digit);\n --exp;\n uint64_t remainder = (static_cast(hi) << -one.e) + lo;\n if (remainder <= delta || size > max_digits) {\n return grisu2_round(\n buffer, size, max_digits, delta, remainder,\n static_cast(data::POWERS_OF_10_32[exp]) << -one.e,\n diff.f, exp);\n }\n }\n // Generate digits for the least significant part (lo).\n for (;;) {\n lo *= 10;\n delta *= 10;\n char digit = static_cast(lo >> -one.e);\n if (digit != 0 || size != 0)\n buffer[size++] = static_cast('0' + digit);\n lo &= one.f - 1;\n --exp;\n if (lo < delta || size > max_digits) {\n return grisu2_round(buffer, size, max_digits, delta, lo, one.f,\n diff.f * data::POWERS_OF_10_32[-exp], exp);\n }\n }\n}\n\n#if FMT_CLANG_VERSION\n# define FMT_FALLTHROUGH [[clang::fallthrough]];\n#elif FMT_GCC_VERSION >= 700\n# define FMT_FALLTHROUGH [[gnu::fallthrough]];\n#else\n# define FMT_FALLTHROUGH\n#endif\n\nstruct gen_digits_params {\n unsigned num_digits;\n bool fixed;\n bool upper;\n bool trailing_zeros;\n};\n\nstruct prettify_handler {\n char *data;\n size_t size;\n buffer &buf;\n\n explicit prettify_handler(buffer &b, size_t n)\n : data(b.data()), size(n), buf(b) {}\n ~prettify_handler() {\n assert(buf.size() >= size);\n buf.resize(size);\n }\n\n template \n void insert(size_t pos, size_t n, F f) {\n std::memmove(data + pos + n, data + pos, size - pos);\n f(data + pos);\n size += n;\n }\n\n void insert(size_t pos, char c) {\n std::memmove(data + pos + 1, data + pos, size - pos);\n data[pos] = c;\n ++size;\n }\n\n void append(size_t n, char c) {\n std::uninitialized_fill_n(data + size, n, c);\n size += n;\n }\n\n void append(char c) { data[size++] = c; }\n\n void remove_trailing(char c) {\n while (data[size - 1] == c) --size;\n }\n};\n\n// Writes the exponent exp in the form \"[+-]d{2,3}\" to buffer.\ntemplate \nFMT_FUNC void write_exponent(int exp, Handler &&h) {\n FMT_ASSERT(-1000 < exp && exp < 1000, \"exponent out of range\");\n if (exp < 0) {\n h.append('-');\n exp = -exp;\n } else {\n h.append('+');\n }\n if (exp >= 100) {\n h.append(static_cast('0' + exp / 100));\n exp %= 100;\n const char *d = data::DIGITS + exp * 2;\n h.append(d[0]);\n h.append(d[1]);\n } else {\n const char *d = data::DIGITS + exp * 2;\n h.append(d[0]);\n h.append(d[1]);\n }\n}\n\nstruct fill {\n size_t n;\n void operator()(char *buffer) const {\n buffer[0] = '0';\n buffer[1] = '.';\n std::uninitialized_fill_n(buffer + 2, n, '0');\n }\n};\n\n// The number is given as v = f * pow(10, exp), where f has size digits.\ntemplate \nFMT_FUNC void grisu2_prettify(const gen_digits_params ¶ms,\n size_t size, int exp, Handler &&handler) {\n if (!params.fixed) {\n // Insert a decimal point after the first digit and add an exponent.\n handler.insert(1, '.');\n exp += static_cast(size) - 1;\n if (size < params.num_digits)\n handler.append(params.num_digits - size, '0');\n handler.append(params.upper ? 'E' : 'e');\n write_exponent(exp, handler);\n return;\n }\n // pow(10, full_exp - 1) <= v <= pow(10, full_exp).\n int int_size = static_cast(size);\n int full_exp = int_size + exp;\n const int exp_threshold = 21;\n if (int_size <= full_exp && full_exp <= exp_threshold) {\n // 1234e7 -> 12340000000[.0+]\n handler.append(full_exp - int_size, '0');\n int num_zeros = static_cast(params.num_digits) - full_exp;\n if (num_zeros > 0 && params.trailing_zeros) {\n handler.append('.');\n handler.append(num_zeros, '0');\n }\n } else if (full_exp > 0) {\n // 1234e-2 -> 12.34[0+]\n handler.insert(full_exp, '.');\n if (!params.trailing_zeros) {\n // Remove trailing zeros.\n handler.remove_trailing('0');\n } else if (params.num_digits > size) {\n // Add trailing zeros.\n size_t num_zeros = params.num_digits - size;\n handler.append(num_zeros, '0');\n }\n } else {\n // 1234e-6 -> 0.001234\n handler.insert(0, 2 - full_exp, fill{to_unsigned(-full_exp)});\n }\n}\n\nstruct char_counter {\n size_t size;\n\n template \n void insert(size_t, size_t n, F) { size += n; }\n void insert(size_t, char) { ++size; }\n void append(size_t n, char) { size += n; }\n void append(char) { ++size; }\n void remove_trailing(char) {}\n};\n\n// Converts format specifiers into parameters for digit generation and computes\n// output buffer size for a number in the range [pow(10, exp - 1), pow(10, exp)\n// or 0 if exp == 1.\nFMT_FUNC gen_digits_params process_specs(const core_format_specs &specs,\n int exp, buffer &buf) {\n auto params = gen_digits_params();\n int num_digits = specs.precision >= 0 ? specs.precision : 6;\n switch (specs.type) {\n case 'G':\n params.upper = true;\n FMT_FALLTHROUGH\n case '\\0': case 'g':\n params.trailing_zeros = (specs.flags & HASH_FLAG) != 0;\n if (-4 <= exp && exp < num_digits + 1) {\n params.fixed = true;\n if (!specs.type && params.trailing_zeros && exp >= 0)\n num_digits = exp + 1;\n }\n break;\n case 'F':\n params.upper = true;\n FMT_FALLTHROUGH\n case 'f': {\n params.fixed = true;\n params.trailing_zeros = true;\n int adjusted_min_digits = num_digits + exp;\n if (adjusted_min_digits > 0)\n num_digits = adjusted_min_digits;\n break;\n }\n case 'E':\n params.upper = true;\n FMT_FALLTHROUGH\n case 'e':\n ++num_digits;\n break;\n }\n params.num_digits = to_unsigned(num_digits);\n char_counter counter{params.num_digits};\n grisu2_prettify(params, params.num_digits, exp - num_digits, counter);\n buf.resize(counter.size);\n return params;\n}\n\ntemplate \nFMT_FUNC typename std::enable_if::type\n grisu2_format(Double value, buffer &buf, core_format_specs specs) {\n FMT_ASSERT(value >= 0, \"value is negative\");\n if (value == 0) {\n gen_digits_params params = process_specs(specs, 1, buf);\n const size_t size = 1;\n buf[0] = '0';\n grisu2_prettify(params, size, 0, prettify_handler(buf, size));\n return true;\n }\n\n fp fp_value(value);\n fp lower, upper; // w^- and w^+ in the Grisu paper.\n fp_value.compute_boundaries(lower, upper);\n\n // Find a cached power of 10 close to 1 / upper and use it to scale upper.\n const int min_exp = -60; // alpha in Grisu.\n int cached_exp = 0; // K in Grisu.\n auto cached_pow = get_cached_power( // \\tilde{c}_{-k} in Grisu.\n min_exp - (upper.e + fp::significand_size), cached_exp);\n cached_exp = -cached_exp;\n upper = upper * cached_pow; // \\tilde{M}^+ in Grisu.\n --upper.f; // \\tilde{M}^+ - 1 ulp -> M^+_{\\downarrow}.\n fp one(1ull << -upper.e, upper.e);\n // hi (p1 in Grisu) contains the most significant digits of scaled_upper.\n // hi = floor(upper / one).\n uint32_t hi = static_cast(upper.f >> -one.e);\n int exp = static_cast(count_digits(hi)); // kappa in Grisu.\n gen_digits_params params = process_specs(specs, cached_exp + exp, buf);\n fp_value.normalize();\n fp scaled_value = fp_value * cached_pow;\n lower = lower * cached_pow; // \\tilde{M}^- in Grisu.\n ++lower.f; // \\tilde{M}^- + 1 ulp -> M^-_{\\uparrow}.\n uint64_t delta = upper.f - lower.f;\n fp diff = upper - scaled_value; // wp_w in Grisu.\n // lo (p2 in Grisu) contains the least significants digits of scaled_upper.\n // lo = supper % one.\n uint64_t lo = upper.f & (one.f - 1);\n size_t size = 0;\n if (!grisu2_gen_digits(buf.data(), size, hi, lo, exp, delta, one, diff,\n params.num_digits)) {\n buf.clear();\n return false;\n }\n grisu2_prettify(params, size, cached_exp + exp, prettify_handler(buf, size));\n return true;\n}\n\ntemplate \nvoid sprintf_format(Double value, internal::buffer &buffer,\n core_format_specs spec) {\n // Buffer capacity must be non-zero, otherwise MSVC's vsnprintf_s will fail.\n FMT_ASSERT(buffer.capacity() != 0, \"empty buffer\");\n\n // Build format string.\n enum { MAX_FORMAT_SIZE = 10}; // longest format: %#-*.*Lg\n char format[MAX_FORMAT_SIZE];\n char *format_ptr = format;\n *format_ptr++ = '%';\n if (spec.has(HASH_FLAG))\n *format_ptr++ = '#';\n if (spec.precision >= 0) {\n *format_ptr++ = '.';\n *format_ptr++ = '*';\n }\n if (std::is_same::value)\n *format_ptr++ = 'L';\n *format_ptr++ = spec.type;\n *format_ptr = '\\0';\n\n // Format using snprintf.\n char *start = FMT_NULL;\n for (;;) {\n std::size_t buffer_size = buffer.capacity();\n start = &buffer[0];\n int result = internal::char_traits::format_float(\n start, buffer_size, format, spec.precision, value);\n if (result >= 0) {\n unsigned n = internal::to_unsigned(result);\n if (n < buffer.capacity()) {\n buffer.resize(n);\n break; // The buffer is large enough - continue with formatting.\n }\n buffer.reserve(n + 1);\n } else {\n // If result is negative we ask to increase the capacity by at least 1,\n // but as std::vector, the buffer grows exponentially.\n buffer.reserve(buffer.capacity() + 1);\n }\n }\n}\n} // namespace internal\n\n#if FMT_USE_WINDOWS_H\n\nFMT_FUNC internal::utf8_to_utf16::utf8_to_utf16(string_view s) {\n static const char ERROR_MSG[] = \"cannot convert string from UTF-8 to UTF-16\";\n if (s.size() > INT_MAX)\n FMT_THROW(windows_error(ERROR_INVALID_PARAMETER, ERROR_MSG));\n int s_size = static_cast(s.size());\n if (s_size == 0) {\n // MultiByteToWideChar does not support zero length, handle separately.\n buffer_.resize(1);\n buffer_[0] = 0;\n return;\n }\n\n int length = MultiByteToWideChar(\n CP_UTF8, MB_ERR_INVALID_CHARS, s.data(), s_size, FMT_NULL, 0);\n if (length == 0)\n FMT_THROW(windows_error(GetLastError(), ERROR_MSG));\n buffer_.resize(length + 1);\n length = MultiByteToWideChar(\n CP_UTF8, MB_ERR_INVALID_CHARS, s.data(), s_size, &buffer_[0], length);\n if (length == 0)\n FMT_THROW(windows_error(GetLastError(), ERROR_MSG));\n buffer_[length] = 0;\n}\n\nFMT_FUNC internal::utf16_to_utf8::utf16_to_utf8(wstring_view s) {\n if (int error_code = convert(s)) {\n FMT_THROW(windows_error(error_code,\n \"cannot convert string from UTF-16 to UTF-8\"));\n }\n}\n\nFMT_FUNC int internal::utf16_to_utf8::convert(wstring_view s) {\n if (s.size() > INT_MAX)\n return ERROR_INVALID_PARAMETER;\n int s_size = static_cast(s.size());\n if (s_size == 0) {\n // WideCharToMultiByte does not support zero length, handle separately.\n buffer_.resize(1);\n buffer_[0] = 0;\n return 0;\n }\n\n int length = WideCharToMultiByte(\n CP_UTF8, 0, s.data(), s_size, FMT_NULL, 0, FMT_NULL, FMT_NULL);\n if (length == 0)\n return GetLastError();\n buffer_.resize(length + 1);\n length = WideCharToMultiByte(\n CP_UTF8, 0, s.data(), s_size, &buffer_[0], length, FMT_NULL, FMT_NULL);\n if (length == 0)\n return GetLastError();\n buffer_[length] = 0;\n return 0;\n}\n\nFMT_FUNC void windows_error::init(\n int err_code, string_view format_str, format_args args) {\n error_code_ = err_code;\n memory_buffer buffer;\n internal::format_windows_error(buffer, err_code, vformat(format_str, args));\n std::runtime_error &base = *this;\n base = std::runtime_error(to_string(buffer));\n}\n\nFMT_FUNC void internal::format_windows_error(\n internal::buffer &out, int error_code, string_view message) FMT_NOEXCEPT {\n FMT_TRY {\n wmemory_buffer buf;\n buf.resize(inline_buffer_size);\n for (;;) {\n wchar_t *system_message = &buf[0];\n int result = FormatMessageW(\n FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS,\n FMT_NULL, error_code, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),\n system_message, static_cast(buf.size()), FMT_NULL);\n if (result != 0) {\n utf16_to_utf8 utf8_message;\n if (utf8_message.convert(system_message) == ERROR_SUCCESS) {\n writer w(out);\n w.write(message);\n w.write(\": \");\n w.write(utf8_message);\n return;\n }\n break;\n }\n if (GetLastError() != ERROR_INSUFFICIENT_BUFFER)\n break; // Can't get error message, report error code instead.\n buf.resize(buf.size() * 2);\n }\n } FMT_CATCH(...) {}\n format_error_code(out, error_code, message);\n}\n\n#endif // FMT_USE_WINDOWS_H\n\nFMT_FUNC void format_system_error(\n internal::buffer &out, int error_code, string_view message) FMT_NOEXCEPT {\n FMT_TRY {\n memory_buffer buf;\n buf.resize(inline_buffer_size);\n for (;;) {\n char *system_message = &buf[0];\n int result = safe_strerror(error_code, system_message, buf.size());\n if (result == 0) {\n writer w(out);\n w.write(message);\n w.write(\": \");\n w.write(system_message);\n return;\n }\n if (result != ERANGE)\n break; // Can't get error message, report error code instead.\n buf.resize(buf.size() * 2);\n }\n } FMT_CATCH(...) {}\n format_error_code(out, error_code, message);\n}\n\nFMT_FUNC void internal::error_handler::on_error(const char *message) {\n FMT_THROW(format_error(message));\n}\n\nFMT_FUNC void report_system_error(\n int error_code, fmt::string_view message) FMT_NOEXCEPT {\n report_error(format_system_error, error_code, message);\n}\n\n#if FMT_USE_WINDOWS_H\nFMT_FUNC void report_windows_error(\n int error_code, fmt::string_view message) FMT_NOEXCEPT {\n report_error(internal::format_windows_error, error_code, message);\n}\n#endif\n\nFMT_FUNC void vprint(std::FILE *f, string_view format_str, format_args args) {\n memory_buffer buffer;\n internal::vformat_to(buffer, format_str,\n basic_format_args::type>(args));\n std::fwrite(buffer.data(), 1, buffer.size(), f);\n}\n\nFMT_FUNC void vprint(std::FILE *f, wstring_view format_str, wformat_args args) {\n wmemory_buffer buffer;\n internal::vformat_to(buffer, format_str, args);\n std::fwrite(buffer.data(), sizeof(wchar_t), buffer.size(), f);\n}\n\nFMT_FUNC void vprint(string_view format_str, format_args args) {\n vprint(stdout, format_str, args);\n}\n\nFMT_FUNC void vprint(wstring_view format_str, wformat_args args) {\n vprint(stdout, format_str, args);\n}\n\nFMT_END_NAMESPACE\n\n#ifdef _MSC_VER\n# pragma warning(pop)\n#endif\n\n#endif // FMT_FORMAT_INL_H_\n" }, { "path": "src/DRAMsim3/ext/fmt/include/fmt/format.h", "content": "/*\n Formatting library for C++\n\n Copyright (c) 2012 - present, Victor Zverovich\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef FMT_FORMAT_H_\n#define FMT_FORMAT_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef __clang__\n# define FMT_CLANG_VERSION (__clang_major__ * 100 + __clang_minor__)\n#else\n# define FMT_CLANG_VERSION 0\n#endif\n\n#ifdef __INTEL_COMPILER\n# define FMT_ICC_VERSION __INTEL_COMPILER\n#elif defined(__ICL)\n# define FMT_ICC_VERSION __ICL\n#else\n# define FMT_ICC_VERSION 0\n#endif\n\n#ifdef __NVCC__\n# define FMT_CUDA_VERSION (__CUDACC_VER_MAJOR__ * 100 + __CUDACC_VER_MINOR__)\n#else\n# define FMT_CUDA_VERSION 0\n#endif\n\n#include \"core.h\"\n\n#if FMT_GCC_VERSION >= 406 || FMT_CLANG_VERSION\n# pragma GCC diagnostic push\n\n// Disable the warning about declaration shadowing because it affects too\n// many valid cases.\n# pragma GCC diagnostic ignored \"-Wshadow\"\n\n// Disable the warning about implicit conversions that may change the sign of\n// an integer; silencing it otherwise would require many explicit casts.\n# pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#endif\n\n# if FMT_CLANG_VERSION\n# pragma GCC diagnostic ignored \"-Wgnu-string-literal-operator-template\"\n# endif\n\n#ifdef _SECURE_SCL\n# define FMT_SECURE_SCL _SECURE_SCL\n#else\n# define FMT_SECURE_SCL 0\n#endif\n\n#if FMT_SECURE_SCL\n# include \n#endif\n\n#ifdef __has_builtin\n# define FMT_HAS_BUILTIN(x) __has_builtin(x)\n#else\n# define FMT_HAS_BUILTIN(x) 0\n#endif\n\n#ifdef __GNUC_LIBSTD__\n# define FMT_GNUC_LIBSTD_VERSION (__GNUC_LIBSTD__ * 100 + __GNUC_LIBSTD_MINOR__)\n#endif\n\n#ifndef FMT_THROW\n# if FMT_EXCEPTIONS\n# if FMT_MSC_VER\nFMT_BEGIN_NAMESPACE\nnamespace internal {\ntemplate \ninline void do_throw(const Exception &x) {\n // Silence unreachable code warnings in MSVC because these are nearly\n // impossible to fix in a generic code.\n volatile bool b = true;\n if (b)\n throw x;\n}\n}\nFMT_END_NAMESPACE\n# define FMT_THROW(x) fmt::internal::do_throw(x)\n# else\n# define FMT_THROW(x) throw x\n# endif\n# else\n# define FMT_THROW(x) do { static_cast(sizeof(x)); assert(false); } while(false);\n# endif\n#endif\n\n#ifndef FMT_USE_USER_DEFINED_LITERALS\n// For Intel's compiler and NVIDIA's compiler both it and the system gcc/msc\n// must support UDLs.\n# if (FMT_HAS_FEATURE(cxx_user_literals) || \\\n FMT_GCC_VERSION >= 407 || FMT_MSC_VER >= 1900) && \\\n (!(FMT_ICC_VERSION || FMT_CUDA_VERSION) || \\\n FMT_ICC_VERSION >= 1500 || FMT_CUDA_VERSION >= 700)\n# define FMT_USE_USER_DEFINED_LITERALS 1\n# else\n# define FMT_USE_USER_DEFINED_LITERALS 0\n# endif\n#endif\n\n// EDG C++ Front End based compilers (icc, nvcc) do not currently support UDL\n// templates.\n#if FMT_USE_USER_DEFINED_LITERALS && \\\n FMT_ICC_VERSION == 0 && \\\n FMT_CUDA_VERSION == 0 && \\\n ((FMT_GCC_VERSION >= 600 && __cplusplus >= 201402L) || \\\n (defined(FMT_CLANG_VERSION) && FMT_CLANG_VERSION >= 304))\n# define FMT_UDL_TEMPLATE 1\n#else\n# define FMT_UDL_TEMPLATE 0\n#endif\n\n#ifndef FMT_USE_EXTERN_TEMPLATES\n# ifndef FMT_HEADER_ONLY\n# define FMT_USE_EXTERN_TEMPLATES \\\n ((FMT_CLANG_VERSION >= 209 && __cplusplus >= 201103L) || \\\n (FMT_GCC_VERSION >= 303 && FMT_HAS_GXX_CXX11))\n# else\n# define FMT_USE_EXTERN_TEMPLATES 0\n# endif\n#endif\n\n#if FMT_HAS_GXX_CXX11 || FMT_HAS_FEATURE(cxx_trailing_return) || \\\n FMT_MSC_VER >= 1600\n# define FMT_USE_TRAILING_RETURN 1\n#else\n# define FMT_USE_TRAILING_RETURN 0\n#endif\n\n#ifndef FMT_USE_GRISU\n# define FMT_USE_GRISU 0\n//# define FMT_USE_GRISU std::numeric_limits::is_iec559\n#endif\n\n// __builtin_clz is broken in clang with Microsoft CodeGen:\n// https://github.com/fmtlib/fmt/issues/519\n#ifndef _MSC_VER\n# if FMT_GCC_VERSION >= 400 || FMT_HAS_BUILTIN(__builtin_clz)\n# define FMT_BUILTIN_CLZ(n) __builtin_clz(n)\n# endif\n\n# if FMT_GCC_VERSION >= 400 || FMT_HAS_BUILTIN(__builtin_clzll)\n# define FMT_BUILTIN_CLZLL(n) __builtin_clzll(n)\n# endif\n#endif\n\n// Some compilers masquerade as both MSVC and GCC-likes or otherwise support\n// __builtin_clz and __builtin_clzll, so only define FMT_BUILTIN_CLZ using the\n// MSVC intrinsics if the clz and clzll builtins are not available.\n#if FMT_MSC_VER && !defined(FMT_BUILTIN_CLZLL) && !defined(_MANAGED)\n# include // _BitScanReverse, _BitScanReverse64\n\nFMT_BEGIN_NAMESPACE\nnamespace internal {\n// Avoid Clang with Microsoft CodeGen's -Wunknown-pragmas warning.\n# ifndef __clang__\n# pragma intrinsic(_BitScanReverse)\n# endif\ninline uint32_t clz(uint32_t x) {\n unsigned long r = 0;\n _BitScanReverse(&r, x);\n\n assert(x != 0);\n // Static analysis complains about using uninitialized data\n // \"r\", but the only way that can happen is if \"x\" is 0,\n // which the callers guarantee to not happen.\n# pragma warning(suppress: 6102)\n return 31 - r;\n}\n# define FMT_BUILTIN_CLZ(n) fmt::internal::clz(n)\n\n# if defined(_WIN64) && !defined(__clang__)\n# pragma intrinsic(_BitScanReverse64)\n# endif\n\ninline uint32_t clzll(uint64_t x) {\n unsigned long r = 0;\n# ifdef _WIN64\n _BitScanReverse64(&r, x);\n# else\n // Scan the high 32 bits.\n if (_BitScanReverse(&r, static_cast(x >> 32)))\n return 63 - (r + 32);\n\n // Scan the low 32 bits.\n _BitScanReverse(&r, static_cast(x));\n# endif\n\n assert(x != 0);\n // Static analysis complains about using uninitialized data\n // \"r\", but the only way that can happen is if \"x\" is 0,\n // which the callers guarantee to not happen.\n# pragma warning(suppress: 6102)\n return 63 - r;\n}\n# define FMT_BUILTIN_CLZLL(n) fmt::internal::clzll(n)\n}\nFMT_END_NAMESPACE\n#endif\n\nFMT_BEGIN_NAMESPACE\nnamespace internal {\n\n// An equivalent of `*reinterpret_cast(&source)` that doesn't produce\n// undefined behavior (e.g. due to type aliasing).\n// Example: uint64_t d = bit_cast(2.718);\ntemplate \ninline Dest bit_cast(const Source& source) {\n static_assert(sizeof(Dest) == sizeof(Source), \"size mismatch\");\n Dest dest;\n std::memcpy(&dest, &source, sizeof(dest));\n return dest;\n}\n\n// An implementation of begin and end for pre-C++11 compilers such as gcc 4.\ntemplate \nFMT_CONSTEXPR auto begin(const C &c) -> decltype(c.begin()) {\n return c.begin();\n}\ntemplate \nFMT_CONSTEXPR T *begin(T (&array)[N]) FMT_NOEXCEPT { return array; }\ntemplate \nFMT_CONSTEXPR auto end(const C &c) -> decltype(c.end()) { return c.end(); }\ntemplate \nFMT_CONSTEXPR T *end(T (&array)[N]) FMT_NOEXCEPT { return array + N; }\n\n// For std::result_of in gcc 4.4.\ntemplate \nstruct function {\n template \n struct result { typedef Result type; };\n};\n\nstruct dummy_int {\n int data[2];\n operator int() const { return 0; }\n};\ntypedef std::numeric_limits fputil;\n\n// Dummy implementations of system functions called if the latter are not\n// available.\ninline dummy_int isinf(...) { return dummy_int(); }\ninline dummy_int _finite(...) { return dummy_int(); }\ninline dummy_int isnan(...) { return dummy_int(); }\ninline dummy_int _isnan(...) { return dummy_int(); }\n\ntemplate \ntypename Allocator::value_type *allocate(Allocator& alloc, std::size_t n) {\n#if __cplusplus >= 201103L || FMT_MSC_VER >= 1700\n return std::allocator_traits::allocate(alloc, n);\n#else\n return alloc.allocate(n);\n#endif\n}\n\n// A helper function to suppress bogus \"conditional expression is constant\"\n// warnings.\ntemplate \ninline T const_check(T value) { return value; }\n} // namespace internal\nFMT_END_NAMESPACE\n\nnamespace std {\n// Standard permits specialization of std::numeric_limits. This specialization\n// is used to resolve ambiguity between isinf and std::isinf in glibc:\n// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=48891\n// and the same for isnan.\ntemplate <>\nclass numeric_limits :\n public std::numeric_limits {\n public:\n // Portable version of isinf.\n template \n static bool isinfinity(T x) {\n using namespace fmt::internal;\n // The resolution \"priority\" is:\n // isinf macro > std::isinf > ::isinf > fmt::internal::isinf\n if (const_check(sizeof(isinf(x)) != sizeof(dummy_int)))\n return isinf(x) != 0;\n return !_finite(static_cast(x));\n }\n\n // Portable version of isnan.\n template \n static bool isnotanumber(T x) {\n using namespace fmt::internal;\n if (const_check(sizeof(isnan(x)) != sizeof(fmt::internal::dummy_int)))\n return isnan(x) != 0;\n return _isnan(static_cast(x)) != 0;\n }\n};\n} // namespace std\n\nFMT_BEGIN_NAMESPACE\ntemplate \nclass basic_writer;\n\ntemplate \nclass output_range {\n private:\n OutputIt it_;\n\n // Unused yet.\n typedef void sentinel;\n sentinel end() const;\n\n public:\n typedef OutputIt iterator;\n typedef T value_type;\n\n explicit output_range(OutputIt it): it_(it) {}\n OutputIt begin() const { return it_; }\n};\n\n// A range where begin() returns back_insert_iterator.\ntemplate \nclass back_insert_range:\n public output_range> {\n typedef output_range> base;\n public:\n typedef typename Container::value_type value_type;\n\n back_insert_range(Container &c): base(std::back_inserter(c)) {}\n back_insert_range(typename base::iterator it): base(it) {}\n};\n\ntypedef basic_writer> writer;\ntypedef basic_writer> wwriter;\n\n/** A formatting error such as invalid format string. */\nclass format_error : public std::runtime_error {\n public:\n explicit format_error(const char *message)\n : std::runtime_error(message) {}\n\n explicit format_error(const std::string &message)\n : std::runtime_error(message) {}\n};\n\nnamespace internal {\n\n#if FMT_SECURE_SCL\ntemplate \nstruct checked { typedef stdext::checked_array_iterator type; };\n\n// Make a checked iterator to avoid warnings on MSVC.\ntemplate \ninline stdext::checked_array_iterator make_checked(T *p, std::size_t size) {\n return {p, size};\n}\n#else\ntemplate \nstruct checked { typedef T *type; };\ntemplate \ninline T *make_checked(T *p, std::size_t) { return p; }\n#endif\n\ntemplate \ntemplate \nvoid basic_buffer::append(const U *begin, const U *end) {\n std::size_t new_size = size_ + internal::to_unsigned(end - begin);\n reserve(new_size);\n std::uninitialized_copy(begin, end,\n internal::make_checked(ptr_, capacity_) + size_);\n size_ = new_size;\n}\n} // namespace internal\n\n// A UTF-8 code unit type.\nenum char8_t: unsigned char {};\n\n// A UTF-8 string view.\nclass u8string_view : public basic_string_view {\n public:\n typedef char8_t char_type;\n\n u8string_view(const char *s):\n basic_string_view(reinterpret_cast(s)) {}\n u8string_view(const char *s, size_t count) FMT_NOEXCEPT:\n basic_string_view(reinterpret_cast(s), count) {}\n};\n\n#if FMT_USE_USER_DEFINED_LITERALS\ninline namespace literals {\ninline u8string_view operator\"\" _u(const char *s, std::size_t n) {\n return {s, n};\n}\n}\n#endif\n\n// The number of characters to store in the basic_memory_buffer object itself\n// to avoid dynamic memory allocation.\nenum { inline_buffer_size = 500 };\n\n/**\n \\rst\n A dynamically growing memory buffer for trivially copyable/constructible types\n with the first ``SIZE`` elements stored in the object itself.\n\n You can use one of the following typedefs for common character types:\n\n +----------------+------------------------------+\n | Type | Definition |\n +================+==============================+\n | memory_buffer | basic_memory_buffer |\n +----------------+------------------------------+\n | wmemory_buffer | basic_memory_buffer |\n +----------------+------------------------------+\n\n **Example**::\n\n fmt::memory_buffer out;\n format_to(out, \"The answer is {}.\", 42);\n\n This will append the following output to the ``out`` object:\n\n .. code-block:: none\n\n The answer is 42.\n\n The output can be converted to an ``std::string`` with ``to_string(out)``.\n \\endrst\n */\ntemplate >\nclass basic_memory_buffer: private Allocator, public internal::basic_buffer {\n private:\n T store_[SIZE];\n\n // Deallocate memory allocated by the buffer.\n void deallocate() {\n T* data = this->data();\n if (data != store_) Allocator::deallocate(data, this->capacity());\n }\n\n protected:\n void grow(std::size_t size) FMT_OVERRIDE;\n\n public:\n explicit basic_memory_buffer(const Allocator &alloc = Allocator())\n : Allocator(alloc) {\n this->set(store_, SIZE);\n }\n ~basic_memory_buffer() { deallocate(); }\n\n private:\n // Move data from other to this buffer.\n void move(basic_memory_buffer &other) {\n Allocator &this_alloc = *this, &other_alloc = other;\n this_alloc = std::move(other_alloc);\n T* data = other.data();\n std::size_t size = other.size(), capacity = other.capacity();\n if (data == other.store_) {\n this->set(store_, capacity);\n std::uninitialized_copy(other.store_, other.store_ + size,\n internal::make_checked(store_, capacity));\n } else {\n this->set(data, capacity);\n // Set pointer to the inline array so that delete is not called\n // when deallocating.\n other.set(other.store_, 0);\n }\n this->resize(size);\n }\n\n public:\n /**\n \\rst\n Constructs a :class:`fmt::basic_memory_buffer` object moving the content\n of the other object to it.\n \\endrst\n */\n basic_memory_buffer(basic_memory_buffer &&other) {\n move(other);\n }\n\n /**\n \\rst\n Moves the content of the other ``basic_memory_buffer`` object to this one.\n \\endrst\n */\n basic_memory_buffer &operator=(basic_memory_buffer &&other) {\n assert(this != &other);\n deallocate();\n move(other);\n return *this;\n }\n\n // Returns a copy of the allocator associated with this buffer.\n Allocator get_allocator() const { return *this; }\n};\n\ntemplate \nvoid basic_memory_buffer::grow(std::size_t size) {\n std::size_t old_capacity = this->capacity();\n std::size_t new_capacity = old_capacity + old_capacity / 2;\n if (size > new_capacity)\n new_capacity = size;\n T *old_data = this->data();\n T *new_data = internal::allocate(*this, new_capacity);\n // The following code doesn't throw, so the raw pointer above doesn't leak.\n std::uninitialized_copy(old_data, old_data + this->size(),\n internal::make_checked(new_data, new_capacity));\n this->set(new_data, new_capacity);\n // deallocate must not throw according to the standard, but even if it does,\n // the buffer already uses the new storage and will deallocate it in\n // destructor.\n if (old_data != store_)\n Allocator::deallocate(old_data, old_capacity);\n}\n\ntypedef basic_memory_buffer memory_buffer;\ntypedef basic_memory_buffer wmemory_buffer;\n\nnamespace internal {\n\ntemplate \nstruct char_traits;\n\ntemplate <>\nstruct char_traits {\n // Formats a floating-point number.\n template \n FMT_API static int format_float(char *buffer, std::size_t size,\n const char *format, int precision, T value);\n};\n\ntemplate <>\nstruct char_traits {\n template \n FMT_API static int format_float(wchar_t *buffer, std::size_t size,\n const wchar_t *format, int precision, T value);\n};\n\n#if FMT_USE_EXTERN_TEMPLATES\nextern template int char_traits::format_float(\n char *buffer, std::size_t size, const char* format, int precision,\n double value);\nextern template int char_traits::format_float(\n char *buffer, std::size_t size, const char* format, int precision,\n long double value);\n\nextern template int char_traits::format_float(\n wchar_t *buffer, std::size_t size, const wchar_t* format, int precision,\n double value);\nextern template int char_traits::format_float(\n wchar_t *buffer, std::size_t size, const wchar_t* format, int precision,\n long double value);\n#endif\n\ntemplate \ninline typename std::enable_if<\n is_contiguous::value,\n typename checked::type>::type\n reserve(std::back_insert_iterator &it, std::size_t n) {\n Container &c = internal::get_container(it);\n std::size_t size = c.size();\n c.resize(size + n);\n return make_checked(&c[size], n);\n}\n\ntemplate \ninline Iterator &reserve(Iterator &it, std::size_t) { return it; }\n\ntemplate \nclass null_terminating_iterator;\n\ntemplate \nFMT_CONSTEXPR_DECL const Char *pointer_from(null_terminating_iterator it);\n\n// An iterator that produces a null terminator on *end. This simplifies parsing\n// and allows comparing the performance of processing a null-terminated string\n// vs string_view.\ntemplate \nclass null_terminating_iterator {\n public:\n typedef std::ptrdiff_t difference_type;\n typedef Char value_type;\n typedef const Char* pointer;\n typedef const Char& reference;\n typedef std::random_access_iterator_tag iterator_category;\n\n null_terminating_iterator() : ptr_(0), end_(0) {}\n\n FMT_CONSTEXPR null_terminating_iterator(const Char *ptr, const Char *end)\n : ptr_(ptr), end_(end) {}\n\n template \n FMT_CONSTEXPR explicit null_terminating_iterator(const Range &r)\n : ptr_(r.begin()), end_(r.end()) {}\n\n FMT_CONSTEXPR null_terminating_iterator &operator=(const Char *ptr) {\n assert(ptr <= end_);\n ptr_ = ptr;\n return *this;\n }\n\n FMT_CONSTEXPR Char operator*() const {\n return ptr_ != end_ ? *ptr_ : Char();\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator++() {\n ++ptr_;\n return *this;\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator++(int) {\n null_terminating_iterator result(*this);\n ++ptr_;\n return result;\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator--() {\n --ptr_;\n return *this;\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator+(difference_type n) {\n return null_terminating_iterator(ptr_ + n, end_);\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator-(difference_type n) {\n return null_terminating_iterator(ptr_ - n, end_);\n }\n\n FMT_CONSTEXPR null_terminating_iterator operator+=(difference_type n) {\n ptr_ += n;\n return *this;\n }\n\n FMT_CONSTEXPR difference_type operator-(\n null_terminating_iterator other) const {\n return ptr_ - other.ptr_;\n }\n\n FMT_CONSTEXPR bool operator!=(null_terminating_iterator other) const {\n return ptr_ != other.ptr_;\n }\n\n bool operator>=(null_terminating_iterator other) const {\n return ptr_ >= other.ptr_;\n }\n\n // This should be a friend specialization pointer_from but the latter\n // doesn't compile by gcc 5.1 due to a compiler bug.\n template \n friend FMT_CONSTEXPR_DECL const CharT *pointer_from(\n null_terminating_iterator it);\n\n private:\n const Char *ptr_;\n const Char *end_;\n};\n\ntemplate \nFMT_CONSTEXPR const T *pointer_from(const T *p) { return p; }\n\ntemplate \nFMT_CONSTEXPR const Char *pointer_from(null_terminating_iterator it) {\n return it.ptr_;\n}\n\n// An output iterator that counts the number of objects written to it and\n// discards them.\ntemplate \nclass counting_iterator {\n private:\n std::size_t count_;\n mutable T blackhole_;\n\n public:\n typedef std::output_iterator_tag iterator_category;\n typedef T value_type;\n typedef std::ptrdiff_t difference_type;\n typedef T* pointer;\n typedef T& reference;\n typedef counting_iterator _Unchecked_type; // Mark iterator as checked.\n\n counting_iterator(): count_(0) {}\n\n std::size_t count() const { return count_; }\n\n counting_iterator& operator++() {\n ++count_;\n return *this;\n }\n\n counting_iterator operator++(int) {\n auto it = *this;\n ++*this;\n return it;\n }\n\n T &operator*() const { return blackhole_; }\n};\n\ntemplate \nclass truncating_iterator_base {\n protected:\n OutputIt out_;\n std::size_t limit_;\n std::size_t count_;\n\n truncating_iterator_base(OutputIt out, std::size_t limit)\n : out_(out), limit_(limit), count_(0) {}\n\n public:\n typedef std::output_iterator_tag iterator_category;\n typedef void difference_type;\n typedef void pointer;\n typedef void reference;\n typedef truncating_iterator_base _Unchecked_type; // Mark iterator as checked.\n\n OutputIt base() const { return out_; }\n std::size_t count() const { return count_; }\n};\n\n// An output iterator that truncates the output and counts the number of objects\n// written to it.\ntemplate ::value_type>::type>\nclass truncating_iterator;\n\ntemplate \nclass truncating_iterator:\n public truncating_iterator_base {\n typedef std::iterator_traits traits;\n\n mutable typename traits::value_type blackhole_;\n\n public:\n typedef typename traits::value_type value_type;\n\n truncating_iterator(OutputIt out, std::size_t limit)\n : truncating_iterator_base(out, limit) {}\n\n truncating_iterator& operator++() {\n if (this->count_++ < this->limit_)\n ++this->out_;\n return *this;\n }\n\n truncating_iterator operator++(int) {\n auto it = *this;\n ++*this;\n return it;\n }\n\n value_type& operator*() const {\n return this->count_ < this->limit_ ? *this->out_ : blackhole_;\n }\n};\n\ntemplate \nclass truncating_iterator:\n public truncating_iterator_base {\n public:\n typedef typename OutputIt::container_type::value_type value_type;\n\n truncating_iterator(OutputIt out, std::size_t limit)\n : truncating_iterator_base(out, limit) {}\n\n truncating_iterator& operator=(value_type val) {\n if (this->count_++ < this->limit_)\n this->out_ = val;\n return *this;\n }\n\n truncating_iterator& operator++() { return *this; }\n truncating_iterator& operator++(int) { return *this; }\n truncating_iterator& operator*() { return *this; }\n};\n\n// Returns true if value is negative, false otherwise.\n// Same as (value < 0) but doesn't produce warnings if T is an unsigned type.\ntemplate \nFMT_CONSTEXPR typename std::enable_if<\n std::numeric_limits::is_signed, bool>::type is_negative(T value) {\n return value < 0;\n}\ntemplate \nFMT_CONSTEXPR typename std::enable_if<\n !std::numeric_limits::is_signed, bool>::type is_negative(T) {\n return false;\n}\n\ntemplate \nstruct int_traits {\n // Smallest of uint32_t and uint64_t that is large enough to represent\n // all values of T.\n typedef typename std::conditional<\n std::numeric_limits::digits <= 32, uint32_t, uint64_t>::type main_type;\n};\n\n// Static data is placed in this class template to allow header-only\n// configuration.\ntemplate \nstruct FMT_API basic_data {\n static const uint32_t POWERS_OF_10_32[];\n static const uint32_t ZERO_OR_POWERS_OF_10_32[];\n static const uint64_t ZERO_OR_POWERS_OF_10_64[];\n static const uint64_t POW10_SIGNIFICANDS[];\n static const int16_t POW10_EXPONENTS[];\n static const char DIGITS[];\n static const char FOREGROUND_COLOR[];\n static const char BACKGROUND_COLOR[];\n static const char RESET_COLOR[];\n static const wchar_t WRESET_COLOR[];\n};\n\n#if FMT_USE_EXTERN_TEMPLATES\nextern template struct basic_data;\n#endif\n\ntypedef basic_data<> data;\n\n#ifdef FMT_BUILTIN_CLZLL\n// Returns the number of decimal digits in n. Leading zeros are not counted\n// except for n == 0 in which case count_digits returns 1.\ninline unsigned count_digits(uint64_t n) {\n // Based on http://graphics.stanford.edu/~seander/bithacks.html#IntegerLog10\n // and the benchmark https://github.com/localvoid/cxx-benchmark-count-digits.\n int t = (64 - FMT_BUILTIN_CLZLL(n | 1)) * 1233 >> 12;\n return to_unsigned(t) - (n < data::ZERO_OR_POWERS_OF_10_64[t]) + 1;\n}\n#else\n// Fallback version of count_digits used when __builtin_clz is not available.\ninline unsigned count_digits(uint64_t n) {\n unsigned count = 1;\n for (;;) {\n // Integer division is slow so do it for a group of four digits instead\n // of for every digit. The idea comes from the talk by Alexandrescu\n // \"Three Optimization Tips for C++\". See speed-test for a comparison.\n if (n < 10) return count;\n if (n < 100) return count + 1;\n if (n < 1000) return count + 2;\n if (n < 10000) return count + 3;\n n /= 10000u;\n count += 4;\n }\n}\n#endif\n\ntemplate \ninline size_t count_code_points(basic_string_view s) { return s.size(); }\n\n// Counts the number of code points in a UTF-8 string.\nFMT_API size_t count_code_points(basic_string_view s);\n\ninline char8_t to_char8_t(char c) { return static_cast(c); }\n\ntemplate \nstruct needs_conversion: std::integral_constant::value_type, char>::value &&\n std::is_same::value> {};\n\ntemplate \ntypename std::enable_if<\n !needs_conversion::value, OutputIt>::type\n copy_str(InputIt begin, InputIt end, OutputIt it) {\n return std::copy(begin, end, it);\n}\n\ntemplate \ntypename std::enable_if<\n needs_conversion::value, OutputIt>::type\n copy_str(InputIt begin, InputIt end, OutputIt it) {\n return std::transform(begin, end, it, to_char8_t);\n}\n\n#if FMT_HAS_CPP_ATTRIBUTE(always_inline)\n# define FMT_ALWAYS_INLINE __attribute__((always_inline))\n#else\n# define FMT_ALWAYS_INLINE\n#endif\n\ntemplate \ninline char *lg(uint32_t n, Handler h) FMT_ALWAYS_INLINE;\n\n// Computes g = floor(log10(n)) and calls h.on(n);\ntemplate \ninline char *lg(uint32_t n, Handler h) {\n return n < 100 ? n < 10 ? h.template on<0>(n) : h.template on<1>(n)\n : n < 1000000\n ? n < 10000 ? n < 1000 ? h.template on<2>(n)\n : h.template on<3>(n)\n : n < 100000 ? h.template on<4>(n)\n : h.template on<5>(n)\n : n < 100000000 ? n < 10000000 ? h.template on<6>(n)\n : h.template on<7>(n)\n : n < 1000000000 ? h.template on<8>(n)\n : h.template on<9>(n);\n}\n\n// An lg handler that formats a decimal number.\n// Usage: lg(n, decimal_formatter(buffer));\nclass decimal_formatter {\n private:\n char *buffer_;\n\n void write_pair(unsigned N, uint32_t index) {\n std::memcpy(buffer_ + N, data::DIGITS + index * 2, 2);\n }\n\n public:\n explicit decimal_formatter(char *buf) : buffer_(buf) {}\n\n template char *on(uint32_t u) {\n if (N == 0) {\n *buffer_ = static_cast(u) + '0';\n } else if (N == 1) {\n write_pair(0, u);\n } else {\n // The idea of using 4.32 fixed-point numbers is based on\n // https://github.com/jeaiii/itoa\n unsigned n = N - 1;\n unsigned a = n / 5 * n * 53 / 16;\n uint64_t t = ((1ULL << (32 + a)) /\n data::ZERO_OR_POWERS_OF_10_32[n] + 1 - n / 9);\n t = ((t * u) >> a) + n / 5 * 4;\n write_pair(0, t >> 32);\n for (unsigned i = 2; i < N; i += 2) {\n t = 100ULL * static_cast(t);\n write_pair(i, t >> 32);\n }\n if (N % 2 == 0) {\n buffer_[N] = static_cast(\n (10ULL * static_cast(t)) >> 32) + '0';\n }\n }\n return buffer_ += N + 1;\n }\n};\n\n// An lg handler that formats a decimal number with a terminating null.\nclass decimal_formatter_null : public decimal_formatter {\n public:\n explicit decimal_formatter_null(char *buf) : decimal_formatter(buf) {}\n\n template char *on(uint32_t u) {\n char *buf = decimal_formatter::on(u);\n *buf = '\\0';\n return buf;\n }\n};\n\n#ifdef FMT_BUILTIN_CLZ\n// Optional version of count_digits for better performance on 32-bit platforms.\ninline unsigned count_digits(uint32_t n) {\n int t = (32 - FMT_BUILTIN_CLZ(n | 1)) * 1233 >> 12;\n return to_unsigned(t) - (n < data::ZERO_OR_POWERS_OF_10_32[t]) + 1;\n}\n#endif\n\n// A functor that doesn't add a thousands separator.\nstruct no_thousands_sep {\n typedef char char_type;\n\n template \n void operator()(Char *) {}\n\n enum { size = 0 };\n};\n\n// A functor that adds a thousands separator.\ntemplate \nclass add_thousands_sep {\n private:\n basic_string_view sep_;\n\n // Index of a decimal digit with the least significant digit having index 0.\n unsigned digit_index_;\n\n public:\n typedef Char char_type;\n\n explicit add_thousands_sep(basic_string_view sep)\n : sep_(sep), digit_index_(0) {}\n\n void operator()(Char *&buffer) {\n if (++digit_index_ % 3 != 0)\n return;\n buffer -= sep_.size();\n std::uninitialized_copy(sep_.data(), sep_.data() + sep_.size(),\n internal::make_checked(buffer, sep_.size()));\n }\n\n enum { size = 1 };\n};\n\ntemplate \nFMT_API Char thousands_sep_impl(locale_ref loc);\n\ntemplate \ninline Char thousands_sep(locale_ref loc) {\n return Char(thousands_sep_impl(loc));\n}\n\ntemplate <>\ninline wchar_t thousands_sep(locale_ref loc) {\n return thousands_sep_impl(loc);\n}\n\n// Formats a decimal unsigned integer value writing into buffer.\n// thousands_sep is a functor that is called after writing each char to\n// add a thousands separator if necessary.\ntemplate \ninline Char *format_decimal(Char *buffer, UInt value, unsigned num_digits,\n ThousandsSep thousands_sep) {\n buffer += num_digits;\n Char *end = buffer;\n while (value >= 100) {\n // Integer division is slow so do it for a group of two digits instead\n // of for every digit. The idea comes from the talk by Alexandrescu\n // \"Three Optimization Tips for C++\". See speed-test for a comparison.\n unsigned index = static_cast((value % 100) * 2);\n value /= 100;\n *--buffer = static_cast(data::DIGITS[index + 1]);\n thousands_sep(buffer);\n *--buffer = static_cast(data::DIGITS[index]);\n thousands_sep(buffer);\n }\n if (value < 10) {\n *--buffer = static_cast('0' + value);\n return end;\n }\n unsigned index = static_cast(value * 2);\n *--buffer = static_cast(data::DIGITS[index + 1]);\n thousands_sep(buffer);\n *--buffer = static_cast(data::DIGITS[index]);\n return end;\n}\n\ntemplate \ninline Iterator format_decimal(\n Iterator out, UInt value, unsigned num_digits, ThousandsSep sep) {\n typedef typename ThousandsSep::char_type char_type;\n // Buffer should be large enough to hold all digits (<= digits10 + 1).\n enum { max_size = std::numeric_limits::digits10 + 1 };\n FMT_ASSERT(ThousandsSep::size <= 1, \"invalid separator\");\n char_type buffer[max_size + max_size / 3];\n auto end = format_decimal(buffer, value, num_digits, sep);\n return internal::copy_str(buffer, end, out);\n}\n\ntemplate \ninline It format_decimal(It out, UInt value, unsigned num_digits) {\n return format_decimal(out, value, num_digits, no_thousands_sep());\n}\n\ntemplate \ninline Char *format_uint(Char *buffer, UInt value, unsigned num_digits,\n bool upper = false) {\n buffer += num_digits;\n Char *end = buffer;\n do {\n const char *digits = upper ? \"0123456789ABCDEF\" : \"0123456789abcdef\";\n unsigned digit = (value & ((1 << BASE_BITS) - 1));\n *--buffer = static_cast(BASE_BITS < 4 ? '0' + digit : digits[digit]);\n } while ((value >>= BASE_BITS) != 0);\n return end;\n}\n\ntemplate \ninline It format_uint(It out, UInt value, unsigned num_digits,\n bool upper = false) {\n // Buffer should be large enough to hold all digits (digits / BASE_BITS + 1)\n // and null.\n char buffer[std::numeric_limits::digits / BASE_BITS + 2];\n format_uint(buffer, value, num_digits, upper);\n return internal::copy_str(buffer, buffer + num_digits, out);\n}\n\n#ifndef _WIN32\n# define FMT_USE_WINDOWS_H 0\n#elif !defined(FMT_USE_WINDOWS_H)\n# define FMT_USE_WINDOWS_H 1\n#endif\n\n// Define FMT_USE_WINDOWS_H to 0 to disable use of windows.h.\n// All the functionality that relies on it will be disabled too.\n#if FMT_USE_WINDOWS_H\n// A converter from UTF-8 to UTF-16.\n// It is only provided for Windows since other systems support UTF-8 natively.\nclass utf8_to_utf16 {\n private:\n wmemory_buffer buffer_;\n\n public:\n FMT_API explicit utf8_to_utf16(string_view s);\n operator wstring_view() const { return wstring_view(&buffer_[0], size()); }\n size_t size() const { return buffer_.size() - 1; }\n const wchar_t *c_str() const { return &buffer_[0]; }\n std::wstring str() const { return std::wstring(&buffer_[0], size()); }\n};\n\n// A converter from UTF-16 to UTF-8.\n// It is only provided for Windows since other systems support UTF-8 natively.\nclass utf16_to_utf8 {\n private:\n memory_buffer buffer_;\n\n public:\n utf16_to_utf8() {}\n FMT_API explicit utf16_to_utf8(wstring_view s);\n operator string_view() const { return string_view(&buffer_[0], size()); }\n size_t size() const { return buffer_.size() - 1; }\n const char *c_str() const { return &buffer_[0]; }\n std::string str() const { return std::string(&buffer_[0], size()); }\n\n // Performs conversion returning a system error code instead of\n // throwing exception on conversion error. This method may still throw\n // in case of memory allocation error.\n FMT_API int convert(wstring_view s);\n};\n\nFMT_API void format_windows_error(fmt::internal::buffer &out, int error_code,\n fmt::string_view message) FMT_NOEXCEPT;\n#endif\n\ntemplate \nstruct null {};\n} // namespace internal\n\nenum alignment {\n ALIGN_DEFAULT, ALIGN_LEFT, ALIGN_RIGHT, ALIGN_CENTER, ALIGN_NUMERIC\n};\n\n// Flags.\nenum { SIGN_FLAG = 1, PLUS_FLAG = 2, MINUS_FLAG = 4, HASH_FLAG = 8 };\n\n// An alignment specifier.\nstruct align_spec {\n unsigned width_;\n // Fill is always wchar_t and cast to char if necessary to avoid having\n // two specialization of AlignSpec and its subclasses.\n wchar_t fill_;\n alignment align_;\n\n FMT_CONSTEXPR align_spec() : width_(0), fill_(' '), align_(ALIGN_DEFAULT) {}\n FMT_CONSTEXPR unsigned width() const { return width_; }\n FMT_CONSTEXPR wchar_t fill() const { return fill_; }\n FMT_CONSTEXPR alignment align() const { return align_; }\n};\n\nstruct core_format_specs {\n int precision;\n uint_least8_t flags;\n char type;\n\n FMT_CONSTEXPR core_format_specs() : precision(-1), flags(0), type(0) {}\n FMT_CONSTEXPR bool has(unsigned f) const { return (flags & f) != 0; }\n};\n\n// Format specifiers.\ntemplate \nstruct basic_format_specs : align_spec, core_format_specs {\n FMT_CONSTEXPR basic_format_specs() {}\n};\n\ntypedef basic_format_specs format_specs;\n\ntemplate \nFMT_CONSTEXPR unsigned basic_parse_context::next_arg_id() {\n if (next_arg_id_ >= 0)\n return internal::to_unsigned(next_arg_id_++);\n on_error(\"cannot switch from manual to automatic argument indexing\");\n return 0;\n}\n\nnamespace internal {\n\n// Formats value using Grisu2 algorithm:\n// https://www.cs.tufts.edu/~nr/cs257/archive/florian-loitsch/printf.pdf\ntemplate \nFMT_API typename std::enable_if::type\n grisu2_format(Double value, buffer &buf, core_format_specs);\ntemplate \ninline typename std::enable_if::type\n grisu2_format(Double, buffer &, core_format_specs) { return false; }\n\ntemplate \nvoid sprintf_format(Double, internal::buffer &, core_format_specs);\n\ntemplate \nFMT_CONSTEXPR void handle_int_type_spec(char spec, Handler &&handler) {\n switch (spec) {\n case 0: case 'd':\n handler.on_dec();\n break;\n case 'x': case 'X':\n handler.on_hex();\n break;\n case 'b': case 'B':\n handler.on_bin();\n break;\n case 'o':\n handler.on_oct();\n break;\n case 'n':\n handler.on_num();\n break;\n default:\n handler.on_error();\n }\n}\n\ntemplate \nFMT_CONSTEXPR void handle_float_type_spec(char spec, Handler &&handler) {\n switch (spec) {\n case 0: case 'g': case 'G':\n handler.on_general();\n break;\n case 'e': case 'E':\n handler.on_exp();\n break;\n case 'f': case 'F':\n handler.on_fixed();\n break;\n case 'a': case 'A':\n handler.on_hex();\n break;\n default:\n handler.on_error();\n break;\n }\n}\n\ntemplate \nFMT_CONSTEXPR void handle_char_specs(\n const basic_format_specs *specs, Handler &&handler) {\n if (!specs) return handler.on_char();\n if (specs->type && specs->type != 'c') return handler.on_int();\n if (specs->align() == ALIGN_NUMERIC || specs->flags != 0)\n handler.on_error(\"invalid format specifier for char\");\n handler.on_char();\n}\n\ntemplate \nFMT_CONSTEXPR void handle_cstring_type_spec(Char spec, Handler &&handler) {\n if (spec == 0 || spec == 's')\n handler.on_string();\n else if (spec == 'p')\n handler.on_pointer();\n else\n handler.on_error(\"invalid type specifier\");\n}\n\ntemplate \nFMT_CONSTEXPR void check_string_type_spec(Char spec, ErrorHandler &&eh) {\n if (spec != 0 && spec != 's')\n eh.on_error(\"invalid type specifier\");\n}\n\ntemplate \nFMT_CONSTEXPR void check_pointer_type_spec(Char spec, ErrorHandler &&eh) {\n if (spec != 0 && spec != 'p')\n eh.on_error(\"invalid type specifier\");\n}\n\ntemplate \nclass int_type_checker : private ErrorHandler {\n public:\n FMT_CONSTEXPR explicit int_type_checker(ErrorHandler eh) : ErrorHandler(eh) {}\n\n FMT_CONSTEXPR void on_dec() {}\n FMT_CONSTEXPR void on_hex() {}\n FMT_CONSTEXPR void on_bin() {}\n FMT_CONSTEXPR void on_oct() {}\n FMT_CONSTEXPR void on_num() {}\n\n FMT_CONSTEXPR void on_error() {\n ErrorHandler::on_error(\"invalid type specifier\");\n }\n};\n\ntemplate \nclass float_type_checker : private ErrorHandler {\n public:\n FMT_CONSTEXPR explicit float_type_checker(ErrorHandler eh)\n : ErrorHandler(eh) {}\n\n FMT_CONSTEXPR void on_general() {}\n FMT_CONSTEXPR void on_exp() {}\n FMT_CONSTEXPR void on_fixed() {}\n FMT_CONSTEXPR void on_hex() {}\n\n FMT_CONSTEXPR void on_error() {\n ErrorHandler::on_error(\"invalid type specifier\");\n }\n};\n\ntemplate \nclass char_specs_checker : public ErrorHandler {\n private:\n char type_;\n\n public:\n FMT_CONSTEXPR char_specs_checker(char type, ErrorHandler eh)\n : ErrorHandler(eh), type_(type) {}\n\n FMT_CONSTEXPR void on_int() {\n handle_int_type_spec(type_, int_type_checker(*this));\n }\n FMT_CONSTEXPR void on_char() {}\n};\n\ntemplate \nclass cstring_type_checker : public ErrorHandler {\n public:\n FMT_CONSTEXPR explicit cstring_type_checker(ErrorHandler eh)\n : ErrorHandler(eh) {}\n\n FMT_CONSTEXPR void on_string() {}\n FMT_CONSTEXPR void on_pointer() {}\n};\n\ntemplate \nvoid arg_map::init(const basic_format_args &args) {\n if (map_)\n return;\n map_ = new entry[args.max_size()];\n bool use_values = args.type(max_packed_args - 1) == internal::none_type;\n if (use_values) {\n for (unsigned i = 0;/*nothing*/; ++i) {\n internal::type arg_type = args.type(i);\n switch (arg_type) {\n case internal::none_type:\n return;\n case internal::named_arg_type:\n push_back(args.values_[i]);\n break;\n default:\n break; // Do nothing.\n }\n }\n }\n for (unsigned i = 0; ; ++i) {\n switch (args.args_[i].type_) {\n case internal::none_type:\n return;\n case internal::named_arg_type:\n push_back(args.args_[i].value_);\n break;\n default:\n break; // Do nothing.\n }\n }\n}\n\ntemplate \nclass arg_formatter_base {\n public:\n typedef typename Range::value_type char_type;\n typedef decltype(internal::declval().begin()) iterator;\n typedef basic_format_specs format_specs;\n\n private:\n typedef basic_writer writer_type;\n writer_type writer_;\n format_specs *specs_;\n\n struct char_writer {\n char_type value;\n\n size_t size() const { return 1; }\n size_t width() const { return 1; }\n\n template \n void operator()(It &&it) const { *it++ = value; }\n };\n\n void write_char(char_type value) {\n if (specs_)\n writer_.write_padded(*specs_, char_writer{value});\n else\n writer_.write(value);\n }\n\n void write_pointer(const void *p) {\n format_specs specs = specs_ ? *specs_ : format_specs();\n specs.flags = HASH_FLAG;\n specs.type = 'x';\n writer_.write_int(reinterpret_cast(p), specs);\n }\n\n protected:\n writer_type &writer() { return writer_; }\n format_specs *spec() { return specs_; }\n iterator out() { return writer_.out(); }\n\n void write(bool value) {\n string_view sv(value ? \"true\" : \"false\");\n specs_ ? writer_.write_str(sv, *specs_) : writer_.write(sv);\n }\n\n void write(const char_type *value) {\n if (!value)\n FMT_THROW(format_error(\"string pointer is null\"));\n auto length = std::char_traits::length(value);\n basic_string_view sv(value, length);\n specs_ ? writer_.write_str(sv, *specs_) : writer_.write(sv);\n }\n\n public:\n arg_formatter_base(Range r, format_specs *s, locale_ref loc)\n : writer_(r, loc), specs_(s) {}\n\n iterator operator()(monostate) {\n FMT_ASSERT(false, \"invalid argument type\");\n return out();\n }\n\n template \n typename std::enable_if<\n std::is_integral::value || std::is_same::value,\n iterator>::type operator()(T value) {\n // MSVC2013 fails to compile separate overloads for bool and char_type so\n // use std::is_same instead.\n if (std::is_same::value) {\n if (specs_ && specs_->type)\n return (*this)(value ? 1 : 0);\n write(value != 0);\n } else if (std::is_same::value) {\n internal::handle_char_specs(\n specs_, char_spec_handler(*this, static_cast(value)));\n } else {\n specs_ ? writer_.write_int(value, *specs_) : writer_.write(value);\n }\n return out();\n }\n\n template \n typename std::enable_if::value, iterator>::type\n operator()(T value) {\n writer_.write_double(value, specs_ ? *specs_ : format_specs());\n return out();\n }\n\n struct char_spec_handler : internal::error_handler {\n arg_formatter_base &formatter;\n char_type value;\n\n char_spec_handler(arg_formatter_base& f, char_type val)\n : formatter(f), value(val) {}\n\n void on_int() {\n if (formatter.specs_)\n formatter.writer_.write_int(value, *formatter.specs_);\n else\n formatter.writer_.write(value);\n }\n void on_char() { formatter.write_char(value); }\n };\n\n struct cstring_spec_handler : internal::error_handler {\n arg_formatter_base &formatter;\n const char_type *value;\n\n cstring_spec_handler(arg_formatter_base &f, const char_type *val)\n : formatter(f), value(val) {}\n\n void on_string() { formatter.write(value); }\n void on_pointer() { formatter.write_pointer(value); }\n };\n\n iterator operator()(const char_type *value) {\n if (!specs_) return write(value), out();\n internal::handle_cstring_type_spec(\n specs_->type, cstring_spec_handler(*this, value));\n return out();\n }\n\n iterator operator()(basic_string_view value) {\n if (specs_) {\n internal::check_string_type_spec(\n specs_->type, internal::error_handler());\n writer_.write_str(value, *specs_);\n } else {\n writer_.write(value);\n }\n return out();\n }\n\n iterator operator()(const void *value) {\n if (specs_)\n check_pointer_type_spec(specs_->type, internal::error_handler());\n write_pointer(value);\n return out();\n }\n};\n\ntemplate \nFMT_CONSTEXPR bool is_name_start(Char c) {\n return ('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || '_' == c;\n}\n\n// DEPRECATED: Parses the input as an unsigned integer. This function assumes\n// that the first character is a digit and presence of a non-digit character at\n// the end.\n// it: an iterator pointing to the beginning of the input range.\ntemplate \nFMT_CONSTEXPR unsigned parse_nonnegative_int(Iterator &it, ErrorHandler &&eh) {\n assert('0' <= *it && *it <= '9');\n if (*it == '0') {\n ++it;\n return 0;\n }\n unsigned value = 0;\n // Convert to unsigned to prevent a warning.\n unsigned max_int = (std::numeric_limits::max)();\n unsigned big = max_int / 10;\n do {\n // Check for overflow.\n if (value > big) {\n value = max_int + 1;\n break;\n }\n value = value * 10 + unsigned(*it - '0');\n // Workaround for MSVC \"setup_exception stack overflow\" error:\n auto next = it;\n ++next;\n it = next;\n } while ('0' <= *it && *it <= '9');\n if (value > max_int)\n eh.on_error(\"number is too big\");\n return value;\n}\n\n// Parses the range [begin, end) as an unsigned integer. This function assumes\n// that the range is non-empty and the first character is a digit.\ntemplate \nFMT_CONSTEXPR unsigned parse_nonnegative_int(\n const Char *&begin, const Char *end, ErrorHandler &&eh) {\n assert(begin != end && '0' <= *begin && *begin <= '9');\n if (*begin == '0') {\n ++begin;\n return 0;\n }\n unsigned value = 0;\n // Convert to unsigned to prevent a warning.\n unsigned max_int = (std::numeric_limits::max)();\n unsigned big = max_int / 10;\n do {\n // Check for overflow.\n if (value > big) {\n value = max_int + 1;\n break;\n }\n value = value * 10 + unsigned(*begin - '0');\n ++begin;\n } while (begin != end && '0' <= *begin && *begin <= '9');\n if (value > max_int)\n eh.on_error(\"number is too big\");\n return value;\n}\n\ntemplate \nclass custom_formatter: public function {\n private:\n Context &ctx_;\n\n public:\n explicit custom_formatter(Context &ctx): ctx_(ctx) {}\n\n bool operator()(typename basic_format_arg::handle h) const {\n h.format(ctx_);\n return true;\n }\n\n template \n bool operator()(T) const { return false; }\n};\n\ntemplate \nstruct is_integer {\n enum {\n value = std::is_integral::value && !std::is_same::value &&\n !std::is_same::value && !std::is_same::value\n };\n};\n\ntemplate \nclass width_checker: public function {\n public:\n explicit FMT_CONSTEXPR width_checker(ErrorHandler &eh) : handler_(eh) {}\n\n template \n FMT_CONSTEXPR\n typename std::enable_if<\n is_integer::value, unsigned long long>::type operator()(T value) {\n if (is_negative(value))\n handler_.on_error(\"negative width\");\n return static_cast(value);\n }\n\n template \n FMT_CONSTEXPR typename std::enable_if<\n !is_integer::value, unsigned long long>::type operator()(T) {\n handler_.on_error(\"width is not integer\");\n return 0;\n }\n\n private:\n ErrorHandler &handler_;\n};\n\ntemplate \nclass precision_checker: public function {\n public:\n explicit FMT_CONSTEXPR precision_checker(ErrorHandler &eh) : handler_(eh) {}\n\n template \n FMT_CONSTEXPR typename std::enable_if<\n is_integer::value, unsigned long long>::type operator()(T value) {\n if (is_negative(value))\n handler_.on_error(\"negative precision\");\n return static_cast(value);\n }\n\n template \n FMT_CONSTEXPR typename std::enable_if<\n !is_integer::value, unsigned long long>::type operator()(T) {\n handler_.on_error(\"precision is not integer\");\n return 0;\n }\n\n private:\n ErrorHandler &handler_;\n};\n\n// A format specifier handler that sets fields in basic_format_specs.\ntemplate \nclass specs_setter {\n public:\n explicit FMT_CONSTEXPR specs_setter(basic_format_specs &specs):\n specs_(specs) {}\n\n FMT_CONSTEXPR specs_setter(const specs_setter &other): specs_(other.specs_) {}\n\n FMT_CONSTEXPR void on_align(alignment align) { specs_.align_ = align; }\n FMT_CONSTEXPR void on_fill(Char fill) { specs_.fill_ = fill; }\n FMT_CONSTEXPR void on_plus() { specs_.flags |= SIGN_FLAG | PLUS_FLAG; }\n FMT_CONSTEXPR void on_minus() { specs_.flags |= MINUS_FLAG; }\n FMT_CONSTEXPR void on_space() { specs_.flags |= SIGN_FLAG; }\n FMT_CONSTEXPR void on_hash() { specs_.flags |= HASH_FLAG; }\n\n FMT_CONSTEXPR void on_zero() {\n specs_.align_ = ALIGN_NUMERIC;\n specs_.fill_ = '0';\n }\n\n FMT_CONSTEXPR void on_width(unsigned width) { specs_.width_ = width; }\n FMT_CONSTEXPR void on_precision(unsigned precision) {\n specs_.precision = static_cast(precision);\n }\n FMT_CONSTEXPR void end_precision() {}\n\n FMT_CONSTEXPR void on_type(Char type) {\n specs_.type = static_cast(type);\n }\n\n protected:\n basic_format_specs &specs_;\n};\n\n// A format specifier handler that checks if specifiers are consistent with the\n// argument type.\ntemplate \nclass specs_checker : public Handler {\n public:\n FMT_CONSTEXPR specs_checker(const Handler& handler, internal::type arg_type)\n : Handler(handler), arg_type_(arg_type) {}\n\n FMT_CONSTEXPR specs_checker(const specs_checker &other)\n : Handler(other), arg_type_(other.arg_type_) {}\n\n FMT_CONSTEXPR void on_align(alignment align) {\n if (align == ALIGN_NUMERIC)\n require_numeric_argument();\n Handler::on_align(align);\n }\n\n FMT_CONSTEXPR void on_plus() {\n check_sign();\n Handler::on_plus();\n }\n\n FMT_CONSTEXPR void on_minus() {\n check_sign();\n Handler::on_minus();\n }\n\n FMT_CONSTEXPR void on_space() {\n check_sign();\n Handler::on_space();\n }\n\n FMT_CONSTEXPR void on_hash() {\n require_numeric_argument();\n Handler::on_hash();\n }\n\n FMT_CONSTEXPR void on_zero() {\n require_numeric_argument();\n Handler::on_zero();\n }\n\n FMT_CONSTEXPR void end_precision() {\n if (is_integral(arg_type_) || arg_type_ == pointer_type)\n this->on_error(\"precision not allowed for this argument type\");\n }\n\n private:\n FMT_CONSTEXPR void require_numeric_argument() {\n if (!is_arithmetic(arg_type_))\n this->on_error(\"format specifier requires numeric argument\");\n }\n\n FMT_CONSTEXPR void check_sign() {\n require_numeric_argument();\n if (is_integral(arg_type_) && arg_type_ != int_type &&\n arg_type_ != long_long_type && arg_type_ != internal::char_type) {\n this->on_error(\"format specifier requires signed argument\");\n }\n }\n\n internal::type arg_type_;\n};\n\ntemplate