Repository: bucaps/marss-riscv
Branch: master
Commit: 82b3ce2738f1
Files: 314
Total size: 4.4 MB
Directory structure:
gitextract_e6jvuvxv/
├── .gitignore
├── .gitmodules
├── Changelog.md
├── LICENSE.md
├── README.md
├── configs/
│ ├── riscv64_inorder_soc.cfg
│ └── riscv64_outoforder_soc.cfg
└── src/
├── DRAMsim3/
│ ├── .clang-format
│ ├── .gitignore
│ ├── .gitmodules
│ ├── .travis.yml
│ ├── CMakeLists.txt
│ ├── LICENSE
│ ├── Makefile
│ ├── README.md
│ ├── configs/
│ │ ├── DDR3_1Gb_x8_1333.ini
│ │ ├── DDR3_4Gb_x16_1600.ini
│ │ ├── DDR3_4Gb_x16_1866.ini
│ │ ├── DDR3_4Gb_x4_1600.ini
│ │ ├── DDR3_4Gb_x4_1866.ini
│ │ ├── DDR3_4Gb_x8_1600.ini
│ │ ├── DDR3_4Gb_x8_1866.ini
│ │ ├── DDR3_8Gb_x16_1600.ini
│ │ ├── DDR3_8Gb_x16_1866.ini
│ │ ├── DDR3_8Gb_x4_1600.ini
│ │ ├── DDR3_8Gb_x4_1866.ini
│ │ ├── DDR3_8Gb_x8_1600.ini
│ │ ├── DDR3_8Gb_x8_1866.ini
│ │ ├── DDR4_4Gb_x16_1866.ini
│ │ ├── DDR4_4Gb_x16_2133.ini
│ │ ├── DDR4_4Gb_x16_2133_2.ini
│ │ ├── DDR4_4Gb_x16_2400.ini
│ │ ├── DDR4_4Gb_x16_2400_2.ini
│ │ ├── DDR4_4Gb_x16_2666.ini
│ │ ├── DDR4_4Gb_x16_2666_2.ini
│ │ ├── DDR4_4Gb_x4_1866.ini
│ │ ├── DDR4_4Gb_x4_2133.ini
│ │ ├── DDR4_4Gb_x4_2133_2.ini
│ │ ├── DDR4_4Gb_x4_2400.ini
│ │ ├── DDR4_4Gb_x4_2400_2.ini
│ │ ├── DDR4_4Gb_x4_2666.ini
│ │ ├── DDR4_4Gb_x4_2666_2.ini
│ │ ├── DDR4_4Gb_x8_1866.ini
│ │ ├── DDR4_4Gb_x8_2133.ini
│ │ ├── DDR4_4Gb_x8_2133_2.ini
│ │ ├── DDR4_4Gb_x8_2400.ini
│ │ ├── DDR4_4Gb_x8_2400_2.ini
│ │ ├── DDR4_4Gb_x8_2666.ini
│ │ ├── DDR4_4Gb_x8_2666_2.ini
│ │ ├── DDR4_8Gb_x16_1866.ini
│ │ ├── DDR4_8Gb_x16_2133.ini
│ │ ├── DDR4_8Gb_x16_2133_2.ini
│ │ ├── DDR4_8Gb_x16_2400.ini
│ │ ├── DDR4_8Gb_x16_2400_2.ini
│ │ ├── DDR4_8Gb_x16_2666.ini
│ │ ├── DDR4_8Gb_x16_2666_2.ini
│ │ ├── DDR4_8Gb_x16_2933.ini
│ │ ├── DDR4_8Gb_x16_2933_2.ini
│ │ ├── DDR4_8Gb_x16_3200.ini
│ │ ├── DDR4_8Gb_x4_1866.ini
│ │ ├── DDR4_8Gb_x4_2133.ini
│ │ ├── DDR4_8Gb_x4_2133_2.ini
│ │ ├── DDR4_8Gb_x4_2400.ini
│ │ ├── DDR4_8Gb_x4_2400_2.ini
│ │ ├── DDR4_8Gb_x4_2666.ini
│ │ ├── DDR4_8Gb_x4_2666_2.ini
│ │ ├── DDR4_8Gb_x4_2933.ini
│ │ ├── DDR4_8Gb_x4_2933_2.ini
│ │ ├── DDR4_8Gb_x4_3200.ini
│ │ ├── DDR4_8Gb_x8_1866.ini
│ │ ├── DDR4_8Gb_x8_2133.ini
│ │ ├── DDR4_8Gb_x8_2133_2.ini
│ │ ├── DDR4_8Gb_x8_2400.ini
│ │ ├── DDR4_8Gb_x8_2400_2.ini
│ │ ├── DDR4_8Gb_x8_2666.ini
│ │ ├── DDR4_8Gb_x8_2666_2.ini
│ │ ├── DDR4_8Gb_x8_2933.ini
│ │ ├── DDR4_8Gb_x8_2933_2.ini
│ │ ├── DDR4_8Gb_x8_3200.ini
│ │ ├── GDDR5X_8Gb_x32.ini
│ │ ├── GDDR5_1Gb_x32.ini
│ │ ├── GDDR5_8Gb_x32.ini
│ │ ├── GDDR6_8Gb_x16.ini
│ │ ├── HBM1_4Gb_x128.ini
│ │ ├── HBM2_4Gb_x128.ini
│ │ ├── HBM2_8Gb_x128.ini
│ │ ├── HBM_4Gb_x128.ini
│ │ ├── HMC2_8GB_4Lx16.ini
│ │ ├── HMC_2GB_4Lx16.ini
│ │ ├── HMC_2GB_4Lx16_dummy.ini
│ │ ├── HMC_4GB_4Lx16.ini
│ │ ├── LPDDR3_8Gb_x32_1333.ini
│ │ ├── LPDDR3_8Gb_x32_1600.ini
│ │ ├── LPDDR3_8Gb_x32_1866.ini
│ │ ├── LPDDR4_8Gb_x16_2400.ini
│ │ ├── ST-1.2x.ini
│ │ ├── ST-1.5x.ini
│ │ ├── ST-2.0x.ini
│ │ ├── ddr3_debug.ini
│ │ ├── ddr4_debug.ini
│ │ └── lpddr_2Gb_x16.ini
│ ├── ext/
│ │ ├── fmt/
│ │ │ ├── LICENSE.rst
│ │ │ └── include/
│ │ │ └── fmt/
│ │ │ ├── core.h
│ │ │ ├── format-inl.h
│ │ │ └── format.h
│ │ └── headers/
│ │ ├── INIHLICENSE.txt
│ │ ├── INIReader.h
│ │ ├── args.hxx
│ │ ├── catch.hpp
│ │ └── json.hpp
│ ├── scripts/
│ │ ├── batch_run.py
│ │ ├── final_PowerTemperature_map.py
│ │ ├── heatmap.py
│ │ ├── parse_config.py
│ │ ├── plot_stats.py
│ │ ├── trace_gen.py
│ │ └── validation.py
│ ├── src/
│ │ ├── bankstate.cc
│ │ ├── bankstate.h
│ │ ├── channel_state.cc
│ │ ├── channel_state.h
│ │ ├── command_queue.cc
│ │ ├── command_queue.h
│ │ ├── common.cc
│ │ ├── common.h
│ │ ├── configuration.cc
│ │ ├── configuration.h
│ │ ├── controller.cc
│ │ ├── controller.h
│ │ ├── cpu.cc
│ │ ├── cpu.h
│ │ ├── dram_system.cc
│ │ ├── dram_system.h
│ │ ├── dramsim3.h
│ │ ├── hmc.cc
│ │ ├── hmc.h
│ │ ├── main.cc
│ │ ├── memory_system.cc
│ │ ├── memory_system.h
│ │ ├── refresh.cc
│ │ ├── refresh.h
│ │ ├── simple_stats.cc
│ │ ├── simple_stats.h
│ │ ├── sp_ienv.c
│ │ ├── thermal.cc
│ │ ├── thermal.h
│ │ ├── thermal_config.h
│ │ ├── thermal_replay.cc
│ │ ├── thermal_replay.h
│ │ ├── thermal_solver.c
│ │ ├── timing.cc
│ │ └── timing.h
│ └── tests/
│ ├── example.trace
│ ├── test_config.cc
│ ├── test_dramsys.cc
│ └── test_hmcsys.cc
├── MIT-LICENSE.txt
├── Makefile
├── VERSION
├── aes.c
├── aes.h
├── block_net.c
├── build_filelist.c
├── cutils.c
├── cutils.h
├── fbuf.h
├── fs.c
├── fs.h
├── fs_disk.c
├── fs_net.c
├── fs_utils.c
├── fs_utils.h
├── fs_wget.c
├── fs_wget.h
├── ide.c
├── ide.h
├── iomem.c
├── iomem.h
├── json.c
├── json.h
├── list.h
├── machine.c
├── machine.h
├── netinit.sh
├── pci.c
├── pci.h
├── pckbd.c
├── ps2.c
├── ps2.h
├── riscv_cpu.c
├── riscv_cpu.h
├── riscv_cpu_fp_template.h
├── riscv_cpu_priv.h
├── riscv_cpu_template.h
├── riscv_cpu_xlen_typedefs.h
├── riscv_machine.c
├── riscvsim/
│ ├── bpu/
│ │ ├── adaptive_predictor.c
│ │ ├── adaptive_predictor.h
│ │ ├── bht.c
│ │ ├── bht.h
│ │ ├── bpu.c
│ │ ├── bpu.h
│ │ ├── btb.c
│ │ ├── btb.h
│ │ ├── ras.c
│ │ └── ras.h
│ ├── core/
│ │ ├── inorder.c
│ │ ├── inorder.h
│ │ ├── inorder_backend.c
│ │ ├── inorder_frontend.c
│ │ ├── ooo.c
│ │ ├── ooo.h
│ │ ├── ooo_backend.c
│ │ ├── ooo_branch.c
│ │ ├── ooo_frontend.c
│ │ ├── ooo_lsu.c
│ │ ├── riscv_sim_cpu.c
│ │ └── riscv_sim_cpu.h
│ ├── decoder/
│ │ ├── fp_decode_template.h
│ │ ├── fp_execute_template.h
│ │ ├── fp_string_generator_template.h
│ │ ├── riscv_instruction.h
│ │ ├── riscv_isa_decoder.c
│ │ ├── riscv_isa_execute.c
│ │ └── riscv_isa_string_generator.c
│ ├── memory_hierarchy/
│ │ ├── cache.c
│ │ ├── cache.h
│ │ ├── dram.c
│ │ ├── dram.h
│ │ ├── dramsim_wrapper.cpp
│ │ ├── dramsim_wrapper.h
│ │ ├── dramsim_wrapper_c_connector.cpp
│ │ ├── dramsim_wrapper_c_connector.h
│ │ ├── memory_controller.c
│ │ ├── memory_controller.h
│ │ ├── memory_controller_utils.h
│ │ ├── memory_hierarchy.c
│ │ ├── memory_hierarchy.h
│ │ ├── ramulator_wrapper.cpp
│ │ ├── ramulator_wrapper.h
│ │ ├── ramulator_wrapper_c_connector.cpp
│ │ ├── ramulator_wrapper_c_connector.h
│ │ ├── temu_mem_map_wrapper.c
│ │ └── temu_mem_map_wrapper.h
│ ├── riscv_sim_macros.h
│ ├── riscv_sim_typedefs.h
│ └── utils/
│ ├── circular_queue.c
│ ├── circular_queue.h
│ ├── cpu_latches.c
│ ├── cpu_latches.h
│ ├── evict_policy.c
│ ├── evict_policy.h
│ ├── sim_exception.c
│ ├── sim_exception.h
│ ├── sim_log.c
│ ├── sim_log.h
│ ├── sim_params.c
│ ├── sim_params.h
│ ├── sim_stats.c
│ ├── sim_stats.h
│ ├── sim_trace.c
│ └── sim_trace.h
├── rtc_timer.c
├── rtc_timer.h
├── sdl.c
├── sha256.c
├── sha256.h
├── simplefb.c
├── slirp/
│ ├── bootp.c
│ ├── bootp.h
│ ├── cksum.c
│ ├── debug.h
│ ├── if.c
│ ├── if.h
│ ├── ip.h
│ ├── ip_icmp.c
│ ├── ip_icmp.h
│ ├── ip_input.c
│ ├── ip_output.c
│ ├── libslirp.h
│ ├── main.h
│ ├── mbuf.c
│ ├── mbuf.h
│ ├── misc.c
│ ├── misc.h
│ ├── sbuf.c
│ ├── sbuf.h
│ ├── slirp.c
│ ├── slirp.h
│ ├── slirp_config.h
│ ├── socket.c
│ ├── socket.h
│ ├── tcp.h
│ ├── tcp_input.c
│ ├── tcp_output.c
│ ├── tcp_subr.c
│ ├── tcp_timer.c
│ ├── tcp_timer.h
│ ├── tcp_var.h
│ ├── tcpip.h
│ ├── tftp.h
│ ├── udp.c
│ └── udp.h
├── softfp.c
├── softfp.h
├── softfp_template.h
├── softfp_template_icvt.h
├── splitimg.c
├── stats_display.c
├── temu.c
├── vga.c
├── virtio.c
├── virtio.h
└── vmmouse.c
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
# exclude all object files
src/*.o
src/riscvsim/*.o
src/slirp/*.o
# exclude all dependency files
src/*.d
src/riscvsim/*.d
src/slirp/*.d
# exclude stats, log and trace files
src/*.csv
src/*.log
src/*.trace
# exclude executables
src/marss-riscv
src/sim-stats-display
src/build_filelist
src/splitimg
# exclude libraries
src/*.so
src/*.a
================================================
FILE: .gitmodules
================================================
================================================
FILE: Changelog.md
================================================
# Version 4.1a
- Added
- Model a arbitrary fixed latency between LLC cache and Memory controller
- Changed
- For Ramulator and DRAMSim3, memory access request is split into MEM_BUS_WIDTH sized parts and latency for each part is queried
- Fixed
- Rounding mode (rm) must be calculated again before executing FP instruction during simulation
# Version 4.0a
- Added
- Comprehensive logging support
- Command-line option `-sim-file-path` to specify a top-level directory to store statistics and log files
- Command-line option `-sim-file-prefix` to specify prefix appended to all simulator generated files
- Command-line option `-sim-emulate-after-icount` to specify the number of instruction to simulate after starting simulation mode
- [DRAMsim3](https://github.com/umd-memsys/DRAMSim3) support
- [Ramulator](https://github.com/CMU-SAFARI/ramulator) support
- Sample MARSS-RISCV configuration files for a 64-bit RISC-V In-order and Out-of-order SoC in [configs](./configs) folder
- More performance counters to count different types of load instructions (byte, half-word, word, double-word)
- Time-stamp to all the statistics files generated by the simulator
- Specify latency in CPU cycles for RISC-V `SYSTEM` class instructions in the config file
- Counter to track the number of CPU pipeline flushes
- Counters to tracks each type of software exceptions and hardware interrupt processed during simulation
- Parallel build support for Makefile
- During the simulation, `mtime` is calculated using simulation clock cycles
- Specify frequency for CPU and RTC device via the config file
- Add option `flush_on_context_switch` in the config file to enable/disable flushing of BPU on a context switch
- Start fetching the target from the next cycle on branch misprediction
- Load for non-word quantities (byte and half-word) take an extra one cycle on cache-hit
- Add function to invalidate entries in mem_request_queue on the miss-speculated path
- Changed
- Re-factor and modularize simulator code-base
- STORE type instructions submit write-request to L1-data cache and exit memory stage in a single cycle
- Delay for reading/writing page-table entries is now simulated via L1-Data cache
- Print IPC for all the RISC-V CPU modes after simulation completes to the console and log file
- In-order core doesn't support parallel execution in multiple functional units
- Replace hot-cold LRU eviction policy with bit-PLRU eviction policy for BTB and caches
- Improve the format of TinyEMU config file
- Update [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)
- Update README.md
- Page walk delays are simulated via L1 D$
- Removed [DRAMsim2](https://github.com/umd-memsys/DRAMSim2) support
- Fixed
- Memory leaks
- Don't start simulating DRAM access delay until cache lookup delay is simulated
- Branch entry is added to BTB, only after the branch is resolved
# Version 3.1a
- Added
- Print TLB stats to the terminal after the simulation completes
- Specify latency for each FPU ALU instruction (`fadd`, `fsub`, `fmul`, `fdiv`, `fmin`, `fmax`, `fcvt`, `cvt`, `fle`, `flt`, `feq`, `fsgnj`, `fqsrt`, `fmv`, `fclass`) via TinyEMU config file
- Figure showing the high-level overview of MARSS-RISCV in README.md
- Changed
- Simplify the base DRAM model
- All memory accesses simulate a fixed latency `mem_access_latency`
- Any subsequent accesses to the same physical page occupies a lower delay, which is roughly 60 percent of the fixed `mem_access_latency`
- More info [here](https://marss-riscv-docs.readthedocs.io/en/latest/)
- Parallel operation of functional units can be enabled or disabled in the in-order core via TinyEMU config file
- Clean exception handling code
- Simulate page table entry read/write delays directly via memory controller using a configurable fixed latency `pte_rw_latency`
- Don't stall the pipeline stage for the write request to complete on the memory controller
- Make FPU-ALU non-pipelined
- Rename `dram_dispatch_queue` to`mem_request_queue`
- Update [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)
- Update README.md
- Update TinyEMU config file [here](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz)
- Fixed
- memory leaks
# Version 3.0a
- Added
- Support for separate RISC-V Bios and Kernel
- Command line option `flush-sim-mem` to flush simulator memory hierarchy on every fresh simulation run
- Command line option `sim-trace` to generate instruction commit trace during simulation
- Distinct configurable read-hit and write-hit latency for all the caches
- Return address stack (RAS)
- Branch prediction and speculative execution support for out of order core
- Print performance counters on terminal when the simulation completes
- More performance counters:
- Instruction types
- ecall
- page walks for loads, stores and instructions
- memory controller delay for data and instructions
- hardware interrupts
- Changed
- Port to TinyEMU version `2019-12-21`
- For bimodal branch predictor, store prediction bits in a separate Branch history table (BHT)
- For in-order core, non-memory instructions can forward their result from MEM stage in addition to EX stage
- For in-order core, relaxed interlocking on WAW data hazard
- Simplified out of order core design, ROB slots are now used as physical registers along with a single rename table and a single global issue queue
- Fixed
- Correctly calculated the rounding mode for floating pointing instruction decoding
- Converted `c.addiw` result buffer into `int32_t` on 64-bit simulation
- Set the data type to `unint64_t` for 64-bit simulation, for the buffer which holds the memory address for atomic instructions
- Issue #13 and #14 (thanks to Okhotnikov Grigory)
# Version 2.0a
- Added
- Added [DRAMSim2](https://github.com/umd-memsys/DRAMSim2) support
- Changed
- Flush all the CPU caches and DRAM models for every new simulation run
- Fixed
- Issue #8: useless cleaning of local variables
# Version 1.1a
- Added
- Add 16550A UART support (thanks to Marc Gauthier)
- Add a timestamp suffix to the stats file
- Changed
- Reworked the dram latency parameters to match the Sifive HiFive U540 Board
- Increased the dram dispatch queue size from 32 to 64
- Fixed
- Calculation of hardware page walk latency
- Miscalculation in page fault counters
- Issue #2: memory leaks in copy_file
- Issue #3: 'log' instead 'log2'
================================================
FILE: LICENSE.md
================================================
MIT License
Copyright (c) 2016-2017 Fabrice Bellard
Copyright (c) 2017-2019 Gaurav Kothari
Copyright (c) 2018-2019 Parikshit Sarnaik
Copyright (c) 2019 Göktürk Yüksek
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
================================================
FILE: README.md
================================================
## MARSS-RISCV: Micro-Architectural System Simulator for RISC-V
MARSS-RISCV (Micro-ARchitectural System Simulator - RISCV) is an **open-source, cycle-level single-core full-system (Linux) micro-architectural simulator** for the [RISC-V](https://riscv.org/specifications/) ISA built on top of [TinyEMU emulator](https://bellard.org/tinyemu) developed by Fabrice Bellard and utilizes the configuration code, RISC-V CPU state, physical memory, MMU, and all the devices emulated by TinyEMU.
It consists of detailed cycle-level models of a generic RISC-V In-order and Out-of-order processor with a branch prediction unit, TLBs, cache-hierarchy, and a simplistic DRAM model. It comes integrated with [DRAMSim3](https://github.com/umd-memsys/DRAMSim3) and [Ramulator](https://github.com/CMU-SAFARI/ramulator), which are cycle-accurate DRAM simulators. It can simulate the entire RISC-V software stack (from the bootloader and kernel to the user level applications, including system calls) cycle-by-cycle along with the real-time I/O without any modifications and provides simulation statistics for all the RISC-V CPU privilege modes (user, supervisor, and machine). Hence, it makes MARSS-RISCV, a full system simulation framework that simulates an entire RISC-V system-on-a-chip (SoC) cycle-by-cycle.
It is currently being developed and maintained by [CAPS](https://github.com/bucaps/) (Computer Architecture and Power-Aware Systems Research Group) at the State University of New York at Binghamton. Our simulator is currently in alpha status as we are validating the cycle accuracy using various development boards. The figure below shows a high-level overview of the MARSS-RISCV simulation framework.
## Table of contents
- [Features](#features)
- [Getting started with the simulator running a Linux guest](#getting-started-with-the-simulator-running-a-linux-guest)
- [Running full system simulations](#running-full-system-simulations)
- [Viewing live simulation stats](#viewing-live-simulation-stats)
- [Generating simulation trace](#generating-simulation-trace)
- [Future work](#future-work)
- [Technical notes](#technical-notes)
- [Authors](#authors)
- [Acknowledgment](#acknowledgment)
- [License](#license)
## Features
- **Full system simulator** which simulates the entire system on a cycle-by-cyle basis, including the bootloader, kernel, libraries, interrupt handlers, and user-level applications
- **Configurable RISC-V CPU** with cycle-level, in-order and out-of-order processor models
- **Multiple execution units** with configurable latencies (execution units can be configured to run iteratively or in a pipelined fashion)
- **Simulates memory access delay for instructions, data and page table walk** via three direct-mapped TLBs (for code, loads and stores), two-level cache hierarchy with various allocation and miss handling policies and following DRAM memory models: A simplistic base DRAM model (which simulates a fixed delay for every main memory access), [DRAMSim3](https://github.com/umd-memsys/DRAMSim3), and [Ramulator](https://github.com/CMU-SAFARI/ramulator)
- **Branch predictor** which supports Bi-modal and 2-level adaptive (Gshare, Gselect, GAg, GAp, PAg, PAp) predictors and a Return address stack (RAS)
- **RISC-V ISA support** includes `RV32GC` and `RV64GC` (user-level ISA version `2.2`, privileged architecture version `1.10`)
- **Emulated devices** include standard platform-level interrupt controller (PLIC), core local interrupter (CLINT), real-time clock device (RTC), universal asynchronous receiver/transmitter (UART), VirtIO, NIC, block device, and 9P filesystem
- **Single JSON configuration file** to configure TinyEMU and simulator parameters, specify RISC-V BIOS and kernel individually
- **Easy to install, use and hack** with a small codebase
For more details regarding the microarchitecture of the simulated CPU, branch predictor, memory hierarchy and simulator configuration, refer to [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)
## Getting started with the simulator running a Linux guest
### System requirements
* 32-bit or 64-bit Linux machine
* Libcurl, OpenSSL and SDL Libraries
* Standard C and C++ compiler
### Installing the dependencies
Make sure that you have all the dependencies (`ssl`, `sdl`, and `curl` libraries) installed on the system. For Debian-based (including Ubuntu) systems, the packages are: `build-essential`, `libssl-dev`, `libsdl1.2-dev`, `libcurl4-openssl-dev`.
```console
$ sudo apt-get update
$ sudo apt-get install build-essential
$ sudo apt-get install libssl-dev
$ sudo apt-get install libsdl1.2-dev
$ sudo apt-get install libcurl4-openssl-dev
```
### Compiling the simulator
First, clone the simulator repository:
```console
$ git clone https://github.com/bucaps/marss-riscv
```
Then, `cd` into the simulator source directory:
```console
$ cd marss-riscv/src/
```
Set the `CONFIG_XLEN` variable in the Makefile to the desired `XLEN` as required. Supported `XLEN` values are `32` and `64`. Default is `64`.
Then, compile the simulator using:
```console
$ make
```
### Preparing the bootloader, kernel and userland image
The simplest way to start is by using a pre-built bootloader, kernel, and userland image. The pre-built 32-bit and 64-bit RISC-V userland, bootloader, and kernel are available here: [marss-riscv-images.tar.gz](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz)
The userland image needs to be decompressed before running the simulator:
```console
$ wget https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz
$ tar -xvzf marss-riscv-images.tar.gz
$ cd marss-riscv-images/riscv64-unknown-linux-gnu/
$ xz -d -k -T 0 riscv64.img.xz
```
When decompression finishes, jump to the marss-riscv `src` folder and launch the simulator with:
```console
$ ./marss-riscv ../configs/riscv64_inorder_soc.cfg
```
Simulation and TinyEMU SoC parameters are configured using the TinyEMU JSON configuration file provided in the [configs](/configs) directory. We have provided sample configuration files for 64-bit RISC-V single-core in-order and out-of-order SoC. The following table provides a summary of various simulation related command-line options supported by MARSS-RISCV.
| Options | Arguments | Description |
|-----------------------------|--------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `-rw` | - | By default, the simulator will boot in `snapshot` mode, meaning it will **not** retain the file system changes after it is shut down. In order to persist the changes, pass `-rw` command-line argument to the simulator. |
| `-simstart` | - | By default, guest boots in emulation mode, to start TinyEMU (boot kernel) in simulation mode run with `-simstart` command-line option. |
| `-sim-stats-display` | `posix-shm-name` | Dump simulation performance stats to a shared memory location `posix-shm-name`, read by sim-stats-display tool. First, open a new terminal before executing the simulator and launch `sim-stats-display` tool with `posix-shm-name` as an argument. Then start the simulator on a different terminal with `-sim-stats-display` command-line option with `posix-shm-name` as an argument. |
| `-sim-mem-model` | `base`, `dramsim3`, `ramulator` | To specify which memory model to use, run with command line option `-sim-mem-model` and specify either `base`, `dramsim3`, or `ramulator`. The default is `base`. For DRAMSim3 and Ramulator, the paths to `config file` can be specified in the TinyEMU config file. |
| `-sim-flush-mem` | - | Flush simulator memory hierarchy on every new simulation run |
| `-sim-flush-bpu` | - | Flush branch prediction unit on every new simulation run |
| `-sim-file-path` | `directory path` | Path of the directory to store stats, log, dramsim3 stats, ramulator stats, and trace files. Default is current directory `.`, the user must create the directory before starting MARSS-RISCV. |
| `-sim-file-prefix` | `prefix` | Prefix appended to stats, log, and trace file names. Default prefix used for all the simulator generated files is `sim`. (E.g., sim_.csv (for stats), sim.log, sim.trace) |
| `-sim-trace` | | Generate instruction commit trace in during simulation. Trace is generated in file named `_trace.txt` |
| `-sim-emulate-after-icount` | `icount` | Switch to emulation mode after simulating `icount` instructions every time simulation starts. |
It may also be desirable to increase the userland image (has roughly 200MB of available free space by default). More information about how to increase the size of the userland image is in the `readme.txt` file, which comes with the [images archive](https://cs.binghamton.edu/~marss-riscv/marss-riscv-images.tar.gz).
Once the guest boots, we need to initialize the environment. Normally, this should happen automatically, but due to an unresolved bug, it needs to done explicitly:
```console
# export PYTHONPATH=/usr/lib64/python2.7/site-packages/
# env-update
```
The system is ready for use and has a working GCC compiler, ssh, git, and virtual network interface. However, there is no host-to-guest routing, so it is not possible to ssh into the guest.
By default, `Ctrl-C` will not kill the simulator. The command `halt` will cleanly shutdown the guest. Alternatively, pass the `-ctrlc` command-line argument to the simulator, which will allow it to be killed using `Ctrl-C`.
After gaining access to the guest machine terminal, refer to the next section for running simulations.
## Running full system simulations
### Using checkpoints
The simulator supports two distinct custom instructions, `SIM_START()` and `SIM_STOP()`, which inform MARSS-RISCV to enable and disable simulation mode, respectively, when encountered during instruction processing. To implement these instructions, we have used two different unused registers from user mode CSR address space, `0x800`, and `0x801`. When the simulation is disabled, MARSS-RISCV runs in the emulation mode.
With these two custom instructions as checkpoints, it is possible to simulate any section in the source code. However, after inserting these markers, the source code must be recompiled inside the guest OS using the installed GCC toolchain. Alternatively, users can compile the programs on their host machine using the RISC-V toolchain and import them onto the disk image.
After the simulator executes `SIM_STOP()` instruction, simulation mode is disabled, and all the performance stats are saved in the file `sim_stats_file` as configured in the simulator configuration file. The code below shows a simple hello world program with checkpoints instructions.
```c
/* hello_world.c */
#include
#define SIM_START() asm("csrs 0x800,zero")
#define SIM_STOP() asm("csrs 0x801,zero")
int main()
{
SIM_START();
printf("Hello World\n");
SIM_STOP();
return 0;
}
```
### Using the simulate script
Alternatively, users can use the simulation script (`simulate.c`) provided [here](https://github.com/bucaps/marss-riscv-utils/blob/master/simulate.c), which forks a child process. The child enters the simulation mode and execs the command. The parent process waits for the child to complete and then switches MARSS-RISCV back to emulation mode. With this script, it is possible to simulate any program without the need to modify and recompile the source code. Since the child switches to simulation mode before calling `exec()`, `exec()` also runs in the simulation. Hence, performance statistics generated at the end of the simulation will also include stats for `exec()`.
### Running benchmarks
We have provided a detailed step-by-step comprehensive tutorial [here](https://marss-riscv-docs.readthedocs.io/en/latest/sections/running-full-system.html) to run the benchmarks on the simulator. This tutorial configures MARSS-RISCV to simulate a simple 5-stage 32-bit in-order RISC-V processor and run [CoreMark](https://github.com/eembc/coremark), an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcontrollers (MCU).
## Viewing live simulation stats
Users can view live simulation stats using the provided `sim-stats-display` tool. First, open a new terminal before executing the simulator and launch `sim-stats-display` with a shared memory name of the user's choice as an argument:
```console
$ ./sim-stats-display marss-riscv-test-shm
```
Then launch the simulator on a different terminal with `-sim-stats-display marss-riscv-test-shm` command-line option.
## Generating simulation trace
To generate instruction, commit trace of the programs running in the simulation, run MARSS-RISCV with `-sim-trace` command-line option.
Sample trace generated is shown below:
```bash
cycle=112 pc=0x6aaaadf8 insn=0x85be863a c.mv a2,a4 mode=PRV_U
cycle=113 pc=0x6aaaadfa insn=0x250385be c.mv a1,a5 mode=PRV_U
cycle=115 pc=0x6aaaadfc insn=0xfa842503 lw a0,s0,-88 mode=PRV_U
```
## Technical notes
This section refers to technical notes for [TinyEMU](https://bellard.org/tinyemu). For simulator specific technical details refer: [MARSS-RISCV Docs](https://marss-riscv-docs.readthedocs.io/en/latest/)
### Floating point emulation
The floating-point emulation is bit-exact and supports all the specified instructions for 32-bit and 64-bit floating-point numbers. It uses the new SoftFP library.
### HTIF console
The standard HTIF console uses registers at variable addresses, which are deduced by loading specific ELF symbols. TinyEMU does not rely on an ELF loader, so it is much simpler to use registers at fixed addresses (0x40008000). A small modification was made in the "riscv-pk" boot loader to support it. The HTIF console is only used to display boot messages and to power off the virtual system. The OS should use the VirtIO console.
### Network usage
The easiest way is to use the "user" mode network driver. No specific configuration is necessary. TinyEMU also supports a "tap" network driver to redirect the network traffic from a VirtIO network adapter. You can look at the ``netinit.sh`` script to create the tap network interface and to redirect the virtual traffic to the Internet through a NAT. The exact configuration may depend on the Linux distribution and local firewall configuration. The TinyEMU configuration file must include:
``eth0: { driver: "tap", ifname: "tap0" }``
Furthermore, configure the network in the guest system with:
```console
$ ifconfig eth0 192.168.3.2
$ route add -net 0.0.0.0 gw 192.168.3.1 eth0
```
### Network filesystem
TinyEMU supports the VirtIO 9P filesystem to access local or remote filesystems. For remote filesystems, it makes HTTP requests to download the files. The protocol is compatible with the vfsync utility. In the ``mount`` command, ``/dev/rootN`` must be used as a device name where ``N`` is the index of the filesystem. When ``N=0``, it is omitted.
The build_filelist tool builds the file list from a root directory. A simple web server is enough to serve the files. The ``.preload`` file gives a list of files to preload when opening a given file.
### Network block device
TinyEMU supports an HTTP block device. The disk image is split into small files. Use the ``splitimg`` utility to generate images. The URL of the JSON blk.txt file must be provided as a disk image filename.
## Authors
* Copyright (c) 2017-2020 Gaurav Kothari {gkothar1@binghamton.edu}
* Copyright (c) 2018-2019 Parikshit Sarnaik {psarnai1@binghamton.edu}
TinyEMU:
* Copyright (c) 2016-2019 Fabrice Bellard
## Acknowledgment
* This work was supported in part by DARPA through an award from the SSITH program.
* Thanks to Fabrice Bellard for the development of TinyEMU.
* We want to thank Gokturk Yuksek, Ravi Theja Gollapudi, and Kanad Ghose for assistance with the internal details of TinyEMU and the development of the MARSS-RISCV simulator.
* Thanks to all the people working on the RISC-V project.
* For DRAMSim3, refer [here](https://github.com/umd-memsys/DRAMSim3).
* For Ramulator, refer [here](https://github.com/CMU-SAFARI/ramulator).
## License
* This project is licensed under the MIT License - refer to the [LICENSE.md](LICENSE.md) file for details.
* The SLIRP library has a two clause BSD license.
* DRAMSim3 has a MIT License.
* Ramulator has a MIT License.
================================================
FILE: configs/riscv64_inorder_soc.cfg
================================================
/* VM configuration file */
{
version: 1,
machine: "riscv64", /* riscv32, riscv64 */
memory_size: 2048, /* MB */
bios: "riscv64-unknown-linux-gnu/bbl64.bin",
kernel: "riscv64-unknown-linux-gnu/kernel-riscv64.bin",
cmdline: "console=hvc0 root=/dev/vda rw",
drive0: { file: "riscv64-unknown-linux-gnu/riscv64.img" },
eth0: { driver: "user" },
core: {
name: "64-bit inorder riscv CPU",
type: "incore", /* incore, oocore */
cpu_freq_mhz: 1000,
rtc_freq_mhz: 10,
incore : {
num_cpu_stages: 5, /* 5, 6 */
},
oocore: {
iq_size: 16,
iq_issue_ports: 3,
rob_size: 64,
rob_commit_ports:4,
lsq_size: 16,
},
/* Note: Latencies for functional units, caches and memory are specified in CPU cycles */
functional_units: {
num_alu_stages: 1,
alu_stage_latency: "1",
num_mul_stages: 1,
mul_stage_latency: "4",
num_div_stages: 1,
div_stage_latency: "67",
/* Note: This will create a pipelined FP-FMA unit with 4 stages with a
* latency of 1 CPU cycle(s) per stage */
num_fpu_fma_stages: 4,
fpu_fma_stage_latency: "1,1,1,1",
/* Note: FP-ALU is non-pipelined */
fpu_alu_stage_latency: {
fadd: 2,
fsub: 2,
fmul: 2,
fdiv: 8,
fsqrt: 8,
fsgnj: 2,
fmin: 4,
fmax: 4,
feq: 2,
flt: 2,
fle: 2,
cvt: 2,
fcvt: 2,
fmv: 2,
fclass: 1,
},
/* Latency for RISC-V SYSTEM opcode instructions (includes CSR and privileged instructions)*/
system_insn_latency: 3,
},
bpu: {
enable: "true", /* true, false */
flush_on_context_switch: "false", /* true, false */
btb: {
size: 32,
ways: 2,
eviction_policy: "lru", /* lru, random */
},
bpu_type: "bimodal", /* bimodal, adaptive */
bimodal: {
bht_size: 256,
},
adaptive: {
ght_size: 1,
pht_size: 1,
history_bits: 2,
aliasing_func_type: "xor", /* xor, and, none */
/* Given config for adaptive predictor will create a Gshare predictor:
* 1) global history table consisting of one entry, entry includes a 2-bit history register
* 2) pattern history table consisting of one entry, entry includes an array of 4 saturating counters
* 3) value of history register will be `xor` ed with branch PC to index into the array of saturating counters
*/
},
ras_size: 6, /* value 0 disables RAS */
},
caches: {
enable_l1_caches: "true", /* true, false */
allocate_on_write_miss: "true", /* true, false */
write_policy: "writeback", /* writeback, writethrough */
line_size: 64, /* Bytes */
icache: {
size: 32, /* KB */
ways: 4,
latency: 1,
eviction: "lru", /* lru, random */
},
dcache: {
size: 32, /* KB */
ways: 8,
latency: 1,
eviction: "lru", /* lru, random */
},
l2_shared_cache: {
enable: "true",
size: 256, /* KB */
ways: 16,
latency: 5,
eviction: "lru", /* lru, random */
},
},
},
memory: {
tlb_size: 32,
/* Memory controller burst-length in bytes */
/* Note: This is automatically set to cache line size if caches are enabled */
burst_length: 64, /* Bytes */
base_dram_model: {
mem_access_latency: 50,
},
dramsim3: {
config_file: "DRAMsim3/configs/DDR4_4Gb_x16_2400.ini",
},
ramulator: {
config_file: "ramulator/configs/DDR4-config.cfg",
},
},
}
================================================
FILE: configs/riscv64_outoforder_soc.cfg
================================================
/* VM configuration file */
{
version: 1,
machine: "riscv64", /* riscv32, riscv64 */
memory_size: 2048, /* MB */
bios: "riscv64-unknown-linux-gnu/bbl64.bin",
kernel: "riscv64-unknown-linux-gnu/kernel-riscv64.bin",
cmdline: "console=hvc0 root=/dev/vda rw",
drive0: { file: "riscv64-unknown-linux-gnu/riscv64.img" },
eth0: { driver: "user" },
core: {
name: "64-bit out-of-order riscv CPU",
type: "oocore", /* incore, oocore */
cpu_freq_mhz: 1000,
rtc_freq_mhz: 10,
incore : {
num_cpu_stages: 5, /* 5, 6 */
},
oocore: {
iq_size: 16,
iq_issue_ports: 3,
rob_size: 64,
rob_commit_ports:4,
lsq_size: 16,
},
/* Note: Latencies for functional units, caches and memory are specified in CPU cycles */
functional_units: {
num_alu_stages: 1,
alu_stage_latency: "1",
num_mul_stages: 1,
mul_stage_latency: "4",
num_div_stages: 1,
div_stage_latency: "67",
/* Note: This will create a pipelined FP-FMA unit with 4 stages with a
* latency of 1 CPU cycle(s) per stage */
num_fpu_fma_stages: 4,
fpu_fma_stage_latency: "1,1,1,1",
/* Note: FP-ALU is non-pipelined */
fpu_alu_stage_latency: {
fadd: 2,
fsub: 2,
fmul: 2,
fdiv: 8,
fsqrt: 8,
fsgnj: 2,
fmin: 4,
fmax: 4,
feq: 2,
flt: 2,
fle: 2,
cvt: 2,
fcvt: 2,
fmv: 2,
fclass: 1,
},
/* Latency for RISC-V SYSTEM opcode instructions (includes CSR and privileged instructions)*/
system_insn_latency: 3,
},
bpu: {
enable: "true", /* true, false */
flush_on_context_switch: "false", /* true, false */
btb: {
size: 32,
ways: 2,
eviction_policy: "lru", /* lru, random */
},
bpu_type: "bimodal", /* bimodal, adaptive */
bimodal: {
bht_size: 256,
},
adaptive: {
ght_size: 1,
pht_size: 1,
history_bits: 2,
aliasing_func_type: "xor", /* xor, and, none */
/* Given config for adaptive predictor will create a Gshare predictor:
* 1) global history table consisting of one entry, entry includes a 2-bit history register
* 2) pattern history table consisting of one entry, entry includes an array of 4 saturating counters
* 3) value of history register will be `xor` ed with branch PC to index into the array of saturating counters
*/
},
ras_size: 6, /* value 0 disables RAS */
},
caches: {
enable_l1_caches: "true", /* true, false */
allocate_on_write_miss: "true", /* true, false */
write_policy: "writeback", /* writeback, writethrough */
line_size: 64, /* Bytes */
icache: {
size: 32, /* KB */
ways: 4,
latency: 1,
eviction: "lru", /* lru, random */
},
dcache: {
size: 32, /* KB */
ways: 8,
latency: 1,
eviction: "lru", /* lru, random */
},
l2_shared_cache: {
enable: "true",
size: 256, /* KB */
ways: 16,
latency: 5,
eviction: "lru", /* lru, random */
},
},
},
memory: {
tlb_size: 32,
/* Memory controller burst-length in bytes */
/* Note: This is automatically set to cache line size if caches are enabled */
burst_length: 64, /* Bytes */
base_dram_model: {
mem_access_latency: 50,
},
dramsim3: {
config_file: "DRAMsim3/configs/DDR4_4Gb_x16_2400.ini",
},
ramulator: {
config_file: "ramulator/configs/DDR4-config.cfg",
},
},
}
================================================
FILE: src/DRAMsim3/.clang-format
================================================
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AlignConsecutiveAssignments: false
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AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: true
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: true
AlwaysBreakTemplateDeclarations: true
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
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AfterControlStatement: false
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
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IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeInheritanceComma: false
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: true
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DerivePointerAlignment: true
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
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IncludeBlocks: Preserve
IncludeCategories:
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Priority: 2
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Priority: 1
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Priority: 2
- Regex: '.*'
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IncludeIsMainRegex: '([-_](test|unittest))?$'
IndentCaseLabels: true
IndentPPDirectives: None
IndentWidth: 4
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: false
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 200
PointerAlignment: Left
RawStringFormats:
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Language: TextProto
BasedOnStyle: google
ReflowComments: true
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SortUsingDeclarations: true
SpaceAfterCStyleCast: false
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SpaceBeforeAssignmentOperators: true
SpaceBeforeParens: ControlStatements
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 2
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SpacesInCStyleCastParentheses: false
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SpacesInSquareBrackets: false
Standard: Auto
TabWidth: 8
UseTab: Never
...
================================================
FILE: src/DRAMsim3/.gitignore
================================================
# project files
build/
debug_build/
data/
ext/SuperLU_MT_3.1/
obj
dramsim3
dramsim3test
dramsim3main
*.log
release
.idea
*.pyc
*.vh
.vs/
# Compiled Object files
*.slo
*.lo
*.o
*.obj
# Precompiled Headers
*.gch
*.pch
# Compiled Dynamic libraries
*.so
*.dylib
*.dll
# Fortran module files
*.mod
*.smod
# Compiled Static libraries
*.lai
*.la
*.a
*.lib
# Executables
*.exe
*.out
*.app
# IDEs / Editors
.vscode/
================================================
FILE: src/DRAMsim3/.gitmodules
================================================
[submodule "ext/SuperLU_MT_3.1"]
path = ext/SuperLU_MT_3.1
url = https://github.com/umd-memsys/SuperLU_MT_3.1.git
ignore = dirty
================================================
FILE: src/DRAMsim3/.travis.yml
================================================
dist: trusty
#sudo: required
sudo: false
language: cpp
warnings_are_errors: true
compiler:
# - gcc
- clang
#addons:
# apt:
# packages:
# - gcc-4.9
# - clang-3.5
# - cmake
script:
- mkdir build
- cd build
- cmake ..
- make -j4
================================================
FILE: src/DRAMsim3/CMakeLists.txt
================================================
cmake_minimum_required(VERSION 3.0.0)
project(dramsim3)
set(default_build_type "Release")
if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
message(STATUS "Setting build type to '${default_build_type}' as none was specified.")
set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE
STRING "Choose the type of build." FORCE)
# Set the possible values of build type for cmake-gui
set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS
"Debug" "Release" "MinSizeRel" "RelWithDebInfo")
endif()
add_library(inih INTERFACE)
target_include_directories(inih INTERFACE ext/headers)
add_library(format INTERFACE)
target_include_directories(format INTERFACE ext/fmt/include)
target_compile_definitions(format INTERFACE FMT_HEADER_ONLY=1)
# argparsing library, only used in main program not the library
add_library(args INTERFACE)
target_include_directories(args INTERFACE ext/headers)
add_library(json INTERFACE)
target_include_directories(json INTERFACE ext/headers)
# Main DRAMSim Lib
add_library(dramsim3 SHARED
src/bankstate.cc
src/channel_state.cc
src/command_queue.cc
src/common.cc
src/configuration.cc
src/controller.cc
src/dram_system.cc
src/hmc.cc
src/refresh.cc
src/simple_stats.cc
src/timing.cc
src/memory_system.cc
)
if (THERMAL)
# dependency check
# sudo apt-get install libatlas-base-dev on ubuntu
find_package(BLAS REQUIRED)
find_package(OpenMP REQUIRED)
# YOU need to build superlu on your own. Do the following:
# git submodule update --init
# cd ext/SuperLU_MT_3.1 && make lib
find_library(SUPERLU
NAME superlu_mt_OPENMP libsuperlu_mt_OPENMP
HINTS ${PROJECT_SOURCE_DIR}/ext/SuperLU_MT_3.1/lib/
)
target_link_libraries(dramsim3
PRIVATE ${SUPERLU} f77blas atlas m ${OpenMP_C_FLAGS}
)
target_sources(dramsim3
PRIVATE src/thermal.cc src/sp_ienv.c src/thermal_solver.c
)
target_compile_options(dramsim3 PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS})
add_executable(thermalreplay src/thermal_replay.cc)
target_link_libraries(thermalreplay dramsim3 inih)
target_compile_options(thermalreplay PRIVATE -DTHERMAL -D_LONGINT -DAdd_ ${OpenMP_C_FLAGS})
endif (THERMAL)
if (CMD_TRACE)
target_compile_options(dramsim3 PRIVATE -DCMD_TRACE)
endif (CMD_TRACE)
if (ADDR_TRACE)
target_compile_options(dramsim3 PRIVATE -DADDR_TRACE)
endif (ADDR_TRACE)
target_include_directories(dramsim3 INTERFACE src)
target_compile_options(dramsim3 PRIVATE -Wall)
target_link_libraries(dramsim3 PRIVATE inih format)
set_target_properties(dramsim3 PROPERTIES
LIBRARY_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR}
CXX_STANDARD 11
CXX_STANDARD_REQUIRED YES
CXX_EXTENSIONS NO
)
# trace CPU, .etc
add_executable(dramsim3main src/main.cc src/cpu.cc)
target_link_libraries(dramsim3main PRIVATE dramsim3 args)
target_compile_options(dramsim3main PRIVATE)
set_target_properties(dramsim3main PROPERTIES
CXX_STANDARD 11
CXX_STANDARD_REQUIRED YES
CXX_EXTENSIONS NO
)
# Unit testing
add_library(Catch INTERFACE)
target_include_directories(Catch INTERFACE ext/headers)
add_executable(dramsim3test EXCLUDE_FROM_ALL
tests/test_config.cc
tests/test_dramsys.cc
tests/test_hmcsys.cc # IDK somehow this can literally crush your computer
)
target_link_libraries(dramsim3test Catch dramsim3)
target_include_directories(dramsim3test PRIVATE src/)
# We have to use this custome command because there's a bug in cmake
# that if you do `make test` it doesn't build your updated test files
# so we're stucking with `make dramsim3test` for now
add_custom_command(
TARGET dramsim3test POST_BUILD
COMMAND dramsim3test
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
DEPENDS dramsim3test dramsim3
)
================================================
FILE: src/DRAMsim3/LICENSE
================================================
Copyright (c) 2019, University of Maryland Memory-Systems Research
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
================================================
FILE: src/DRAMsim3/Makefile
================================================
# ONLY use this makefile if you do NOT have a cmake 3.0+ version
CC=gcc
CXX=g++
FMT_LIB_DIR=ext/fmt/include
INI_LIB_DIR=ext/headers
JSON_LIB_DIR=ext/headers
ARGS_LIB_DIR=ext/headers
INC=-Isrc/ -I$(FMT_LIB_DIR) -I$(INI_LIB_DIR) -I$(ARGS_LIB_DIR) -I$(JSON_LIB_DIR)
CXXFLAGS=-Wall -O2 -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1
LIB_NAME=libdramsim3.so
EXE_NAME=dramsim3main.out
STATIC_LIB_NAME=libdramsim3.a
SRCS = src/bankstate.cc src/channel_state.cc src/command_queue.cc src/common.cc \
src/configuration.cc src/controller.cc src/dram_system.cc src/hmc.cc \
src/memory_system.cc src/refresh.cc src/simple_stats.cc src/timing.cc
EXE_SRCS = src/cpu.cc src/main.cc
OBJECTS = $(addsuffix .o, $(basename $(SRCS)))
EXE_OBJS = $(addsuffix .o, $(basename $(EXE_SRCS)))
EXE_OBJS := $(EXE_OBJS) $(OBJECTS)
all: $(LIB_NAME) $(EXE_NAME)
$(EXE_NAME): $(EXE_OBJS)
$(CXX) $(CXXFLAGS) -o $@ $^
$(LIB_NAME): $(OBJECTS)
$(CXX) -g -shared -Wl,-soname,$@ -o $@ $^
$(STATIC_LIB_NAME): $(OBJECTS)
$(AR) rcs $@ $(OBJECTS)
%.o : %.cc
$(CXX) $(CXXFLAGS) -o $@ -c $<
%.o : %.c
$(CC) -fPIC -O2 -o $@ -c $<
clean:
-rm -f $(EXE_OBJS) $(LIB_NAME) $(EXE_NAME)
================================================
FILE: src/DRAMsim3/README.md
================================================
[](https://travis-ci.com/umd-memsys/DRAMsim3)
# About DRAMsim3
DRAMsim3 models the timing paramaters and memory controller behavior for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected oriented model that includes a parameterized DRAM bank model, DRAM controllers, command queues and system-level interfaces to interact with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed to be accurate, portable and parallel.
If you use this simulator in your work, please consider cite:
[1] S. Li, Z. Yang, D. Reddy, A. Srivastava and B. Jacob, "DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator," in IEEE Computer Architecture Letters. [Link](https://ieeexplore.ieee.org/document/8999595)
See [Related Work](#related-work) for more work done with this simulator.
## Building and running the simulator
This simulator by default uses a CMake based build system.
The advantage in using a CMake based build system is portability and dependency management.
We require CMake 3.0+ to build this simulator.
If `cmake-3.0` is not available,
we also supply a Makefile to build the most basic version of the simulator.
### Building
Doing out of source builds with CMake is recommended to avoid the build files cluttering the main directory.
```bash
# cmake out of source build
mkdir build
cd build
cmake ..
# Build dramsim3 library and executables
make -j4
# Alternatively, build with thermal module enabled
cmake .. -DTHERMAL=1
```
The build process creates `dramsim3main` and executables in the `build` directory.
By default, it also creates `libdramsim3.so` shared library in the project root directory.
### Running
```bash
# help
./build/dramsim3main -h
# Running random stream with a config file
./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini --stream random -c 100000
# Running a trace file
./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100000 -t sample_trace.txt
# Running with gem5
--mem-type=dramsim3 --dramsim3-ini=configs/DDR4_4Gb_x4_2133.ini
```
The output can be directed to another directory by `-o` option
or can be configured in the config file.
You can control the verbosity in the config file as well.
### Output Visualization
`scripts/plot_stats.py` can visualize some of the output (requires `matplotlib`):
```bash
# generate histograms from overall output
python3 scripts/plot_stats dramsim3.json
# or
# generate time series for a variety stats from epoch outputs
python3 scripts/plot_stats dramsim3epoch.json
```
Currently stats from all channels are squashed together for cleaner plotting.
### Integration with other simulators
**Gem5** integration: works with a forked Gem5 version, see https://github.com/umd-memsys/gem5 at `dramsim3` branch for reference.
**SST** integration: see http://git.ece.umd.edu/shangli/sst-elements/tree/dramsim3 for reference. We will try to merge to official SST repo.
**ZSim** integration: see http://git.ece.umd.edu/shangli/zsim/tree/master for reference.
## Simulator Design
### Code Structure
```
├── configs # Configs of various protocols that describe timing constraints and power consumption.
├── ext #
├── scripts # Tools and utilities
├── src # DRAMsim3 source files
├── tests # Tests of each model, includes a short example trace
├── CMakeLists.txt
├── Makefile
├── LICENSE
└── README.md
├── src
bankstate.cc: Records and manages DRAM bank timings and states which is modeled as a state machine.
channelstate.cc: Records and manages channel timings and states.
command_queue.cc: Maintains per-bank or per-rank FIFO queueing structures, determine which commands in the queues can be issued in this cycle.
configuration.cc: Initiates, manages system and DRAM parameters, including protocol, DRAM timings, address mapping policy and power parameters.
controller.cc: Maintains the per-channel controller, which manages a queue of pending memory transactions and issues corresponding DRAM commands,
follows FR-FCFS policy.
cpu.cc: Implements 3 types of simple CPU:
1. Random, can handle random CPU requests at full speed, the entire parallelism of DRAM protocol can be exploited without limits from address mapping and scheduling pocilies.
2. Stream, provides a streaming prototype that is able to provide enough buffer hits.
3. Trace-based, consumes traces of workloads, feed the fetched transactions into the memory system.
dram_system.cc: Initiates JEDEC or ideal DRAM system, registers the supplied callback function to let the front end driver know that the request is finished.
hmc.cc: Implements HMC system and interface, HMC requests are translates to DRAM requests here and a crossbar interconnect between the high-speed links and the memory controllers is modeled.
main.cc: Handles the main program loop that reads in simulation arguments, DRAM configurations and tick cycle forward.
memory_system.cc: A wrapper of dram_system and hmc.
refresh.cc: Raises refresh request based on per-rank refresh or per-bank refresh.
timing.cc: Initiate timing constraints.
```
## Experiments
### Verilog Validation
First we generate a DRAM command trace.
There is a `CMD_TRACE` macro and by default it's disabled.
Use `cmake .. -DCMD_TRACE=1` to enable the command trace output build and then
whenever a simulation is performed the command trace file will be generated.
Next, `scripts/validation.py` helps generate a Verilog workbench for Micron's Verilog model
from the command trace file.
Currently DDR3, DDR4, and LPDDR configs are supported by this script.
Run
```bash
./script/validataion.py DDR4.ini cmd.trace
```
To generage Verilog workbench.
Our workbench format is compatible with ModelSim Verilog simulator,
other Verilog simulators may require a slightly different format.
## Related Work
[1] Li, S., Yang, Z., Reddy D., Srivastava, A. and Jacob, B., (2020) DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator, IEEE Computer Architecture Letters.
[2] Jagasivamani, M., Walden, C., Singh, D., Kang, L., Li, S., Asnaashari, M., ... & Yeung, D. (2019). Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die. IEEE Micro, 39(6), 64-72.
[3] Li, S., Reddy, D., & Jacob, B. (2018, October). A performance & power comparison of modern high-speed DRAM architectures. In Proceedings of the International Symposium on Memory Systems (pp. 341-353).
[4] Li, S., Verdejo, R. S., Radojković, P., & Jacob, B. (2019, September). Rethinking cycle accurate DRAM simulation. In Proceedings of the International Symposium on Memory Systems (pp. 184-191).
[5] Li, S., & Jacob, B. (2019, September). Statistical DRAM modeling. In Proceedings of the International Symposium on Memory Systems (pp. 521-530).
[6] Li, S. (2019). Scalable and Accurate Memory System Simulation (Doctoral dissertation).
================================================
FILE: src/DRAMsim3/configs/DDR3_1Gb_x8_1333.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 16384
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.5
AL = 0
CL = 10
CWL = 7
tRCD = 10
tRP = 10
tRAS = 24
tRFC = 74
tREFI = 5200
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tWTR_S = 5
tFAW = 20
tWR = 10
tCCD_S = 4
tRTP = 5
tCKE = 4
tCKESR = 1
tXS = 81
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 33
IDD2P = 12
IDD2N = 17
IDD3P = 14
IDD3N = 23
IDD4W = 77
IDD4R = 72
IDD5AB = 155
IDD6x = 12
[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
trans_queue_size = 32
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
[other]
epoch_period = 666666
output_level = 1
[thermal]
loc_mapping = 30,30,30,29:27,26:13,12:3
power_epoch_period = 10000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x16_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 208
tRFC2 = 208
tRFC4 = 208
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 6
tWTR_L = 6
tFAW = 32
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 216
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 66
IPP0 = 0.0
IDD2P = 18
IDD2N = 32
IDD3P = 38
IDD3N = 47
IDD4W = 171
IDD4R = 235
IDD5AB = 235
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x16_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 243
tRFC4 = 243
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 7
tWTR_L = 7
tFAW = 33
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 73
IPP0 = 0.0
IDD2P = 18
IDD2N = 35
IDD3P = 41
IDD3N = 49
IDD4W = 190
IDD4R = 252
IDD5AB = 242
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x4_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 2048
device_width = 4
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 208
tRFC2 = 208
tRFC4 = 208
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 6
tWTR_L = 6
tFAW = 24
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 216
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 55
IPP0 = 0.0
IDD2P = 18
IDD2N = 32
IDD3P = 38
IDD3N = 38
IDD4W = 118
IDD4R = 147
IDD5AB = 235
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x4_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 2048
device_width = 4
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 243
tRFC4 = 243
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 7
tWTR_L = 7
tFAW = 26
tWR = 15
tWR2 = 15
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 62
IPP0 = 0.0
IDD2P = 18
IDD2N = 35
IDD3P = 41
IDD3N = 41
IDD4W = 133
IDD4R = 164
IDD5AB = 242
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x8_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 208
tRFC2 = 208
tRFC4 = 208
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 6
tWTR_L = 6
tFAW = 24
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 216
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 55
IPP0 = 0.0
IDD2P = 18
IDD2N = 32
IDD3P = 38
IDD3N = 38
IDD4W = 125
IDD4R = 157
IDD5AB = 235
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_4Gb_x8_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 243
tRFC4 = 243
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 5
tRRD_L = 5
tWTR_S = 7
tWTR_L = 7
tFAW = 26
tWR = 15
tWR2 = 15
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 62
IPP0 = 0.0
IDD2P = 18
IDD2N = 35
IDD3P = 41
IDD3N = 41
IDD4W = 141
IDD4R = 174
IDD5AB = 242
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x16_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 280
tRFC2 = 280
tRFC4 = 280
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 6
tWTR_L = 6
tFAW = 32
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 288
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 67
IPP0 = 0.0
IDD2P = 11
IDD2N = 36
IDD3P = 36
IDD3N = 51
IDD4W = 185
IDD4R = 185
IDD5AB = 270
IDD6x = 24
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x16_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 328
tRFC2 = 328
tRFC4 = 328
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 7
tWTR_L = 7
tFAW = 33
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 338
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 69
IPP0 = 0.0
IDD2P = 11
IDD2N = 38
IDD3P = 38
IDD3N = 53
IDD4W = 195
IDD4R = 195
IDD5AB = 275
IDD6x = 24
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x4_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 4096
device_width = 4
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 280
tRFC2 = 280
tRFC4 = 280
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 6
tWTR_L = 6
tFAW = 32
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 288
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 67
IPP0 = 0.0
IDD2P = 11
IDD2N = 36
IDD3P = 36
IDD3N = 51
IDD4W = 125
IDD4R = 125
IDD5AB = 245
IDD6x = 24
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x4_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 4096
device_width = 4
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 328
tRFC2 = 328
tRFC4 = 328
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 7
tWTR_L = 7
tFAW = 33
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 338
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 69
IPP0 = 0.0
IDD2P = 11
IDD2N = 38
IDD3P = 38
IDD3N = 53
IDD4W = 135
IDD4R = 135
IDD5AB = 250
IDD6x = 24
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x8_1600.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 2048
device_width = 8
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 11
CWL = 8
tRCD = 11
tRP = 11
tRAS = 28
tRFC = 280
tRFC2 = 280
tRFC4 = 280
REFI = 6240
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 6
tWTR_L = 6
tFAW = 32
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tCKESR = 5
tXS = 288
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 67
IPP0 = 0.0
IDD2P = 11
IDD2N = 36
IDD3P = 36
IDD3N = 51
IDD4W = 125
IDD4R = 125
IDD5AB = 245
IDD6x = 24
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR3_8Gb_x8_1866.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 2048
device_width = 8
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 9
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 328
tRFC2 = 328
tRFC4 = 328
REFI = 7290
tRPRE = 0
tWPRE = 0
tRRD_S = 6
tRRD_L = 6
tWTR_S = 7
tWTR_L = 7
tFAW = 33
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 6
tXS = 338
tXP = 6
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 69
IPP0 = 0.0
IDD2P = 11
IDD2N = 38
IDD3P = 38
IDD3N = 53
IDD4W = 135
IDD4R = 135
IDD5AB = 250
IDD6x = 24
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 150
tRFC4 = 103
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 5
tRRD_L = 6
tWTR_S = 3
tWTR_L = 7
tFAW = 28
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.6
IDD2P = 27
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 220
IDD4R = 180
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 6
tRRD_L = 7
tWTR_S = 3
tWTR_L = 8
tFAW = 32
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.6
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 250
IDD4R = 195
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 6
tRRD_L = 7
tWTR_S = 3
tWTR_L = 8
tFAW = 32
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.6
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 250
IDD4R = 195
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 8
tWTR_S = 3
tWTR_L = 9
tFAW = 36
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.6
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 285
IDD4R = 205
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 0
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 8
tWTR_S = 3
tWTR_L = 9
tFAW = 36
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.6
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 285
IDD4R = 205
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 9
tWTR_S = 4
tWTR_L = 10
tFAW = 40
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 70
IPP0 = 3.6
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 310
IDD4R = 225
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x16_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 9
tWTR_S = 4
tWTR_L = 10
tFAW = 40
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 70
IPP0 = 3.6
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 310
IDD4R = 225
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 150
tRFC4 = 103
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 5
tWTR_S = 3
tWTR_L = 7
tFAW = 16
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 140
IDD4R = 125
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 16
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 155
IDD4R = 135
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 16
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 155
IDD4R = 135
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 16
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 60
IPP0 = 3.0
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 175
IDD4R = 145
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
cmd_queue_size = 8
trans_queue_size = 32
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 16
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 60
IPP0 = 3.0
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 175
IDD4R = 145
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 16
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.0
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 195
IDD4R = 170
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x4_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 16
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.0
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 195
IDD4R = 170
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 243
tRFC2 = 150
tRFC4 = 103
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 5
tWTR_S = 3
tWTR_L = 7
tFAW = 22
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 253
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 140
IDD4R = 125
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 23
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 155
IDD4R = 135
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 278
tRFC2 = 171
tRFC4 = 118
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 23
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 289
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 55
IPP0 = 3.0
IDD2P = 27
IDD2N = 42
IDD3P = 40
IDD3N = 55
IDD4W = 155
IDD4R = 135
IDD5AB = 170
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 26
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 60
IPP0 = 3.0
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 175
IDD4R = 145
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 312
tRFC2 = 192
tRFC4 = 132
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 26
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 324
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 60
IPP0 = 3.0
IDD2P = 29
IDD2N = 45
IDD3P = 40
IDD3N = 60
IDD4W = 175
IDD4R = 145
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 28
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.0
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 195
IDD4R = 170
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_4Gb_x8_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 347
tRFC2 = 214
tRFC4 = 147
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 28
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 360
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 65
IPP0 = 3.0
IDD2P = 34
IDD2N = 50
IDD3P = 40
IDD3N = 65
IDD4W = 195
IDD4R = 170
IDD5AB = 175
IDD6x = 20
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 327
tRFC2 = 243
tRFC4 = 150
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 5
tRRD_L = 6
tWTR_S = 3
tWTR_L = 7
tFAW = 28
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 337
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 75
IPP0 = 4.0
IDD2P = 25
IDD2N = 33
IDD3P = 39
IDD3N = 44
IDD4W = 225
IDD4R = 225
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 6
tRRD_L = 7
tWTR_S = 3
tWTR_L = 8
tFAW = 32
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 75
IPP0 = 4.0
IDD2P = 25
IDD2N = 33
IDD3P = 39
IDD3N = 44
IDD4W = 225
IDD4R = 225
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 6
tRRD_L = 7
tWTR_S = 3
tWTR_L = 8
tFAW = 32
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 75
IPP0 = 4.0
IDD2P = 25
IDD2N = 33
IDD3P = 39
IDD3N = 44
IDD4W = 225
IDD4R = 225
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 8
tWTR_S = 3
tWTR_L = 9
tFAW = 36
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 80
IPP0 = 4.0
IDD2P = 25
IDD2N = 34
IDD3P = 41
IDD3N = 47
IDD4W = 228
IDD4R = 243
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 8
tWTR_S = 3
tWTR_L = 9
tFAW = 36
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 80
IPP0 = 4.0
IDD2P = 25
IDD2N = 34
IDD3P = 41
IDD3N = 47
IDD4W = 228
IDD4R = 243
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 9
tWTR_S = 4
tWTR_L = 10
tFAW = 40
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 85
IPP0 = 4.0
IDD2P = 25
IDD2N = 35
IDD3P = 43
IDD3N = 50
IDD4W = 244
IDD4R = 263
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 9
tWTR_S = 4
tWTR_L = 10
tFAW = 40
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 85
IPP0 = 4.0
IDD2P = 25
IDD2N = 35
IDD3P = 43
IDD3N = 50
IDD4W = 244
IDD4R = 263
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2933.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 21
CWL = 16
tRCD = 21
tRP = 21
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 8
tRRD_L = 10
tWTR_S = 4
tWTR_L = 11
tFAW = 44
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 90
IPP0 = 4.0
IDD2P = 25
IDD2N = 36
IDD3P = 45
IDD3N = 53
IDD4W = 261
IDD4R = 283
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_2933_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 20
CWL = 16
tRCD = 20
tRP = 20
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 8
tRRD_L = 10
tWTR_S = 4
tWTR_L = 11
tFAW = 44
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 90
IPP0 = 4.0
IDD2P = 25
IDD2N = 36
IDD3P = 45
IDD3N = 53
IDD4W = 261
IDD4R = 283
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x16_3200.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 8
[timing]
tCK = 0.63
AL = 0
CL = 22
CWL = 16
tRCD = 22
tRP = 22
tRAS = 52
tRFC = 560
tRFC2 = 416
tRFC4 = 256
tREFI = 12480
tRPRE = 1
tWPRE = 1
tRRD_S = 9
tRRD_L = 11
tWTR_S = 4
tWTR_L = 12
tFAW = 48
tWR = 24
tWR2 = 25
tRTP = 12
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 576
tXP = 10
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 95
IPP0 = 4.0
IDD2P = 25
IDD2N = 37
IDD3P = 47
IDD3N = 56
IDD4W = 278
IDD4R = 302
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1587301
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 327
tRFC2 = 243
tRFC4 = 150
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 5
tWTR_S = 3
tWTR_L = 7
tFAW = 16
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 337
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 40
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 30
IDD3N = 35
IDD4W = 95
IDD4R = 100
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 16
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 40
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 30
IDD3N = 35
IDD4W = 95
IDD4R = 100
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 16
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 40
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 30
IDD3N = 35
IDD4W = 95
IDD4R = 100
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 16
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 43
IPP0 = 3.0
IDD2P = 25
IDD2N = 34
IDD3P = 32
IDD3N = 38
IDD4W = 103
IDD4R = 110
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 16
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 43
IPP0 = 3.0
IDD2P = 25
IDD2N = 34
IDD3P = 32
IDD3N = 38
IDD4W = 103
IDD4R = 110
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 16
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 46
IPP0 = 3.0
IDD2P = 25
IDD2N = 35
IDD3P = 34
IDD3N = 41
IDD4W = 112
IDD4R = 121
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 16
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 46
IPP0 = 3.0
IDD2P = 25
IDD2N = 35
IDD3P = 34
IDD3N = 41
IDD4W = 112
IDD4R = 121
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2933.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 21
CWL = 16
tRCD = 21
tRP = 21
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 11
tFAW = 16
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 49
IPP0 = 3.0
IDD2P = 25
IDD2N = 36
IDD3P = 36
IDD3N = 44
IDD4W = 121
IDD4R = 132
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_2933_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 20
CWL = 16
tRCD = 20
tRP = 20
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 11
tFAW = 16
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 49
IPP0 = 3.0
IDD2P = 25
IDD2N = 36
IDD3P = 36
IDD3N = 44
IDD4W = 121
IDD4R = 132
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x4_3200.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8
[timing]
tCK = 0.63
AL = 0
CL = 22
CWL = 16
tRCD = 22
tRP = 22
tRAS = 52
tRFC = 560
tRFC2 = 416
tRFC4 = 256
tREFI = 12480
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 12
tFAW = 16
tWR = 24
tWR2 = 25
tRTP = 12
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 576
tXP = 10
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 52
IPP0 = 3.0
IDD2P = 25
IDD2N = 37
IDD3P = 38
IDD3N = 47
IDD4W = 130
IDD4R = 143
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 32768
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1587301
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_1866.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 13
CWL = 10
tRCD = 13
tRP = 13
tRAS = 32
tRFC = 327
tRFC2 = 243
tRFC4 = 150
tREFI = 7285
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 5
tWTR_S = 3
tWTR_L = 7
tFAW = 22
tWR = 14
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 5
tCKE = 5
tCKESR = 6
tXS = 337
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 45
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 35
IDD3N = 40
IDD4W = 115
IDD4R = 125
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2133.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 16
CWL = 11
tRCD = 16
tRP = 16
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 23
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 45
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 35
IDD3N = 40
IDD4W = 115
IDD4R = 125
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2133_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.94
AL = 0
CL = 15
CWL = 11
tRCD = 15
tRP = 15
tRAS = 36
tRFC = 374
tRFC2 = 278
tRFC4 = 171
tREFI = 8328
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 8
tFAW = 23
tWR = 16
tWR2 = 17
tRTP = 8
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 385
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 45
IPP0 = 3.0
IDD2P = 25
IDD2N = 33
IDD3P = 35
IDD3N = 40
IDD4W = 115
IDD4R = 125
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1063829
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 12
tRCD = 17
tRP = 17
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 26
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 48
IPP0 = 3.0
IDD2P = 25
IDD2N = 34
IDD3P = 37
IDD3N = 43
IDD4W = 123
IDD4R = 135
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
[thermal]
loc_mapping = 33,33,32-31,30-29,26:13-27-28,12:3
power_epoch_period = 100000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 0; 0: x direction first, 1: y direction first
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2400_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.83
AL = 0
CL = 16
CWL = 12
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9360
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 26
tWR = 18
tWR2 = 19
tRTP = 9
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 48
IPP0 = 3.0
IDD2P = 25
IDD2N = 34
IDD3P = 37
IDD3N = 43
IDD4W = 123
IDD4R = 135
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2666.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 19
CWL = 14
tRCD = 19
tRP = 19
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 28
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 51
IPP0 = 3.0
IDD2P = 25
IDD2N = 35
IDD3P = 39
IDD3N = 46
IDD4W = 132
IDD4R = 146
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2666_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.75
AL = 0
CL = 18
CWL = 14
tRCD = 18
tRP = 18
tRAS = 43
tRFC = 467
tRFC2 = 347
tRFC4 = 214
tREFI = 10398
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 7
tWTR_S = 4
tWTR_L = 10
tFAW = 28
tWR = 20
tWR2 = 21
tRTP = 10
tCCD_S = 4
tCCD_L = 7
tCKE = 7
tCKESR = 8
tXS = 480
tXP = 8
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 51
IPP0 = 3.0
IDD2P = 25
IDD2N = 35
IDD3P = 39
IDD3N = 46
IDD4W = 132
IDD4R = 146
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1333333
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2933.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 21
CWL = 16
tRCD = 21
tRP = 21
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 11
tFAW = 31
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 54
IPP0 = 3.0
IDD2P = 25
IDD2N = 36
IDD3P = 41
IDD3N = 49
IDD4W = 141
IDD4R = 157
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_2933_2.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.68
AL = 0
CL = 20
CWL = 16
tRCD = 20
tRP = 20
tRAS = 47
tRFC = 514
tRFC2 = 382
tRFC4 = 235
tREFI = 11439
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 11
tFAW = 31
tWR = 22
tWR2 = 23
tRTP = 11
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 528
tXP = 9
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 54
IPP0 = 3.0
IDD2P = 25
IDD2N = 36
IDD3P = 41
IDD3N = 49
IDD4W = 141
IDD4R = 157
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1470588
output_level = 1
================================================
FILE: src/DRAMsim3/configs/DDR4_8Gb_x8_3200.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.63
AL = 0
CL = 22
CWL = 16
tRCD = 22
tRP = 22
tRAS = 52
tRFC = 560
tRFC2 = 416
tRFC4 = 256
tREFI = 12480
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 12
tFAW = 34
tWR = 24
tWR2 = 25
tRTP = 12
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 576
tXP = 10
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 57
IPP0 = 3.0
IDD2P = 25
IDD2N = 37
IDD3P = 43
IDD3N = 52
IDD4W = 150
IDD4R = 168
IDD5AB = 250
IDD6x = 30
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1587301
output_level = 1
================================================
FILE: src/DRAMsim3/configs/GDDR5X_8Gb_x32.ini
================================================
[dram_structure]
protocol = GDDR5X
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 32
BL = 16
bankgroup_enable = false
[timing]
tCK = 0.666 (1/1.5)
CL = 24
CWL = 7
tRCDRD = 18
tRCDWR = 15
tRP = 18
tRAS = 42
tRFC = 98
tREFI = 11699
tRPRE = 1; read preamble
tWPRE = 1; TODO figure this out, should be 1 or 2
tRRD_S = 9
tRRD_L = 9
tWTR_S = 8
tWTR_L = 8
tFAW = 35
tWR = 18
tCCD_S = 2
tCCD_L = 3
tXS = 116
tCKE = 16
tCKSRE = 8
tXP = 12
tRTRS = 0
tRTP_L = 3
tRTP_S = 3
tPPD = 2
t32AW = 280
[power]
VDD = 1.35
IDD0 = 500
IDD2P = 220
IDD2N = 260
IDD3P = 330
IDD3N = 480
IDD4W = 2320
IDD4R = 2160
IDD5AB = 600
IDD5PB = 60
IDD6x = 65
[system]
channel_size = 4096
channels = 1
bus_width = 128
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1501501
output_level = 1
[thermal]
power_epoch_period = 1000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
================================================
FILE: src/DRAMsim3/configs/GDDR5_1Gb_x32.ini
================================================
[dram_structure]
protocol = GDDR5
bankgroups = 4
banks_per_group = 4
rows = 4096
columns = 64
device_width = 32
BL = 8
bankgroup_enable = false
[timing]
tCK = 0.667
CL = 24
CWL = 7
tRCDRD = 18
tRCDWR = 15
tRP = 18
tRAS = 42
tRFC = 98
tREFI = 11699
tRPRE = 1; read preamble
tWPRE = 1; TODO figure this out, should be 1 or 2
tRRD_S = 9
tRRD_L = 9
tWTR_S = 8
tWTR_L = 8
tFAW = 35
tWR = 18
tCCD_S = 2
tCCD_L = 3
tXS = 116
tCKE = 16
tCKESR = 8
tXP = 12
tRTRS = 0
tRTP_L = 3
tRTP_S = 3
tPPD = 2
t32AW = 280
[power]
VDD = 1.5
IDD0 = 490
IDD2P = 210
IDD2N = 250
IDD3P = 310
IDD3N = 450
IDD4W = 1160
IDD4R = 1080
IDD5AB = 450
IDD5PB = 45
IDD6x = 60
[system]
channel_size = 1024
channels = 1
bus_width = 256
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1499250
output_level = 1
================================================
FILE: src/DRAMsim3/configs/GDDR5_8Gb_x32.ini
================================================
[dram_structure]
protocol = GDDR5
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 128
device_width = 32
BL = 8
bankgroup_enable = false
[timing]
tCK = 0.667
CL = 24
CWL = 7
tRCDRD = 24
tRCDWR = 20
tRP = 24
tRAS = 56
tRFC = 74
tREFI = 3800
tRPRE = 1; read preamble
tWPRE = 1; TODO figure this out, should be 1 or 2
tRRD_S = 10
tRRD_L = 10
tWTR_S = 10
tWTR_L = 10
tFAW = 40
tWR = 24
tCCD_S = 2
tCCD_L = 3
tXS = 94
tCKESR = 2
tXP = 12
tRTRS = 1
tRTP_L = 2
tRTP_S = 2
tPPD = 5
t32AW = 360
tRFCb = 30
tREFIb = 238
[power]
VDD = 1.5
IDD0 = 71
IDD2P = 45
IDD2N = 60
IDD3P = 50
IDD3N = 61
IDD4W = 231
IDD4R = 248
IDD5AB = 286
IDD5PB = 45
IDD6x = 35
[system]
channel_size = 4096
channels = 1
bus_width = 128
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1499250
output_level = 1
================================================
FILE: src/DRAMsim3/configs/GDDR6_8Gb_x16.ini
================================================
[dram_structure]
protocol = GDDR6
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 128
device_width = 16
BL = 16
bankgroup_enable = false
[timing]
tCK = 0.66
CL = 24
CWL = 16
tRCDRD = 24
tRCDWR = 20
tRP = 24
tRAS = 54
tRFC = 126
tREFI = 11862
tRPRE = 1; read preamble
tWPRE = 1; TODO figure this out, should be 1 or 2
tRRD_S = 9
tRRD_L = 9
tWTR_S = 7
tWTR_L = 7
tFAW = 32
tWR = 16
tCCD_S = 3
tCCD_L = 4
tXS = 132
tCKESR = 8
tXP = 12
tRTRS = 1
tRTP_L = 3
tRTP_S = 3
tPPD = 2
t32AW = 420
tRFCb = 30
tREFIb = 238
[power]
VDD = 1.35
IDD0 = 71
IDD2P = 45
IDD2N = 60
IDD3P = 50
IDD3N = 61
IDD4W = 231
IDD4R = 248
IDD5AB = 286
IDD5PB = 45
IDD6x = 35
[system]
channel_size = 4096
channels = 1
bus_width = 128
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1499250
output_level = 1
;16n prefetch
================================================
FILE: src/DRAMsim3/configs/HBM1_4Gb_x128.ini
================================================
[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 128
BL = 4
num_dies = 4
[timing]
tCK = 2
CL = 7
CWL = 2
tRCDRD = 7
tRCDWR = 7
tRP = 7
tRAS = 17
tRFC = 130
tREFI = 1950
tREFIb = 64
tRPRE = 1
tWPRE = 1
tRRD_S = 2
tRRD_L = 3
tWTR_S = 3
tWTR_L = 4
tFAW = 15
tWR = 8
tCCD_S = 1
tCCD_L = 1
tXS = 134
tCKE = 4
tCKSRE = 5
tXP = 4
tRTP_L = 3
tRTP_S = 2
[power]
VDD = 1.2
IDD0 = 65
IDD2P = 28
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 440
IDD4R = 360
IDD5AB = 250
IDD6x = 31
[system]
channel_size = 512
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False
[other]
epoch_period = 500000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/HBM2_4Gb_x128.ini
================================================
[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 128
BL = 4
num_dies = 4
[timing]
tCK = 1
CL = 14
CWL = 4
tRCDRD = 14
tRCDWR = 14
tRP = 14
tRAS = 34
tRFC = 260
tREFI = 3900
tREFIb = 128
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 6
tWTR_L = 8
tFAW = 30
tWR = 16
tCCD_S = 1
tCCD_L = 2
tXS = 268
tCKE = 8
tCKSRE = 10
tXP = 8
tRTP_L = 6
tRTP_S = 4
[power]
VDD = 1.2
IDD0 = 65
IDD2P = 28
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 500
IDD4R = 390
IDD5AB = 250
IDD6x = 31
[system]
channel_size = 512
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False
[other]
epoch_period = 1000000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/HBM2_8Gb_x128.ini
================================================
[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 32768
columns = 64
device_width = 128
BL = 4
num_dies = 4
[timing]
tCK = 1
CL = 14
CWL = 4
tRCDRD = 14
tRCDWR = 14
tRP = 14
tRAS = 34
tRFC = 260
tREFI = 3900
tREFIb = 128
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 6
tWTR_L = 8
tFAW = 30
tWR = 16
tCCD_S = 1
tCCD_L = 2
tXS = 268
tCKE = 8
tCKSRE = 10
tXP = 8
tRTP_L = 6
tRTP_S = 4
[power]
VDD = 1.2
IDD0 = 65
IDD2P = 28
IDD2N = 40
IDD3P = 40
IDD3N = 55
IDD4W = 500
IDD4R = 390
IDD5AB = 250
IDD6x = 31
[system]
channel_size = 1024
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False
[other]
epoch_period = 1000000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/HBM_4Gb_x128.ini
================================================
[dram_structure]
protocol = HBM
bankgroups = 4
banks_per_group = 4
rows = 16384
columns = 64
device_width = 128
BL = 4
num_dies = 4
[timing]
tCK = 2
AL = 0
CL = 7
CWL = 4
tRCDRD = 7
tRCDWR = 6
tRP = 7
tRAS = 17
tRFC =
tREFI = 1950
tRPRE = 1; read preamble
tWPRE = 1; TODO figure this out, should be 1 or 2
tRRD_S = 4
tRRD_L = 5
tWTR_S = 2
tWTR_L = 4
tFAW = 20
tWR = 8
tCCD_S = 2
tCCD_L = 3
tXS = 0
tCKSRE = 0
tXP = 5
tRTP_L = 7
tRTP_S = 6
tPPD = 5
t32AW = 330
tRFCb =
tREFIb =
tRREFD =
tRFCPB =
[power]
VDD = 1.2
IDD0 = 48
IDD2P = 25
IDD2N = 34
IDD3P = 37
IDD3N = 43
IDD4W = 123
IDD4R = 135
IDD5AB = 250
IDD6x = 31
[system]
channel_size = 512
channels = 8
bus_width = 128
address_mapping = rorabgbachco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = False
[other]
epoch_period = 500000
output_level = 1
[thermal]
power_epoch_period = 10000; power epoch period (# cycle)
logic_bg_power = 5
logic_max_power = 25
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 1024;
mat_dim_y = 1024;
bank_order = 1; 0: x direction first, 1: y direction first
bank_layer_order = 0;
================================================
FILE: src/DRAMsim3/configs/HMC2_8GB_4Lx16.ini
================================================
[hmc]
num_links = 4
link_width = 16
link_speed = 25000
block_size = 64
xbar_queue_depth = 32
[dram_structure]
protocol = HMC
bankgroups = 1
banks_per_group = 16
rows = 65536
columns = 64
device_width = 32
num_dies = 8
[timing]
tCK = 0.8
CL = 17
CWL = 17
tRCD = 17
tRP = 17
tRAS = 34
tRFC = 420
tREFI = 9364; average periodic refresh interval, 3.9us
tRRD_S = 6
tRRD_L = 6
tWTR_S = 3
tWTR_L = 3
tFAW = 27
tWR = 19
tCCD_S = 6
tCCD_L = 6
tXS = 12
tCKSRE = 1
tXP = 8
tRTP_L = 10
tRTP_S = 10
tRTRS = 0
[power]
VDD = 1.2
IDD0 = 25
IDD2P = 17
IDD2N = 19
IDD3P = 20
IDD3N = 21
IDD4W = 61
IDD4R = 64
IDD5AB = 150
IDD6x = 21
[system]
channel_size = 256
channels = 32
bus_width = 32
address_mapping = rocorabgbach
queue_structure = PER_BANK
row_buf_policy = CLOSE_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = True
[thermal]
power_epoch_period = 10000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
bank_layer_order = 0;
[other]
epoch_period = 1250000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/HMC_2GB_4Lx16.ini
================================================
[hmc]
num_links = 4
link_width = 16
link_speed = 10000
block_size = 64
xbar_queue_depth = 6
[dram_structure]
protocol = HMC
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 64
device_width = 32
num_dies = 4
[timing]
tCK = 0.8
CL = 17
CWL = 17
tRCD = 17
tRP = 17
tRAS = 34
tRFC = 420
tREFI = 9364; average periodic refresh interval, 3.9us
tRRD_S = 4
tRRD_L = 4
tWTR_S = 3
tWTR_L = 3
tFAW = 27
tWR = 17
tCCD_S = 6
tCCD_L = 6
tXS = 12
tCKSRE = 1
tXP = 8
tRTP_L = 8
tRTP_S = 8
tRTRS = 0
[power]
VDD = 1.2
IDD0 = 25
IDD2P = 17
IDD2N = 19
IDD3P = 20
IDD3N = 21
IDD4W = 61
IDD4R = 64
IDD5AB = 150
IDD6x = 21
[system]
channel_size = 128
channels = 16
bus_width = 32
address_mapping = rocorabgbach
queue_structure = PER_BANK
row_buf_policy = CLOSE_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = True
[other]
epoch_period = 1250000
output_level = 1
[thermal]
power_epoch_period = 10000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
bank_layer_order = 0;
================================================
FILE: src/DRAMsim3/configs/HMC_2GB_4Lx16_dummy.ini
================================================
[hmc]
num_links = 4
link_width = 16
link_speed = 10000
block_size = 128
xbar_queue_depth = 6
[dram_structure]
protocol = HMC
bankgroups = 1
banks_per_group = 8
rows = 65536
columns = 64
device_width = 32
BL = 2
num_dies = 4
[timing]
tCK = 0.8
CL = 17
CWL = 17
tRCD = 17
tRP = 17
tRAS = 34
tRFC = 420
tREFI = 9364; average periodic refresh interval, 3.9us
tRRD_S = 4
tRRD_L = 4
tWTR_S = 3
tWTR_L = 3
tFAW = 27
tWR = 17
tCCD_S = 6
tCCD_L = 6
tXS = 12
tCKSRE = 1
tXP = 8
tRTP_L = 8
tRTP_S = 8
tRTRS = 0
[power]
VDD = 1.2
IDD0 = 25
IDD2P = 17
IDD2N = 19
IDD3P = 20
IDD3N = 21
IDD4W = 61
IDD4R = 64
IDD5AB = 150
IDD6x = 21
[system]
channel_size = 128
channels = 16
bus_width = 32
address_mapping = rocorabgbach
queue_structure = PER_BANK
row_buf_policy = CLOSE_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = True
[other]
epoch_period = 1250000
output_level = 1
[thermal]
power_epoch_period = 10000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
bank_layer_order = 0;
================================================
FILE: src/DRAMsim3/configs/HMC_4GB_4Lx16.ini
================================================
[hmc]
num_links = 4
link_width = 16
link_speed = 15000
block_size = 64
xbar_queue_depth = 6
[dram_structure]
protocol = HMC
bankgroups = 1
banks_per_group = 16
rows = 65536
columns = 64
device_width = 32
num_dies = 4
[timing]
tCK = 0.8
CL = 17
CWL = 17
tRCD = 17
tRP = 17
tRAS = 34
tRFC = 420
tREFI = 9364; average periodic refresh interval, 3.9us
tRRD_S = 4
tRRD_L = 4
tWTR_S = 3
tWTR_L = 3
tFAW = 27
tWR = 17
tCCD_S = 6
tCCD_L = 6
tXS = 12
tCKSRE = 1
tXP = 8
tRTP_L = 8
tRTP_S = 8
tRTRS = 0
[power]
VDD = 1.2
IDD0 = 25
IDD2P = 17
IDD2N = 19
IDD3P = 20
IDD3N = 21
IDD4W = 61
IDD4R = 64
IDD5AB = 150
IDD6x = 21
[system]
channel_size = 256
channels = 16
bus_width = 32
address_mapping = rocorabgbach
queue_structure = PER_BANK
row_buf_policy = CLOSE_PAGE
cmd_queue_size = 8
trans_queue_size = 32
unified_queue = True
[other]
epoch_period = 1250000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/LPDDR3_8Gb_x32_1333.ini
================================================
[dram_structure]
protocol = LPDDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 32
BL = 8
[timing]
tCK = 1.5
AL = 0
CL = 10
CWL = 8
tRCD = 12
tRP = 12
tRAS = 28
tRFC = 140
tRFCb = 60
tRFC2 = 140
tRFC4 = 140
REFI = 2600
tREFIb = 325
tRPRE = 1
tWPRE = 1
tRRD_S = 7
tRRD_L = 7
tWTR_S = 5
tWTR_L = 5
tFAW = 34
tWR = 10
tWR2 = 10
tRTP = 5
tCCD_S = 4
tCCD_L = 4
tCKE = 5
tCKESR = 10
tXS = 147
tXP = 5
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 40.0
IPP0 = 0
IDD2P = 1.3
IDD2N = 20.0
IDD3P = 7
IDD3N = 20.5
IDD4W = 215
IDD4R = 220
IDD5AB = 150
IDD6x = 20.5
[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 666666
output_level = 1
================================================
FILE: src/DRAMsim3/configs/LPDDR3_8Gb_x32_1600.ini
================================================
[dram_structure]
protocol = LPDDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 32
BL = 8
[timing]
tCK = 1.25
AL = 0
CL = 12
CWL = 9
tRCD = 15
tRP = 15
tRAS = 34
tRFC = 168
tRFCb = 72
tRFC2 = 168
tRFC4 = 168
REFI = 3120
tREFIb = 390
tRPRE = 1
tWPRE = 1
tRRD_S = 8
tRRD_L = 8
tWTR_S = 6
tWTR_L = 6
tFAW = 40
tWR = 12
tWR2 = 12
tRTP = 6
tCCD_S = 4
tCCD_L = 4
tCKE = 6
tCKESR = 12
tXS = 176
tXP = 6
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 40.0
IPP0 = 0
IDD2P = 1.3
IDD2N = 20.5
IDD3P = 7
IDD3N = 21.0
IDD4W = 245
IDD4R = 250
IDD5AB = 150
IDD6x = 21.0
[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 800000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/LPDDR3_8Gb_x32_1866.ini
================================================
[dram_structure]
protocol = LPDDR3
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 32
BL = 8
[timing]
tCK = 1.07
AL = 0
CL = 14
CWL = 11
tRCD = 17
tRP = 17
tRAS = 40
tRFC = 196
tRFCb = 85
tRFC2 = 196
tRFC4 = 196
REFI = 3645
tREFIb = 456
tRPRE = 1
tWPRE = 1
tRRD_S = 10
tRRD_L = 10
tWTR_S = 7
tWTR_L = 7
tFAW = 47
tWR = 15
tWR2 = 15
tRTP = 7
tCCD_S = 4
tCCD_L = 4
tCKE = 7
tCKESR = 15
tXS = 206
tXP = 7
tRTRS = 1
[power]
VDD = 1.2
IDD0 = 41.5
IPP0 = 0
IDD2P = 1.3
IDD2N = 21.5
IDD3P = 7
IDD3N = 22.0
IDD4W = 285
IDD4R = 290
IDD5AB = 150
IDD6x = 22.0
[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 934579
output_level = 1
================================================
FILE: src/DRAMsim3/configs/LPDDR4_8Gb_x16_2400.ini
================================================
[dram_structure]
protocol = LPDDR4
bankgroups = 2
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 16
BL = 16
[timing]
tCK = 0.83
AL = 0
CL = 17
CWL = 14
tRCD = 15
tRP = 15
tRAS = 32
tRFC = 392
tRFC2 = 268
tRFC4 = 172
tREFI = 8660
tRPRE = 1
tWPRE = 1
tRRD_S = 8
tRRD_L = 8
tWTR_S = 8
tWTR_L = 16
tFAW = 32
tWR = 30
tWR2 = 32
tRTP = 12
tCCD_S = 4
tCCD_L = 6
tCKE = 6
tCKESR = 7
tXS = 432
tXP = 6
tRTRS = 1
tPPD = 2
[power]
VDD = 1.2
IDD0 = 80
IPP0 = 4.0
IDD2P = 25
IDD2N = 34
IDD3P = 41
IDD3N = 47
IDD4W = 228
IDD4R = 243
IDD5AB = 280
IDD6x = 30
[system]
channel_size = 8192
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 1204819
output_level = 1
================================================
FILE: src/DRAMsim3/configs/ST-1.2x.ini
================================================
; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC)
;
;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416
;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations.
[dram_structure]
protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 8
BL=4
[timing]
tCK = 1.25;
CL = 11;
CWL = 11
AL = 0;
tRCDRD=14
tRCDWR=14
tRP=14
tRAS=20
tRFC = 1
tREFI = 6240
tRRD_S = 6
tRRD_L = 6
tWTR_S = 2
tWTR_L = 2
tFAW = 29
tWR = 12
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tXP = 5
tRTP_L = 6
tRTP_S = 6
; tRC=34
tRTRS=1
; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations.
[power]
VDD = 1.5
IDD0=1305;
IDD1=1395;
IDD2P=846;
IDD2Q=1030;
IDD2N=1050;
IDD3Pf=60;
IDD3Ps=60;
IDD3N=1310;
IDD4W=1765;
IDD4R=230;
IDD5=1940;
IDD6=246;
IDD6L=246;
IDD7=2160;
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rorabgbachco
queue_structure = PER_RANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 16
trans_queue_size = 32
[other]
epoch_period = 100000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/ST-1.5x.ini
================================================
; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC)
;
;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416
;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 1.5x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations.
[dram_structure]
protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 8
BL=4
[timing]
tCK = 1.25;
CL = 11;
CWL = 11
AL = 0;
tRCDRD=17
tRCDWR=17
tRP=17
tRAS=23
tRFC = 1
tREFI = 6240
tRRD_S = 8
tRRD_L = 8
tWTR_S = 6
tWTR_L = 6
tFAW = 36
tWR = 12
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tXP = 5
tRTP_L = 6
tRTP_S = 6
; tRC=40
tRTRS=1
REFRESH_PERIOD=7800;
; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations.
[power]
VDD=1.5
IDD0=1305;
IDD1=1395;
IDD2P=846;
IDD2Q=1030;
IDD2N=1050;
IDD3Pf=60;
IDD3Ps=60;
IDD3N=1310;
IDD4W=1765;
IDD4R=230;
IDD5=1940;
IDD6=246;
IDD6L=246;
IDD7=2160;
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rorabgbachco
queue_structure = PER_RANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 16
trans_queue_size = 32
[other]
epoch_period = 100000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/ST-2.0x.ini
================================================
; (C) Copyright 2006-2018 Barcelona Supercomputing Center (BSC)
;
;The copyright holder is BSC-CNS, and the authorship correspond to Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. The complete explanation of the derivation of the data can be found in the following study: Kazi Asifuzzaman, Rommel Sanchez Verdejo, and Petar Radojkovic. 2017. Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS '17). Washington DC, USA, 283-292. DOI: https://doi.org/10.1145/3132402.3132416
;Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
;1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
;2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
; This configuration lists detailed timing parameters for STT-MRAM main memory, specifying a 2x deviation from respective DRAM timing parameters. Please note, the current parameters (IDD0, IDD1.. etc) DOES NOT correspond to STT-MRAM and should not be used for current/energy estimations.
[dram_structure]
protocol = DDR3 ; it's STT-MRAM, but using DDR3 protocol
bankgroups = 1
banks_per_group = 8
rows = 32768
columns = 1024
device_width = 8
BL=4
[timing]
tCK = 1.25;
CL = 11;
CWL = 11
AL = 0;
tRCDRD=22
tRCDWR=22
tRP=22
tRAS=28
tRFC = 1
tREFI = 6240
tRRD_S = 10
tRRD_L = 10
tWTR_S = 6
tWTR_L = 6
tFAW = 36
tWR = 48
tCCD_S = 4
tCCD_L = 4
tCKE = 4
tXP = 5
tRTP_L = 6
tRTP_S = 6
; tRC=50
tRTRS=1
REFRESH_PERIOD=7800
; The following current parameters DOES NOT correspond to STT-MRAM, and should not be used used for current/energy estimations.
[power]
VDD=1.5;
IDD0=1305;
IDD1=1395;
IDD2P=846;
IDD2Q=1030;
IDD2N=1050;
IDD3Pf=60;
IDD3Ps=60;
IDD3N=1310;
IDD4W=1765;
IDD4R=230;
IDD5=1940;
IDD6=246;
IDD6L=246;
IDD7=2160;
[system]
channel_size = 4096
channels = 1
bus_width = 64
address_mapping = rorabgbachco
queue_structure = PER_RANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 16
trans_queue_size = 32
[other]
epoch_period = 100000
output_level = 1
================================================
FILE: src/DRAMsim3/configs/ddr3_debug.ini
================================================
[dram_structure]
protocol = DDR3
bankgroups = 1
banks_per_group = 8
rows = 16384
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 1.5
AL = 0
CL = 10
CWL = 7
tRCD = 10
tRP = 10
tRAS = 24
tRFC = 74
tREFI = 5200
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tWTR_S = 5
tFAW = 20
tWR = 10
tCCD_S = 4
tRTP = 5
tCKE = 4
tCKESR = 1
tXS = 81
tXP = 5
tRTRS = 1
[power]
VDD = 1.35
IDD0 = 33
IDD2P = 12
IDD2N = 17
IDD3P = 14
IDD3N = 23
IDD4W = 77
IDD4R = 72
IDD5AB = 155
IDD6x = 12
[system]
channel_size = 2048
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
epoch_period = 666666
output_level = 1
================================================
FILE: src/DRAMsim3/configs/ddr4_debug.ini
================================================
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 65536
columns = 1024
device_width = 8
BL = 8
[timing]
tCK = 0.833
AL = 0
CL = 16
CWL = 16
tRCD = 16
tRP = 16
tRAS = 39
tRFC = 420
tRFC2 = 312
tRFC4 = 192
tREFI = 9364
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 6
tWTR_S = 3
tWTR_L = 9
tFAW = 26
tWR = 19
tWR2 = 1
tCCD_S = 4
tCCD_L = 6
tXS = 12
tCKSRE = 12
tXP = 8
tRFCb = 20
tREFIb = 1950
activation_window_depth = 4
tRREFD = 5
tRTRS = 2
tRTP = 10
tCAS = 3
tCWD = 3
[power]
VDD = 1.2
IDD0 = 48
IDD2P = 25
IDD2N = 34
IDD3P = 37
IDD3N = 44.0
IDD4W = 123
IDD4R = 135
IDD5AB = 250
IDD6x = 31
[system]
channel_size = 16384
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
validation_output = ddr4_verification.log
epoch_period = 1200480
output_level = 1
================================================
FILE: src/DRAMsim3/configs/lpddr_2Gb_x16.ini
================================================
[dram_structure]
protocol = LPDDR
bankgroups = 1
banks_per_group = 4
rows = 16384
columns = 2048
device_width = 16
BL = 8
[timing]
tCK = 4.8
AL = 0
CL = 3
CWL = 3
tRCD = 4
tRP = 3
tRAS = 9
tRFC = 15
tREFI = 1625
tRPRE = 1
tWPRE = 1
tRRD_L = 3
tWTR_L = 2
tFAW = 4
tWR = 3
tCCD_L = 0
tRTP = 0
tXP = 2
tCKE = 1
tRTRS = 1
tCMD = 1
activation_window_depth = 4
[system]
channel_size = 1024
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
[other]
validation_output = lpddr_verification.log
epoch_period = 208333
output_level = 1
[thermal]
power_epoch_period = 10000; power epoch period (# cycle)
chip_dim_x = 0.008; chip size in x dimension [m]
chip_dim_y = 0.008; chip size in y dimension [m]
amb_temp = 40; The ambient temperature in [C]
mat_dim_x = 512;
mat_dim_y = 512;
bank_order = 1; 0: x direction first, 1: y direction first
================================================
FILE: src/DRAMsim3/ext/fmt/LICENSE.rst
================================================
Copyright (c) 2012 - 2016, Victor Zverovich
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
================================================
FILE: src/DRAMsim3/ext/fmt/include/fmt/core.h
================================================
// Formatting library for C++ - the core API
//
// Copyright (c) 2012 - present, Victor Zverovich
// All rights reserved.
//
// For the license information refer to format.h.
#ifndef FMT_CORE_H_
#define FMT_CORE_H_
#include
#include // std::FILE
#include
#include
#include
#include
// The fmt library version in the form major * 10000 + minor * 100 + patch.
#define FMT_VERSION 50202
#ifdef __has_feature
# define FMT_HAS_FEATURE(x) __has_feature(x)
#else
# define FMT_HAS_FEATURE(x) 0
#endif
#if defined(__has_include) && !defined(__INTELLISENSE__) && \
!(defined(__INTEL_COMPILER) && __INTEL_COMPILER < 1600)
# define FMT_HAS_INCLUDE(x) __has_include(x)
#else
# define FMT_HAS_INCLUDE(x) 0
#endif
#ifdef __has_cpp_attribute
# define FMT_HAS_CPP_ATTRIBUTE(x) __has_cpp_attribute(x)
#else
# define FMT_HAS_CPP_ATTRIBUTE(x) 0
#endif
#if defined(__GNUC__) && !defined(__clang__)
# define FMT_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
#else
# define FMT_GCC_VERSION 0
#endif
#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
# define FMT_HAS_GXX_CXX11 FMT_GCC_VERSION
#else
# define FMT_HAS_GXX_CXX11 0
#endif
#ifdef _MSC_VER
# define FMT_MSC_VER _MSC_VER
#else
# define FMT_MSC_VER 0
#endif
// Check if relaxed C++14 constexpr is supported.
// GCC doesn't allow throw in constexpr until version 6 (bug 67371).
#ifndef FMT_USE_CONSTEXPR
# define FMT_USE_CONSTEXPR \
(FMT_HAS_FEATURE(cxx_relaxed_constexpr) || FMT_MSC_VER >= 1910 || \
(FMT_GCC_VERSION >= 600 && __cplusplus >= 201402L))
#endif
#if FMT_USE_CONSTEXPR
# define FMT_CONSTEXPR constexpr
# define FMT_CONSTEXPR_DECL constexpr
#else
# define FMT_CONSTEXPR inline
# define FMT_CONSTEXPR_DECL
#endif
#ifndef FMT_USE_CONSTEXPR11
# define FMT_USE_CONSTEXPR11 \
(FMT_USE_CONSTEXPR || FMT_GCC_VERSION >= 406 || FMT_MSC_VER >= 1900)
#endif
#if FMT_USE_CONSTEXPR11
# define FMT_CONSTEXPR11 constexpr
#else
# define FMT_CONSTEXPR11
#endif
#ifndef FMT_OVERRIDE
# if FMT_HAS_FEATURE(cxx_override) || \
(FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1900
# define FMT_OVERRIDE override
# else
# define FMT_OVERRIDE
# endif
#endif
#if FMT_HAS_FEATURE(cxx_explicit_conversions) || \
FMT_GCC_VERSION >= 405 || FMT_MSC_VER >= 1800
# define FMT_USE_EXPLICIT 1
# define FMT_EXPLICIT explicit
#else
# define FMT_USE_EXPLICIT 0
# define FMT_EXPLICIT
#endif
#ifndef FMT_NULL
# if FMT_HAS_FEATURE(cxx_nullptr) || \
(FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1600
# define FMT_NULL nullptr
# define FMT_USE_NULLPTR 1
# else
# define FMT_NULL NULL
# endif
#endif
#ifndef FMT_USE_NULLPTR
# define FMT_USE_NULLPTR 0
#endif
// Check if exceptions are disabled.
#if (defined(__GNUC__) && !defined(__EXCEPTIONS)) || \
FMT_MSC_VER && !_HAS_EXCEPTIONS
# define FMT_EXCEPTIONS 0
#else
# define FMT_EXCEPTIONS 1
#endif
// Define FMT_USE_NOEXCEPT to make fmt use noexcept (C++11 feature).
#ifndef FMT_USE_NOEXCEPT
# define FMT_USE_NOEXCEPT 0
#endif
#if FMT_USE_NOEXCEPT || FMT_HAS_FEATURE(cxx_noexcept) || \
(FMT_GCC_VERSION >= 408 && FMT_HAS_GXX_CXX11) || FMT_MSC_VER >= 1900
# define FMT_DETECTED_NOEXCEPT noexcept
# define FMT_HAS_CXX11_NOEXCEPT 1
#else
# define FMT_DETECTED_NOEXCEPT throw()
# define FMT_HAS_CXX11_NOEXCEPT 0
#endif
#ifndef FMT_NOEXCEPT
# if FMT_EXCEPTIONS || FMT_HAS_CXX11_NOEXCEPT
# define FMT_NOEXCEPT FMT_DETECTED_NOEXCEPT
# else
# define FMT_NOEXCEPT
# endif
#endif
#ifndef FMT_BEGIN_NAMESPACE
# if FMT_HAS_FEATURE(cxx_inline_namespaces) || FMT_GCC_VERSION >= 404 || \
FMT_MSC_VER >= 1900
# define FMT_INLINE_NAMESPACE inline namespace
# define FMT_END_NAMESPACE }}
# else
# define FMT_INLINE_NAMESPACE namespace
# define FMT_END_NAMESPACE } using namespace v5; }
# endif
# define FMT_BEGIN_NAMESPACE namespace fmt { FMT_INLINE_NAMESPACE v5 {
#endif
#if !defined(FMT_HEADER_ONLY) && defined(_WIN32)
# ifdef FMT_EXPORT
# define FMT_API __declspec(dllexport)
# elif defined(FMT_SHARED)
# define FMT_API __declspec(dllimport)
# endif
#endif
#ifndef FMT_API
# define FMT_API
#endif
#ifndef FMT_ASSERT
# define FMT_ASSERT(condition, message) assert((condition) && message)
#endif
// libc++ supports string_view in pre-c++17.
#if (FMT_HAS_INCLUDE() && \
(__cplusplus > 201402L || defined(_LIBCPP_VERSION))) || \
(defined(_MSVC_LANG) && _MSVC_LANG > 201402L && _MSC_VER >= 1910)
# include
# define FMT_STRING_VIEW std::basic_string_view
#elif FMT_HAS_INCLUDE() && __cplusplus >= 201402L
# include
# define FMT_STRING_VIEW std::experimental::basic_string_view
#endif
// std::result_of is defined in in gcc 4.4.
#if FMT_GCC_VERSION && FMT_GCC_VERSION <= 404
# include
#endif
FMT_BEGIN_NAMESPACE
namespace internal {
// An implementation of declval for pre-C++11 compilers such as gcc 4.
template
typename std::add_rvalue_reference::type declval() FMT_NOEXCEPT;
template
struct result_of;
template
struct result_of {
// A workaround for gcc 4.4 that doesn't allow F to be a reference.
typedef typename std::result_of<
typename std::remove_reference::type(Args...)>::type type;
};
// Casts nonnegative integer to unsigned.
template
FMT_CONSTEXPR typename std::make_unsigned::type to_unsigned(Int value) {
FMT_ASSERT(value >= 0, "negative value");
return static_cast::type>(value);
}
/** A contiguous memory buffer with an optional growing ability. */
template
class basic_buffer {
private:
basic_buffer(const basic_buffer &) = delete;
void operator=(const basic_buffer &) = delete;
T *ptr_;
std::size_t size_;
std::size_t capacity_;
protected:
// Don't initialize ptr_ since it is not accessed to save a few cycles.
basic_buffer(std::size_t sz) FMT_NOEXCEPT: size_(sz), capacity_(sz) {}
basic_buffer(T *p = FMT_NULL, std::size_t sz = 0, std::size_t cap = 0)
FMT_NOEXCEPT: ptr_(p), size_(sz), capacity_(cap) {}
/** Sets the buffer data and capacity. */
void set(T *buf_data, std::size_t buf_capacity) FMT_NOEXCEPT {
ptr_ = buf_data;
capacity_ = buf_capacity;
}
/** Increases the buffer capacity to hold at least *capacity* elements. */
virtual void grow(std::size_t capacity) = 0;
public:
typedef T value_type;
typedef const T &const_reference;
virtual ~basic_buffer() {}
T *begin() FMT_NOEXCEPT { return ptr_; }
T *end() FMT_NOEXCEPT { return ptr_ + size_; }
/** Returns the size of this buffer. */
std::size_t size() const FMT_NOEXCEPT { return size_; }
/** Returns the capacity of this buffer. */
std::size_t capacity() const FMT_NOEXCEPT { return capacity_; }
/** Returns a pointer to the buffer data. */
T *data() FMT_NOEXCEPT { return ptr_; }
/** Returns a pointer to the buffer data. */
const T *data() const FMT_NOEXCEPT { return ptr_; }
/**
Resizes the buffer. If T is a POD type new elements may not be initialized.
*/
void resize(std::size_t new_size) {
reserve(new_size);
size_ = new_size;
}
/** Clears this buffer. */
void clear() { size_ = 0; }
/** Reserves space to store at least *capacity* elements. */
void reserve(std::size_t new_capacity) {
if (new_capacity > capacity_)
grow(new_capacity);
}
void push_back(const T &value) {
reserve(size_ + 1);
ptr_[size_++] = value;
}
/** Appends data to the end of the buffer. */
template
void append(const U *begin, const U *end);
T &operator[](std::size_t index) { return ptr_[index]; }
const T &operator[](std::size_t index) const { return ptr_[index]; }
};
typedef basic_buffer buffer;
typedef basic_buffer wbuffer;
// A container-backed buffer.
template
class container_buffer : public basic_buffer {
private:
Container &container_;
protected:
void grow(std::size_t capacity) FMT_OVERRIDE {
container_.resize(capacity);
this->set(&container_[0], capacity);
}
public:
explicit container_buffer(Container &c)
: basic_buffer(c.size()), container_(c) {}
};
// Extracts a reference to the container from back_insert_iterator.
template
inline Container &get_container(std::back_insert_iterator it) {
typedef std::back_insert_iterator bi_iterator;
struct accessor: bi_iterator {
accessor(bi_iterator iter) : bi_iterator(iter) {}
using bi_iterator::container;
};
return *accessor(it).container;
}
struct error_handler {
FMT_CONSTEXPR error_handler() {}
FMT_CONSTEXPR error_handler(const error_handler &) {}
// This function is intentionally not constexpr to give a compile-time error.
FMT_API void on_error(const char *message);
};
template
struct no_formatter_error : std::false_type {};
} // namespace internal
#if FMT_GCC_VERSION && FMT_GCC_VERSION < 405
template
struct is_constructible: std::false_type {};
#else
template
struct is_constructible : std::is_constructible {};
#endif
/**
An implementation of ``std::basic_string_view`` for pre-C++17. It provides a
subset of the API. ``fmt::basic_string_view`` is used for format strings even
if ``std::string_view`` is available to prevent issues when a library is
compiled with a different ``-std`` option than the client code (which is not
recommended).
*/
template
class basic_string_view {
private:
const Char *data_;
size_t size_;
public:
typedef Char char_type;
typedef const Char *iterator;
FMT_CONSTEXPR basic_string_view() FMT_NOEXCEPT : data_(FMT_NULL), size_(0) {}
/** Constructs a string reference object from a C string and a size. */
FMT_CONSTEXPR basic_string_view(const Char *s, size_t count) FMT_NOEXCEPT
: data_(s), size_(count) {}
/**
\rst
Constructs a string reference object from a C string computing
the size with ``std::char_traits::length``.
\endrst
*/
basic_string_view(const Char *s)
: data_(s), size_(std::char_traits::length(s)) {}
/** Constructs a string reference from a ``std::basic_string`` object. */
template
FMT_CONSTEXPR basic_string_view(
const std::basic_string &s) FMT_NOEXCEPT
: data_(s.data()), size_(s.size()) {}
#ifdef FMT_STRING_VIEW
FMT_CONSTEXPR basic_string_view(FMT_STRING_VIEW s) FMT_NOEXCEPT
: data_(s.data()), size_(s.size()) {}
#endif
/** Returns a pointer to the string data. */
FMT_CONSTEXPR const Char *data() const { return data_; }
/** Returns the string size. */
FMT_CONSTEXPR size_t size() const { return size_; }
FMT_CONSTEXPR iterator begin() const { return data_; }
FMT_CONSTEXPR iterator end() const { return data_ + size_; }
FMT_CONSTEXPR void remove_prefix(size_t n) {
data_ += n;
size_ -= n;
}
// Lexicographically compare this string reference to other.
int compare(basic_string_view other) const {
size_t str_size = size_ < other.size_ ? size_ : other.size_;
int result = std::char_traits::compare(data_, other.data_, str_size);
if (result == 0)
result = size_ == other.size_ ? 0 : (size_ < other.size_ ? -1 : 1);
return result;
}
friend bool operator==(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) == 0;
}
friend bool operator!=(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) != 0;
}
friend bool operator<(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) < 0;
}
friend bool operator<=(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) <= 0;
}
friend bool operator>(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) > 0;
}
friend bool operator>=(basic_string_view lhs, basic_string_view rhs) {
return lhs.compare(rhs) >= 0;
}
};
typedef basic_string_view string_view;
typedef basic_string_view wstring_view;
/**
\rst
The function ``to_string_view`` adapts non-intrusively any kind of string or
string-like type if the user provides a (possibly templated) overload of
``to_string_view`` which takes an instance of the string class
``StringType`` and returns a ``fmt::basic_string_view``.
The conversion function must live in the very same namespace as
``StringType`` to be picked up by ADL. Non-templated string types
like f.e. QString must return a ``basic_string_view`` with a fixed matching
char type.
**Example**::
namespace my_ns {
inline string_view to_string_view(const my_string &s) {
return { s.data(), s.length() };
}
}
std::string message = fmt::format(my_string("The answer is {}"), 42);
\endrst
*/
template
inline basic_string_view
to_string_view(basic_string_view s) { return s; }
template
inline basic_string_view
to_string_view(const std::basic_string &s) { return s; }
template
inline basic_string_view to_string_view(const Char *s) { return s; }
#ifdef FMT_STRING_VIEW
template
inline basic_string_view
to_string_view(FMT_STRING_VIEW s) { return s; }
#endif
// A base class for compile-time strings. It is defined in the fmt namespace to
// make formatting functions visible via ADL, e.g. format(fmt("{}"), 42).
struct compile_string {};
template
struct is_compile_string : std::is_base_of {};
template <
typename S,
typename Enable = typename std::enable_if::value>::type>
FMT_CONSTEXPR basic_string_view
to_string_view(const S &s) { return s; }
template
class basic_format_arg;
template
class basic_format_args;
// A formatter for objects of type T.
template
struct formatter {
static_assert(internal::no_formatter_error::value,
"don't know how to format the type, include fmt/ostream.h if it provides "
"an operator<< that should be used");
// The following functions are not defined intentionally.
template
typename ParseContext::iterator parse(ParseContext &);
template
auto format(const T &val, FormatContext &ctx) -> decltype(ctx.out());
};
template
struct convert_to_int: std::integral_constant<
bool, !std::is_arithmetic::value && std::is_convertible::value> {};
namespace internal {
struct dummy_string_view { typedef void char_type; };
dummy_string_view to_string_view(...);
using fmt::v5::to_string_view;
// Specifies whether S is a string type convertible to fmt::basic_string_view.
template
struct is_string : std::integral_constant()))>::value> {};
template
struct char_t {
typedef decltype(to_string_view(declval())) result;
typedef typename result::char_type type;
};
template
struct named_arg_base;
template
struct named_arg;
enum type {
none_type, named_arg_type,
// Integer types should go first,
int_type, uint_type, long_long_type, ulong_long_type, bool_type, char_type,
last_integer_type = char_type,
// followed by floating-point types.
double_type, long_double_type, last_numeric_type = long_double_type,
cstring_type, string_type, pointer_type, custom_type
};
FMT_CONSTEXPR bool is_integral(type t) {
FMT_ASSERT(t != internal::named_arg_type, "invalid argument type");
return t > internal::none_type && t <= internal::last_integer_type;
}
FMT_CONSTEXPR bool is_arithmetic(type t) {
FMT_ASSERT(t != internal::named_arg_type, "invalid argument type");
return t > internal::none_type && t <= internal::last_numeric_type;
}
template
struct string_value {
const Char *value;
std::size_t size;
};
template
struct custom_value {
const void *value;
void (*format)(const void *arg, Context &ctx);
};
// A formatting argument value.
template
class value {
public:
typedef typename Context::char_type char_type;
union {
int int_value;
unsigned uint_value;
long long long_long_value;
unsigned long long ulong_long_value;
double double_value;
long double long_double_value;
const void *pointer;
string_value string;
string_value sstring;
string_value ustring;
custom_value custom;
};
FMT_CONSTEXPR value(int val = 0) : int_value(val) {}
value(unsigned val) { uint_value = val; }
value(long long val) { long_long_value = val; }
value(unsigned long long val) { ulong_long_value = val; }
value(double val) { double_value = val; }
value(long double val) { long_double_value = val; }
value(const char_type *val) { string.value = val; }
value(const signed char *val) {
static_assert(std::is_same::value,
"incompatible string types");
sstring.value = val;
}
value(const unsigned char *val) {
static_assert(std::is_same::value,
"incompatible string types");
ustring.value = val;
}
value(basic_string_view val) {
string.value = val.data();
string.size = val.size();
}
value(const void *val) { pointer = val; }
template
explicit value(const T &val) {
custom.value = &val;
custom.format = &format_custom_arg;
}
const named_arg_base &as_named_arg() {
return *static_cast*>(pointer);
}
private:
// Formats an argument of a custom type, such as a user-defined class.
template
static void format_custom_arg(const void *arg, Context &ctx) {
// Get the formatter type through the context to allow different contexts
// have different extension points, e.g. `formatter` for `format` and
// `printf_formatter` for `printf`.
typename Context::template formatter_type::type f;
auto &&parse_ctx = ctx.parse_context();
parse_ctx.advance_to(f.parse(parse_ctx));
ctx.advance_to(f.format(*static_cast(arg), ctx));
}
};
// Value initializer used to delay conversion to value and reduce memory churn.
template
struct init {
T val;
static const type type_tag = TYPE;
FMT_CONSTEXPR init(const T &v) : val(v) {}
FMT_CONSTEXPR operator value() const { return value(val); }
};
template
FMT_CONSTEXPR basic_format_arg make_arg(const T &value);
#define FMT_MAKE_VALUE(TAG, ArgType, ValueType) \
template \
FMT_CONSTEXPR init make_value(ArgType val) { \
return static_cast(val); \
}
#define FMT_MAKE_VALUE_SAME(TAG, Type) \
template \
FMT_CONSTEXPR init make_value(Type val) { return val; }
FMT_MAKE_VALUE(bool_type, bool, int)
FMT_MAKE_VALUE(int_type, short, int)
FMT_MAKE_VALUE(uint_type, unsigned short, unsigned)
FMT_MAKE_VALUE_SAME(int_type, int)
FMT_MAKE_VALUE_SAME(uint_type, unsigned)
// To minimize the number of types we need to deal with, long is translated
// either to int or to long long depending on its size.
typedef std::conditional::type
long_type;
FMT_MAKE_VALUE(
(sizeof(long) == sizeof(int) ? int_type : long_long_type), long, long_type)
typedef std::conditional::type ulong_type;
FMT_MAKE_VALUE(
(sizeof(unsigned long) == sizeof(unsigned) ? uint_type : ulong_long_type),
unsigned long, ulong_type)
FMT_MAKE_VALUE_SAME(long_long_type, long long)
FMT_MAKE_VALUE_SAME(ulong_long_type, unsigned long long)
FMT_MAKE_VALUE(int_type, signed char, int)
FMT_MAKE_VALUE(uint_type, unsigned char, unsigned)
// This doesn't use FMT_MAKE_VALUE because of ambiguity in gcc 4.4.
template
FMT_CONSTEXPR typename std::enable_if<
std::is_same::value,
init>::type make_value(Char val) { return val; }
template
FMT_CONSTEXPR typename std::enable_if<
!std::is_same::value,
init>::type make_value(char val) { return val; }
FMT_MAKE_VALUE(double_type, float, double)
FMT_MAKE_VALUE_SAME(double_type, double)
FMT_MAKE_VALUE_SAME(long_double_type, long double)
// Formatting of wide strings into a narrow buffer and multibyte strings
// into a wide buffer is disallowed (https://github.com/fmtlib/fmt/pull/606).
FMT_MAKE_VALUE(cstring_type, typename C::char_type*,
const typename C::char_type*)
FMT_MAKE_VALUE(cstring_type, const typename C::char_type*,
const typename C::char_type*)
FMT_MAKE_VALUE(cstring_type, signed char*, const signed char*)
FMT_MAKE_VALUE_SAME(cstring_type, const signed char*)
FMT_MAKE_VALUE(cstring_type, unsigned char*, const unsigned char*)
FMT_MAKE_VALUE_SAME(cstring_type, const unsigned char*)
FMT_MAKE_VALUE_SAME(string_type, basic_string_view)
FMT_MAKE_VALUE(string_type,
typename basic_string_view::type,
basic_string_view)
FMT_MAKE_VALUE(string_type, const std::basic_string&,
basic_string_view)
FMT_MAKE_VALUE(pointer_type, void*, const void*)
FMT_MAKE_VALUE_SAME(pointer_type, const void*)
#if FMT_USE_NULLPTR
FMT_MAKE_VALUE(pointer_type, std::nullptr_t, const void*)
#endif
// Formatting of arbitrary pointers is disallowed. If you want to output a
// pointer cast it to "void *" or "const void *". In particular, this forbids
// formatting of "[const] volatile char *" which is printed as bool by
// iostreams.
template
typename std::enable_if::value>::type
make_value(const T *) {
static_assert(!sizeof(T), "formatting of non-void pointers is disallowed");
}
template
inline typename std::enable_if<
std::is_enum::value && convert_to_int::value,
init>::type
make_value(const T &val) { return static_cast(val); }
template
inline typename std::enable_if<
is_constructible, T>::value &&
!internal::is_string::value,
init, string_type>>::type
make_value(const T &val) { return basic_string_view(val); }
template
inline typename std::enable_if<
!convert_to_int::value && !std::is_same::value &&
!std::is_convertible>::value &&
!is_constructible, T>::value &&
!internal::is_string::value,
// Implicit conversion to std::string is not handled here because it's
// unsafe: https://github.com/fmtlib/fmt/issues/729
init>::type
make_value(const T &val) { return val; }
template
init
make_value(const named_arg &val) {
basic_format_arg arg = make_arg(val.value);
std::memcpy(val.data, &arg, sizeof(arg));
return static_cast(&val);
}
template
FMT_CONSTEXPR11 typename std::enable_if<
internal::is_string::value,
init, string_type>>::type
make_value(const S &val) {
// Handle adapted strings.
static_assert(std::is_same<
typename C::char_type, typename internal::char_t::type>::value,
"mismatch between char-types of context and argument");
return to_string_view(val);
}
// Maximum number of arguments with packed types.
enum { max_packed_args = 15 };
template
class arg_map;
} // namespace internal
// A formatting argument. It is a trivially copyable/constructible type to
// allow storage in basic_memory_buffer.
template
class basic_format_arg {
private:
internal::value value_;
internal::type type_;
template
friend FMT_CONSTEXPR basic_format_arg
internal::make_arg(const T &value);
template
friend FMT_CONSTEXPR typename internal::result_of::type
visit_format_arg(Visitor &&vis, const basic_format_arg &arg);
friend class basic_format_args;
friend class internal::arg_map;
typedef typename Context::char_type char_type;
public:
class handle {
public:
explicit handle(internal::custom_value custom): custom_(custom) {}
void format(Context &ctx) const { custom_.format(custom_.value, ctx); }
private:
internal::custom_value custom_;
};
FMT_CONSTEXPR basic_format_arg() : type_(internal::none_type) {}
FMT_EXPLICIT operator bool() const FMT_NOEXCEPT {
return type_ != internal::none_type;
}
internal::type type() const { return type_; }
bool is_integral() const { return internal::is_integral(type_); }
bool is_arithmetic() const { return internal::is_arithmetic(type_); }
};
struct monostate {};
/**
\rst
Visits an argument dispatching to the appropriate visit method based on
the argument type. For example, if the argument type is ``double`` then
``vis(value)`` will be called with the value of type ``double``.
\endrst
*/
template
FMT_CONSTEXPR typename internal::result_of::type
visit_format_arg(Visitor &&vis, const basic_format_arg &arg) {
typedef typename Context::char_type char_type;
switch (arg.type_) {
case internal::none_type:
break;
case internal::named_arg_type:
FMT_ASSERT(false, "invalid argument type");
break;
case internal::int_type:
return vis(arg.value_.int_value);
case internal::uint_type:
return vis(arg.value_.uint_value);
case internal::long_long_type:
return vis(arg.value_.long_long_value);
case internal::ulong_long_type:
return vis(arg.value_.ulong_long_value);
case internal::bool_type:
return vis(arg.value_.int_value != 0);
case internal::char_type:
return vis(static_cast(arg.value_.int_value));
case internal::double_type:
return vis(arg.value_.double_value);
case internal::long_double_type:
return vis(arg.value_.long_double_value);
case internal::cstring_type:
return vis(arg.value_.string.value);
case internal::string_type:
return vis(basic_string_view(
arg.value_.string.value, arg.value_.string.size));
case internal::pointer_type:
return vis(arg.value_.pointer);
case internal::custom_type:
return vis(typename basic_format_arg::handle(arg.value_.custom));
}
return vis(monostate());
}
template
FMT_CONSTEXPR typename internal::result_of::type
visit(Visitor &&vis, const basic_format_arg &arg) {
return visit_format_arg(std::forward(vis), arg);
}
// Parsing context consisting of a format string range being parsed and an
// argument counter for automatic indexing.
template
class basic_parse_context : private ErrorHandler {
private:
basic_string_view format_str_;
int next_arg_id_;
public:
typedef Char char_type;
typedef typename basic_string_view::iterator iterator;
explicit FMT_CONSTEXPR basic_parse_context(
basic_string_view format_str, ErrorHandler eh = ErrorHandler())
: ErrorHandler(eh), format_str_(format_str), next_arg_id_(0) {}
// Returns an iterator to the beginning of the format string range being
// parsed.
FMT_CONSTEXPR iterator begin() const FMT_NOEXCEPT {
return format_str_.begin();
}
// Returns an iterator past the end of the format string range being parsed.
FMT_CONSTEXPR iterator end() const FMT_NOEXCEPT { return format_str_.end(); }
// Advances the begin iterator to ``it``.
FMT_CONSTEXPR void advance_to(iterator it) {
format_str_.remove_prefix(internal::to_unsigned(it - begin()));
}
// Returns the next argument index.
FMT_CONSTEXPR unsigned next_arg_id();
FMT_CONSTEXPR bool check_arg_id(unsigned) {
if (next_arg_id_ > 0) {
on_error("cannot switch from automatic to manual argument indexing");
return false;
}
next_arg_id_ = -1;
return true;
}
void check_arg_id(basic_string_view) {}
FMT_CONSTEXPR void on_error(const char *message) {
ErrorHandler::on_error(message);
}
FMT_CONSTEXPR ErrorHandler error_handler() const { return *this; }
};
typedef basic_parse_context parse_context;
typedef basic_parse_context wparse_context;
namespace internal {
// A map from argument names to their values for named arguments.
template
class arg_map {
private:
arg_map(const arg_map &) = delete;
void operator=(const arg_map &) = delete;
typedef typename Context::char_type char_type;
struct entry {
basic_string_view name;
basic_format_arg arg;
};
entry *map_;
unsigned size_;
void push_back(value val) {
const internal::named_arg_base &named = val.as_named_arg();
map_[size_] = entry{named.name, named.template deserialize()};
++size_;
}
public:
arg_map() : map_(FMT_NULL), size_(0) {}
void init(const basic_format_args &args);
~arg_map() { delete [] map_; }
basic_format_arg find(basic_string_view name) const {
// The list is unsorted, so just return the first matching name.
for (entry *it = map_, *end = map_ + size_; it != end; ++it) {
if (it->name == name)
return it->arg;
}
return {};
}
};
// A type-erased reference to an std::locale to avoid heavy include.
class locale_ref {
private:
const void *locale_; // A type-erased pointer to std::locale.
friend class locale;
public:
locale_ref() : locale_(FMT_NULL) {}
template
explicit locale_ref(const Locale &loc);
template
Locale get() const;
};
template
class context_base {
public:
typedef OutputIt iterator;
private:
basic_parse_context parse_context_;
iterator out_;
basic_format_args args_;
locale_ref loc_;
protected:
typedef Char char_type;
typedef basic_format_arg format_arg;
context_base(OutputIt out, basic_string_view format_str,
basic_format_args ctx_args,
locale_ref loc = locale_ref())
: parse_context_(format_str), out_(out), args_(ctx_args), loc_(loc) {}
// Returns the argument with specified index.
format_arg do_get_arg(unsigned arg_id) {
format_arg arg = args_.get(arg_id);
if (!arg)
parse_context_.on_error("argument index out of range");
return arg;
}
// Checks if manual indexing is used and returns the argument with
// specified index.
format_arg get_arg(unsigned arg_id) {
return this->parse_context().check_arg_id(arg_id) ?
this->do_get_arg(arg_id) : format_arg();
}
public:
basic_parse_context &parse_context() { return parse_context_; }
basic_format_args args() const { return args_; }
internal::error_handler error_handler() {
return parse_context_.error_handler();
}
void on_error(const char *message) { parse_context_.on_error(message); }
// Returns an iterator to the beginning of the output range.
iterator out() { return out_; }
iterator begin() { return out_; } // deprecated
// Advances the begin iterator to ``it``.
void advance_to(iterator it) { out_ = it; }
locale_ref locale() { return loc_; }
};
template
struct get_type {
typedef decltype(make_value(
declval::type&>())) value_type;
static const type value = value_type::type_tag;
};
template
FMT_CONSTEXPR11 unsigned long long get_types() { return 0; }
template
FMT_CONSTEXPR11 unsigned long long get_types() {
return get_type::value | (get_types() << 4);
}
template
FMT_CONSTEXPR basic_format_arg make_arg(const T &value) {
basic_format_arg arg;
arg.type_ = get_type::value;
arg.value_ = make_value(value);
return arg;
}
template
inline typename std::enable_if>::type
make_arg(const T &value) {
return make_value(value);
}
template
inline typename std::enable_if>::type
make_arg(const T &value) {
return make_arg(value);
}
} // namespace internal
// Formatting context.
template
class basic_format_context :
public internal::context_base<
OutputIt, basic_format_context, Char> {
public:
/** The character type for the output. */
typedef Char char_type;
// using formatter_type = formatter;
template
struct formatter_type { typedef formatter type; };
private:
internal::arg_map map_;
basic_format_context(const basic_format_context &) = delete;
void operator=(const basic_format_context &) = delete;
typedef internal::context_base base;
typedef typename base::format_arg format_arg;
using base::get_arg;
public:
using typename base::iterator;
/**
Constructs a ``basic_format_context`` object. References to the arguments are
stored in the object so make sure they have appropriate lifetimes.
*/
basic_format_context(OutputIt out, basic_string_view format_str,
basic_format_args ctx_args,
internal::locale_ref loc = internal::locale_ref())
: base(out, format_str, ctx_args, loc) {}
format_arg next_arg() {
return this->do_get_arg(this->parse_context().next_arg_id());
}
format_arg get_arg(unsigned arg_id) { return this->do_get_arg(arg_id); }
// Checks if manual indexing is used and returns the argument with the
// specified name.
format_arg get_arg(basic_string_view name);
};
template
struct buffer_context {
typedef basic_format_context<
std::back_insert_iterator>, Char> type;
};
typedef buffer_context::type format_context;
typedef buffer_context::type wformat_context;
/**
\rst
An array of references to arguments. It can be implicitly converted into
`~fmt::basic_format_args` for passing into type-erased formatting functions
such as `~fmt::vformat`.
\endrst
*/
template
class format_arg_store {
private:
static const size_t NUM_ARGS = sizeof...(Args);
// Packed is a macro on MinGW so use IS_PACKED instead.
static const bool IS_PACKED = NUM_ARGS < internal::max_packed_args;
typedef typename std::conditional, basic_format_arg>::type value_type;
// If the arguments are not packed, add one more element to mark the end.
static const size_t DATA_SIZE =
NUM_ARGS + (IS_PACKED && NUM_ARGS != 0 ? 0 : 1);
value_type data_[DATA_SIZE];
friend class basic_format_args;
static FMT_CONSTEXPR11 long long get_types() {
return IS_PACKED ?
static_cast(internal::get_types()) :
-static_cast(NUM_ARGS);
}
public:
#if FMT_USE_CONSTEXPR11
static FMT_CONSTEXPR11 long long TYPES = get_types();
#else
static const long long TYPES;
#endif
#if (FMT_GCC_VERSION && FMT_GCC_VERSION <= 405) || \
(FMT_MSC_VER && FMT_MSC_VER <= 1800)
// Workaround array initialization issues in gcc <= 4.5 and MSVC <= 2013.
format_arg_store(const Args &... args) {
value_type init[DATA_SIZE] =
{internal::make_arg(args)...};
std::memcpy(data_, init, sizeof(init));
}
#else
format_arg_store(const Args &... args)
: data_{internal::make_arg(args)...} {}
#endif
};
#if !FMT_USE_CONSTEXPR11
template
const long long format_arg_store::TYPES = get_types();
#endif
/**
\rst
Constructs an `~fmt::format_arg_store` object that contains references to
arguments and can be implicitly converted to `~fmt::format_args`. `Context`
can be omitted in which case it defaults to `~fmt::context`.
\endrst
*/
template
inline format_arg_store
make_format_args(const Args &... args) { return {args...}; }
template
inline format_arg_store
make_format_args(const Args &... args) { return {args...}; }
/** Formatting arguments. */
template
class basic_format_args {
public:
typedef unsigned size_type;
typedef basic_format_arg format_arg;
private:
// To reduce compiled code size per formatting function call, types of first
// max_packed_args arguments are passed in the types_ field.
unsigned long long types_;
union {
// If the number of arguments is less than max_packed_args, the argument
// values are stored in values_, otherwise they are stored in args_.
// This is done to reduce compiled code size as storing larger objects
// may require more code (at least on x86-64) even if the same amount of
// data is actually copied to stack. It saves ~10% on the bloat test.
const internal::value *values_;
const format_arg *args_;
};
typename internal::type type(unsigned index) const {
unsigned shift = index * 4;
unsigned long long mask = 0xf;
return static_cast(
(types_ & (mask << shift)) >> shift);
}
friend class internal::arg_map;
void set_data(const internal::value *values) { values_ = values; }
void set_data(const format_arg *args) { args_ = args; }
format_arg do_get(size_type index) const {
format_arg arg;
long long signed_types = static_cast(types_);
if (signed_types < 0) {
unsigned long long num_args =
static_cast